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The Setup for Triangle Rasterization By Andres Kugler Eurographics ’ 96 Computer Graphics Lab in Tubingen Univ. 2005.6.2 Jiwon Choo. Contents. Abstract & Introduction The Graphic Rendering Pipeline Scan Conversion pipeline Initialization Data Latency Intensive Computation - PowerPoint PPT Presentation
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The Setup for Triangle RasterizaThe Setup for Triangle Rasterizationtion
By Andres Kugler Eurographics ’96By Andres Kugler Eurographics ’96Computer Graphics Lab in Tubingen UnivComputer Graphics Lab in Tubingen Univ
2005.6.2Jiwon Choo
Contents
Abstract & Introduction The Graphic Rendering Pipeline Scan Conversion pipeline Initialization Data Latency Intensive Computation Setup Architecture and Bandwidth Conclusion
Abstract
Integrating Slope and setup calculation to rasterizer increase 3D system performance host processing is greatly reduced Data flow from host to sub system is also
greatly reduced.
Intoroduction
Rasterizer Performance Bottleneck
world coordinate transformation to screen coordinate and computing vertex colors
calculating the triangle edge slope and increment necessary for the scan-conversion
the rate at which the fixed point iterators generate pixel values
the achieved bandwidth into the frame buffer and texture memory
The Graphic Rendering Pipeline
The Graphic Rendering Pipeline
The Graphic Rendering Pipeline
Scan Conversion pipeline
Initialization Data
Initialization Data
Latency Intensive Computation
Latency Intensive Computation
Multiplication easily parallelized by breaking the
multiplication of two values in two, or four individual multiplication and summing the partial results.
Needs 4 pipeline stage
Latency Intensive Computation
Division Common way: subtractive and multiplicative method.
pj+1 = rpj – qj+1.D Needs N pipeline stage
Faster way: series of expansion of the reciprocal. Newton-Raphson implementation xi+1 = xi .(2-b.xi) Needs 10 pipeline stage Initial approximation for reciprocal is taken from a
ROM Look-up-table - LUT Additionally guard bit reduce latency & size of rasterizer
Latency Intensive Computation
Latency Intensive Computation
Setup Architecture and Bandwidth
Setup Architecture and Bandwidth
Setup Architecture and Bandwidth
Setup Architecture and Bandwidth
Input stack Register File with Setup Values
Reciprocal evaluation for color, depth, texture coordinate increment
Gradient computation Slope calculation
Setup Architecture and Bandwidth
Modeling the throughput of setup Pipeline Setup & raster pipeline clock 80MHz. Producing 1 rendered pixel per cycle. Standard VRAM&DRAM are used for frame buffer and z-buffer. Page mode with a memory controller operating at 80MHz Z buffer has 10way inter leaving
Conclusion
Conclusion
Moving the setup from the geometry processor to the rasterizer greatly improves the available input
bandwidth to the rasterizer virtually permits to send triangles to the
setup at the same rate as they can be written into the frame buffer by rasterizer.