2007 12 ICC Incremental Training

Predictable Success

IC Compiler 2007.12 Incremental Training

IC Compiler CAE

© 2007 Synopsys, Inc. (2)

Predictable Success(2)

IC Compiler 2007.12 Update Training

Agenda Agenda •• Timing/SI Timing/SI •• MCMMMCMM•• Hierarchical Flow (Includes ILM)Hierarchical Flow (Includes ILM)•• Low Power Low Power •• DFM & RoutingDFM & Routing•• User InterfaceUser Interface

New commands/options added in 2007.12 highlighted in Blue



IC Compiler 2007.12 – Timing/SI

clock_optclock_opt

Chip Finishing Chip Finishing

signoff_optsignoff_opt

FloorplanningFloorplanning

Design Setup Design Setup

place_optplace_opt

route_optroute_opt

• Optimization runtime improvement• Improved report_congestion

• Integrated clock global router • Fix DRCs beyond exceptions mark_clock_tree

• Layer based GR congestion map –User Interface

• Mixed mode extraction • Auto extraction

• Min delta delay correlation • SI run time improvement• User Interface improvements for

noise

• IC Compiler Feasibility flow

• Min Chip Technology



check_library • Overview

Data consistency check between Logical v/s Physical librariesPhysical library database consistency checkEnhanced Tech File checking and man pages

• User Interfacecheck_library -mw_library_name {phys_library_name_list} -logic_library_name {logical_library_name_list} –cell_list{cell_list}

• User Benefit • Identifies the library problems earlier and provided the details reports to

user• Helps the turn around time and avoids late detection of library issues



IC Compiler Feasibility Flow• Overview

The feasibility flow should be run before detail implementationIt helps to eliminate potential issues in early design stagesThere are three main checks in the flow:

• Routeability • Power network integrity• Timing

• User InterfaceN/A

• User BenefitGives faster turn around time (TAT) Gives early prediction of timing closure



IC Compiler Feasibility Flow

•route_fp_protp•report_congestionCheck Timing Environment

Timing Optimization

Virtual Flat Placement

Initialize Floorplan

Read Netlist / Constraints

PNA/PNS

Floorplan refinement

Refine PG mesh

Bad SDC NO

Update SDC

NO Bad floorplan

place_optclock_optroute_opt

psynopt

Power OK

Timing OK

Global Route

Routability OK

NO

Yes

•read_verilog_to_cel•read_io_constraints•read_sdc

•initiialize_floorplan

•create_fp_placement

•analyze_fp_rail•synthesize_fp_rail

• check_fp_timing_environmentIdentifies unconstrained paths, zero wire delay timing violations,bottleneck cells, timing with virtualoptimization to quickly identify badtiming paths, modules

•optimize_fp_timingquick optimization



Min Chip Technology • Overview

Min chip preserves user’s investment in floorplan• Floorplan is preserved (block shape, macro placements, blockages)• Pins preserved (relative side and order, including on rectilinear edges)

Min chip supports proportional sizing of voltage areasMin chip accounts for power routing using Power Network Synthesis

• Each voltage area may have different mesh patterns (strap pitch, layers, rings)

Min chip supports complex I/O (multi-height, multi-ring, staggered)

• User InterfaceRun the Tcl command estimate_fp_area orGUI: Floorplan Estimate Area

• User BenefitSearch for smallest routable de size

• Preserves floor planning investment• Eliminates costly resizing iterations

Improves designer productivity



Min Chip TechnologyFlow Recommendations

• Start with original netlist for P&R flow• Minchip needs an optimized

database as an input or results will be too optimistic

• Minchip produces the smallest routable new floorplan

• After Minchip use original netlist and new floorplan for P&R flow

Detailed ImplementationDetailed Implementation

Design Data(Original Netlist)

Design Data(Original Netlist)

MinChipMinChip

Design PlanningDesign Planning

Detailed ImplementationDetailed Implementation

Design Data(Original Netlist + New

MinChip Floorplan)

Design Data(Original Netlist + New

MinChip Floorplan)



Optimization Runtime Improvement • Overview

Improved buffering runtime for optimization

• User InterfaceNo User Interface changes are required

• User BenefitAverage 30% runtime improvement @ place_opt stage No QoR impactWorks with any optimizations

• Pre route optimizationplace_opt, psynopt, clock_opt

• Post route optimizationroute_opt



Integrated Clock Global Router (ICGR)

• Overview2007.12 with the integrated clock global router replaces virtual route for optimize_clock_treeand balance_inter_clock_delay

• In prior releases clock tree implementation used virtual route for wire delay and capacitance estimation which caused correlation issues between clock and signal route

• User Interfacects_integrated_global_router <true|false:default>



Integrated Clock Global Router (ICGR)

• User BenefitCompared to virtual route based CTS flow, ICGR has shown improved clock tree correlation between

• Post-cto and post clock route (average correlation within 10%) • Post-cto and post clock/signal route( average correlation within

10%)• CTO with ICGR run time: +20%

Note: Correlation can be further improved with clock spacing and shielding and also the Non Default Rules



Integrated Clock Global Router (ICGR)compile_clock_tree

set cts_integrated_global_router true

optimize_clock_tree

route_group –all_clock_nets

set droute_wrongWayExtraCost 0set groute_incremental 0

set droute_wrongWayExtraCost 20set groute_incremental 2

Enable ICGR before CTO (default: false)

Set clock routing variables

Reset clock routing variables



Fix DRC Beyond Exceptions

• OverviewCTS fixes, reports and removes the DRCs beyond exceptions – stop, sync and exclude pins

• User InterfaceNo Change

• User BenefitDRC fixing is done by default during CTSImprove TTR & QoR



Fix DRC Beyond Exceptions

• Flow log examplecompile_clock_tree

CTS: clock tree synthesis summaryCTS: 2 buffer trees insertedCTS: 17 buffers used (total size = 217.689)CTS: summary of DRC fixing beyond exception pinCTS: 1 buffer trees insertedCTS: 3 buffers used (total size = 41.1845)

report_clock_tree –structureshows the structure of new clock tree including beyond exceptions

remove_clock_treeSUMMARY 14 buffer(s) & 0 inverter(s) are removedRemoving cells added for drc fixing beyond exceptions...

3 buffer(s) and 0 inverter(s) are removed



mark_clock_tree

• OverviewModify clock related attributes on clock cells and nets

• Clock net NDR and routing layer• Clock tree imported from Astro or 3rd party tool• Fix or soft-fix sinks for routing resource adjustment

• User BenefitMark clock tree to identify imported clock tree and continue clock optimizationModify existing clock tree attributes for subsequent optimization and routing



mark_clock_tree

• User Interface•mark_clock_tree

-clock_trees-clock_net-clock_synthesized-fix_sinks-routing_rule-use_default_routing_for_sinks-layer_list-ideal_net-remove



mark_clock_tree

• Flow recommendationsUse this command to mark clock attributes on imported clock treestructures for sub-sequent IC Compiler clock operationsTo modify NDR rules applied on a already synthesized clock network

• Known LimitationsETM model internal clock pin are not supported



Mixed Mode Extraction

• OverviewEnhance extract_rc to perform detail route extraction and virtual route estimation

• User Interface Set the following variable to true • set complete_mixed_mode_extraction true• Default: false • When mixed mode extraction will be ON by default, then for backward

compatibility, -routed_nets_only option will be added to extract_rc and write_parasitics commands

• User BenefitMinimized number of commands when extracting a partially routed design (clock routed stage); • extract_rc• can now be replaces• extract_rc –estimate; extract_rc

Please keep in mind that place_opt currently doesn’t support mixed mode extraction



Auto Extraction

• OverviewPreserving parasitic is possible in 2007.12 when timing constraints need to be removed (SDC) ; Fixes issues in auto-extraction for not to extract if the design is not re-linked, tluplus files and temperatures are not changed

• User Interface Option –keep_parasitics is added to remove_sdc command

• User BenefitParasitics need not be re-extracted after remove_sdcEase of use and reduced runtime by not having to re-extract the parasitics



Auto Extraction

• Usage /GUIUse the -keep_parasitics option to retain the parasitics information during remove_sdc•remove_sdc –keep_parasitics

• Flow RecommendationsUse remove_sdc –keep_parasitics when removing CTS SDC after clock_opt



Ignore Layers Support In Virtual Route

• OverviewTo honor ignored layers in virtual route topology creation

• User Interface No change in User Interface

• User BenefitImproved correlation of virtual route and detail route topology when ignored layers are used

• Ex. On a 7-metal layer design, if M6 and M7 are ignored, and there is a Macro that blocks layers M1-M5, virtual route will now detour around it (consistent with detail router topology)



Ignore Layers Support In Virtual Route

• Usage /GUI No change in User Interfaceextract_rc –estimate (executed stand-alone and also invoked during pre-route optimization commands) will now honor the ignored layers



Improved report_congestion

• Overviewreport_congestion is updated to use the IC Compiler global route to ensure consistency and convergence

• User Interfacereport_congestion

• Changes to this feature are explained later

• User BenefitGlobal router based congestion map and correlates with GUI display of hotspots/overflows Good correlation between pre route and post route stage




• Usagereport_congestion -search_repair-no_reroute-grc_based-coordinate

-search_repair• Controls groute iteration. Default is 1 iteration. If this option is specified,

groute runs 4 iterations-no_reroute

• In default, report_congestion automatically runs groute to generate congestion map

-grc_based• Reports GRC base. Worse 10 GRC reported

- coordinate• Specify the region to report. Entire design reported by default






Layer-Based Global Route Congestion Map• Overview

The old congestion map for display is two dimensional (x & y)The global router is a 3 dimensional routing engine with metal layer being the third dimension

• The demand and capacity of metal layers on the same direction is added and displayed as one single demand and capacity

Hence, the old congestion map does not reflect the realistic picture of congestion

• This is true if some metal layers have significant congestion and some metal layers don’t

• User BenefitThe new congestion map allows user to display and view congestion information per layer basis

• Congestion map is consistent with log file report• Studying congestion on a specific layer is possible



Layer-Based Global Route Congestion Map

• User Interface / GUI (Examples)

M2 congestion hot spot is shown in the new

congestion map

Almost no congestion is shown in the old

congestion map

Overflow on M2 is cancelled out by underflow on M4

and M6



Layer-Based Global Route Congestion Map

• User Interface / GUIThere is no User Interface changeGUI: Route -> Global Route Congestion Map

NEW



• OverviewCoupling capacitance is partially grounded for min crosstalk delta delay calculation to improve correlation with PTSI

• User Interface set si_use_partial_grounding_for_min_analysis false

Feature not ON by default

• User BenefitBetter correlation in min-corner (Hold) timing

• Percentage of paths with arrival time difference less than 3% isimproved from 89% to 97%

Min Delta Delay Correlation



• OverviewReduce SI analysis runtime in low effort crosstalk mode while improving the correlation with PTSI

• User Interface No NEW User Interface changeTo Enable:• set_si_options –analysis_effort low• Default: medium

• User BenefitReduced runtime in update_timing, route_opt with SI low effort mode• update_timing runtime reduced by 8%• route_opt runtime reduced by 3.2%

Improved IC Compiler-PT-SI correlation in low effort mode

SI Runtime Improvement



• OverviewImproved SI delta delay user interface in IC Compiler

• You get detail information on the individual aggressor contribution

• Report the details of the active and screened aggressors

• User Interface report_delay_calculation –crosstalk

• User BenefitEase of use for debugging PT-SI delta delay correlation on specific timing arcs

Xtalk User Interface Improvement



Xtalk User Interface ImprovementIC Compiler report_delay_calculation -crosstalk

Operating Conditions: WCCOM Library: tcbn90gthpwc

Annotated max rise net delta delay: 0.010671 arc delay: 0.011469Annotated max fall net delta delay: 0.000000 arc delay: 0.000800

Annotated max rise net delta transition: 0.010078 pin transition: 0.450000Annotated max fall net delta transition: 0.000000 pin transition: 0.242500Reporting for Crosstalk:Victim net name: n12228Number of aggressors: 4Number of effective (non-filtered) aggressors: 4Victim driver rail voltage(VDD): 1.080000

Attributes:A - aggressor is ActiveS - aggressor is screened

Victim is rising:Victim Coupling Driver ClocksNet Cap Lib Cell

-------------- --------- ------------ ---------------n12228 0.002741 OAI21D1 FE_CLK

Aggressor Coupling Driver Clocks Attributes Switching Bump

Net Cap Lib Cell (ratio of VDD) -------------- --------- ----------- ------------- --------

---- ----------------n3397 0.001798 INVD1 FE_CLK A

0.024420n32801 0.000199 ND3D0 FE_CLK S

-n32807 0.000396 ND3D0 FE_CLK S

-n32835 0.000348 NR2D0 FE_CLK S

-

PTSI report_delay_calculation -crosstalk

Annotated max rise net delta delay: 0.010671 arc delay: 0.011469Annotated max fall net delta delay: 0.000000 arc delay: 0.000800

Annotated max rise net delta transition: 0.010078 pin transition: 0.450000Annotated max fall net delta transition: 0.000000 pin transition: 0.242500Reporting for Crosstalk:Victim net name: n12228Number of aggressors: 4Number of effective (non-filtered) aggressors: 4Victim driver rail voltage(VDD): 1.080000si_xtalk_analysis_effort_level: mediumsi_xtalk_delay_analysis_mode: all_pathssi_analysis_logical_correlation_mode: trueCrosstalk composite aggressor mode: disabled

Attributes:A - aggressor is Active

C - aggressor is a composite aggressorE - aggressor is screened due to user ExclusionI - aggressor has Infinite arrival with respect to the victimL - aggressor is screened due to Logical correlationN - aggressor does Not overlap for the worst case alignmentS - aggressor is screened for Small bumpsU - aggressor/victim RC calculation is skippedX - aggressor is screened due to aggressor eXclusion

Victim is rising:Victim Coupling Driver ClocksNet Cap Lib Cell

-------------- --------- ------------ ---------------n12228 0.002741 OAI21D1 FE_CLK

Aggressor Coupling Driver Clocks Attributes Switching BumpNet Cap Lib Cell (ratio of VDD)

-------------- --------- ----------- ------------- ------------ ----------------n3397 0.001798 INVD1 FE_CLK A 0.024420n32801 0.000199 ND3D0 FE_CLK S -n32807 0.000396 ND3D0 FE_CLK S -

n32835 0.000348 NR2D0 FE_CLK S -



• OverviewImprove SI static noise user interface in IC Compiler

• You get detail information on the individual aggressor contribution• Report the details of active and screened aggressors

• User Interface report_noise -verbose -all_violators -slack_lesser_than slack_limitreport_noise_calculation -from from_pin -to to_pin -significant_digits digits

• User BenefitEase of use for debugging PT-SI static noise correlation on specific timing arcs

Noise User Interface Improvement



Noise User Interface ImprovementIC Compiler report_noise_calculation

Analysis mode : report_at_sourceRegion : below_highVictim driver pin : exetop0/e_dptop0/e_flag0/I27/YVictim driver library cell : MX4X4Victim net : exetop0/e_dptop0/e_flag0/N194Steady state resistance source : estimation set valueDriver voltage swing : 1.620

Attributes:A - aggressor is ActiveS - aggressor is screened

Height Width Area Aggressor Attributes---------------------------------------------------------------------------

Aggressors:exetop0/e_rndm0/n35 0.028 0.843 0.012 Aexetop0/e_rndm0/n10 0.025 0.702 0.009 Aexetop0/e_rndm0/n19178 0.000 0.000 0.000 Sexetop0/e_rndm0/n18454 0.029 0.282 0.004 Aexetop0/s_AEI2_0_ 0.000 0.000 0.000 S

Total: 0.082 0.603 0.025

Noise slack calculation:

Constraint type: user margin

Height Area---------------------------------------------------------------------Required Time 0.567 (0.567 * 0.603) -Actual 0.082 (0.082 * 0.603)

---------------------------------------------------------------------Slack 0.485 0.293

PTSI report_noise_calculationAnalysis mode : report_at_sourceRegion : below_highVictim driver pin : exetop0/e_dptop0/e_flag0/I27/YVictim driver library cell : MX4X4Victim net : exetop0/e_dptop0/e_flag0/N194Steady state resistance source : estimation set valueDriver voltage swing : 1.620

Driver voltage swing : 1.080000Noise derate height offset : 0.000000Noise derate height scale factor : 1.000000Noise derate width scale factor : 1.000000Noise effort threshold : 0.000000Noise composite aggressor mode : disabledNoise calculations:

Attributes:A - aggressor is activeC - aggressor is a composite aggressorD - aggressor is analyzed with detailed engineE - aggressor is screened due to user exclusionG - aggressor is analyzed with gate level simulatorI - aggressor has infinite windowL - aggressor is screened due to logical correlationS - aggressor is screened due to small bump heightX - aggressor is screened due to aggressor exclusion

Height Width Area Aggressor Attributes---------------------------------------------------------------------------

Aggressors:exetop0/e_rndm0/n35 0.028 0.843 0.012 Aexetop0/e_rndm0/n10 0.025 0.702 0.009 Aexetop0/e_rndm0/n19178 0.000 0.000 0.000 Sexetop0/e_rndm0/n18454 0.029 0.282 0.004 Aexetop0/s_AEI2_0_ 0.000 0.000 0.000 S

Total: 0.082 0.603 0.025

Noise slack calculation:

Constraint type: user margin

Height Area---------------------------------------------------------------------Required Time 0.567 (0.567 * 0.603) -Actual 0.082 (0.082 * 0.603)

---------------------------------------------------------------------Slack 0.485 0.293




1.1. Timing/SI Timing/SI 2.2. MCMMMCMM3.3. Hierarchical Flow (includes ILM)Hierarchical Flow (includes ILM)4.4. Low Power Low Power 5.5. DFM & Route RulesDFM & Route Rules6.6. User InterfaceUser Interface

New commands/options added in 2007.12 highlighted in

Blue



IC Compiler 2007.12 – MCMM

clock_optclock_opt





place_optplace_opt

route_optroute_opt

•More Than 3 TLUPlus Support•Support For Netlist ECO Commands•MCMM Reporting Enhancements



More Than 3 TLUPlus Support

• Overview• This feature addresses the previous limitation of using up to 3

TLUPlus in one MCMM session.With 2007.12, the user can now use as many TLUPlus as needed in a MCMM session.

• User Interface No change in User Interface. The user will use more than 3 TLUPlus files by creating more scenarios.

• User BenefitThe users can see significant improvements in usage as they can now optimize their design across any number of TLUPlus corners.



More Than 3 TLUPlus Support

• UsageTLUPlus files must be set by the set_tlu_plus_filescommand under the scope of each scenario

• Flow RecommendationsFirst create a scenarioThen set TLUPlus files for that scenario



Netlist ECO Commands To Support MCMM

• Overviewinsert_buffer/size_cell are MCMM compatible

• User InterfaceThe command selects the lib_cel from the library based on the operating condition setting (associated with scenario), user can use one of •<.db file name>:<library name>/<lib_cell name>

•<library name>/<lib_cell name>

•<lib_cell name>

to specify the lib_cell



MCMM Reporting Enhancements

• New report_scenario commandLists scenarios status

• all, active, current, CTS and leakage scenariosReturns libraries, operating conditions, TLUPlus per scenario

• Enhancements to existing commandsIncreased number of commands supporting a scenario listCommands working on current scenario only

• Scenario now reported in report header



report_scenarios Command****************************************Report : scenariosDesign : small_testScenario(s): s1 s2Version: A-2007.12-IC Compiler-ALPHA3Date : Thu Sep 20 13:10:18 2007****************************************

All scenarios (Total=4): s1 s2 s3 s4All Active scenarios (Total=2): s1 s2Current scenario : s2CTS scenario : s3Leakage-only scenario: not defined.

Scenario #0: s1 is active.Library(s) Used:xx_worst (File: /des/90nm/LM/xx_worst.lib_T85.db)

Operating condition(s) Used:Max Operating Condition: xx_worst:WORSTMax Process : 1.00Max Voltage : 1.10Max Temperature: 85.00Min Operating Condition: xx_best:BESTMin Process : 1.00Min Voltage : 1.30Min Temperature: 0.00

Tlu Plus Files Used:Max TLU+ file: /des/xx_worst_TLUP.tfMin TLU+ file: /des/xx_best_TLUP.tfTech2ITF mapping file: /remote/tf2itf.map

Scenario #1: s2 is active.Library(s) Used:xx_worst (File: /des/90nm/LM/xx_worst.lib_T85.db)

Operating condition(s) Used:Max Operating Condition: xx_worst:WORSTMax Process : 1.00Max Voltage : 1.10Max Temperature: 85.00Min Operating Condition: xx_worst:WORSTMin Process : 1.00Min Voltage : 1.10Min Temperature: 85.00

Tlu Plus Files Used:Max TLU+ file: /des/xx_worst_TLUP.tfMin TLU+ file: /des/xx_best_TLUP.tfTech2ITF mapping file: /remote/tf2itf.map




Commands supporting -scenario {scenario list}:• report_timing

• report_timing_derate

• report_clock

• report_path_group

• report_net (scenario specific info only eg. -transition_times)

• report_power

• report_extraction_options

• report_tlu_plus_files

• report_constraint -all_violators/-verbose




report_path_group

****************************************Report : path_groupDesign : small_test

Scenario(s): s2Version: A-2007.12-IC Compiler-ALPHA3Date : Thu Sep 20 13:54:16 2007****************************************

CriticalGroup Name Weight Range Scenario----------------------------------------------reg2reg 1.00 0.00 s2clk 1.00 0.00 s2

Path Group clk: (Scenario: s2)-to clk

report_path_group -scenario [all_scenarios]

****************************************Report : path_groupDesign : small_test

Scenario(s): s1 s2 s3 s4Version: A-2007.12-IC Compiler-ALPHA3Date : Thu Sep 20 13:54:16 2007****************************************








•report_annotated_check•report_annotated_transition•report_annotated_delay•report_attribute•report_case_analysis•report_ideal_network•report_internal_loads •report_clock_gating_check•report_clock_tree•report_clock_tree_power•report_delay_calculation•report_delay_estimate_options•report_transitive_fanout

•report_disable_timing•report_latency_adjustment_options•report_net•report_power•report_power_calculation•report_noise•report_signal_em•report_timing_derate•report_timing_requirements•report_transitive_fanin•report_crpr•report_clock_timing

• Commands reporting only on current scenario now have scenario information in the report header



MCMM Reporting Enhancements****************************************Report : netDesign : small_test

Scenario(s): s2Version: A-2007.12-IC Compiler-ALPHA3Date : Thu Sep 20 14:30:40 2007****************************************

Parasitic source : LPEParasitic mode : RealRCExtraction mode : MIN_MAXExtraction derating : 85/85

Operating Conditions: WORST Library: xx_worstWire Load Model Mode: top

Attributes:c - annotated capacitancer - annotated resistance

Net Fanout Fanin Load Resistance Pins Attributes--------------------------------------------------------------------------------a 1 1 11.14 0.00 2 c, rb 1 1 7.76 0.00 2 c, rc 1 1 16.32 0.00 2 c, rc1 1 1 9.21 0.00 2 c, rc2 2 1 13.53 0.00 3 c, r…w17 1 1 9.25 0.00 2 c, rw18 1 1 7.04 0.00 2 c, r--------------------------------------------------------------------------------Total 40 nets 43 40 433.19 0.00 83Maximum 2 1 34.03 0.00 3Average 1.08 1.00 10.83 0.00 2.08



IC Compiler 2007.12 Update Training1. Timing/SI 2. MCMM3. Hierarchical Flow (includes ILM))4. Low Power5. DFM & Route Rules6. User Interface




IC Compiler 2007.12 – Hierarchical Flow

clock_optclock_opt





place_optplace_opt

route_optroute_opt

•Hierarchical Flow •Plan Group Based Placement•Plan Group Shaping•Clock Planning•Pin Assignment•Budgeting Flow•Black Box Support•ILM Enhancement •Hierarchical Verilog Netlist



Hierarchical Design Flow

• Overview2007.12 IC Compiler provides hierarchical design methodology to divide and conquer large designs

• User InterfaceUse IC Compiler Design Planning to perform hierarchical floorplanning, check design feasibility, generate hierarchical design databaseUse standard IC Compiler flow to finish block implementationGenerate ILM and FRAM models for blocksImplement top level using ILM/FRAM

• User BenefitManage capacity and run timeSupport hierarchical design methodology in different scenarios

• Black Box flow, Lower power, MCMM etc.



Block level

Hierarchical Design Planning

Top level

Virtual Flat Placement

Pin Assignment

Create plan groupshaping/refinement

plangroup aware routing

Initial floorplan

Set Pin Assignment Constraints

PNA/PNS

In Place Optimization

Hierarchical Design Flow

Read Netlist/constraints

Timing Budgeting

Commit Hierarchy

clock_opt

place_opt

Load Design/SDC

route_opt

ILM/FRAM Generation

clock_opt

place_opt

Load Design/ILM

route_opt

Replace CEL wt FRAM

read_SDC



Plan Group Based Placement• Overview

Plan Group:• Represents a module in the logical hierarchy that needs to be physically

implemented• Physical implementation block inherits the shape and size of the

PlanGroupVirtual Flat Placement in design with Plan Groups

• Place cells and hard macros of same physical implementation block together

• User InterfaceRun the Tcl Command create_plan_groups orGUI: Floorplan Create Plan Group

• User BenefitPlacement result can be used to decide

• Hard macro locations• Locations, shapes and sizes of the physical blocks



Plan Group Shaping• Overview

Plan Group Shaping feature :• Places the Plan Groups based on cell distribution• Can create both “rectangular” and “rectilinear” shapes for Plan

Groups• Run virtual flat placement again to put cells into plan group area

• User InterfaceRun the Tcl Command shape_fp_blocks orGUI: Placement Place and Shape Plan Groups

• User BenefitAutomatically Place and Shape plan group boundaries, black boxesand other soft macros in the core area



Clock Planning

• OverviewClock planning performs the following tasks:

Inserts anchor cells on the plan group input ports.Generates the clock trees inside each plan group.Defines the input pin of each anchor cell to be a float pin.Generates the top-level clock tree.Performs detail routing on the clock interface nets

• User Interface set_fp_clock_plan_options Sets options for the clock planning clock tree synthesis enginereport_fp_clock_plan_options Reports options for the clock planning clock tree synthesis enginecompile_fp_clock_plan Performs clock planning

GUI: Clock Set Clock Plan OptionsCompile Clock Plan



Flow Recommendation On Clock Planning

Commit Hierarchy

Timing Budget

Report Timing

Proto Route

Clock Planning

Extraction RC

In Place Optimization optimize_fp_timing

set_fp_clock_plan_options -anchor_cell Anchor_Cell_Namereport_fp_clock_plan_optionscompile_fp_clock_plan

route_fp_proto

extract_rcreport_timingcheck_fp_timing_environmentallocate_fp_budgets

Extraction RC



Pin Assignment • Overview

Assignment of pins on the soft marco boundaries based on user defined constrains to achieve optimal timing and routablility

• User Interface• set_fp_pin_constraints:

set pin constraints (including TDF file) on soft macros• analyze_fp_routing:

use option “-list_feedthrough_nets” to output feedthrough (FT) nets; use option “-finalize” to finalize FT nets and pins and to cut pins based on Global Routing results.

• check_fp_pin_assignment: reports whether pin assignment has observed pin constraints.

• check_fp_pin_alignment: check pin alignment (provide pin detour report).



Pin Assignment

•place_fp_pinsplace pins of Soft Macros from top level or within block level

•commit_fp_plan_groups:

Creates Soft Macros and place pins on each Soft Macro •uncommit_fp_soft_macros:

converts Soft Macros to plan group.•push_down_fp_objects:

push down objects (cells,preroute, … ) into Soft Macro•push_up_fp_objects:

push up objects from Soft Macro back to plan group.



Pin Assignment

Feedthrough IPO

Budgeting

Commit

Analyze Routing

Plangroup Aware Global Route

mark_clock_treeset_fp_pin_constraints (on Plan Groups)set_parameter -name readPlanGroup -value 1route_globalanalyze_fp_routing -finalize

optimize_fp_timing -feedthrough_buffering_only

extract_rcallocate_fp_budgets

commit_fp_plan_groups -push_down_power_and_ground_straps

After placement and optimization:



Timing Budgeting Flow• Overview

The objective of this feature is to generate SDC timing constraints for block-level by

• Distributing positive and negative slack in the path• Determines input and output delays by analyzing delays of

interblock timing arcs

• User InterfaceRun the Tcl Command allocate_fp_budgets or

GUI: Timing Allocate Budgets

• User Benefit• Early detection of feasibility of top-level timing closure• Good SDC achieves good implementation of blocks



Budgeting Based On Crosstalk Effect• Overview

Does budgeting using noise-induced delayTimer estimates coupling effect based on congestion mapHierarchical Signal Integrity information will be written out on plangroup pins

Store top-level xtalk effect for block implementation

• User Interfaceset enable_hier_si true

allocate_fp_budgets Budgeter stores effective aggressor driving strength for input pins and coupling cap across block boundary into block CEL view

Effective driving strength

Cc1Store into block MW CEL view

QD

Cc2 Cc3



check_fp_budget_result

• Post-Budgeting Analysis:Generate a report containing real and budgeted delays through a hierarchical block

• Flop-to-flop paths within blocks are not reported

• User InterfaceTcl Command: check_fp_budget_resultGUI: N/AMust be performed during the same session as allocate_fp_budgets



Timing-Driven Black Box Flow• Overview

The objective of this flow is to provide you a virtual flat timing-driven black box flow with

• Tcl commands on how to identify black box• A complete virtual flat timing-driven black box flow with steps only for

black box flow in different color from the color for steps of traditional virtual flat flow.

• User Interface Flow can be executed with a script of sequence Tcl commands; orFlow can be executed using each individual GUI operation

• User BenefitYou start the floorplan early without a complete netlist for some modules (implemented as black boxes).



Timing-Driven Black Box Flow Summary Read Netlist with Black Box

Import Black Box; Estimate Size

Initialize Floorplan

import_fp_black_boxesestimate_fp_black_boxessave_mw_cel -hierarchy

QTM Timing Modelset fp_bb_flow true create_qtm_model…save_qtm_modelwrite_qtm_model

z Step for Black Box Only

Power Planning

IPO

Create Plan Group; Shaping; VF Placement

Set Black Box Pin Constraints;

Place Black Box Pins

push_down_fp_objects (push down cell row and P/G on black box)set_fp_pin_constraints (on black box)place_fp_pins (on black box)Analyze Routing

Plangroup Aware Global Route

Feedthrough IPO

Budgeting

Commit



Feedthrough Net Support

• OverviewStarting with 2007.12, feedthroughs are supported throughout the IC Compiler hierarchical flow, including ILM usagePrior to 2007.12, ILMs could not have feedthroughs or multiple-port nets.

• You had to use the set_fix_multiple_port_nets command before block level synthesis & model creation (FRAM and ILM)

• No longer required in 2007.12• User Interface

No User Interface change

• User BenefitProvides consistent support throughout the hierarchical flow, where feedthroughs may be the best solution (i.e. for routing through blocks)Applies to both signal and clock nets

• Top-level CTS supports the use of clock feedthroughs on ILM blocks



Nested ILM Support• Overview

Nested ILMs are fully supported throughout the hierarchical flow from 2007.12The feature targets very large designs where multiple levels of abstraction are used

Nested ILM

Block2

ILM1

• User Interfacecreate_ilm

• User BenefitInner ILMs are transparently absorbed into upper level ILM, so that only the logic involved in the upper level ILM’s timing paths are retained from lower level ILMsThis helps to minimize the size of the upper level ILM and keep the overall memory footprint small.



Compact ILM Support• Overview• Reduces ILM size by including only the timing critical portion of the

interface logicFor each block-level port, retains only the most critical paths (i.e. those related to max_rise, max_fall, min_rise, min_fall corners)

• User InterfaceBlock-level: create_ilm –compact

Top-level: create_ilm_models –compact {list of reference blocks}

• User BenefitSmaller memory footprint than regular ILMs is possibleResults in faster top-level runtime



CTS Supports ILMs

• OverviewIC Compiler CTS now supports clocks created inside ILM and those going through ILMIt also supports clock exceptions defined on ILM ports and inside ILM

• User InterfaceAll new features are on by default

• User BenefitFaster runtime and uses less memoryEase of Use in the top level flow



CTS Support For ILM

• CTS adds guide buffers to ILM clock inputs & outputs

ATop-level FFs driven by ILM muxed clockC

Top-level FFs driven by ILM generated clock

BGenerated clock

Muxed clock

GuidebufferCLK

Guide Buffer

Top-level FFs driven by CLK

ILM

• CTS honors clock definitions and clock exceptions inside ILM and/or on I/O ports of ILM

• CTS synthesizes the tree for top-level FFs after ports B and C and driven by CLK

• Nets between guide buffers are marked with a ‘dont_buffer_net’



Writing Out a Full Verilog Netlist

• You can write out a full Verilog netlist (e.g. for handoff to PrimeTime) for hierarchical designs containing ILMs

• It only takes one command to do this:write_verilog -macro_definitionFull_Design.vg

CEL views (full block level designs) are written out for all blocks modeled by ILMs




1.1. Timing/SI Timing/SI 2.2. MCMMMCMM3.3. Hierarchical Flow (includes ILM)Hierarchical Flow (includes ILM)4.4. Low PowerLow Power5.5. DFM & Route RulesDFM & Route Rules6.6. User Interface User Interface




IC Compiler 2007.12 – Low Power

clock_optclock_opt





place_optplace_opt

route_optroute_opt

•Pre CTS Optimization•Simultaneous PNS/PNA•MTCMOS Design Planning & Exploration

• UPFUser Interface EnhancementUPF Flat Flow Recommendations In 2007.12

•MV Checker•Adaptive Leakage Optimization (ALO)



Optimize Pre CTS Design For Power

• OverviewThe objective of this feature is to optimize the placed design for power by

• Physical optimization of Integrated Clock Gating (ICGs) cells, and• Low power placement

• User Interface Set options to enable clock gate optimization and low power placement. By default both these options are false

set_power_options –clock_gating true -low_power_placement true

Run optimize_pre_cts_power optimize_pre_cts_power orclock_opt –power



Optimize Pre CTS Design for Power

• User BenefitImprovement in power (average 10%), with minimal impact to timing and CTS QoR

• Significant improvement is seen on designs with large number of clock gates which have small fan out

• Power improvement comes with a cost of runtime



Optimize Pre CTS Design For Power

• Flow Recommendations

Set clock optionsset_clock_tree_optionsSet clock tree referencesset_clock_tree_referencesSet clock tree exceptionsset_clock_tree_exceptions

IC Compiler pre placement CEL view

place_opt

route_opt

Using this feature with IC Compiler default flow

clock_opt -power

set_power_options –clock_gating true

–low_power_placement true –leakage false

Set clock options before power aware placement is done; CTS is run under the hood during power aware

placement

By default, both clock gate

optimization and low power

placement are disabled; only

leakage optimization is on by default when –

power is used

Set clock optionsset_clock_tree_optionsSet clock tree referencesset_clock_tree_referencesSet clock tree exceptionsset_clock_tree_exceptions

IC Compiler pre placement CEL view

place_opt -power

route_opt -power

Using this feature with IC Compiler low power flow

clock_opt -power

set_power_options –clock_gating true

–low_power_placement true –leakage true



Simultaneous PNS/PNA in MVDD Design

• OverviewThe objective of this feature is to synthesize multiple power networks on multiple voltage areas with user specified P/G constraints at same time.

• User Interface Set four groups of power network synthesis constraints for each voltage

set_fp_rail_voltage_area_constraints -voltage_area -nets –layer –global –ring_nets

Run synthesize_fp_rail

-synthesize_voltage_area -power_budget

• User BenefitTo generate multiple power networks on different voltage area concurrent to reduce turn around time.To create common ground over multiple voltage area, common grounds transition smoothly among voltage areas.PNS- Power Network Synthesis, PNA- Power Network Analysis



MTCMOS Design Planning

• OverviewThe objective of this feature is to explore MTCMOS planning

• User Interface explore_header_footer

To explore MTCMOS cell placement and IR drop, based on the inserted MTCMOS

• User BenefitInsert and place MTCMOS array to explore if whole chip IR drop meets IR drop target with inserted MTCMOS array



MTCMOS Design PlanningMW design lib & floorplan creation

voltage area (power domain) creation and planning

virtual flat placement

create base power meshpower network creation and analysis

LS / ISO insertion (recommend done in logic synthesis)

placement refine and routeability check)

MTCMOS cell explorer

power switch insertion

pre route power switch cell

power network analysis

place_opt / clock_opt / route_opt

explore_header_footer

add_header_footer_cell_array connect_virtual_pg_net

optimize_header_footer(preroute main and virtual pg net in physical)

analyze_fp_rail

Additional Step



Unified Power Format (UPF)• Overview

UPF 1.0 key commands supported in IC CompilerBinary flow through MW recommendedAutomatic pg derivation based on UPF power intentSpecial cells insertion (Isolation Cells; Retention Register) must be done in Design Compiler as in non-upf mode

• Libraries need to have power and ground (PG) pin definitionsCustomer Consumable Application Note on Library requirements forPG Pin syntax Modeling : https://solvnet.synopsys.com/retrieve/022443.htmlLevel Shifter and Isolation Cell Modeling : https://solvnet.synopsys.com/retrieve/020279.htmlSwitch Cell Modeling : https://solvnet.synopsys.com/retrieve/020281.htmlRetention Cell Modeling: https://solvnet.synopsys.com/retrieve/020282.htmlAlways ON cell Modeling : https://solvnet.synopsys.com/retrieve/022442.html

• Please refer to IC Compiler 2007.12 User Guide for ICC UPF methodology

https://solvnet.synopsys.com/retrieve/022443.html







User Interface Enhancement For UPF Support

create_power_domain

remove_power_domain

report_power_domain

create_supply_port

remove_supply_port

report_supply_port

set_domain_supply_net

create_supply_net

connect_supply_net

report_supply_net

remove_supply_net

create_power_switch

remove_power_switch

report_power_switch

•OverviewNew UPF objects have been added to Milkyway database and User Interface

•User Interface14 new Tcl User Interface commands are added to IC Compiler to manipulate those new UPF objects

•Usage/GUI•New Tcl User Interface commands are:



User Interface Enhancement For UPF Support

• Flow RecommendationsIC Compiler must be in UPF mode, otherwise these new 14 User Interface commands won’t be available. A design must be loaded before any of these new commands could be executed successfullyCommands need GALAXY-MV feature license.

• (i.e. create_*, remove_*, set_domain_supply_net, and connect_supply_net)

• Except all of the report_* commandsMinimal runtime and memory impact for the new commands.



UPF: Recommendation In 2007.12 MV Flat Flow (upf_mode)

place_opt

clock_opt

route_opt Chip finishingsave_upf

open_mw_cel

Design Planning phase•VA creation•Switch cell mapping + insertion•Secondary power pin routing•check_physical_design •derive_pg_connection

check_mv_design

Please refer to 2007.12 User Guide for Flow DetailsHighlighted are only applicable to upf_mode

Note:Libraries must have power and ground (PG)Pin Connections



MV Checker

• OverviewExisting check_mv_design addresses logical checking onlyLack of physical analysis and checking capability for MV designsA debug utility to check the validity of user constraints

• Usage /GUI

check_physical_design –for_mv



MV Checker•User Benefit

The report from checking the physical constraints helps debug and guides your error corrections

• Report and count of special cells (level shifters, isolation cells etc.) in the design

• Report of special cells that are fixed placement or in RP blocks

• If the voltage area site rows contains the required site-types

• Utilization of always-on power wells to determine the size of power wells

• If voltage area contains fixed cells located outside

• Absence of guard-band• Absence of power domain in

association with voltage area



Adaptive Leakage Optimization (ALO)• Overview

Improves leakage optimization QoRALO makes place_opt, clock_opt and route_optleakage aware

• Enables optimization to use as many low leakage cells as possible

• User Interface Off by default. To enable ALO,set adaptive_leakage_opto true

• User BenefitAverage 15% lower leakage power than 2007.03 after route_opt

Note: Runtime hit of up to 10% is expected for overall flow



Adaptive Leakage Optimization (ALO)

• Usage /GUITo use the ALO, the user interface remains the same

set adaptive_leakage_opto true

…set target_library “hvt.db lvt.db”…set_power_options –leakage trueplace_opt –power…clock_opt –power…route_opt –power…




1.1. Timing/SI Timing/SI 2.2. MCMMMCMM3.3. Hierarchical Flow (Includes ILM)Hierarchical Flow (Includes ILM)4.4. Low Power Low Power 5.5. DFM & Route RulesDFM & Route Rules6.6. GUI GUI




IC Compiler 2007.12 – Route Rules

clock_optclock_opt





place_optplace_opt

route_optroute_opt

•Via Farm Rule •Poly Contact Enclosure•Area Based Antenna Rule•Coaxial Shielding•Via Enclosure•Parallel Length Dot Short



Via Farm Rule

• OverviewThis is an enhancement for PG Route Via Farm Rule to honor the rule specified in technology file on via farms spacing and maximum number of rows only in the longer direction of wires intersection

• User BenefitDesign satisfies specified via farm rule on PG wires



Via Farm Rule

• Existing via farm rulemaxNumRows = 2

viaFarmSpacing = spacing

• New via farm rulemaxNumRows = 2

viaFarmSpacing = spacing

viaFarmLongDirection = 1

viaFarmSpacing

viaFarmSpacing



Via Farm Rule

• UsageFor existing via farm rule, specify the following in the ContactCode section of the technology file:• maxNumRows = number

• viaFarmSpacing = spacing

For the new via farm rule, specify the following in the Contact Code section of the technology file: • maxNumRows = number

• viaFarmSpacing = spacing

• viaFarmLongDirection = 1



Poly Contact Enclosure

• OverviewIn 45nm design, poly contact requires different metal enclosure with respect to metal width and projection/parallel length to the adjacent metals

• User Interface New droute options are added to trigger the metal extension rule

set_droute_options –name M1FloatingSpaceForViaOffLimit \–value 0.08

set_droute_options –name M1FloatingParaLenForViaOffLimit \–value 0.27

• User BenefitDrouter shifts the via to meet metal enclosure rule if the tech file variables and droute options were defined



Poly Contact Enclosure

• Usage /GUI

W1

Metal enclosure of poly contact =0.015 if width of W1 or W2 >= 0.11, space < 0.08 and projection/parallel length > 0.27This rule is ignored if double contacts with cut spacing < 0.11

W2

X1

S

X2

DesignRule {layer1 = “METAL1"layer2 = “CO" endOfLineEncTblSize = 2 endOfLineEncSideThreshold = (0.11, 0.21)fatWireViaKeepoutMinSize = ( 2, 2) fatWireViaKeepoutEnclosure = ( 0.015, 0 ) }

S is defined in droute option M1FloatingSpaceForViaOffLimit = 0.08

P is defined in droute option M1FloatingParaLenForViaOffLimit = 0.27

X1/X2: fatWireViaKeepoutEnclosure

P



Area Based Antenna Rule

• OverviewIn general, antenna is checked by considering antenna ratio (antenna_area/gate_size). With this new enhancement, router is able to consider antenna by area and insert a diode at a specific distance to gate.

• User Interface New Tcl command defines antenna area rule•define_antenna_area_rule-mode <ignore_lower_layers|include_lower_layers|include_all_lower_layers>-max_area max_metal_area[-diode_distance diode_distance]




• Usage /GUI

If area of metal3 violates max_area=50, then a diode must be placed within the diode_distance to protect the gate from excessive charges

Gate

Metal3

Metal2

Metal1VIA1

VIA2

define_antenna_area_rule -mode ignore_lower_layers \-max_area 50 -diode_distance 200

report_antenna_rules -output dump.rule lib_name

diode_distance = 200

Define/report antenna area rules in IC Compiler_shell:




• User BenefitRouter detects the area-base-antenna violation and uses metal-splitting (route_search_repair) or insert a diode (insert_diode) to overcome the violation



Coaxial Shielding

• OverviewIn general, shielding only takes place on the same layerIC Compiler shields a net with same, upper and lower (coaxially)metal layers. The upper or lower shields are placed at one another track

• User Interface New options are added to both GUI and Tcl command create_auto_shield•[-coaxial_below] •[-coaxial_above]

• User BenefitCoaxial shielded nets can have better noise-resistance



Coaxial Shielding• Usage / GUI

• Upper and lower shields are placed at one another track

M4

M3VIA34

M2/M4

M3/M5

Clock net

Clock Net

Shielding Net

Cross-view

M4M3

M5

Top-view



Coaxial Shielding

• Flow Recommendations Route specific group of nets first and then do coaxial shielding

• Known LimitationsLong runtime if coaxial shields are created in a complete routeddesign



Parallel Length Dot Short• Overview

Provides the detection and fixing floating antenna violation with respect to floating metal’s area and parallel distance and spacing to the adjacent metal wire

• User Interface

report_antenna_ratio to report floating antenna violation

• A new droute option is added to setup the detection/fixing mode:set_droute_options –name floatingWireMode –value 1;; range [0,2], default=0, stored in cell;;; 0: fixing based on antenna conx (if any)

;; 1: fixing based on floating antenna conx only;; 2: fixing based on floating antenna conx only (ignore violations on user routes)



Parallel Length Dot Short – User Interface set_droute_options -name m1FloatingWireArea -value 70.000

set_droute_options -name m1FloatingWireSpacing -value 10

set_droute_options -name ignoreFloatingWireSpacing -value 0 set_droute_options -name M1FloatingWirePLength1 -value 0.0set_droute_options -name M1FloatingWirePLength2 -value 0.5 set_droute_options -name M1FloatingWirePLength3 -value 0.6set_droute_options -name M1FloatingWirePLMinSpc1 -value 3.0 set_droute_options -name M1FloatingWirePLMinSpc2 -value 1.5 set_droute_options -name M1FloatingWirePLMinSpc3 -value 0.24



Parallel Length Dot Short

• User BenefitReports floating antenna violationFixes floating antenna violation by Search & Repair

• Flow RecommendationsSet all constraints by drouter variable then fix “dot short” by Search and Repair

• Known LimitationsFloating antenna does not check on pre routes



DRC Rules Support In IC Compiler 2007.12• For More details on the DRC Support in IC Compiler • 45 nm DRC Support in IC Compiler• https://solvnet.synopsys.com/retrieve/021298.html

• 65 nm DRC Support in IC Compiler• https://solvnet.synopsys.com/retrieve/018370.html






1.1. Timing/SI Timing/SI 2.2. MCMMMCMM3.3. Hierarchical Flow (Includes ILM)Hierarchical Flow (Includes ILM)4.4. Low Power Low Power 5.5. DFM & Route RulesDFM & Route Rules6.6. User InterfaceUser Interface




IC Compiler 2007.12 – User Interface

clock_optclock_opt





place_optplace_opt

route_optroute_opt

• New Highlight tool

• Show GUI Dialog•check_library



New Highlight Tool

• HighlightsAllows highlighting objects w/o making/changing selection Allows highlighting objects with their original object colorsAllows highlighting nets of the chosen wire segmentsAllows query on highlighted objects

• UsageClick on the “highlighter” tool icon in the “Mouse Tools” toolbarCheck the options in the “Highlight Tool Options” command dialogCheck on/off the menu item “Highlight->Highlight Using Object Color”Check on/off the menu item “View->InfoTip



New Highlight Tool

Highlight with highlight color

Highlight with object color



New Highlight Tool



Show GUI Dialog

• Show GUI Dialog Or Menu LocationsBring up the corresponding GUI command dialog box of a given Tcl command (without knowing & choosing the menu item)Show the menu locations of a given group of Tcl commands

• Usageicc_shell> GUI_show_form route*

icc_shell> GUI_show_form place_opt



Show GUI Dialog



New Command Check_library

•check_library command has been implemented in DC-T and IC Compiler in 2007.12 release

• Recommendation is to use this command before/after you setup your design and make sure the libraries do not have problems

• You can perform selective checks by setting the options using set_check_library_options

• If no options are set using set_check_library_options, check_library will perform default checking

• You can report the options set by set_check_library_options using the command report_check_library_options



Types Of Checks Currently AvailableNumber Checks performed ( Logical v/s Physical ) Option

1 If no options are specified in set_check_library_options, by default, it will check for missing cells and pins and mismatched pins including pg_pin’s in .lib vs. Power and Ground pins in Milkyway

No Option specified

2 Checks area attribute of cells in logical library vs. actual area by cell PR boundary in physical library

-cell_area

3 Checks cell PR boundary and pins in physical library among a class of cells with the same cell_footprint attribute

-cell_footprint

4 Checks and reports bus delimiters in logical and physical libraries

-bus_delimiter



Types of Checks Currently AvailableNumber Checks performed ( Physical Library checks ) Option

1 Cell view vs. FRAM view in reference library with missing views and mismatched views (e.g. earlier FRAM views)

reported

-view_comparison

-antenna2 Missing antenna property for cells and antenna rules in the layers,

Missing signal EM rule -signal_em

3 Cells with identical names in different reference libraries withnames of cells reported

-same_name_cell

4 Report boundaries for (macro) cells, rectilinear or rectangular, and coordinates

-rectilinear_cell

5 Check and report physical properties (e.g. pin types, cell symmetry, preferred routing direction, tile pattern,

pr_boundary, and wire_track)

-phys_property {place route cell}



Types of Checks Currently AvailableNumber Checks performed ( Physical Library Checks ) Option

6 Report physical only cells (filler cells with and without metal,diode cells with antenna props, and corner cells)

-physical_only_cell

7 TF consistency check enhancement between main and reference libraries

-tech_consistency

8 technology data quality for a single library (from cmCheckLibrary)

-tech

9 DRC checks for library cells (FRAM view) (from cmCheckLibrary)

-drc

10 Routeability: physical pin access (pin on tracks) -routeability



check_library

•check_library -mw_library_name{phys_library_name_list} -logic_library_name{logical_library_name_list} –cell_list{cell_list}

• Where-mw_library_name {phys_library_names}• Specifies Milkyway Reference library names to be checked. If not specified,

the reference libraries used in the current design will be checked-logic_library_name {logical_library_names}• Specifies one or more logical library names (filenames) to be checked. If

not specified link libraries used in the current design will be checked-cell_list {cell_list}• Specifies a list of cell names that should be checked. If not specified all the

cells in the libraries will be checked.



set_check_library_options

• You should set_check_library_options before running check_library command if you want to check specific options

• If you don’t set any options using set_check_library_options the default behavior is to check for missing cells and pins and mismatched pins

• In addition to the options mentioned in the tables there are 4 other options:

•set_check_library_options[-physical][-logic_vs_physical][-reset][-all]



Thank You



Appendix

• Timing Budgeting Flow• Block Box Flow • Auto Orientation of Relative Placement Blocks• Relative Placement – Keep out GUI support• Relative Placement – size_only flows for clock_opt & place_opt

• Scan Wire Length Reduction• Binary Scan DEF flow (Beta)• AHFS User Interface Update



“import_fp_black_boxes” generates separate cel view for black box modules• Black box cel view is used for shaping, pin assigment, floorplan pushdown etc

get_cells with black box filters• First level filter

"is_logical_black_box==true”Filter out black box before “import_fp_black_boxes”

“is_pyhsical_black_box==true”Filter out black box after “import_fp_black_boxes”

• Second level filter“black_box_type==Empty““black_box_type==Missing”“black_box_type==Tie-Off”“black_box_type==Feedthru”“black_box_type==DF”

Example:• [get_cells -hier -filter "is_logical_black_box==true && black_box_type==Empty"]

Timing-Driven Black Box Flow: Identifying Black Box



Relative Placement Keep Out GUI Support• Overview

Request from customers to have the relative placement (RP) keepout displayed in GUI layout window

• Usage/GUIAdded under “RP Keepout” in the layout “View Setting” toolbarDisplayed in layout windowDisplayed in relative placement hierarchy view window

• User BenefitEnable users to check the quality of keep out creation and placementEnable users to manipulate the RP keepouts during RP placement and optimization via GUI



Relative Placement Keep Out GUI Support

• Layout window: Three keepouts placed inside a RP group

Use these arrows to browse the

three RP keepouts



Relative Placement Keep Out GUI Support

• Relative placement hierarchy view window: Two keepouts placed in the RP group Oprnd_B_reg

Keepout placed at column0 row3 Keepout placed next to

RP cell at column0 row1



Auto-Orientation of RP Blocks

• OverviewTo enable the coarse placer to have more control to orient the relative placement groups according to data flowBefore 2007.12, RP columns are always placed from left to right (i.e. RP group orientation = N)

• This may result in longer wire length if data flow is from right to leftIn 2007.12, RP columns can be placed starting from the last column to the first (i.e. RP group orientation = FN)

• Result in shorter wire length if data flow is from right to leftBy default, orientation is automatically selected to minimize wire length



Auto-Orientation of Relative Placement Blocks

set_rp_group_options[all_rp_groups] –orient N

set_rp_group_options [all_rp_groups] –orient FN

RP group orientations versus data flow



Auto-Orientation of Relative Placement Blocks

• User BenefitQoR changes with data flow

• Left to right: no change• Right to left: 5% better

Runtime impact is within 1%



Size-Only Flows For clock_opt, route_opt

• OverviewCurrent implementation in the RP flow to preserve the RP structures

• Fixes the RP cells in clock_opt and route_opt• Restricts optimizer from further optimizing the design

This feature enables sizing after place_opt in addition to the fixed_placement option

• Changes to set_rp_group_options and create_rp_group commands

• Added size_only for -cts_option• Added in_place_size_only for -route_opt_option

• User BenefitQoR improvement expected within 5% with a 1% runtime/memory hit




• Sample script for size_only in clock_optsource setup.tcl

# create RP groups and constraints for placement & synthesis

source rp.tcl# avoid RP cells being removed during place_opt by set_size_only

set_size_only [rp_group_references -leaf]

place_opt# check if there is any RP violationcheck_rp_groups -all# allow size_only in clock_optset_rp_group_options [all_rp_groups] -cts_option size_only

clock_optcheck_rp_group –all

# check RP placement result in GUIGUI_start




• Sample script for in_place_size_only in route_opt

# set up design...# create RP groupssource rp.tcl# avoid RP cells being removed during place_optset_size_only [rp_group_references -leaf]place_opt

set_rp_group_options [all_rp_groups] \# allow size_only in clock_opt and in_place_size_only for route_opt -cts_option size_only \

-route_opt_option in_place_size_onlyclock_optcheck_rp_group -allroute_optcheck_rp_group -all




• Known Limitationsize_only for -cts_option of set_rp_group_options and create_rp_group commands applies only to clock_opt core command but not to atomic commands •optimize_clock_tree

•compile_clock_tree



Scan Wire Length Reduction

• OverviewSome design types cause the current scan chain repartitioning algorithm to have scan wire length increase.No reordering done if repartitioning + reordering has wire length increase.In 2007.12, optimize_dft (in place_opt flow) will now attempt reordering alone if repartitioning + reordering does not produce scan wire length reduction.

• User InterfaceNo user interface or flow change. Feature enabled by default

• User BenefitAutomatically obtains scan wire length reduction on designs which previously did not have any reduction.Customers had to manually remove PARTITION labels to accomplish this previously. This is no longer required



IC Compiler-RM Roadmap Update

Placement and Placement based optimization

CTS and post CTS optimization

Routing and post route optimization including SI

ChipfinishingCell/metal filler, antenna, CAA

Signoff driven closure with Star-RCXT/PrimeTime SI

Flat Design PlanningFloorplan Exploration

2007.12TT

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2007.12 –SP1 2007.12 –SP2

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Thank You

Documents

2007 12 ICC Incremental Training