2009 Wang 60GHz Phased Array

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 10, OCTOBER 2009 2341

A 60-GHz Phased Array Receiver Front-End in0.13-�m CMOS Technology

Chao-Shiun Wang, Member, IEEE, Juin-Wei Huang, Kun-Da Chu, and Chorng-Kuang Wang, Fellow, IEEE

Abstract—This paper presents a fully integrated dual-antennaphased-array RF front-end receiver architecture for 60-GHzbroadband wireless applications. It contains two differentialreceiver chains, each receiver path consists of an on-chip balun, a� -boosted current-reuse low-noise amplifier (LNA), a sub-har-monic dual-gate down-conversion mixer, an IF mixer, and abaseband gain stage. An active all-pass filter is employed to adjustthe phase shift of each LO signal. Associated with the proposeddual conversion topology, the phase shift of the LO signal can bescaled to one-third. Differential circuitry is adopted to achievegood common-mode rejection. The � -boosted current-reuse dif-ferential LNA mitigates the noise, gain, robustness, stability, andintegration challenges. The sub-harmonic dual-gate down-con-version mixer prevents the third harmonic issue in LO as well.Realized in a 0.13- m 1P8M RF CMOS technology, the chip oc-cupies an active area of 1.1 1.2 mm�. The measured conversiongain and input P1 dB of the single receiver path are 30 dB and�� dBm, respectively. The measured noise figure at 100 MHz

baseband output is around 10 dB. The measured phased arrayin the receiver achieves a total gain of 34.5 dB and theoreticallyimproves the receiver SNR by 4.5 dB. The proposed 60 GHzreceiver dissipates 44 mW from a 1.2 V supply voltage. The wholetwo-channel receiver, including the vector modulator circuits forbuilt-in testing, consumes 93 mW from a 1.2 V supply voltage.

Index Terms—Current-reuse, dual-gate, � -boosting, LNA,MIXER, phase-array, receiver, sub-harmonic.

I. INTRODUCTION

W ITH the 7-GHz unlicensed spectrum around 60 GHzbeing available, increasing interests are drawn in this

band for high data rate wireless consumer applications. Theapplication of 60 GHz nowadays contains high-speed wirelessLAN, and wireless home video and data link that need lots ofbandwidth. The scaling down of CMOS technology, the unitycurrent gain frequency, , in MOSFET can be comparable tothat in III/V technologies. Moreover, CMOS technology fea-tures high integration with digital baseband processing blocks.

Manuscript received February 23, 2009; revised June 21, 2009 and July 24,2009. First published September 09, 2009; current version published September30, 2009. This work was supported by the National Science Council Taiwanunder NSC 97-2220-E-002-022, and by NTU-MediaTek Lab. (MediaTek Inc.).This paper was recommended by Associate Editor S. Mirabbasi.

C.-S. Wang and C.-K. Wang are with the Graduate Institute of Elec-tronics Engineering, National Taiwan University, Taipei, Taiwan 106 (e-mail:[email protected]; [email protected]).

J.-W. Huang was with the Graduate Institute of Electronics Engineering, Na-tional Taiwan University, Taipei, Taiwan 106. He is now with the Novatek Mi-croelectronics Corp., Hsinchu, Taiwan 300.

K.-D. Chu was with the Graduate Institute of Electronics Engineering, Na-tional Taiwan University, Taipei, Taiwan 106, ROC. He is now with the MStarSemiconductor, Inc, Hsinchu, Taiwan 300.

Digital Object Identifier 10.1109/TCSI.2009.2031697

These advantages make 60-GHz CMOS transceiver a promisingoption with the high integration and low cost [1], [2]. However,circuitry processing short wavelength signals suffers from lossyand multi-path channels, which hinders the 60 GHz communi-cations from achieving high SNR performance required by highthroughput system specifications. Many efforts have been fo-cused on phased array systems that directly tackle these defi-ciencies by combining signals along multiple received paths toimprove the receiver SNR and spatial selectivity [3]–[10]. Un-fortunately, as for phased array implementations, phase shiftingand power combining along the RF signal path result in anotherchallenge due to the noise figure degradation.

To deal with these issues described above, this paper adopts afully integrated dual-antenna phased-array receiver architectureperforming phase shifting in the LO path, at 20 GHz instead ofphase shifting in the signal path. It decouples the receiver gainand the LO signal variation and presents an efficient solutionto improving the signal-to-noise ratio (SNR) and spatial diver-sity in phased arrays [3]–[5]. The proposed topology employsan active all-pass filter as an adjustable phase shifter in each LOsignal path, which theoretically increases 3 times the phase shiftrange of each LO signal path. In order to obtain good common-mode performance, such as power supply/common-mode noiserejection, on-chip baluns have been realized to enable differen-tial operation of the active circuits. Each of the receiver chainsperforms single-to-differential transformation in the RF input,down-converts the signal from 60 GHz to 20 GHz IF, and sub-sequently translates the signal to the baseband for combinationand amplification. This phased array RF front-end receiver ar-chitecture features better integration and signal integrity whileconsuming less power.

This paper concerns the design of the differential phase arrayRF front-end receiver. After the description of the receiver ar-chitecture and operation in Section II, the detailed circuit designconsiderations of the building blocks in the 60-GHz receiver arediscussed in Section III. Section IV demonstrates measurementresults of the 60-GHz receiver with on-chip baluns and gives theperformance comparisons with other published works. Finally,the conclusion is drawn in Section V.

II. PHASE-ARRAY RECEIVER ARCHITECTURE

Fig. 1 is the proposed circuit diagram of the dual-antennaphased-array 60 GHz receiver prototype implemented with aphase shifter at each 20-GHz LO stage. By using the secondharmonic of the LO at the RF mixer and the first harmonicat the IF mixer, only a 20-GHz LO is required for this dual-conversion heterodyne receiver that avoids complex frequency

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2342 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 10, OCTOBER 2009

Equation (1).

Fig. 1. Proposed 60-GHz fully differential receiver.

division/multiplication designs [11]. The fully differential re-ceiver architecture can provide good common-mode noise re-jection and power supply variation. As opposed to conventionalphased-array antennas controlled by RF phase shifting, this re-ceiver architecture employs an LO phase shifting, which alle-viates the receiver gain degradation due to the LO signal vari-ation. In addition, the loss in the LO phase shifting networkscan be easily compensated by high gain amplifiers without anyamplitude control.

The conventional active phase shift has limited phase shiftand a phase response which varies with frequency [12]. Theproposed frequency plan, as shown in Fig. 2, assists to extendthe phase shifting range and adjust the relative phase difference,which is very critical in phase-shifting network. Assuming theoutput phase of the mixer is a linear combination of its inputphases and the high order mixing frequency is filtered out, thereceived baseband signal from each receiver path can be de-scribed by equation (1), shown at the top of the page, where

and is the received frequency and the LO frequency,respectively, is the phase difference between the two re-ceived signal, and , are the controlled LO phaseshift signals. The maximum baseband signal will be obtain,

while the is equal to the ). This illus-trates that the relative phase shift difference in LO correspondsto three times the phase shift in the signal itself, which extendsthe phase shift range easily. Thus, it can cover the whole 360of phase shift with the 120 control range of the phase shifter.The constant-amplitude LO signals can be attained by control-ling the resonant network of the phase shifters, which will bedescribed later. Moreover, the polarity of the LO driving buffersare controlled to enlarge the linear phase control range. In gen-eral, the drawback of the all-pass phase shifter is the variationin phase shift with frequency. The differential phase shift con-trolled between the Rx1 and Rx2 was proposed to overcome thisdisadvantage.

In order to realize on-chip differential 60-GHz RF and20-GHz LO signals for better common-mode noise rejectionand power supply variation, on-chip Marchand single-endedto differential (S/D) converters (balun) are integrated with thereceiver circuit for the testing purpose. Due to the fact thatthe conventional passive reactive components are small inmillimeter-wave applications, transmission lines are used inbias networks, impedance matching, and interstage connection.

In order to obtain high quality factor ( ) at 60 GHz, thin-filmmicrostrip (TFMS) configuration is chosen for easy routing andarea saving [1]. The layout of the overall TFMS transmissionlines are verified by EM simulation to guarantee the perfor-mance at 60 GHz.

The front-end is composed of two receiver chains. Each re-ceiver path consists of on-chip baluns, -boosted current-reuselow-noise amplifier (LNA), sub-harmonic dual-gate down con-version mixer, and the second IF mixer. The received signalson each path will be combined at the baseband gain stages. Theproposed circuits are illustrated in the following sections.

III. RECEIVER BUILDING BLOCK DESIGN

A. -Boosted and Current-Reuse LNA

Among the millimeter-wave low-noise amplifier architec-tures, the common-source architecture (CSLNA) with inductivedegeneration and the common-gate architecture (CGLNA) arethe most popular [7], [13]–[15]. The CSLNA has superior noiseperformance for the narrow band application. However, in the

WANG et al.: A 60-GHZ PHASED ARRAY RECEIVER FRONT-END IN 0.13- m CMOS TECHNOLOGY 2343

Fig. 2. Proposed 60-GHz frequency plan.

Fig. 3. � -boosted low noise amplifier.

millimeter-wave applications, it is preferred to use CGLNAtopology for the advantages such as lower power consumption,wide band input matching, lower sensitivity to parasitics andbetter reverse isolation.

To alleviate the higher noise figure in CGLNA, the-boosted technique, as shown in Fig. 3(a), can be ap-

plied to increase the dc gain of a cascode stage [16], [17].As shown, with a negative feedback, , the effectivetransconductance of M1 is increased by a factor ofand then the noise factor is reduced to:

(2)

where and are empirical process- and bias-dependentparameters respectively. In a differential circuit, as shown inFig. 3(b), the cross-coupling signal from the opposite polarityinput can be viewed as the negative feedback:

(3)

where is the coupling capacitor and is the bias resistor.This forms a first order high pass response and indicates6-dB -boost at high frequencies. Another advantage of thecommon-gate differential input stage with -boosting is thatthe input effective transconductance is doubled due to the

capacitive cross-coupling without more current. Fig. 4 showsthe simulated noise performance of CSLNA, CGLNA, and

-boosted LNA, with , and . The ofthe 0.13- m 1P8M RF CMOS technology is around 80 GHz.Therefore, the -boosted LNA is attractive for low noiseperformance for designs above the 40 GHz ( ).

Furthermore, the -boosted LNA architecture can compen-sate for the input phase and amplitude imbalance. As shown inFig. 5(a), the amplifier circuit consists of a common-gate am-plifier and a -boosted amplifier. The superposition method isused to describe the differential output signal transfer function,as shown in

if

(4)

As a derived result, the differential output signal only dependson the device matching between the transistors, M1 and M2 andthe inductances, , , and . The relationship among thephasors of the input signals and output signals can be interpretedin Fig. 5(b). The maximum differential output will be obtained,while the magnitude of the differential input signals is identical,and the phase is opposite. The -boosted circuit also can act asa single-to-differential active balun, if signal is applied single-ended. Thus, the requirement for the differential phase balanceof the received signal can be relaxed.

In order to improve the gain performance of the 60 GHzLNA circuit, the current-reuse technique is also used to reducethe power consumption. Fig. 6 presents the detailed schematic


Fig. 4. Noise figure simulated comparison of the low noise amplifier.

Fig. 5. � -boosted low noise amplifier (a) analysis (b) phasor diagram.

of the -boosted and current reuse LNA comprising twocascaded amplifiers, the pre-amplifier of the -boosted andcommon-source (CS) stages and the post-amplifier of twoCS stages, both of which adopt the current-reuse scheme tominimize the power consumption. The output noise is reducedby the -boosted technique in the pre-amplifying stage, whilethe gain is enhanced via several current-reuse CS stages. Therequired inverting gain in the negative feedback of -boostingtechnique is readily available (with ) in the differentialconfiguration, wherein TL1 and TL2 resonates with the inputnode capacitance at the operating frequency. The implementa-tion of the gain between source and gate is mainly determinedby noise considerations.

The bottom of each amplifier stage acts as the bias current.The outputs of the bottom stage are coupled to the gates ofthe top devices, M3 and M4, through the coupling capacitors,C1 and C2. The sources of M3 and M4 are shorted to providean AC ground. Transmission lines from TL3 to TL6 forma matching network between the two cascoded stages. The

Fig. 6. � -boosted current-reuse low noise amplifier.

Fig. 7. Floorplan of the proposed � -boosted current-reuse low noiseamplifier.

-boosted stage incorporated with a current reuse stage em-ploys higher power efficiency than a conventional single-stagecommon-source LNA (CSLNA) with comparable power gain.

The post-amplifier employs a common-source gain stage cas-coded with a current-reused differential pair. The same as thosein the pre-amplifier, transmission lines from TL9 to TL12 aredesigned for inter stage impedance matching. The rest of thetransmission lines, TL7, TL8, TL13 and TL14, construct thetuned load to resonate with the parasitic capacitances. Fig. 7shows the floor plan of the differential LNA. The folded TSMStransmission lines allow symmetric placement of the active de-vices in close proximity. The lowest metal ground plane is max-imized under the microstrips to provide a good quality factor forthe TFMS transmission line.

Fig. 8 presents the experimental results of -parameter ofLNA test chip, which includes a 5.5 dB loss from the Marchandbalun in front of the LNA to provide single to differential con-version. The LNA is measured on one of the open-drain buffers’outputs while the other output is terminated by 50 . As shown,

and are below dB from 60 GHz to 75 GHz. Thereverse isolation, , is below dB for all desired frequen-cies. The measured is 11 dB, including the 5.5 dB attenua-tion in the input balun and the 6-dB loss in the open-drain output


TABLE IPERFORMANCE SUMMARY OF V-BAND LNA

Fig. 8. Experimental results of �-parameter of V-band LNA.

Fig. 9. Measured noise figure and voltage gain of V-band LNA.

stage. Fig. 9 shows the measured noise figure and voltage gain.Considering the effects of Marchand balun loss and 3 dB lossin the single-ended output, the noise figure of the LNA itselfis dB in the desired frequency band. To demonstratethe real performance of the LNA, the equivalent voltage gainof LNA is calculated [18]. Due to the inaccuracy of the pas-sive and active models, the center frequency of LNA drifts to54 GHz. The equivalent voltage gain is 21 dB at 54 GHz. Themeasured IIP3 is dBm which excludes the 5.5 dB atten-uation from the Marchand balun. The whole differential LNA

Fig. 10. Dual-gate down conversion Mixer.

Fig. 11. Sub-harmonic Dual-gate down conversion Mixer.

circuit draws 6 mA current from a 1.2 V supply voltage. Theproposed -boosted current-reuse LNA achieves a decent gainwhile only occupying an active area of 0.4 0.37 mm . Table Icompares the measured results of this design to those of previ-ously reported 60 GHz LNAs [15], [19]–[21].

B. Sub-Harmonic Dual-Gate Down Conversion Mixer

In the integrated receiver design, DC offsets and LO-RF feed-through during down-conversion are the most critical design is-sues since they cause unwanted DC components degrading thesystem dynamic range. To overcome these challenges, a sub-harmonic mixer is proposed. By choosing the LO as a sub-har-monic of the RF frequency, the sub-harmonic mixer alleviates


Fig. 12. The schematic of the proposed sub-harmonic dual-gate mixer.

the DC offset due the LO-RF feedthrough and the third har-monic conversion of the LO signals.

Fig. 10(a) presents the conventional dual-gate down conver-sion mixer. The dual-gate mixer structure has the advantageof well isolated signal and local oscillator ports, which ismore suitable for millimeter-wave applications [22], [23]. Inthe dual-gate mixer, the LO signal is applied at the gate ofthe upper MOS, M2, as demonstrated in Fig. 10(a), imposinga large bias change on VG2 and also the drain-to-sourcevoltage of the bottom MOS, M1, since the upper MOS actsas a source follower. Hence, the time-varying drain-to-sourcevoltage of bottom MOS varies the transconductance ( ) andalso modulates the power gain to perform frequency conver-sion. Fig. 10(b) shows the simulated transconductance of theM1versus VG2. The gate bias of the bottom MOS, VG1, isdetermined from the tradeoff between the conversion gain andnoise figure, while the gate bias to the upper MOS, VG2, isdecided upon the operating point of the lower MOS.

The dual-gate mixer can be implemented as a sub-harmonicmixing structure. Since the balanced LO input is generally alarge signal, the twice LO frequency signal can be achieved atthe common-source of a differential pair. This 2X frequencytime-varying drain-to-source voltage of bottom MOS varies thetransconductance ( ) and modulates the power gain to pro-vide frequency conversion as well. Therefore, the sub-harmonicmixing with half LO frequency can be achieved, as shown inFig. 11. This configuration can alleviate DC offsets and LO-RFfeedthrough problem, as the even order harmonic will only ap-pear at node Vx.

Fig. 12 shows the circuit diagram of the sub-harmonic dual-gate mixer. The 60 GHz RF signal is mixed down to a 20 GHz IFfrequency by an LO at 20 GHz. Then, the IF signal is down con-verted to baseband by the same LO at 20 GHz. The core of thefirst downconverter in this design is the sub-harmonic dual-gatemixer. To avoid the bandwidth drops due to parasitic capaci-tance seen at the drain of the bottom MOS, which introducesa pole on the order of , a folded cascade configuration is

Fig. 13. The simulated conversion gain of the sub-harmonic dual-gate mixerwith IF amplifier.

chosen as the input stage [13], [14]. The inductors (a microstriptransmission line) of the 2nd stage in LNA are designed to tuneout the parasitic capacitance. The 60 GHz RF is mixed withthe second harmonic of LO at 20 GHz to down convert to 20GHz IF frequencies. The size of the transistors determines thenoise and conversion gain performance of the mixer. Large tran-sistors have smaller on resistance and hence have better noiseperformance.

The IF down converter is also depicted in Fig. 12. The am-plifier output inductor L1 and L2 resonate with the total capaci-tance seen at the node X and Y. Most of the 20-GHz IF signal iscommutated with the same LO at 20 GHz to baseband by M1,M2, M3, and M4.

The simulated conversion gain of the sub-harmonic dual-gatemixer with IF amplifier versus the LO amplitude is shown inFig. 13. According the simulation results, the SSB noise figurefalls to about 11.7 dB and the IIP3 rises to dBm. The mixercore with IF amplifier consumes 2.4 mA from a 1.2-V supply.


Fig. 14. All-pass active phase shifter circuit.

C. Active All-Pass Phase Shifter

A variety of different techniques for phase shifting have beenreported, such as switched high-pass (HP)/low-pass (LP) phaseshifter, reflective-type phase shifter, vector modulator, tunableall-pass phase shifter, and distributed phase shifter. In order toobtain a compact and relatively simple design among the mostimportant techniques, the tunable all-pass filter (TAPF) phaseshifter implementation is chosen for this work [12], [24], [25].Although the tunable all-pass filter is an active circuit and hashigh noise-figure, by performing phase shift along the LO paths,the receiver noise performance is no longer sensitive to the LOsignal disturbance and high NF of phase shifter.

The active phase shifter circuit, shown in Fig. 14, exploitsthe all-pass network characteristics of the variable LC resonantcircuits. A common-source stage (M1) is shunt fed back by aparallel LC resonant circuit comprising an inductor (L1), andcapacitors (with varactors, C1, C2) for the active all-pass filter.In order to provide sufficient gain at the 20 GHz, the cascodestage (M2) and the shunt inductor (LO1, LO2) are introducedto improve the isolation and resonate out the parasitic capaci-tors at the output node. In addition, another common-source cas-code amplifier (M3, M4 or M5, M6) is connected to this circuitoutput as the polarity-controlled LO driving buffer. The positiveor negative LO output signal can be obtained via the control sig-nals (EN, EN). It is equivalent doubling the linear phase controlrange of the active all-pass filter from 120 to . Practi-cally, the phase of the active phase shifter can be changed withconstant amplitude by varying the capacitance (C2) of the reso-nant circuit (L1, C1 and C2). The voltage transfer function of thethird-order all-pass phase shifter can be expressed as following:

(5)

The phase characteristics can be shown as

where (6)

where is the LO signal frequency. The capacitance ratio be-tween and is constant, since identical devices are chosen.If of is varied, the phase of output signal will be changed inan almost linear fashion. Thus, only one control voltage ( ) inthe phase shifter is needed. As mentioned previously, the vari-ation of phase shift is also determined by the frequency . Thedifferential phase shift controlled between Rx1 and Rx2 wasproposed to overcome this problem.

The simulated phase diagram and the gain variation of thethird order all-pass filter are shown in Fig. 15. The simulationshows that the phase will be changed with the amplitude byvarying the capacitance of the resonant circuit. However, with alarge LO signal swing at the LO ports of the mixers, the sensi-tivity of the mixer gain to the LO signal amplitude is rather low.

D. LO Buffers and Baseband Combiner

The LO buffers are differential pairs with inductive loads. TheMarchand baluns are also implemented for signal coupling andimpedance matching in the LO signals.

The baseband output buffers consist of a simple differentialpair followed by open-drain common-source devices used todrive 50 instrumentation. It also acts as a combiner for thebaseband signals from two receiver paths. The targeted voltagegain is about 10 dB to ensure the receiver output noise over-whelms the noise floor of spectrum analyzers and noise figuremeters. Delivering a high voltage swing to a 50- load, each ofthe open-drain common-source devices consumes only 5 mA.


Fig. 15. Simulated all-pass active phase shifter circuit.

Fig. 16. Baseband Combiner circuit.

Fig. 17. Die micrograph.

IV. EXPERIMENTAL RESULTS

Fig. 17 shows the die micrograph of the dual-channel phasedarray receiver which is implemented in a 0.13 m RF CMOSprocess. The folded TFMS transmission lines are chosen forbias network, impedance matching, and interstage connectionin the LNA. The lowest metal ground plane is maximized underthe microstrips to attain good quality factors of the TFMS trans-mission line. The proposed -boosted current-reuse LNA

Fig. 18. Design of on-chip Marchand balun.

Fig. 19. Measured amplitude/phase imbalances for the balun test circuit.

circuit consumes only 7.2 mW. In each channel, the 60 GHzfront-end dissipates 44 mW from a 1.2-V supply voltage. Theoverall dual-channel receiver including the vector modulatorcircuits for built-in testing consumes 93 mW from a 1.2-Vsupply voltage and occupies 1.1 1.2 mm of die area.

Reducing the form factor, on-chip balun offers capabilities ofhigh integration and causes less parasitic effects due to shorterinterconnections to devices. For high tolerance of process vari-ations, a wideband, passive Marchand-type balun is used [26],[27]. Fig. 18 shows the simplified transmission line configu-ration and the physical layout of the on-chip Marchand balun.The vertically stacked on-chip spiral transformers are adoptedto achieve high mutual coupling factor. For further reducing thesubstrate loss, the balun coils are routed on top of two metallayers. The shape of the balun is optimized to reducing occu-pied area and minimizing the distance between the differentialports. The characteristic impedance of the two upper metal stripsdominates the impedance ratio between the unbalance port andthe balance ports.

The port reduction method is employed to extract thethree-port S-parameters [28]. The measured insertion loss andamplitude/phase imbalances for the Marchand balun test circuitversus frequency are plotted in Fig. 19. Around 60 GHz, themeasured values of and are dB and dBrespectively. This large bandwidth indicates a good broadbandamplitude balance. The measured phase difference at 60 GHzbetween the differential outputs is 187 . This leads to a phaseimbalance of 7.0 . The on-chip balun achieves a phase im-balance of less than 10 over a broadband frequency range of50-70 GHz.


Fig. 20. Set up for testing (a) single channel and (b) dual channels receiver.

Fig. 21. Measured output power and conversion gain.

On-wafer measurements were made on the single channel re-ceiver and the full dual channel phase array receiver. Fig. 20(a)shows the test setup for a single channel receiver while otherchannels are not active. In order to generate 60-GHz signals with

Fig. 22. Measured conversion gain and noise figure versus frequency.

different phases for the dual-channel array testing, the vectormodulator circuits, shown in Fig. 20(b), are also implementedon the receiver chip. The received signal (Rx2) is generated bytwo signal paths with a phase offset of 90 from the on-chipvector modulators. Every desired phase within the 360 phasecontrol range can be obtained by weighting the amplitudes of


TABLE IIPERFORMANCE SUMMARY AND COMPARISON OF PHASED ARRAY RECEIVER CHIPS.

Fig. 23. Measured conversion gain versus different LO phase shift.

these phase paths. The output amplitude of the amplifiers can beset by analog control voltages of each VGA circuit. The outputmatching network of the built-in test circuitry is designed tomatch 50 . Before the phase-array receiver is measured, thereceived signal (Rx2) of the vector modulator circuits is cali-brated by the vector network analyzer (VNA).

The measured performances of each channel are slightly dif-ferent due to the layout mismatch. The input referred compres-sion point in each single channel receiver measured at the peakfrequency, 61 GHz, is dBm, as shown in Fig. 21. Fig. 22demonstrates the measured conversion gain with a peak of 30dB at 61 GHz and a 3 dB bandwidth of 4 GHz. The noise figureis around 10 dB, which is measured by the noise meter at the100 MHz baseband output. The pads and the on-chip Machand

balun are de-embedded. Fig. 23 shows the measured conversiongains for different LO phase shift. The gain error for all phasestates of Rx1 and Rx2 is less than 1.5 dB at 61 GHz.

Fig. 24 shows the normalized array gain as a function ofsignal incident angle at two different LO-phase settings for thedual-channel operation. The synthesized array pattern for a2-element array is based on the measured conversion gain withall coupling effects. It clearly demonstrates the programmablespatial selectivity of the phased-array receiver and can beextended to multi-channel receiver application. The measureddual-channel receiver patterns for a few angles of radiation/in-cidence are generated by the on-chip vector modulator circuits.A close match between the measured and the simulated arraypatterns is observed. The phased array in the receiver achievesa total voltage gain of 34.5 dB and theoretically improves thereceiver SNR by 4.5 dB [3]. The SNR performance degradationis caused by the phase mismatch between the two receiverchannels. Table II summarizes the measured performance andthe comparison of the receiver chip with data found in literature.

V. CONCLUSION

A fully integrated 0.13 m CMOS dual-antenna phased-arrayRF front-end receiver for 60-GHz broadband wireless appli-cations was demonstrated. Active all-pass filters as adjustablephase shifters are integrated on-chip. To desensitize the receiverSNR degradation upon the phase shifting and power combiningalong the RF path, this architecture exhibits a measured SNRimprovement of 4.5 dB with an overall measured gain of 34.5dB. In order to attain better common-mode noise rejection,the receiver front-end employs fully differential architectureenabled by the on-chip buluns. The proposed -boosted


Fig. 24. Measured dual-channel receiver patterns.

current-reuse LNA circuit with a low power consumption of7.2 mW mitigates the noise, gain, robustness, stability, andintegration challenges. The sub-harmonic dual-gate down con-version mixer mitigates the problem of the third harmonic ofthe LO as well. An active all-pass filter is employed to adjustthe phase shift of each LO signal. Associated with the proposeddual conversion topology, the phase shift of the LO signal canbe reduced to one-third. The measured conversion gain and theinput dB of the proposed receiver are 30 dB and dBm,respectively. The measured noise figure at 100 MHz basebandoutput is around 10 dB. In each channel, the 60 GHz front-enddissipates 44 mW from a 1.2 V supply voltage. Includingthe vector modulator circuits for on-chip testing, the overallfabricated dual-channel receiver consumes 93 mW. The chipsare in the 0.13 m standard CMOS RF process. All circuits,including the on-chip baluns, are integrated on a single chipand occupy a die area of 1.1 1.2 mm . The proposed receiveris available to integration while consuming lower power.

ACKNOWLEDGMENT

The authors would like to acknowledge Chip ImplementationCenter (CIC) for chip fabrication. They also thank High Fre-quency Testing Center (HFTC) NDL on chip measurement. Oneof the authors, C.-S. Wang, is grateful to W.-C. Li, Dr. C.-C. Lin,and Dr. M. A. Sanduleanu for valuable comments.

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Chao-Shiun-Wang (M’04) received the B.S.E.E.and the M.S.E.E. degrees from the National CentralUniversity, Chung-Li, Taiwan, in 1997 and 1999,respectively.

From 1999 to 2004, he was with SoC TechnologyCenter of ITRI, Hsinchu, Taiwan, working onCMOS RFIC design. Currently, he is a Co-operationDesign Engineer at the IBM T.J. Watson ResearchCenter, Yorktown Heights, NY, where he workedon integrated circuits for high-frequency wirelessreceivers. He is working toward the Ph.D. degree in

electrical engineering at the National Taiwan University, Taiwan. His researchinterests are in CMOS RF design, low power and high-speed analog integratedcircuit design.

Juin-Wei Huang was born in Taipei, Taiwan, in1982. He received the B.S. degree in electricalengineering from National Central University,Chugng-Li, Taiwan, in 2004 and the M.S. degreein electrical engineering from National TaiwanUniversity, Taipei, Taiwan, in 2007. His researchfocused on millimeter-wave CMOS circuit design.

He is currently with Novatek Inc., HsinChu,Taiwan, where he is engaged in the developmentof low-cost LCD driver ICs for mobile deviceapplications.

Kun-Da Chu was born in Taipei, Taiwan, in 1982.He received the B.S. degree in electronic engineeringfrom National Taiwan University of Science andTechnology, Taipei, Taiwan, in 2005, and M.S. de-gree in electrical engineering from National TaiwanUniversity, Taipei, Taiwan, in 2008, respectively.

He is currently with the MStar Semiconductor Inc.,Hsinchu, Taiwan. His research interests include wire-less communication and millimeter-wave circuits.

Chorng-Kuang Wang (M’90–SM’00–F’08) wasborn in Taiwan in 1947. He received the B.S. degreein electronic engineering from National Chiao TungUniversity and the M.S. degree in Geophysics fromNational Central University, Taiwan in 1970 and1973, respectively, and the M.S. and Ph.D. degreesin electrical engineering and computer Science fromthe University of California, Berkeley, in 1979 and1986, respectively, where he worked on MOS analogintegrated circuits using scaled technologies.

He has held industrial positions with Itron inTaiwan (1973–1977), National Semiconductor, Rockwell and IBM in Cal-ifornia (1979–1991), where he was involved in the development of CMOSmemory, data modems and disk-drive integrated circuits. He acted as a con-sultant to the Computer & Communication Research Lab of the IndustrialTechnology Research Institute (1991–2000) and an advisor to the Ministry ofEducation Advisory Office (1997–2001) in Taiwan. From 1991 to 1998, he waswith the Department of Electrical Engineering, National Central Universityin Taiwan, where he was a Professor. Thereafter, he has been a professor ofthe Department of Electrical Engineering in National Taiwan University. Hisresearch interests are in the areas of wireless transceiver system and circuitdesign, high-speed data link circuits, mm-wave CMOS development, andflexible electronics.

Prof. . Wang has been involved in chairing and launching programs fortechnical and executive committees of AP-ASIC, A-SSCC and ISSCC. Hecurrently serves as an ex-officio member of the SSCS AdCom, and memberof IEEE Donald O. Pederson Award in Solid-State Circuits Committee. Heawarded IEEE Fellow in 2008 for contributions to communications circuitdesign and for leadership in promoting the profession.

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2009 Wang 60GHz Phased Array