2011_Advanced Technology for High Performance & Low Power Applications

8/3/2019 2011_Advanced Technology for High Performance & Low Power Applications

1/12

Advanced Technology for HighPerformance & Low PowerApplications


2/12

High Performance Applications

OverviewTSMC provides the foundry segment's leading advanced process technologies and design collaterals for high performance

application. We provide the optimal combination of gate density, speed, and power making them ideal for a broad range of

computing, wired communications and consumer electronics applications. Each node is a robust easy-to-port platform for

SoC designs featuring both TSMC internal macros and the segment's largest third party IP and library portfolio.

TSMC advanced technology is significantly ahead of the ITRS roadmap. The company delivers a new advanced technology

generation every two years. Each node is usually half the area of the previous one with a 30% to 50% performance increase

at similar leakage levels. TSMC provides substantial capacity by ramping the same node at multiple 300mm GIGAFABsTM .

40nm TechnologyTSMC's 40nm technology is the foundry's first and offers many advanced features. A combination of 193nm immersion

photo-lithography and extreme low-k (ELK) material brings product to the next level. More than 500 million transistors easily

fit into 70mm2 die area thanks to ultra-high gate density and ultra-high density (UHD) 6T SRAM cell. SRAM size is about half

of that of 65nm.

65GP55GP40G 85G 80GC 90G90GT

1.0V1.0V0.9V 1.0V 1.0V

V(uLVt)

1.0V1.2V

HVt

SVt

LVt

1.5V

1.8V

2.5V

3.3V

HD

HC

HDDP

HCDP

High Density

High Performance

2X Pitch Top Metal

Low Resistance Top Metal

PerformanceDriven

0.13/0.11m

90/80nm

RF Design Support

for High Bitrate

High Density

Memory Feature

CLN65GP CLN40G

CLN55GP

CRN65GP CRN40GP

CLN65GPeDRAM

CLN40GeDRAM

2007 2008 2009 2010 2011

2.35XGate density

*Left edge of each box represents risk production schedule.

Vdd

Core Device

I/O Device

SRAM

BEOL

Available Under drive Over drive


3/12

65nm TechnologyThe 65nm process offers cost-effective benefits superior to the 90nm node. It features twice the 90nm gate density and

boasts a speed improvement of between 30 to 50 percent. The 65nm process also provides a smaller SRAM cell and

reduces power with a multiple Vt architecture and other process innovation.

TSMC's 65nm high performance process has a gate density of around 854 K gate/mm2, based on TSMC's standard cell

library. SRAM cells range from 0.499-micons2 (6T) to 1.158 micons2 (8T/10T).


4/12

High Performance Applications

Mixed Signal/RFTSMC's fully logic-compatible mixed signal/RF technology features:

High Q inductor on both copper and aluminum thick-top metalHigh density MiM capacitors for 65nm and aboveMetal fringe capacitors (MoM)Precision poly transistorsA deep N-well for noise immunityMultiple Vt devices for selective circuit performance

Varactors with large tuning range

TSMC is the mixed signal/RF foundry leaders, having shipped millions of mixed-signal/RF wafers covering a wide range of

communications, computing and consumer electronics applications.

When speed and performance are a must, TSMC's advanced 65nm and 45nm mixed signal/RF technologies empower

designs. Outstanding Ft and low noise parameters satisfy most commercial applications. While providing a general-purpose

(GP/GS) version, TSMC also provides a low power (LP) version for the appropriate balance on a tight power budget.

The process design kit (PDK) is the cornerstone of all mixed-signal/RF designs. TSMC's PDKs are manufacturing-optimized,

simulated with TSMC's SPICE model, checked with thorough technology files, and re-simulated with accurate layout parastic

extraction models. In addition, TSMC has partnered with industry leading EDA suppliers to deliver a robust mixed-signal/RF

portfolio.

Convergence of wired communication and computing devices

TechnologyAdvancement

High Performance

Wired Communication Computing Consumer Wireless Communication


5/12

Low Power Process Technology

OverviewTSMC's low power process technology family is in full production and represents the foundry segment's most advanced

processes technologies. The processes are ideal for highly integrated, cost-effective, very low power devices targeted at a

wide variety of applications.

The low power advanced technologies place TSMC significantly ahead of the ITRS roadmap and continue the company's

track record of delivering a new advanced technology generation approximately every two years. Each node reduces area by

nearly half and improves performance by 30 to 50 percent while maintaining power leakage levels.

TSMC also provides a half-node process technology that achieves a more than 20 percent increase in gross die with thesame defect density as the full node.

The 45/40nm Technology FamilyTSMC's 45/40nm technology family features 193nm immersion photo-lithography manufacturing and extreme low-k (ELK)

material to take your products to the next level.

The 40nm process, although using half-node design rules, is a full-node technology, with full IP ecosystem support. It

provides 2.35 times more standard cell raw gate density than the 65nm process. The 40nm low power (LP) processes

reached first wafers out status and completed product qualification in October 2008. The 40LP processes offer a full range of

mixed-signal/RF options, along with embedded memory to support a broad range of analogy/RF-intensive and memory-rich

applications.

The 40LP process targets low-power applications including cellular base band, application processors, portable consumer

and wireless connectivity devices. It provides the best shrink value.

Each process supports low, standard, and high Vt options. The average 40LP operating voltage is 1.1V volts with a 1.26V

Vdd maximum. The SRAM cell size is about half that of the 65nm process technology. The high density SRAM 0.242m2 cell

is the smallest available in the 45/40nm generation.

TSMC's 40nm technology features a choice of metal schemes. The high density (HD) scheme includes M1, Mx, and Mz. Thehigh performance (HPF) scheme includes M1, Mx, My, and Mz. My can also be used for the top metal in the 2XTM scheme.

TSMC can increase top metal thickness to provide a lower resistance Mr layer. There are 10 copper layers and one aluminum

pad layer available, regardless of the selected metal scheme. The aluminum pad layer can also be used for power and

ground routing to further reduce IR drop or chip size.

40LPG

LP G40LP 55LP 65LP 0.13LP90LP

0.9V1.1V1.1V 1.2V 1.2V 1.5V1.2V

HVt

SVt

LVt

1.8V

2.5V

3.3V

High Density

High Current

Dual-Port

Vdd Nominal

Core Device

I/O Device

SRAM


6/12

Design EcoSystemTSMC's design infrastructure is a comprehensive ecosystem that encompasses all critical IC implementation areas to reduce

design barriers and improve first-time silicon success. The ecosystem includes:

The foundry segment's largest and most complete silicon-proven IP and library portfolioAn advanced design methodology delivery through reference flows, design for manufacturing, and process design kitsComprehensive design ecosystem alliance programs covering market-leading EDA, library and IP, and design services

suppliers

The IP/Library Alliance is the segment's largest and most comprehensive catalog of silicon-verified, production-proven IPand process-specific libraries. IP cores are validated in TSMC silicon through our CyberShuttleTM prototyping service,

providing the best design experience, easiest design reuse, and fastest integration.

The EDA Alliance, consisting of leading electronic design automation companies, provides a comprehensive set of process

technology files and PDKs that simplify the design process. Selected alliance members work closely with our design

technology services teams to implement TSMC's design methodology and Reference Flows. Through the Alliance, EDA

companies gain access to TSMC's technical insights to validate their tools and methodologies. TSMC supports the industry's

most popular design and verification tools with technology files posted on TSMC-Online. These tech files are kept current

with optimal accuracy through the cooperation of EDA Alliance members.

The Design Center Alliance (DCA) is a global network of experienced, qualified IC design centers that brings design ideas

from concept to finished product. TSMC's DCA provides a wide range of IC implementation services. The Alliance's

combined service capability and capacity dramatically reduce design, manufacturing, and schedule risks.

DFMTSMC created the foundry segment's first Design for Manufacturing (DFM) initiative through a careful, detailed compilation

of manufacturing data. It delivers a competitive edge to designs produced in TSMC's fabs. DFM produces more good die per

wafer through the application of manufacturing-related information in the design implementation stage. TSMC provides

DFM Data Kits (DDKs) and tool-specific utilities to enhance yields and accelerate time-to-volume. TSMC also makes available

its own internal expertise and resources to address design-specific DFM improvements before tape out.

TSMC delivers its Design for Manufacturing services through a Desktop Approach and number of services options. The

Desktop Approach is delivered by qualified third-party EDA and IP companies, as well as by TSMC, through the TSMC DFM

Toolkit. The DFM Toolkit includes comprehensive data and utilities for design implementation, with up-to-date DFM

advisories that provide descriptive guides and DDKs. The DFM service options extend TSMC's expertise to the design

community. Service options include lithographic process checking (LPC), chemical mechanical polishing effect simulation

(CMP), and yield sensitivity analysis (YSA). Designers can implement these services through either TSMC-qualified tools or

through TSMC's professional services.


7/12


Reference Flow

TSMC introduced the foundry segment's first Reference Flow in 2001. Since then, the company has established Reference

Flow as a foundry design service standard and continues to enhance its capabilities. The result is a comprehensive design

flow portfolio, featuring eight consecutive releases targeted to a broad range of TSMC's advanced technologies.


8/12

65nm TechnologyTSMC's 65nm process offers superior cost-performance benefits, doubling the 90nm process gate density and boasting a 30

percent speed improvement. The 65nm process supports the foundry segment's smallest SRAM cell and reduces power

through a multiple-Vt architecture and other process innovations.

The 65nm process family includes general purpose (GP), low power (LP), ultra-low power (ULP), and triple-gate oxide (LPG)

options. Each process supports low, standard, and high Vt options. Operating voltages range from 0.9V to 1.32V. I/O

voltages include 1.8V, 2.5V, and 3.3V (5V tolerant). A 5V HVMOS transistor that supports System-on-Chip power

management design has been added to the 65/55 LP process.

The 65nm mixed-signal/RF process is compatible with the logic process and features a complete set of active and passive

devices including resistors, high resistance resistors, MOS varactors, DNW-BJTs, metal fringe capacitors (MoM), and Metal-

Insulator-Metal (MiM) capacitors. The integration of high performance logic functions with reliable mixed-signal features

enhances chip performance and functionality while reducing total material costs. For RF applications, TSMC offers a thick

copper top metal or a logic-compatible top metal layer for high quality inductors. The company also provides a number of

models for high precision analog and RF designs including a mis-matching model, a 1/f noise model, a thermal noise model,

a CMOS RF model, SPICE models and a statistical model. TSMC process design kits (PDKs) provide design infrastructure and

flexibility that shorten design cycle time and, ultimately, time-to-market.

The 65ULP process is another power saving option. The 65ULP and 65LP share the same process but the voltage is reduced

from 1.2V to 1.0V for power saving. Active power and standby power can be reduced to around 66% and 86% respectively

compared to 65LP, but with a 39% speed degradation trade-off. The 65ULP process requires one more mask layer than the

65LP process and has achieved the same D0.

65nm/55nm Tape out Distribution by Application (Cumulative data by 2010/E)

Blu-ray DVD Player---1%

Multi-Project Wafer------3%

Network Processor------2%

PC Chipset------1%

PC Graphics------2%

PLD, FPGA------3%

Printer------1%

Router------2%

Set-top Box------4%

WiMAX------2%

Wireless Base Station------2%

Wireless LAN------6%

Others-----17%

DTV/HDTV--------------9%

Ethernet NIC-----------1%

Ethernet Switch-------9%

Flash Controller-------1%

GPS----------------------1%

Hard Dr ive-------------7%

Mobile Phone-------24%


9/12


55nm TechnologyTSMC's 55nm process is a 90% linear-shrink of the 65nm process. It provides cost savings while maintaining the same

speed at similar or lower power. The 55nm process logic family includes general purpose (GP) and low power (LP) options.

Different from other half node process, 80GC or 0.11G, the 55nm process has no non-shrinkable rule. It means customer

doesn't need to pay effort to modify layout to meet layout rule after shrink if the simulation results shows performance can

meet original target. As with other half-nodes, the 55nm process provides a silicon-based SPICE model. The 55nm process

also provides standard cell, compiler and critical IPs for customer direct design-in. The 55nm technology provides compatible

speed but better power than comparable 65nm processes. The most attractive point is the directly shrink that provides more

than 20% gross die.

55LP Tape out Distribution by Application (Cumulative data by 2010/E)

55nm GP Tape out Distribution by Application (Cumulative data by 2010/E)

Wireless LAN---------16%

xDSL---------------------3%

Bluetooth---------------2%

DTV/HDTV--------------7%

FPD Timing Controller-3%

DTV/HDTV--------------13%

DVD-Video Player------1%Ethernet Hub------------1%Ethernet NIC-------------1%

Ethernet Switch---------7%

FPD Timing Controller-1%

Hard Dr ive--------------20%

Mobile Phone-----------1%

Multi-Project Wafer--12%

Media Tablet------------2%

Mobile Phone------38%

Digital Camera------4%

Network Processor------6%

Others------1%

PC Chipest------2%

PC Graphics------14%

PMP (Protable Media Player) 1%PVR------1%

Set-top Box------3%

SONET/SDH------1%

Wireless Base Station------2%

Blu-ray DVD Player------7%

Multi-Project Wafer------17%

Set-top Box------9%

Ethernet Switch--------3%


10/12

90nm/0.13m

TSMC began 90nm production in its 12-in. state-of-the-art GIGAFABs TM in 2003. More than 600 tape outs for 100

customers been completed using this technology.

TSMC was the first foundry to provide 0.13-micron copper interconnects and 90nm low-k production.

The 0.13-micron process runs in both 8-inch and 12-inch fabs and began production in 2001. TSMC has completed more

than 1,000 tape outs for 140 customers.

90nm BenefitsThe 90nm process family provides numerous advantages over the 0.13-micron process:

Double the gate densityA 35 percent speed increaseA 60 percent improvement in active power savings20 percent interconnect RC improvement

The TSMC's 90nm process is a full-fledged SoC platform that provides both CMOS logic and mixed-signal/RF families.

Embedded memory options include 6T SRAM, electrical fuse, one-time programmable (OTP), multi-time programmable

(MTP), embedded Flash, and Embedded DRAM. The 90nm mixed-signal/RF process features modeling with excellent

accuracy and repeatability and a process design kit (PDK) with the most comprehensive technology files. TSMC began its

Design for Manufacturing (DFM) initiative at the 90nm node. The company also provides reference flows to help create

competitive designs.


11/12


0.13-Micron BenefitsThe 0.13-micron process provides a 40% die size reduction and a 70% speed improvement over the 0.18-micron process.

The 0.11-micron process is a 90 percent linear shrink of the 0.13-micron technology.

The 0.13-micron technology comes with logic process, mixed-signal/RF and embedded memory (6T SRAM, 1T-P, 1T-Q, OTP,

Electrical Fuse), making the technology ideal for a variety of System-on-Chip (SoC) applications.

Collaborate, innovate and grow with TSMCThe trusted technology and capacity provider


12/12

TSMC Headquaters

8, Li-Hsin Rd. 6 Hsinchu Science Park, Hsinchu, Taiwan 300-78

Tel: 886-3-563-6688, Fax: 886-3-563-7000

TSMC North America

2585 Junction Avenue, San Jose, CA 95134, U.S.A.

Tel: 1-408-382-8000, Fax: 1-408-382-8008

TSMC Europe B.V.

World Trade Center (H7), Zuidplein 60 1077 XV, Amsterdam, The Netherlands

Tel: 31-20-305-9900, Fax: 31-20-305-9911

TSMC Japan Limited

21F, Queens Tower C, 2-3-5, Minato Mirai, Nishi-Ku, Yokohama, Kanagawa, 220-6221, Japan

Tel: 81-45-682-0670, Fax: 81-45-682-0673

TSMC (China) Company Limited

4000, Wen Xiang Road, Songjiang, Shanghai, China, Postcode: 201616

Tel: 86-21-5776-8000, Fax: 86-21-5776-2525

TSMC Korea Limited

15F, AnnJay Tower, 718-2, Yeoksam-dong, Gangnam-gu, Seoul 135-080, Korea

Tel: 82-2-2051-1688, Fax: 82-2-2051-1669

TSMC India

1st Floor, Pine Valley, Embassy Golf-Links Business Park, Bangalore560071, India.

Tel: +91-80-4176-8615, Fax: +91-80-4176-4568

Information in this document is subject to change without notice Copyright 2011 Taiwan Semiconductor Manufacturing Company Ltd All rights reserved All trademarks are the property of their respective owners

Documents

2011_Advanced Technology for High Performance & Low Power Applications