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Basic Logic Design with Verilog HDL(Combinational Circuits)
Lecture note ver.1 by Chen-han Tsai
ver.2 by Chih-hao Chao
ver.3 by Xin-Yu Shi
ver.4 by Bo-Yuan Peng
ver.5 by Chieh-Chuan Chiu & Chieh-Chi Kao
Outline
Introduction to Verilog HDL
Syntax in Verilog HDL
Gate-Level Modeling
Test-Bench
Compilation and Simulation Tools
Preview of Lab Questions
2
Introduction to Verilog HDL
What is Verilog HDL?
Why using Hardware Description Language?
Design abstraction: HDL layout by human
Hardware modeling
Reduce cost and time to design hardware
Two Popular HDLs
VHDL
Verilog
4
What is Verilog HDL?
Key features of Verilog
Supports various levels of abstraction
Behavior level
Register transfer level
Gate level
Transistor level
Simulate design functions
5
Different Levels of Abstraction
System
Algorithm
Architecture
Register Transfer Level
Gate Level
Transistor Level 6
Architectural / Algorithmic Level
Implement a design algorithm in high-level language constructs.
Register Transfer Level
Describes the flow of data between registers and how a design process these data.
Different Levels of Abstraction
System
Algorithm
Architecture
Register Transfer Level
Gate Level
Transistor Level 7
Gate Level
Describe the logic gates and the interconnections between them.
Transistor Level
Describe the transistors and the interconnections between them.
Simplified Hardware Design Flow
8
RTL
Editor
Logic
Synthesizer
RTL
Simulation
Gate Level
Simulation
Place & Route
Post Gate
Level
Simulation
Chip
RTL Code
Gate Level Code
Physical Layout
Tape Out
Designer
Level
High
Low
Cost
Low
High
Verilog
Example: 1-bit Multiplexer
9
in1
in2
out
0
1
sel
if (sel==0)
out = in1;
else
out = in2;
out = (selin1) + (selin2)
sel in1 in2 out
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
to select output
Gate Level Description
10
Gate Level: you see only netlist (gates and wires) in the code.
a2
a1
in2
in1
sel
out o1
sel a2_o
a1_o n1
iv_sel
out = (selin1) + (selin2)
Syntax in Verilog HDL
A Simple Verilog Code
12
declaration syntax
module name in/out port
port/wire declaration
kernel hardware gate-connection
Module
Basic building block in Verilog
Module
1. Created by declaration (cant be nested)
2. Used by instantiation
Interface is defined by ports
May contain instances of other modules
All modules run concurrently
13
Instances
A module provides a template from which you can create actual objects.
When a module is invoked, Verilog creates a unique object from the template.
Each object has its own name, variables, parameters and I/O interface.
14
Module Instantiation
15
Adder
Adder Adder
Adder_tree
instance example
Port Connection
Connect module port by order list FA1 fa1(c_o, sum, a, b, c_i);
Connect module port by name (Recommended) Usage: .PortName (NetName)
FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));
Not fully connected FA1 fa3(c_o, , a, b, c_i);
16
Verilog Language Rule
Case sensitive
Identifiers Digits 0123456789
Underscore _
Upper and lower case letters from the alphabet
Terminate statement/declaration with semicolon ;
Comments Single line: // its a single line comment example
Multi-line: /* When the comment exceeds single line, multi-line comment is necessary */
17
Data Type: Register
Register
Keyword: reg, integer, time, real
Event-driven modeling
Storage element (modeling sequential circuit)
Assignment in always block (LHS of expressions)
18
Data Type: Net
Net
Keyword: wire, wand, wor, tri, triand, trior, supply0, supply1
Doesnt store value, just a connection
Input, output and inout ports are default wire
19
Four-valued Logic Value
Nets and registers in Verilog codes hold four-valued data
0 represent a logic 0 or false condition
1 represent a logic 1 or true condition
z
Output of an non-driven tri-state driver High-Z value
Models case where nothing is setting a wires value
x
Models when the simulator cant (doesnt) decide the value un-initialized or unknown logic value
Initial state of registers
A wire is being driven to 0 and 1 simultaneously
Output of a gate with z inputs
20
Logic System
Four values: 0, 1, x/X, z/Z (not case sensitive)
The logic value x denotes an unknown (ambiguous) value
The logic value z denotes a high-impedance value (High-Z value)
Primitives have built-in Logic
Simulators describe 4-value logic
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Logic System: Example
22
a
b
y
0 1
x
a
b
y
x
xx
z
z z z zx x x x
0 1 X Z
0 0 0 0 0
1 0 1 X X
X 0 X X X
Z 0 X X X
Number Representation
Format:
- decimal specification of bits count Default: unsized and machine-dependent but at least 32 bits
- ' followed by arithmetic base of number d or D decimal (default if no base format given)
h or H hexadecimal
o or O octal
b or B binary
- value given in base of base format
_ can be used for reading clarity
x and z are automatically extended
23
Number Representation
Examples: 6b010_111 gives 010111
8b0110 gives 00000110
4bx01 gives xx01
16H3AB gives 0000001110101011
24 gives 00011000
5O36 gives 11110
16Hx gives xxxxxxxxxxxxxxxx
8hz gives zzzzzzzz
24
Net Concatenation
25
3o7
Module A
Module B
Module C
Representations Meanings
{b[3:0], c[2:0]} {b[3], b[2], b[1], b[0], c[2], c[1], c[0]} {a, b[3:0], w} {a, b[3], b[2], b[1], b[0], w} {4{w}} {w, w, w, w}
Operators
Arithmetic Operators
Relational Operators
Equality Operators
Logical Operators
Bit-wise Operators
Unary Reduction
Shift Operators
Conditional Operators
Concatenations
+, -, *, /, %
=
==, !=, ===, !==
!, &&, ||
~, &, |, ^, ~^
&, ~&, |, ~|, ^, ~^
>>,
Operator Examples
27
Excerpts from CIC training course: Verilog_9807.pdf
All bits are 0 logic false
Compiler Directives
'define 'define RAM_SIZE 16
Defining a name and gives a constant value to it.
'include 'include adder.v
Including the entire contents of other verilog source file.
'timescale 'timescale 100ns/1ns
Setting the reference time unit and time precision of your simulation. 28
System Tasks
$finish $finish Terminate the simulation
29
Gate Level Modeling
Gate Level Modeling
Steps
Develop the Boolean function of output
Draw the circuit with logic gates/primitives
Connect gates/primitives with net (usually wire)
HDL: Hardware Description Language
Figure out architecture first, then write code.
31
Primitives
Primitives are modules ready to be instanced Smallest modeling block for simulator Verilog build-in primitive gate
and, or, xor, nand, nor, xnor prim_name #delay inst_name( out0, in0, in1,.... );
not, buf prim_name #delay inst_name( out0, out1, ..., in0);
User defined primitive (UDP) building block defined by designer
32
Case Study: Full Adder
A B
CiCo
S
Full
Adder
Ci A B SCo
0 0 0 00
0 0 1 10
0 1 0 10
0 1 1 01
1 0 0 10
1 0 1 01
1 1 0 01
1 1 1 11
33
Case Study: Full Adder
Co = AB + BCi + CiA
34
A
B
B
CiCiA
Co
Case Study: Full Adder
sum = a b ci
35
a
bc
sum
a
b
csum
Case Study: Full Adder
Full Adder Connection
Instance ins_c from FA_co
Instance ins_s from FA_sum
36
a
bc
sum
a
b
b
c
c
a
co
carry out
connection
sum
connection
full adder
Test-Bench
Test Methodology
Systematically verify the functionality of a model.
Procedure of simulation
Detect syntax violations in source code
Simulate behavior
Monitor results
38
Test Methodology
TestbenchHardware Design
(Design Under Test)
Stimulus
Response
39
Verilog Simulator
40
Testbench for Full Adder
41
module t_full_add(); reg a, b, cin; // for stimulus waveforms wire sum, c_out; FA_gatelevel M1 (sum, c_out, a, b, cin); //DUT initial #200 $finish; // Stopwatch initial begin // Stimulus patterns #10 a = 0; b = 0; cin = 0; // Statements execute in sequence #10 a = 0; b = 1; cin = 0; #10 a = 1; b = 0; cin = 0; #10 a = 1; b = 1; cin = 0; #10 a = 0; b = 0; cin = 1; #10 a = 0; b = 1; cin = 1; #10 a = 1; b = 0; cin = 1; #10 a = 1; b = 1; cin = 1; end endmodule Time Signal
Summary
Design module / DUT Divide-and-Conquer
Partition the whole design into several parts
Architecture figure of each sub-module Make architecture figures before you write Verilog codes
Create hardware design in gate-level or RT-level Connection of sub-modules
Test-bench Feed input data and compare output values at right timing
slots Usually describe in behavioral level Not real hardware, just like software programming (e.g.
C/C++)
42
Note
Verilog is a platform Support hardware design (design module)
Also support C/C++ like coding (test bench)
How to write verilog well? Know basic concepts and syntax
Get a good reference codes (a person or some code files)
Form a good coding style
Hardware Combinational circuits (todays topic)
Sequential circuits (we wont model them in this course) 43
Compilation and Simulation Tools Workstations X-window Verilog-XL and NC-Verilog nWave
Workstations
Why workstations? Multiple Users, multiple tasking
Stable Operations
How to run tasks on the workstations? Operating System: Unix-like
Example: Linux
Example: Solaris
User Interface Text Mode
X-Window
45
Workstations
Where are the workstations?
http://cad.ee.ntu.edu.tw/
You are receiving the account and the password to the workstations.
NOTE: This account expires on 12/30/2011. Answer the lab questions before the expiration date.
If you want to continue enjoying the resources on the workstations, contact the TA managing the IC design Lab to get more information.
Usually you need to attend the Special Projects held by the professors in ICS or EDA group
46
47
48
Workstations
How can I connect to the workstations?
putty download site:
http://www.chiark.greenend.org.uk/~sgtatham/putty/download.html
pietty download site:
http://ntu.csie.org/~piaip/pietty/
MobaXterm download site:
http://mobaxterm.mobatek.net/download.html
In the following examples, we will use MobaXterm.
MobaXterm_v3.2.zip 12.7MB
49
50
ssh user_account@work_station_ip
Ex: ssh [email protected]
51 Account for B99901888 IP address for cad21
Rules of Workstations
1. reboot
2. 1G 5G 10G QUOTA
3.
4.
5.
6.
7. http://cad.ee.ntu.edu.tw 52
Rules of Workstations
943 901
b99901001b99001
r90942001r0942001
:
switch
53
Enter your password 54
Save the password if you want
55
Workstations
Basic instructions
Change Password: passwd
Log out: logout
Show processes: ps (processes and PIDs)
Delete a process: kill -9 PID
56
passwd Change your password 57
ps and kill 58
Workstations
Useful commands
man : manual page
ls : list a folders contents
ls a : list all files (including the hidden files)
ls aux : list all files with detailed information
cp : copy files from one folder/directory to another cp filename1 filename2
cp r : copy the whole folder to another
mkdir : create a folder
pwd : display your current path 59
Workstations
More useful commands cd : Change folder ps : display process status by process identification number and
name kill -9 PID: terminate a running process
kill -9 1234
rm : delete files rm r : remove the whole folder quota v : show disk space tar : pack and compress files
-cvf : for creating compressed file -xvf : for extracting compressed file
mv : move or rename file exit : turn the terminal off logout 60
X-window
Why X-window?
Most important graphic user interface on UNIX and similar system
How to use X-window?
You need an X-window server to use the X-window.
Not an X-window client. An X-window client is a program with GUI that runs on the workstations.
61
X-window
62
Useful program
NotePad ++
Source code editor and Notepad replacement that supports several languages
Running in the MS Windows environment
http://notepad-plus-plus.org/
63
NotePad ++
64
Verilog-XL and NC-verilog
Verilog-XL
Designed by Phil Moorby, the father of verilog
Interpreter of verilog
Designed for syntax checking and simulation
NC-verilog
Designed by Cadence
Inherited from Verilog-XL
In the following examples, we use NC-verilog.
65
Example: Full Adder and its test-bench FA_co.v module FA_co ( co, a, b,
ci );
input a, b, ci;
output co;
wire ab, bc, ca;
and g0( ab, a, b );
and g1( bc, b, ci );
and g2( ca, ci, a );
or g3( co, ab, bc, ca );
endmodule
FA_sum.v module FA_sum ( sum, a, b,
ci );
input a, b, ci;
output sum;
xor g0( sum, a, b, ci );
endmodule
66
Example: Full Adder and its test-bench FA_gatelevel.v module FA_gatelevel ( sum, co, a, b, ci );
input a, b, ci;
output sum, co;
FA_co ins_c( co, a, b, ci );
FA_sum ins_s( sum, a, b, ci );
endmodule
67
Example: Full Adder and its test-bench FA_tb.v module FA_tb();
reg a, b, cin;
wire sum, c_out;
FA_gatelevel fa1 ( sum, c_out, a, b, cin );
initial #200 $finish;
initial begin
#10 a = 0; b = 0; cin = 0;
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
endmodule
68
Remember to source source file before using ncverilog and nWave
source ~cvsd/cvsd.cshrc
source ~cvsd/verdi.cshrc
Example: Full Adder and its test-bench
69
Example: Full Adder and its test-bench How to observe the timing diagram?
$fsdbDumpfile("filename");
$fsdbDumpvars;
nWave (part of debussy)
70
71
ncverilog +access+r
nWave &
72
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74
75
Double-click all of the signals you want to observe
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Preview of Lab Questions
Verilog Lab
The lab questions are due on 12/8/2011
The attendance of verilog lab is counted into grading (included in Participation 2%)
Lab question are available on course website
Information for the verilog lab
Time slots: 11/21~25, 11/28~12/2 18:00~20:30
Registration: Choose the slot you want on the website of EE student association (http://ntuee.org/course/)
80
Verilog Lab Registration
Registration time: 11/4~11/11
Thanks to for the help of registration system!!
81
About Midterm
Check the classroom for midterm on the website
It is different from Quiz1
Submit your HW3 at midterm
Finish your verilog lab registration before midterm!
TA office hour
Time: 6 p.m. to 8p.m
Location: BL-112
HW3: 11/7,8,9
Midterm: 11/8,9,10
82