2015 Euromicro Conference on

Digital System Design (DSD 2015)

Madeira, Portugal26-28 August 2015

IEEE Catalog Number: CFP15291-POD

ISBN: 978-1-4673-8036-2

2015 Euromicro Conference

on Digital System Design

DSD 2015

Table of Contents

Message from the General Chairs xvii

Message from the Program Chairs xviii

Organizing Committee xx

Program Committee xxiii

Additional Reviewers xxix

RECONFIG-1: Reconfigurable Computing (1)

Towards Efficient Field Programmable Pattern Matching Array 1

Vlastimil Kosaf and Jan Korenek

An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy

Broadcast Problem 9

Pedro Vieira dos Santos, Jose Carlos Alves, and Joao Canas Ferreira

ADES: Analysis and Design of Embedded Systems

Worst-Case Throughput Analysis of SDF-Based Parametrized Dataflow 17

Mladen Skelin, Marc Geilen, Francky Catthoor, and Sverre Hendseth

A Scenario-Aware Dataflow Programming Model 25

Reinier van Kampenhout, Sander Stuijk, and Kees Goossens

Integrating Task Migration Capability in Software Tool-Chain for Data-Flow

Applications Mapped on Multi-tiled Architectures 33

Ashraf El-Antably, Nicolas Fournel, and Frederic Rousseau

Hardware Support for Cost-Effective System-Level Protection in Multi-core

SoCs 41

George Kornaros, loannis Christoforakis, Othon Tomoutzoglou,

Dimitrios Bakoyiannis, Kallia Vazakopoulou, Miltos Grammatikakis,

and Antonis Papagrigoriou

V

AIGP: Advanced Image and Graphics Processing

High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA 49

Panu Sjovall, Janne Virtanen, Jarno Vanne, and Timo D. Hamalainen

Accelerating Clifford Algebra Operations Using GPUs and an OpenCL Code

Generator 57

Silvia Franchini, Antonio Gentile, Giorgio Vassallo, and Salvatore Vitabile

Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder

on FPGA 65

Tiago Rodrigues and Mario Vestias

SYNVER: Circuit Synthesis and Verification

Bi-Decomposition Using Boolean Relations 72

Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco,

and Tiziano Villa

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial

EDA Framework 79

Matheus Gibiluka, Matheus Trevisan Moreira, and Ney Laert Vilar Calazans

Automation and Optimization of Coverage-driven Verification 87

Marcela Simkova and Zdenek Kotasek

ASAIT: Architectures and Systems for Automotive and IntelligentTransportation

Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures 95

Matthias Becker, Dakshina Dasari, Vincent Nelis, Moris Behnam,

Luis Miguel Pinho, and Thomas Nolte

Distributed Parallel Computing with Low Cost Microcontrollers for HighPerformance Electric Vehicles 104

Victor Wilson Gongalves Azevedo and Joao Dionisio Barros

EPDSD-1: European Projects in Digital System Design (1)

Harnessing Performance Variability: A HPC-Oriented Application Scenario 111

Giuseppe Massari, Simone Libutti, Antoni Portero, Radim Vavrik,

Stepan Kuchar, Vit Vondrak, Luca Borghese, and William Fornaciari

vi

The AXIOM Software Layers 117

Carlos Alvarez, Eduard Ayguade, Javier Bueno, Antonio Filgueras,

Daniel Jimenez-Gonzalez, Xavier Martorell, Nacho Navarro,

Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Davide Catani,

Claudio Scordino, Paolo Gai, Carlos Segura, Carles Fernandez, David Oro,

Javier Rodriguez Saeta, Pierluigi Passera, Alberto Pomella, Antonio Rizzo,

and Roberto Giorgi

EMC2 a Platform Project on Embedded Microcontrollers in Applications

of Mobility, Industry and the Internet of Things 125

Werner Weber, Alfred Hoess, Frank Oppenheimer, Bernd Koppenhdefer,

Bastijn Vissers, and Bj0rn Nordmoen

FDR: Flexible Digital Radio

A Flexible Research Testbed for C-RAN 131

Diogo Riscado, Jorge Santos, Daniel Dinis, Gustavo Anjos, Daniel Belo,

Nuno Borges Carvalho, and Arnaldo S. R. Oliveira

Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip

Multiprocessor 139

Eren Unlu and Christophe Moy

An Agile and Wideband All-Digital SDR Receiver for 5G Wireless

Communications 146

Andre Prata, Arnaldo S. R. Oliveira, and Nuno Borges Carvalho

EPDSD-2: European Projects in Digital System Design (2)

Enhanced Quality Using Intensive Test and Analysis on Simulators 152

Reda Nouacer, Manel Djemal, Smail Niar, Gilles Mouchard, Nicolas Rapin,

Jean-Pierre Gallois, Philippe Fiani, Frangois Chastrette, Toni Adriano,

and Bryan MacEachen

Playful Supervised Smart Spaces (P3S)—A Framework for Designing,

Implementing and Deploying Multisensory Play Experiences for Children

with Special Needs 158

Giovanni Agosta, Luca Borghese, Carlo Brandolese, Francesco Clasadonte,

William Fornaciari, Franca Garzotto, Mirko Gelsomini, Matteo Grotto,

Cristina Fra, Danny Noferi, and Massimo Valla

ASHWPA-1: Advanced Systems in Healthcare, Wellness, and PersonalAssistance (1)

Implantable MEMS Pressure Sensors Modelling Tool 165

Jose Angel Miguel, David Rivas, Yolanda Lechuga, Miguel Angel Allende,

and Mar Martinez

Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone 173

Alair Dias Junior, Srinivasan Murali, Francisco Rincon, and David Atienza

DTFT-1: Dependability, Testing, and Fault Tolerance in Digital Systems(1)

Reliable and Continuous Measurement of SET Pulse Widths 181

Varadan Savulimedu Veeravalli and Andreas Steininger

Measuring the Distribution of Metastable Upsets over Time 189

Thomas Polzer and Andreas Steininger

Generic Self Repair Architecture with Multiple Fault Handling Capability 197

Marcel Balaz and Stefan Kristofik

A System for Radiation Testing and Physical Fault Injection into the FPGAs

and Other Electronics 205

Tomas Vahat, Jan Pospisil, Filip Krizek, Jozef Ferencei, and Hana Kubatova

ETCS: Emerging Technologies and Circuit Synthesis

Biconditional-BDD Ordering for Autosymmetric Functions 211

Anna Bernasconi, Valentina Ciriani, and Gabriella Trucco

Enhanced Spin-Diode Synthesis Using Logic Sharing 218

Mayler Martins, Felipe Marranghello, Joseph Friedman, Alan Sahakian,

Renato Ribas, and Andre Reis

SDSG-1: System Design for the Smart Grid (1)

A Glimpse of SmartHG Project Test-bed and Communication Infrastructure 225

Vadim Alimguzhin, Federico Mari, Igor Melatti, Enrico Tronci, E. Ebeid,

S. A. Mikkelsen, Rune Hylsberg Jacobsen, Jorn K. Gruber, Barry Hayes,

Francisco Huerta, and Milan Prodanovic

Towards the Use of Pairing-Based Cryptography for Resource-Constrained

Home Area Networks 233

Rune Hylsberg Jacobsen, S0ren Aagaard Mikkelsen, and Niels Holm Rasmussen

Distributed Grid Storage by Ordinary House Heating Variations: A Swiss Case

Study 241

Gilbert Maitre, Gillian Basso, Claudio Steiner, Dominique Gabioud,

and Pierre Roduit

viii

Posters 1

Buffer Allocation for Dynamic Real-Time Streaming Applications Running on

a Multi-processor without Back-Pressure 250

Hrishikesh Salunkhe, Alok Lele, Orlando Moreira, and Kees van Berkel

A Framework for Dynamic Real-Time Reconfiguration 255

Joao Gabriel Reis, Lucas Wanner, and Antonio Augusto Frohlich

Minimization Method of Finite State Machines for Low Power Design 259

Adam Klimowicz, Valery Solov'ev, and Tomasz Grzes

Parameterizable Ethernet Network-on-Chip Architecture on FPGA 263

Helio Fernandes da Cunha Junior, Bruno de Abreu Silva, and Vanderlei Bonato

Dynamic Detection and Mitigation of DMA Races in MPSoCs 267

Selma Saidi and Ylies Falcone

Green Computing: Power Optimisation of VFI-Based Real-Time

Multiprocessor Dataflow Applications 271

Waheed Ahmad, Philip K.F. Holzenspies, Marielle Stoelinga, and Jaco van de Pol

Low-Cost Fault Localization and Error Correction for a Signed Digit Adder

Design Utilizing the Self-Dual Concept 276

Hossein Moradian and Jeong-A Lee

Novel C-Element Based Error Detection and Correction Method Combining

Time and Area Redundancy 280

Jan Belohoubek, Petr Fiser, and Jan Schmidt

Software Fault Tolerance: The Evaluation by Functional Verification 284

Ondrej Cekan, Jakub Podivinsky, and Zdenek Kotasek

A Framework for Comprehensive Automated Evaluation of Concurrent Online

Checkers 288

Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan,

Gert Jervan, and Thomas Hollstein

Safe Drive Map Concept for Road Curve Monitoring 293

Pietro Dell'Acqua, Francesco Bellotti, Riccardo Berta, Alessandro De Gloria,

Gautam Dange, Pratheep Paranthaman, Kay Massow,

and Fabian Maximilian Thiele

Information and Communication Technology Research Opportunities

in Dynamic Charging for Electric Vehicle 297

Oussama Smiai, Francesco Bellotti, Alessandro De Gloria, Riccardo Berta,

Angelos Amditis, Yannis Damousis, and Andrew Winder

Consumer-Centric and Service-Oriented Architecture for the Envisioned

Energy Internet 301

S0ren Aagaard Mikkelsen and Rune Hylsberg Jacobsen

ix

POWER: Power Design

Experimental Evaluation and Modeling of Thermal Phenomena on Mobile

Devices 306

Matteo Ferroni, Alessandro Antonio Nacci, Matteo Turn,

Marco Domenico Santambrogio, and Donatella Sciuto

Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip

Multi-processors 314

Arghavan Asad, Ozcan Ozturk, Mahmood Fathy,

and Mohammad Reza Jahed-Motlagh

RECONFIG-2: Reconfigurable Computing (2)

Automated Design of High Performance Integer Arithmetic Cores on FPGA 322

Ayan Palchaudhuri, Rajat Subhra Chakraborty, and Durga Prasad Sahoo

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture 330

Joao Pinhao, Wilson Jose, Horacio Neto, and Mario Vestias

Computing Framework for Dynamic Integration of Reconfigurable Resources

in a Cloud 337

Oliver Knodel and Rainer G. Spallek

Analysis and Comparison of Attainable Hardware Acceleration in All

Programmable Systems-on-Chip 345

Valery Sklyarov, louliia Skliarova, Joao Silva, and Alexander Sudnitson

TSTVER: Test and Verification

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in

a VLIW Processor 353

Yong Zhao and Hans G. Kerkhoff

Leveraging the Analysis for Invariant Independence in Formal System Models 359

Nils Przigoda, Robert Wille, and Rolf Drechsler

Collision Based Attacks in Practice 367

Ibrahima Diop, Pierre-Yvan Liardet, Yanis Linge, and Philippe Maurine

Verification-Driven Design Across Abstraction Levels: A Case Study 375

Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, and Rolf Drechsler

X

ASHWPA-2: Advanced Systems in Healthcare, Wellness, and Personal

Assistance (2)

A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical

Applications 383

Lang Yang and Thomas W. Chen

A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture

Designed for Evolvability 390

Frangois Patou, Maria Dimaki, Winnie E. Svendsen, Klaus Kjaegaard,

and Jan Madsen

Wireless Sensor Tag and Network for Improved Clinical Triage 399

Joao Ricardo Borges dos Santos, Gabriel Blard,

Arnaldo Silva Rodrigues Oliveira, and Nuno Borges de Carvalho

AHSA-1: Architectures and Hardware for Security Applications (1)

Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based

vs. Physical-Based Approaches in Standard CMOS Technology 407

Duhyun Jeon, Jong Hak Baek, Dong Kyue Kim, and Byong-Deok Choi

Integrated Sensor: A Backdoor for Hardware Trojan Insertions? 415

Xuan Thuy Ng, Zakaria Naj, Shivam Bhasin, Debapriya Basu Roy,

Jean-Luc Danger, and Sylvain Guilley

Side-Channel Leakage Models for RISC Instruction Set Architectures

from Empirical Data 423

Hermann Seuschek and Stefan Rass

Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel

Attack Resistance 431

Apostolos P. Fournaris and Odysseas Koufopavlou

DTFT-2: Dependability, Testing, and Fault Tolerance in Digital Systems(2)

On-Line Device Replacement Techniques for SSD RAID 438

AlistairA. McEwan and Muhammed Ziya Komsul

Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits

Considering Process Variations 445

Mohsen Raji, Behnam Ghavami, and Hossein Pedram

xi

MCSDIA-1: Mixed Criticality System Design, Implementation,and Analysis (1)

Mixed-Criticality Embedded Systems—A Balance Ensuring Partitioningand Performance 453

Michael Paulitsch, Oscar Medina Duarte, Hassen Karray, Kevin Mueller,

Daniel Muench, and Jan Nowotsch

Enabling TDMA Arbitration in the Context of MBPTA 462

Milos Panic, Jaume Abella, Carles Hernandez, Eduardo Quinones,

Theo lingerer, and Francisco J. Cazorla

SDSG-2: System Design for the Smart Grid (2)

SEMIAH: An Aggregator Framework for European Demand Response

Programs 470

Rune Hylsberg Jacobsen, Dominique Gabioud, Gillian Basso, Pierre-Jean Alet,

Armin Ghasem Azar, and Emad Samuel Malki Ebeid

User Flexibility Aware Price Policy Synthesis for Smart Grids 478

Toni Mancini, Federico Mari, Igor Melatti, Ivano Salvo, Enrico Tronci,

Jorn Klaas Gruber, Barry Hayes, Milan Prodanovic, and Lars Elmegaard

An Extensible Simulator for Dynamic Control of Residential Area: Case Study

on Heating Control 486

Gillian Basso, Pierre Ferrez, Dominique Gabioud, and Pierre Roduit

Efficient Clustering of DERs in a Virtual Association for Profit Optimization 494

Vasileios Botsis, Nikolaos Doulamis, Anastasios Doulamis, Prodromos Makris,

and Emmanouel Varvarigos

DHCPS: Design of Heterogeneous Cyber-Physical Systems

Composable Platform-Aware Embedded Control Systems on a Multi-core

Architecture 502

Juan Valencia, Dip Goswami, and Kees Goossens

Low-Cost Software Control-Flow Error Recovery 510

Ghazaleh Nazarian, Razvan Nane, and Georgi N. Gaydadjiev

Network-Aware Virtual Platform for the Verification of Embedded Software

for Communications 518

Alain Pegatoquet, Frangois Verdier, Calypso Barnes, Jean-Marie Cottin,

Enrico Fraccaroli, Stefano Angeleri, and Davide Quaglia

xii

Posters 2

Dataflow Support in x86_64 Multicore Architectures through Small Hardware

Extensions 526

Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero,

and Roberto Giorgi

QEMU-Based Fault Injection for a System-Level Analysis of Software

Countermeasures Against Fault Attacks 530

Andrea Holler, Armin Krieg, Tobias Rauter, Johannes Iber, and Christian Kreiner

White-Box Error Effect Simulation for Assisted Safety Analysis 534

Sebastian Reiter, Alexander Viehl, Oliver Bringmann, and Wolfgang Rosenstiel

A Many-Core Co-Processor for Embedded Parallel Computing on FPGA 539

Wilson Jose, Horacio Neto, and Mario Vestias

Parallel Native-Simulation for Multi-processing Embedded Systems 543

Alejandro Nicolas and Pablo Sanchez

A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan

Detection Applications 547

Paris Kitsos and Artemios G. Voyiatzis

Clockwise Randomization of the Observable Behaviour of Crypto ASICs

to Counter Side Channel Attacks 551

Zoya Dyka, Christian Wittke, and Peter Langendoerfer

CLEFIA Implementation with Full Key Expansion 555

Joao Carlos Bittencourt, Joao Carlos Resende, Wagner Luiz de Oliveira,

and Ricardo Chaves

Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's

Perspective 559

Durga Prasad Sahoo, Rajat Subhra Chakraborty, and Debdeep Mukhopadhyay

Linking the Physical with the Perceptual: Health and Exposure Monitoring

with Cyber-physical Questionnaires 563

Christopher Scaffidi, Laurel Kind, Diana Rohlman, and Kim Anderson

Design for Dependability and Autonomy of a Wearable Cardiac and CoronaryMonitor 567

Jose Machado da Silva, Cristina Oliveira, Bruno Mendes, Ruben Dias,

and Tiago Marques

A Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor 571

Asier Larrucea, Jon Perez, Irune Agirre, Vicent Brocal, and Roman Obermaisser

xiii

ACCEL: Application-Specific Accelerators

An Embedded FTL for SSD RAID 575

AlistairA. McEwan and Irfan Mir

Scalable FPGA Accelerator of the NRM Algorithm for Efficient Stochastic

Simulation of Large-Scale Biochemical Reaction Networks 583

Evangelos Koutsouracfis, George Provelengios, Elias Kouskoumvekakis,

and Elias S. Manolakos

A Locality Aware Convolutional Neural Networks Accelerator 591

Runbin Shi, Zheng Xu, Zhihao Sun, Maurice Peemen, Ang Li, Henk Corporaal,

and Di Wu

SOCNOC: Systems and Networks on Chip

Hardware Design Space Exploration with a New Dimension-IP Protection

Robustness 599

Qiang Liu and Haie Li

TEST: Assessing NoC Policies Facing Aging and Leakage Power 606

Davide Zoni, Luca Borghese, Giuseppe Massari, Simone Libutti,

and William Fornaciari

SOC Power Management Strategy Based on Global Hardware Functional

State Analysis 614

Hend Affes and Michel Auguin

An Analytic Approach on End-to-End Packet Error Rate Estimation

for Network-on-Chip 621

Michael Vonbun, Stefan Wallentowitz, Andreas Oeldemann,

and Andreas Herkersdorf

MSDA: Multicore Systems: Design and Appplications

Systematic Reverse Engineering of Cache Slice Selection in Intel Processors 629

Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar

A System-Level Simulation Framework for Evaluating Resource Management

Policies for Heterogeneous System Architectures 637

Antonio Miele, Gianluca Carlo Durelli, Marco Domenico Santambrogio,

and Cristiana Bolchini

AHSA-2: Architectures and Hardware for Security Applications (2)

Suit up!—Made-to-Measure Hardware Implementations of ASCON 645

Hannes Grofl, Erich Wenger, Christoph Dobraunig, and Christoph Ehrenhofer

Fast and Secure Finite Field Multipliers 653

Danuta Pamula and Arnaud Tisserand

xiv

A Petite and Power Saving Design for the AES S-Box

Markus Stefan Wamser, Lukas Holzbaur, and Georg Sigl

,661

New ASIC/FPGA Cost Estimates for SHA-1 Collisions 669

Muhammad Hassan, Ayesha Khalid, Anupam Chattopadhyay,

Christian Rechberger, Tim Guneysu, and Christof Paar

MCSDIA-2: Mixed Criticality System Design, Implementation,and Analysis (2)

IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators

for Probabilistic Timing Analysis 677

Irune Agirre, Mikel Azkarate-askasua, Carles Hernandez, Jaume Abella,

Jon Perez, Tullio Vardanega, and Francisco J. Cazorla

CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel

Applications on Many-Cores 685

Milos Panic, Eduardo Quinones, Carles Hernandez, Jaume Abella,

and Francisco J. Cazorla

Time-Triggered Extension Layer for On-Chip Network Interfaces

in Mixed-Criticality Systems 693

Hamidreza Ahmadian and Roman Obermaisser

DTFT-3: Dependability, Testing, and Fault Tolerance in Digital Systems(3)

Double Phase Fault Collapsing with Linear Complexity in Digital Circuits

Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska,

and Stephen Adeboye Oyeniran

700

Matching Detection and Correction Schemes for Soft Error Handling

in Sequential Logic

Erol Koser, Felix Miller, and Walter Stechele

,706

A Detailed Characterization of Errors in Logic Circuits due to Single-Event

Transients

Nanditha P. Rao and Madhav P. Desai

714

Enhanced Metastability Characterization Based on AC Analysis

Thomas Polzer and Andreas Steininger

722

EPDSD-3: European Projects in Digital System Design (3)

DEWI—Wirelessly into the Future

Werner Rom, Peter Priller, Jani Koivusaari, Maarjana Komi, Ramiro Robles,

Luis Dominguez, Javier Rivilla, and Willem van Driel

730

XV

The Human Brain Project: High Performance Computing for Brain Cells

Hw/Sw Simulation and Understanding 740

Egidio D'Angelo, Giovanni Danese, Giordana Florimbi, Francesco Leporati,

Alessandra Majani, Stefano Masoli, Sergio Solinas, and Emanuele Torti

Methodologies for the WCET Analysis of Parallel Applications on Many-Core

Architectures 748

Vincent Nelis, Patrick Meumeu Yomsi, and Luis Miguel Pinho

Author Index 756

xvi