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Introduction
Sungho Kang
Yonsei University
2CS&RSOC YONSEI UNIVERSITY
Outline
VLSIDesign StylesOverview of Optimal Logic SynthesisModelGraph Algorithm and ComplexityAsymptotic ComplexityBrief Summary of MOS Device Behavior
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VLSIVLSI
Manufacturing TechnologyMinimum length of MOS channelsThe number of interconnection layers
Design TechnologyCAD tools
Why VLSINew marketsOperation speedProtection investments in design
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Design StyleDesign Style - Decomposition
Behavioral SynthesisResource allocation; Pipelining; Control flow parallelization; Communicating Sequential Processes; Partitioning
Sequential SynthesisRegister Movement and Retiming; State Minimization; State Assignment; Synthesis for Testable FSM’s; State Machine Verification
Logic SynthesisExtraction of combinational logic to HDL; Two-level minimization; Algebraic Decomposition; Multilevel Logic Minimization; Synthesis for Multi-fault Testability; Test Generation via Minimization; Technology mapping; Timing optimization
Technology MappingMapping to Library of Logic Gates; Timing Optimization
Physical Design SynthesisCell Placement; Routing; Fabrication; Engineering Changes
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Design StyleLogic Design Styles
Full custom designEvery circuit part is especially optimized for the purpose it must serve in the design
Semi-custom designThe circuit is designed by assembling pre-designed and pre-characterized sub-circuitsManufacturing may use a pre-diffused substrate
Programmed designThe design is obtained by programming a standard partSome circuits may be programmed only once while others may be programmed an unlimited number of times
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SOC DesignSOC Design Paradigm
Emergence of Very large transistor counts on a single chipMixed technologies on the same chip
Logic, Analog, Memory, ProcessorCreation of Intellectual Property (IP)Reusable core-based design
Cores replacing standard parts, such as DSP, DRAM, MCU, Flash, and FPGA
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SOC DesignSOC Evolution
OriginalDesignBlock
OriginalDesignBlock
UserDefinedLogic(UDL)
SRAM
ROM
OriginalDesignBlock
uP(IP Core)
UserDefinedLogic(UDL)
DRAM
Analog
ROM
ATM(IP Core)
MPEG(IP Core)
ASIC
Block-Based SOC
Core-Based SOC
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SOC DesignIP Core types
Hard Core(Technology dependent layout)Predictable area and performanceLack flexibility
Soft Core(RTL)leave much of the implementation to the designerFlexible and process-independent
Firm Core(Netlist)
Each type of core has different modeling and test requirements
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Logic SynthesisDesign Tradeoffs
Factors to be optimized in chip design:AreaDelayPowerTestability
These competing objectives require Tradeoffs
Synthesis tools automate tradeoffAccording to the commands used by the designer, area or delay (or power, or testability) is reduced
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Logic SynthesisArea vs Delay:The Bit-Serial Adder
A typical tradeoff is area versus delayWith just one full adder, this circuit can do 32-bit additionBut, it is 32x slower than a parallel adder (32 full adders, 1 bit output per clock cycle)
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Logic SynthesisDesign Tradeoff Curve
Holding other factors constant, the Area vs Delay tradeoff curve is typically parabolicThe first design requirement is meet Constraints on Chip Area and Critical Path Delay (0 to 1)
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Logic SynthesisDesign Tradeoffs
The next priority is to optimize a feasible designDesign 2 is optimal, in the sense that area and delay cannot both be decreased from this pointTradeoff is now necessary, according to policy
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Logic SynthesisDesign Tradeoffs
A typical design policy is to optimize area subject to a delay constraint (2 to 3)Often a preferred policy is to optimize delay subject to an area constraint (2 to 4)
4
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Logic SynthesisPrioritizing Testability
Sometimes other factors, such as testability or power, take priorityTypically this moves the area-delay tradeoff curve up and to the rightThus designs 1 and 2 are optimal
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Logic SynthesisArea Optimization
Typically performed in a technology independent view of the circuitIn this view gates are regarded as logic functionsThese functions are converted to physical gates by Technology Mapping
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Logic SynthesisTechnology Independent View
In this view the gates of the full adder circuit are just logic equations
a = xi yib = xi’ yi’e = a’ b’zi = eci-1‘ +e’ci-1c = xi yid = xi + y + i f = dci-1ci = c + f
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Logic SynthesisOptimization and Technology Mapping
Common subfunctions sharedFunctions “Technology Mapped” to negative gates
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Logic SynthesisTesting
Faults ModelsStuck-at faultsDelay faults
Test vectorsFault simulationAutomatic test pattern generation
DiagnosisTestable Design
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Logic SynthesisDelay Optimization
First step is to identify the Critical PathSimplest delay model: “number of logic levels”
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Logic SynthesisCritical Path Analyzers
Static Delay Models:Levels of LogicDelay function of size, load Worst, best case models
Dynamic Delay ModelsSimplified device modelsFull Spice analysis
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Model GenerationModel
BehavioralRepresents the behavior of the systemBehavior can be specified as a mapping of logic values or of data words, etc.Functional model is a representation of its logic functionBehavioral model consists of a function model with a representation associated with timing relationsAdvantages from the separation between function and timing
Circuits with the same function but different timingFunction and timing can be dealt in design verification
Structural Collection of interconnected elementsPrimitive elementsBlock diagram : CPU, RAM, etcSchematic diagram : AND, OR etc
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Model GenerationModel
ExternalModel viewed by the userGraphic or text-basedHDL (Hardware Description Language)RTL (Register Transfer Level)
InternalData structures and programs inside
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Model GenerationTruth Tables
Simplest wayn variables requires 2n entry
X1 X2 Y0 0 00 1 01 0 01 1 1
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Model GenerationCube
A cube of Z(x1,x2,x3) has the form (v1,v2,v3|vz) wherevz=(v1,v2,v3) An implicant of g of Z can be represented by a cube constructed
Set vi=1(0) if xi(xi’) appears in g Set vi=x if neither xi nor xi’ appears in g Set vz=1
If the cube q can be obtained from the cube p by replacing one or more x values in p by 0 or 1 then p covers q Primitive cube
Cube representing a prime implicantPrimitive cubes provide a compact representation of a function
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Model GenerationIntersection Operator
Inconsistency : ∅Consistency : Except ∅
Compatible Values whose intersection is consistentIntersection of 2 cubes is compatible iff all corresponding values are compatible
To determine ZForm the cube (v1,v2, … vn|x) Intersect this cube with the primitive cube of Z until a consistent intersection is obtainedThe value of z is obtained in the rightmost position
∩ 0 1 X0 0 ∅ 01 ∅ 1 1X 0 1 X
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Model GenerationState Tables
Represents synchronous sequential circuitsRow corresponding to every internal stateColumn corresponding to every possible inputN(qi,Im), Z(qi, Im)
Entry in row qi and column Im represents the next state and the output produced if Im is applied when the machine is in state qiN : next state Z : output function
x0 1
1 2,1 3,0q 2 2,1 4,0
3 1.0 4,04 3,1 3,0
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Model GenerationState Tables
Canonical Structure
F/F
combinationalcircuit C
F/F
x
CLOCK
z
y Y
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Model GenerationFlow Tables
Represents a behavior of asynchronousState transition may involve a sequence of state changes caused by a single input change to Ij until a stable configuration is reached, denoted by N(qi, Ij)=qi
combinationalcircuit C
x z
y
x1 x2
00 01 11 101 1,0 5,1 2,0 1,02 1,0 2,0 2,0 5,13 3,1 2,0 4,0 3,04 3,1 5,1 4,0 4,05 3,1 5,1 4,0 5,1
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Model GenerationIterative Array
C(0) pseudoF/F C(0) pseudo
F/Fpseudo
F/FC( i )Y(1) y(1) Y(2) y(2) y(i) Y(i+1) y(i+1)
Y(0)
x(0)
z(0)
x(1)
z(1)
x( i )
z( i )
time frame 0cell 0
time frame 1cell 1
time frame icell i
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Model GenerationPrograms as Functional Models
CE = A & B & CF = ~DZ = E \ F
AssemblyLDA A /* load accumulator with value of A*/AND B /* compute A.B */AND C /* compute A.B.C */STA E /* store partial result */LDA D /* load accumulator with value of D */INV /* compute DOR E /* compute A.B.C + D */STA Z /* store result */
ABC
D F
E
Z
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Model GenerationStructural Models
FanoutFanout-freeReconvergent fanputInversion Parity
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Logic SynthesisGraph Models and FSM
GraphEdgeVertexUndirected graphDigraph (directed graph)
All edges are directedMixed graph
Directed and undirectedDAG (directed acyclic graph)
If digraph has no cycles
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Logic Synthesis
Graph: ordered set of two sets G= (V,E)V : a set of vertices or nodesE : a set of edges or arcs->4 : the successors (fanouts) of node 4 4->=1,3->4 : the predecessors (fanins) of node 4 ->4=1,2
Graph Terminology
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Logic SynthesisGraph Models
Transitive closureThe extended edge relation E*(u,v) derived from a given edge relation E(u,v) is called transitive closure of E
fanoutfaninSource
v has no predecessorsSink
v has no successors
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Asymptotic ComplexityAsymptotic Complexity
A function F(n) is in the set O(g(n)) if and only if there exist positive constants co and no such that
F(n) ≤cog(n) for all n ≥ no
This means that F(n) is asymptotically bounded from above by a linear function of g(n)
A function F(n) is in the set Ω(g(n)) if and only if there exist positive constants cΩ and nΩ such that
F(n) ≥ cΩ g(n) for all n ≥ nΩ
This means that F(n) is asymptotically bounded from below by a linear function of g(n)
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ConlcusionConclusion
Design time spent in each design phase
Verification : 39% RTL design and synthesis : 17%IC layout : 13%System design and integration : 11%Test vector creation : 11%Evaluation and Procurement : 6%Other : 3%