2_1 Verilog HDL

1- 1 -20052005 VLSI Training CourseVLSI Training Course

Verilog HDL

Teaching Assistant: Lien-Fei Chen ()Instructor: Prof. Yeong-Kang Lai

Multimedia & Communication IC Design LabElectrical Engineering, National Chung Hsing University

Fall, 2005

- 2 -20052005 VLSI Training CourseVLSI Training Course

Outline

Introduction to Introduction to VerilogVerilog HDLHDL Verilog data types and models Verilog test bench Introduction to Verilog-XL simulator Annotating SDF Timing


What is a Hardware Description Language ?

High-level programming language with special constructs used to model the function of hardware logic circuits

The special language constructs provides the ability to Describe the connectivity of the circuit Describe the functionality of a circuit Describe a circuit at various levels of abstraction Describe the timing of a circuit Express concurrency


Why Use an HDL ?

There are several benefits in using an HDL to describe your design Top-down methodology using synthesis

Design at an implementation-independent, higher level Explore design alternatives easily Find problems eariler in the design cycle Automate mapping of high-level descriptions to technology-

specific implementations An HDL provides greater flexibility

Re-use Choice of tools, vendors

An HDL provides the advantages of decades of software practices Faster design capture Easier to manage


What is Verilog HDL ?

A hardware description language Verilog models digital electronic system Verilog lets you model at different levels of abstraction Verilog lets you develop tests to verify the functionality of the

devices you model


A Brief History of Verilog

1981 Gateway Design Automation released GenRads Hardware Description Language (GHDL)

1983 Gateway released Verilog HDL 1985 Enhanced simulator Verilog-XL released 1989 Cadence bought Gateway 1990 Cadence released Verilog to public domain 1993 EE Times reported 85% designs submitted to

ASIC foundries were designed and submitted using Verilog

1995 Reviewed and adopted as IEEE standard 1364


Levels of Abstraction for VerilogHDL & VHDL

vital

System

Algorithm

RTL

Logic

Gate

Verilog

VHDL

Synthesizable RTL Code

BehavioralLevel

BehavioralLevel

RTLLevelRTL

Level

GateLevelGateLevel


Levels of Abstraction for Verilog

Models can be written with different levels of details Three main levels of abstraction in Verilog

Behavioral Describes a system by the flow of data between its functional

blocks Schedules assignments at functional boundaries only when

necessary Register Transfer Level (RTL)Register Transfer Level (RTL)

Describes a system by the flow of data and controls signals within and between functional blocks

Defines the model in terms of cycles, based on a defined clock

Structural (Gate-level) Models components by connecting primitives or low-level

components (gates) for greater accuracy, especially in timing Uses technology-specific, low-level components when mapping

from an RTL description to a gate-level netlist, such as during synthesis


Behavioral and RTL (1/2)

The behavioral/RTL description does not handle unknown and tristate inputs exactly as the structural implementation would, and has no propagation delays

module mux2to1 (a, b, sel, out);input [7:0] a, b;input sel;output [7:0] out;reg [7:0] out;

always @ (a or b or sel)begin

if (sel == 1b1)out = a;

elseout = b;

endendmodule

a

bout

sel


Behavioral and RTL (2/2)

Behavioral model The function of the logic is modeled using high level

language constructs, such as @, while, wait, if/elseand case

RTL model Based on clock RTL model must be accurate at the boundary of every

clocked elements RTL level is appropriate for synthesis, so designers use RTL

to mean the synthesizable subset of behavioral Verilog Testbenchs, or test fixtures, are typically modeled at

the behavioral level. All behavior constructs are legal for testbenchs.


Overall Structure

No glue logic within top module

Top module


Outline

Introduction to Verilog HDL VerilogVerilog data types and modelsdata types and models

VerilogVerilog operationsoperations VerilogVerilog data typesdata types VerilogVerilog modelsmodels

Verilog test bench Introduction to Verilog-XL simulator Annotating SDF Timing


Module Definition

module MyCPU (clk, rst, data, address, result);input clk, rst;input [31:0] data, address;output [31:0] result;

.

.

.

.

.

.endmodule

I/O port declarations

Resource/variable declarations

RTL modeling


Value Set and Numbers

Value set 0 logic zero or false condition 1 logic one or true condition x unknown or dont care logic value z high-impedance state

Number representation base b, d, o ,h


Data Types (1/2)

Signal nets wire, tri

Wired nets wand, wor, triand, trior trireg tri0, tri1

Supply nets supply0, supply1


Data Types (2/2)

Registers reg

Memories array of register variables

Integers (32-bit) integer

Time (64-bit) time

Real numbers real

Parameters parameter


Operators (1/2)

Arithmetic operators +, 1, *, /, %

Relational operators (0, 1, x) , =

Equality operators (0, 1) ==, !=, ===, !==

Logical operators (0, 1) &&, ||, !

Bit-wise operators ~, &, |, ^, ~^, ^~


Operators (2/2)

Reduction operators (unary) &, |, ^, ~&, ~|, ~^, ^~

Shift operators (fill with zeros)

Conditional operator ?...:

Concatenations {, }

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Module Connectivity

Order list

Name

module top ();

wire [7:0] data, result;inv INV0 (data, result);

endmodule

module inv (in, out);input [7:0] in, out;

out = ~in;endmodulemodule top ();

wire [7:0] data, result;

inv INV0 (.in(data),.out(result));

endmodule

module inv (in, out);input [7:0] in, out;

out = ~in;endmodule

Better !!!


Parameters

Use parameters to declare run-time constants You can use a parameter anywhere that you can use

a literal Parameters are local, known only to the module in

which they are definedmodule mod (in1, in2, out);

parameter cycle = 20, prop_del = 3,setup = cycle/2 prop_del,p1 = 8,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

...wire [p1:0] w1; // a wire declaration using parameter

...endmodule

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Overriding the Values of Parameters (1/2)

module mod (in1, in2, out);

parameter p1 = 8,real_constant = 2.039,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

...endmodule

module test;...mod I1 (.in1(in1), .in2(in2), .out(out));defparam

I1.p1 = 6;I1.file = ../my_mem.dat;

endmodule

Defparam StatementDefparam Statement


Overriding the Values of Parameters (2/2)

module mod (in1, in2, out);

parameter p1 = 8,real_constant = 2.039,x_word = 16bx,file = /usr1/jdough/design/mem_file.dat;

endmodule

module top;...mod #(5, 3.0, 16bx, ../my_mem.dat)

I1 (.in1(in1), .in2(in2), .out(out));...

endmodule

Module Instance Parameter OverrideModule Instance Parameter Override

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Register Arrays

You can declare an array of registers in Verilog

An array of the datatype reg is often called a memory

You can use parameters to model memory size

integer nums [7:0]; // array of 8 integer variablestime t_vals [3:0]; // array of 4 time variables

reg [15:0] MEM [0:1023]; // 1K x 16-bit memory arrayreg [7:0] PREP [`hFFFE:`hFFFF]; // 2 x 8-bit memory array

parameter WORDSIZE = 16;parameter MEMSIZE = 1024;reg [WORDSIZE-1:0] mem3 [MEMSIZE-1:0];


Memory Addressing

module mems;

reg [7:0] mema [0:255]; // declare memory called memareg [7:0] mem_word; // temp register called mem_word

...initialbegin

// Display contents of the 6th memory address$display(mema[5]);// Display the MSB of the 6th memory wordmem_word = mema[5];$displayb(mem_word[7]); // Display the MSB

endendmodule

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Behavioral Modeling

Event-driven procedures always, initial

Sequential blocks Begin...end

Parallel blocks Fork...join


Procedure blocks

All procedure blocks are activated at time 0 All procedural blocks execute concurrently

initial always

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Procedure Timing Control

Simple delays, or pound delays #

Event control (edge-sensitive) @

Level-sensitive timing control wait


Edge-Sensitive Timing

module reg_adder(clk, a, b, out);

input clk;input [2:0] a, b;output [3:0] out;reg [3:0] out, sum;

always @ (a or b) // when any change occurs on a or b#5 sum = a + b;

always @ (negedge clk) // at every negative edge of clkout = sum;

endmoduleExampleExample

15


Conditional Statements

if ()

if ()

else

if (index>0)if (rega > regb)

result = rega;else

result = regb;

if (index > 0)begin

if (rega > regb)result = rega;

endelse

result = regb;


Multi-way Decision Statements

if ()

else if ()

else if ()

else

case/casez/casex ()

endcase

reg [15:0] rega;reg [7:0] result;...

case (rega)16d0: result = 8hff;16d1: result = 8hbf;16d2: result = 8hdf;...default result = 8hxx;

endcase

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Nonblocking Procedural Assignment

module swap_vals (clk, rst, a, b);

parameter BIT_SIZE = 4

input clk, rst;output [BIT_SIZE-1:0] a, b;

// Non-blocking procedural assignmentalways @ (posedge clk)begin

if (rst == 1b1)begin

a

17


Functions and Tasks (1/2)

Tasks and functions provides the ability to execute common procedures from several different places in a description


Functions and Tasks (2/2)

Task Is typically used to perform debugging operations, or to

behaviorally describe hardware Can contain timing controls (#, @, wait) Can have input, output, and inout arguments Can enable other tasks or functions

Function Is typically used to perform a computation, or to represent

combinational logic Cannot contain any delays; functional happen in zero

simulation time Has only input arguments and returns a single value through

the function name Can enable other functions, but not tasks

18


Verilog Tasks

module mult (clk, a, b, out, en_mult);input clk, en_mult;input [3:0] a, b;output [7:0] out;

reg [7:0] out;

always @ (posedge clk)multme (a, b, out); // task invocations

task multme; // task definitioninput [3:0] xme, tome;output [3:0] result;wait (en_mult)

result = xme * tome;endtask

endmodule


Verilog Functions

module foo (loo, goo);input [7:0] loo;output [7:0] goo;

// you can call a function from a continuous assignmentwire [7:0] goo = zero_count (loo);

function [3:0] zero_count // task definitioninput [3:0] in_bus;integer i;begin

zero_count = 0;for (i = 0; i < 8; i = i + 1)

if (!in_bus[i])zero_count = zero_count + 1;

endendfunction

endmodule

19


Special Language Token

System Tasks and Functions: $ The $ sign denotes Verilog system tasks and

functions A number of system tasks and functions are available

to perform different operations, such as $time finding the current simulation time $display, $monitor Displaying/monitoring the values

of the signals $stop stopping the simulation $finish finishing the simulation

Example$monitor($time, a = %b, b = %h, a, b);


Text Substitution

The `define compiler directive provides a simple text-substitution facility.

`define Example

`define D_NOT #1`define D_AND #2`define D_OR #1

module mux2to1 (a, b, sel, out);input a, b, sel;output out;

not `D_NOT not1(sel_, sel);and `D_AND and1(a1, a, sel_);and `D_AND and2(b1, b, sel);or `D_OR or1(out, a1, b1);

endmodule

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Text Inclusion

Use the ìnclude compiler directive to insert the contents of an entire file

You can use ìnclude to Include global or commonly used definitions, such as text

macros Include tasks without encapsulating repeated code within

module boundaries

ìnclude global.vìnclude parts/count.vìnclude ../../library/mux.v


Timescale `timescale compiler directive declares the time

unit and precision `timescale /

The `timescale compiler directive must appear before a module boundary

Keep precision as close in scale to the time units as is practical

`timescale 1ns/100ps

`timescale 1ns/10ps// All time units are in multiples of 1 nanosecondmodule mux2to1 (a, b, sel, out);input a, b, sel;output out;

not #1 not1(sel_, sel);and #2 and1(a1, a, sel_);and #2 and2(b1, b, sel);or #1 or1(out, a1, b1);

endmodule

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Outline

Introduction to Verilog HDL Verilog data types and models VerilogVerilog test benchtest bench Introduction to Verilog-XL simulator Annotating SDF Timing


Test Bench Organization

Design to verify

Testbench

Design to verify

Testbench

Simple test benchSimple test bench

Sophisticated test benchSophisticated test bench

22


Test Fixture

module testfixture;

// data type declarationreg [7:0] a, b;reg sel;wire [7:0] out;

// instantiate modulesmux2to1 test_mux (.a(a),

.b(b),

.sel(sel),

.out(out));// apply stimulus// display results

endmodule


Test Fixture Response Generation

Verilog provides a number of system tasks and system functions, including: $time is a system function that returns the current

simulation time. $monitor is a system task that displays the values of the

argument list at the end of any time unit in which any of the arguments change.

$monitor ([format_specifiers,]);example

$monitor($time, o, in1, in2);$monitor($time,, out,, a,, b,, sel);$monitor($time, %b %h %d %o, sig1, sig2, sig3, sig4);

23


Test Fixture Describing Stimulus module testfixture;// data type declarationreg a, b, sel;wire out;

// instantiate modulesmux2to1 test_mux (.a(a),

.b(b),

.sel(sel),

.out(out));

// apply stimulusinitialbegin

a = 0; b = 1; sel = 0;#5 b = 0;#5 b = 1; sel = 0;#5 a = 1;$finish;

end

// display resultsInitial

$monitor($time,,out = %b a = %b b = %b sel = %b, out, a, b, sel);endmodule


The VCD Database

Verilog provides a set of system tasks to record signal value changes in the standard VCD (Value Change Dump) format. Most wave display tools read this formant, among others.

System task Action

$dumpfile(file.dump); Open a VCD database for recording $dumpvars(); Select signals for recording $dumpflush; Flush all VCD data to disk $dumpoff; Stop recording $dumpon; Start recording again $dumplimit(); Lim it the s ize (in bytes) of the VCD database created $dumpall; Dump the values of all specified signal values

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Dumping Signals

Supply levels and scope arguments to $dumpvars

$dumpvars could replace the $monitor command

$dumpvars; // Dump all signals in the hierarchy$dumpvars (1, top); // Dump all signals in module top

//Dump signals in instance top.u1 and its subscope$dumpvars (2, top.u1);

//Dump signals in top.u2 and below, and signal top.u1.u13.q$dumpvars (0, top.u2, top.u1.u13.q);

//Dump signals in top.u1 and top.u2, and in all their subscopes of them, two level down$dumpvars (3, top.u2, top.u1)

Exampleinitialbegin

$dumpfile(verilog_dump.vcd);$dumpvars(0, testfixture);

end


File Input (1/2)

$readmemb

$readmemh

$readmemb(file_name,);$readmemb(file_name,,);$readmemb(file_name,,,);

$readmemh(file_name,);$readmemh(file_name,,);$readmemh(file_name,,,);

25


File Input (2/2)

0000_00000110_0001 0011_0010// addresses 3-255 are not defined@100 //hex1111_1100/* addresses 257-1022 are not defined */@3FF1110_0010

Text Filemem_file.txt

00000000

01100001

00110010

11111100

11100010

0...

256

...

1023

0 7

Declared Memory Arrayreg[0:7] mem[0:1023]


File Output (1/2) $fopen opens a file and returns a multi-channel

descriptor (MCD) The MCD is a 32-bit unsigned integer uniquely associated

with the file If the file cannot be opened for writing, MCD will equal 0 If the file is successfully opened, one bit in the MCD will be

set. Display system tasks that begin with $f direct their

output to whichever file or files are associated with the MCD MCD1 = $fopen();

$fdisplay(MCD1, P1, P2, , Pn);$fwrite(MCD1, P1, P2, , Pn);$fstrobe(MCD1, P1, P2, , Pn);$fmonitor(MCD1, P1, P2, , Pn);

$fclose(MCD1); ExampleExample

26


File Output (2/2)

...integer message, broadcast, cpu_chann, alu_chann;

initialbegin

cpu_chann = $fopen(cpu.dat); if (!cpu_chann) $finish;alu_chann = $fopen(alu.dat); if (!alu_chann) $finish;// channel to both cpu.dat and alu.datmessage = cpu_chann | alu_chann;// channel to both files, standard out, verilog.logbroadcast = 1 | message;

end

always @ (posedge clk)$fdisplay(alu_chann, acc = %h f = %h a = %h b = %h, acc, f, a, b);

/* at every rst print a message to alu.dat, cpu.dat, standard outputand the verilog.log file */

always @ (posedge rst)$fdisplay(broadcast, system reset at time %d, $time);

...


In Line Stimulus

Variable can be listed only when their values change Complex timing relationship are easy to define A test bench can become very large for complex

tests module inline_tb;reg [7:0] data_bus, addr;wire [7:0] results;

DUT u1 (data_bus, addr, results);

initialfork

data_bus = 8h00;addr = 8h3f;#10 data_bus = 8h45;#15 addr = 8hf0;#40 data_bus = 8h0f;#60 $finish;

joinendmodule

ExampleExample

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Stimulus From Loops

The same set of stimulus variables are modified in every iteration

Timing relationships are regular in nature Code is compact

module loop_tb;

reg clk;reg [7:0] stimulus;wire [7:0] results;integer i;

DUT u1 (clk, stimulus, results);always begin // clk generator

#5 clk = ~clk;end

initialbegin

clk = 1b1;for (i = 0; i < 256; i = i + 1)

@ (negedge clk) stimulus = i;#20 finish;

endendmodule

ExampleExample


Stimulus From Arrays

The same set of stimulus variables are modified in every iteration

Stimulus can be read into an array directly from a filemodule array_tb;

reg [7:0] data_bus, stim_array[0:15];integer i ;

DUT u1 (data_bus, addr, results);

initialbegin

// load array with values#20 stimulus = stim_array[0];#30 stimulus = stim_array[15]; // in line#20 stimulus = stim_array[1];for (i = 14; i > 1; i = i - 1) // from loop

#50 stimulus = stim_array[i];#30 finish;

endendmodule

ExampleExample

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Stimulus From Vector

module read_file_tb;

parameter num_vecs = 256;reg [7:0] data_bus, stim[0:num_vecs-1:0];wire [7:0] resultsinteger i ;

DUT u1 (data_bus, results);

initialbegin // Vectors are loaded

$readmemb(vec.txt, stim);for (i = 0; i < num_vecs; i = i + 1)

#50 data_bus = stim[i];endendmodule

ExampleExample


Outline

Introduction to Verilog HDL Verilog data types and models Verilog test bench Introduction to Introduction to VerilogVerilog--XL simulatorXL simulator Annotating SDF Timing

29


Simulation Algorithms

There are three broad categories of simulation algorithm Time-based (used by SPICE simulators) Event-based (used by Verilog-XL and NC-Verilog simulators) Cycle-based


Simulation of a Verilog Model

Verilog simulation takes the following steps Compilation Initialization

During initialization, parameters are initialized, undriven nets default to z, and other nodes get the value x. These values propagate through the design hierarchy as they do during a real simulation

Simulation Simulation commences at time zero. Initial and always block are not preceded by timing controls.

These assignments can trigger events at time zero and at later times

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Invoking Verilog-XL

Syntax verilog [verilog-xl_operations] design_files

No command line options verilog mux.v test.v

Using the -c command-line option to check the syntax and connectivity of your design without actually simulating verilog c mux.v test.v

Using the -f command-line option to specify a file that contains command-line arguments verilog f run.f

mux.vtest.v-c

run.f


Outline

Introduction to Verilog HDL Verilog data types and models Verilog test bench Introduction to Verilog-XL simulator Annotating SDF TimingAnnotating SDF Timing

31


Delay Calculators

Two categories of delay calculators Delay calculators embedded in the tools Custom delay calculators

User-defined Vendor-supplied


Standard Delay Format

Standard Delay Format (SDF) provides a tool-independent, uniform way to represent timing information

SDF represent Module path delays conditional and unconditional Device delays Interconnect delays Port delays Timing checks Path and net timing constraints

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SDF Annotator

Use the $sdf_annotate system task to annotate SDF timing information

You can invoke this task interactively or from within the source code

$sdf_annotate(sdf_file,[module_instance,config_file, log_file, mtm_spec,scale_factors, scale_type]);

ExampleExample


Running the SDF Annotator

module top;...

cpu u1 (...);fpu u2 (...);dma u3 (...);

...initialbegin

$sdf_annotate(sdffiles/cpu.sdf,m1,,logfiles/cpu_sdf.log);$sdf_annotate(sdffiles/fpu.sdf,m1,,logfiles/fpu_sdf.log);$sdf_annotate(sdffiles/dma.sdf,m1,,logfiles/dma_sdf.log);

end...

endmoduleExampleExample

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Reference

1. , CIC: Verilog Training Manual, July. 2004

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2_1 Verilog HDL