2100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. …newport.eecs.uci.edu/~Payam/DualBand_MMW_VCO.pdf: A BICMOS DUAL-BAND MILLIMETER-WAVE FREQUENCY SYNTHESIZER FOR AUTOMOTIVE

2100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 8, AUGUST 2009

A BiCMOS Dual-Band Millimeter-Wave FrequencySynthesizer for Automotive Radars

Vipul Jain, Student Member, IEEE, Babak Javid, and Payam Heydari, Senior Member, IEEE

Abstract—Design and implementation of a millimeter-wavedual-band frequency synthesizer, operating in the 24 GHz and77 GHz bands, are presented. All circuits except the voltagecontrolled oscillators are shared between the two bands. Amulti-functional injection-locked circuit is used after the oscil-lators to simplify the reconfiguration of the division ratio insidethe phase-locked loop. The 1 mm 0.8 mm synthesizer chip isfabricated in a 0.18 m silicon-germanium BiCMOS technology,featuring 0.15 m emitter-width heterojunction bipolar transis-tors. Measurements of the prototype demonstrate a locking rangeof 23.8–26.95 GHz/75.67–78.5 GHz in the 24/77 GHz modes, witha low power consumption of 50/75 mW from a 2.5 V supply. Theclosed-loop phase noise at 1 MHz offset from the carrier is less than

100 dBc/Hz in both bands. The frequency synthesizer is suitablefor integration in direct-conversion transceivers for K/W-bandautomotive radars and heterodyne receivers for 94 GHz imagingapplications.

Index Terms—Bipolar transistor oscillators, divide-by-three,dual-band, frequency conversion, frequency synthesizers, in-jection-locked oscillators, millimeter-wave integrated circuits,phase-locked loops, radar, 24 GHz, 77 GHz.

I. INTRODUCTION

N EXT-GENERATION short- and long-range automotiveradar sensors, operating in the millimeter-wave (MMW)

spectrum, will almost certainly be manufactured in silicon (Si)or silicon-germanium (SiGe) technologies. SiGe is already aproven technology for automotive radars in the 24 GHz band [1],[2], and recent work has demonstrated its potential for MMWapplications as well. Highly-integrated MMW SiGe transmittersand receivers, intended for 77 GHz radar applications as well asthe more popular 60 GHz band, have been reported in recent lit-erature [3]–[11]. Performance of SiGe technology for imagingapplications in the W-band (94 GHz) and D-band (140 GHz) hasalso been explored [8], [9]. Recently reported SiGe transceivershave achieved record operation frequencies in the vicinity of170 GHz [9], [11]. With further improvements in transistor per-formance, it is likely that SiGe will emerge as the technologyof choice for beyond-100-GHz applications including passiveimaging and short-range communications.

Similar to the trends in cellular and WLAN applicationsduring the last decade, low-cost requirements will necessitate

Manuscript received December 08, 2008; revised February 27, 2009. Currentversion published July 22, 2009. This work was supported in part by an NSFgrant under contract CRI-0551735, and by Fujitsu Labs of America (FLA). Chipfabrication was provided by Jazz Semiconductor.

The authors are with the Nanoscale Communication IC (NCIC) Laboratory,University of California, Irvine, CA 92697 USA (e-mail: [email protected];[email protected]).

Digital Object Identifier 10.1109/JSSC.2009.2022299

multiband operation with lower component count in future gen-erations of radar sensors. For instance, long- and short-rangedetection can potentially be combined by integration of22–29 GHz (hereafter referred to as 24 GHz, for brevity) and77 GHz radars on a single chip [12]. A paramount challengefor these systems, however, will be the efficient generation ofmultiple frequencies on a single-chip while maintaining ade-quate isolation between different frequency bands. In this work,we describe the first attempt to design a dual-band frequencysource for such systems.

Only a few frequency synthesizers have been reported in theMMW spectrum, mostly for the 60 GHz band [13]–[17] andonly two targeting the W-band [18], [19]. In this paper, wepresent a highly-integrated MMW frequency synthesizer, basedon the work first reported by the authors in [19]. The designhas been implemented in a 0.18 m SiGe BiCMOS processfeaturing 200/180 GHz heterojunction bipolar tran-sistors (HBTs) with 0.15 m emitter-width. All circuits exceptthe voltage-controlled oscillators (VCOs) are shared betweenthe two radar bands, and a seamless reconfiguration of divisionratio is incorporated. All components except the loop filter areintegrated on-chip. The synthesizer design is targeted for inte-gration within a dual-band automotive radar direct-conversiontransceiver chip [12]. It can potentially be utilized in a 94 GHzheterodyne receiver for imaging applications, as described later.

The remainder of this paper is organized as follows: Section IIdiscusses the architectural considerations for the dual-band syn-thesizer. The circuit design and analysis of key building blocksof the synthesizer are described in Section III. Measurement re-sults carried out on an experimental synthesizer prototype arepresented in Section IV. Finally, Section V provides concludingremarks.

II. DUAL-BAND ARCHITECTURE

The block diagram of the proposed dual-band architecturefor the MMW frequency synthesizer is shown in Fig. 1. It con-sists of two LC VCOs, a divide-by-three injection-locked circuit(ILC),1 a divide-by-32 emitter-coupled logic (ECL) frequencydivider, a divide-by-8 static CMOS frequency divider, a CMOSphase/frequency detector (PFD), a CMOS charge pump (CP),and an off-chip low-pass filter (LPF). In the W-band mode, the77 GHz VCO is enabled and the division ratio is 768. The ILCis injection-locked to the 77 GHz VCO output. In the K-bandmode, the 24 GHz VCO is enabled. In this mode, the ILC islocked to the 24 GHz VCO output and thus acts as a tuned buffer,resulting in a division ratio of 256. Although the ILC could be

1Hereafter, the circuit is referred to as ILC in order to avoid confusion betweenits two injection-locking modes.

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JAIN et al.: A BICMOS DUAL-BAND MILLIMETER-WAVE FREQUENCY SYNTHESIZER FOR AUTOMOTIVE RADARS 2101

Fig. 1. Block diagram of the 24/77 GHz dual-band frequency synthesizer.

used as a VCO for the K-band mode (with the 77 GHz VCOdisabled), the ILC phase noise is inadequate for this purpose.This is because the ILC in this work incorporates a tank with arelatively low quality factor (Q) in order to achieve a wide injec-tion-locking range. The proposed scheme allows the use of thesame low phase noise reference input in both operating bandsof the synthesizer. The reference frequency of the synthesizer is92–105 MHz.

A key building block that significantly influences the overallperformance of a phase-locked loop (PLL) or frequency synthe-sizer is the frequency divider in the feedback loop. Frequency di-vision presents stringent trade-offs between operating frequencyrange, power consumption, and phase noise. Static dividers canachieve a broad operating frequency range, but at the cost ofhigh power dissipation and phase noise. On the other hand,injection-locked frequency dividers (ILFDs) can achieve highoperation frequency and low phase noise with moderate currentconsumption, due to their LC tank-based operation. It is not sur-prising then that an ILFD is often employed as the first dividerstage in MMW frequency synthesizers [3], [13], [15]–[19].

With an input signal of 77 GHz, a divide-by-two ILFD wouldprovide an output frequency of 38 GHz. Although a staticdivider could be used following the divide-by-two ILFD, anadditional ILFD would still be preferred to the lower powerdissipation and improve the phase noise, thus resulting intwo back-to-back divide-by-two ILFDs. On the other hand, adivide-by-three circuit would divide the 77 GHz input down to26 GHz, a frequency range in which static dividers can provideacceptable performance. Considering that ILFDs can achievehigher ( 2) division ratios [13], [20], we determine that adivide-by-three ILFD is thus the optimum topology requiringno additional ILFDs in the divider chain. Moreover, recog-nizing that the divide-by-three output is in the 26 GHz band,a technique for dual-band operation is readily implemented,as discussed above and further elaborated in Section III. It isinteresting to note that a divide-by-four ILFD is also feasible[21], [22], but would require a higher input power to achievethe same locking range as a divide-by-three ILFD. In summary,

the use of a divide-by-three ILFD enables a simple architecturefor dual-band operation while also relaxing the requirements ofthe MMW divider-chain.

As mentioned earlier, the proposed synthesizer can also beemployed in a 94 GHz heterodyne receiver. The 77 GHz VCOoutput can be used as the first local oscillator (LO) signal forthe down-conversion of the 94 GHz input and the quadratureoutputs of the divide-by-6 output (i.e., the output of the seconddivider) can provide the second LO signal. The synthesizer istherefore highly versatile and can serve as a useful buildingblock in several MMW applications.

Next, the circuit design details of the key building blocks ofthe synthesizer are described.

III. CIRCUIT DESIGN

A. 24 GHz and 77 GHz Voltage-Controlled Oscillators

Several MMW VCOs have been reported in recent literature[14]–[19], [21], [23]–[25]. While some novel topologies havebeen introduced, cross-coupled and Colpitts oscillators remainthe most popular due to their simple design and usually adequateperformance. The design of MMW cross-coupled oscillators inSiGe and BiCMOS technologies has been constrained by therelatively low maximum achievable oscillation frequency of aBJT/HBT-based negative-resistance cell. This is due to the highbase resistance of bipolar devices. The oscillation frequencylimit , defined by the point at which the effective neg-ative resistance of the cross-coupled pair becomes positive, isgiven by [26]

(1)

where is the device transconductance, and and arethe base and emitter physical resistances, respectively. Fig. 2(a)shows the simulated equivalent parallel resistance lookinginto the cross-coupled pair, , for the 0.18 m BiCMOStechnology used in this work, indicating an ofabout 77 GHz. This restricts the practical operating frequencyof cross-coupled oscillators in this technology to less than 60GHz. Similarly, the maximum achievable oscillation frequency

of a Colpitts oscillator can be expressed as [26]

(2)

where is the emitter degeneration capacitance in Fig. 2(b).Unlike the cross-coupled case, the frequency limit of a Colpittsoscillator depends on the capacitances used to form its tank andis ultimately limited by the parasitic capacitances of the device.As confirmed by the simulation results2 of Fig. 2(b), a Colpittsoscillator can achieve higher oscillation frequency (a maximumof 135 GHz in the used technology) than a cross-coupled de-sign. Note that (1) and (2) are approximate and exact valuesmust be obtained through simulations; nevertheless, these limitsprovide great deal of insight in designing MMW oscillators.

2Note that the graphs in Fig. 2 represent the highest oscillation frequenciespossible for the corresponding topologies. Device sizes and bias currents werevaried to locate the optimum for each topology and ideal passives were used.



Fig. 2. Comparison of frequency capabilities of different oscillator topologies:(a) cross-coupled, (b) Colpitts, and (c) Colpitts with inductive degeneration.� indicates the frequency at which the equivalent parallel resistance ofthe active core turns positive, thereby preventing oscillation start-up.

Moreover, can be used to characterize device tech-nologies in addition to the conventional figures-of-merit, and

[27]. It is also noteworthy that CMOS technologies do notsuffer from a low because gate resistance of MOS-FETs can be minimized by optimizing the multi-finger layoutof the transistor [28]. Consequently, the choice of topology forCMOS oscillators is governed by other performance parame-ters rather than the maximum achievable oscillation frequency.For instance, a Colpitts oscillator may still be preferred overa cross-coupled topology due to its better phase noise perfor-mance and higher tuning range, even though it may have a lower

in CMOS, as demonstrated in [29].Due to the aforementioned reasons, the 77 GHz VCO design

in this work is based on a modified differential Colpitts oscillatortopology shown in Fig. 2(c) [25], [29]. Compared to a Colpittstopology, the design employs additional inductance for emitterdegeneration. A simplified model for analysis is shown in Fig. 3,where is an arbitrary degeneration impedance. The base

Fig. 3. Colpitts topology with an arbitrary emitter degeneration impedance.The table shows the oscillation frequency of the circuit as the degenerationimpedance is varied.

inductance is also included to complete the tank circuit. Ifis purely capacitive, the topology reduces to a simple Col-

pitts oscillator, whereas if is purely inductive, the circuitfails to oscillate. Furthermore, if is a parallel LC network,the effective impedance can be inductive, capacitive or resistive,depending on whether the operating frequency is lower than,higher than or equal to the LC resonant frequency

, respectively. It is readily inferred that isthe lower limit of the oscillation frequency for the topology ofFig. 2(c), because the degeneration impedance below this fre-quency becomes inductive. Since the oscillation frequency mustbe above , the degeneration impedance is capacitive andan effective capacitance can be defined as

(3)

From (3), it is observed that a higher oscillation frequency canbe achieved with this topology, as also predicted by the simula-tion results in Fig. 2(c). Although this simplistic picture is com-plicated by the presence of non-idealities such as finite qualityfactors of the degeneration inductance and capacitance (formedpartly by lossy varactors), simulations indicate that higher oscil-lation frequencies can indeed be achieved by optimizing the de-generation impedance. The oscillation frequency, , for thistopology can be expressed approximately as shown in (4) at thebottom of the page, where , isthe base-to-emitter capacitance, and is the base-to-collectorcapacitance [29]. Due to the complicated dependence of oncircuit components in (4), simulations are necessary to estimatethe maximum achievable . As indicated in Fig. 2(c), this fre-quency limit, , is in the neighborhood of 145 GHz forthe technology used in this work.

(4)



Since phase noise is one of the most critical specificationsto meet in MMW systems, it is important to study the effectof LC emitter degeneration on the phase noise of the Colpittsoscillator. The phase noise of a conventional Colpitts oscillator,based on Leeson’s model [30], is given by [31]

(5)

where denotes the phase noise spectral density,

is the average input white noise power of the transistor,is the tank swing, and is the offset from the carrier angularfrequency. It is shown in Appendix I that for a Colpitts oscillatorwith capacitive degeneration given by in (3), the phasenoise is expressed as

(6)

where is given by

(7)

and is the oscillation frequency of the emitter-degeneratedoscillator. Since , as discussed earlier, and(Appendix I), the denominator in (6) is always larger than thatin (5). Therefore, it can be inferred from (5)–(7) that LC degen-eration improves the phase noise of the Colpitts oscillator.

Since Leeson’s model does not account for the time-variantnature of the device-noise-to-phase-noise conversion, a lineartime-variant (LTV) model based on impulse sensitivity function(ISF) [32]–[34] is now used to examine the phase noise of the os-cillator topologies (see Appendix I for details). The phase noiseof the conventional Colpitts oscillator, taking only collector shotnoise and tank noise into account, is

(8)where is the Boltzmann’s constant, is the equivalent par-allel tank resistance, and is given by

(9)

The LC emitter-degenerated Colpitts oscillator exhibits a lowerphase noise (as shown in Appendix I) expressed as

(10)

where

(11)

Fig. 4. Schematic of the 77 GHz differential Colpitts VCO with LC emitter-degeneration.

Intuitively, the loaded quality factor of the tank is increased,because the frequency-dependent capacitance results ina steeper phase transition at the oscillation frequency [25]. Thefaster transition manifests itself into a direct improvement of thephase noise of the oscillator. It is noteworthy here that ifis a parallel LC network, the tank in Fig. 3 is readily identified asa fourth-order network. Recent work corroborates the potentialof higher-order networks in achieving high oscillation frequen-cies [17], [18], [24], [29], [35].

The circuit schematic of the 77 GHz VCO is shown in Fig. 4.Microstrip transmission lines and are used at the HBTbase terminals to realize small tank inductance ( 25 pH) witha high 20 . A center-tapped spiral inductor with 150 pHhalf-inductance is used to realize the emitter degeneration.As discussed above, the emitter degeneration also improvesthe tuning range of the oscillator because the fixed portion ofthe effective tank capacitance is reduced. Tail current sourcesconsisting of active devices are replaced by resistive biasingin order to avoid additional noise contributions. Moreover,LC emitter-degeneration helps in filtering the noise from thebias resistors. Metal–insulator–metal (MIM) capacitorsand (150 fF) are employed to implement the additionalbase-to-emitter capacitances. The linear MIM capacitors re-duce the effect of the voltage nonlinearity of the base-to-emitterdevice capacitances on the VCO phase noise. At 77 GHz, the

of 0.18 m MOS varactors is too low to sustain oscilla-tions with sufficient margin. Therefore, frequency tuning isachieved by using HBT varactors and (10 3 m)with variable base-to-collector junction capacitance of 85 fFto 110 fF . The simulated of the HBTvaractors is 10 at 77 GHz. The varactors are connected to theVCO tank through dc-blocking MIM capacitors and(0.5 pF), which operate beyond their self-resonant frequencies.Differential operation is achieved by connecting two MIMcapacitors and (55 fF) across the emitters of the twoHBTs, and (4 5.5 m). The VCO has been designedfor a center frequency of 78 GHz with a simulated tuning rangeof 4 GHz to compensate for process variations and modelingerrors. The VCO circuit draws 10 mA from a 2.5 V supply.



Fig. 5. 24 GHz cross-coupled VCO schematic.

At 24 GHz, a cross-coupled oscillator can be employed, asthe operating frequency is sufficiently lower than ,and the topology achieves acceptable phase noise. An additionaladvantage is that a cross-coupled pair LC oscillator requiressmaller loop gain than a Colpitts oscillator in order to start os-cillating. Therefore, the cross-coupled topology results in lowerpower dissipation for the 24 GHz VCO. The schematic of thedifferential LC oscillator used for the 24 GHz VCO is shownin Fig. 5. The center-tapped inductor (200 pH) and accumu-lation-mode MOS varactors and form the VCO tank.The varactor capacitance can be varied from 175 fF to 275 fF

. MIM capacitors and (0.75 pF)are employed to prevent forward biasing the base-to-collectorp-n junction. Similar to the 77 GHz VCO, resistive biasing isused instead of an active tail current source to avoid phase noisedegradation. The simulated tuning range of the VCO is from24 GHz to 28.5 GHz. The 24 GHz VCO requires a bias currentof 4 mA.

Each of the two VCOs is followed by two emitter-followerbuffer stages, to provide sufficient isolation from the outputload. The two VCO signals are then multiplexed together via anopen-collector differential amplifier stage. The open-collectoroutputs of the 24 GHz and 77 GHz differential buffer chainsare tied together and then connected to the load resistors. Adigital control signal is used to switch between the two bandsby turning on or off the NMOS tail current sources in the twodifferential pairs. At the same time, the unused VCO is disabledto avoid any leakage into the other band and to reduce powerdissipation.

B. Dual-Mode Injection-Locked Frequency Divider

As discussed in Section II, harmonic injection-lockedfrequency dividers are attractive at MMW frequencies as theyhave lower power consumption and lower phase noise thanstatic frequency dividers. Intuitively, ILFDs have lower powerconsumption as there is little energy loss in the tank in eachoscillation cycle, whereas more energy is required to chargeand discharge the device capacitances in static dividers. This isalso analogous to the difference between ring oscillators andLC oscillators, where LC oscillators can achieve higher oper-ation frequency and lower phase noise. These improvementsin the LC-tank-based injection-locked circuits are achieved at

Fig. 6. Schematic of the dual-mode injection-locked circuit. The table lists thefunctions realized by the circuit in different operating modes.

the expense of the operating frequency range of the circuit.Consequently, ILFDs suffer from a smaller locking range thanthat of static dividers.

In this work, an injection-locked circuit is employed to seam-lessly reconfigure the division ratio between the two bands of thefrequency synthesizer. The output of the ILC consists of a tanktuned in the 24 GHz band. When the input frequency is either77 GHz or 24 GHz, the ILC output is phase-locked to the inputsignal. In other words, the circuit implements two functions: (i)frequency-division by three for a 77 GHz input and, (ii) tunedbuffer for a 24 GHz input. Note that the ILC can not lock to a48 GHz input (second harmonic of 24 GHz), as discussed laterin this section.

Few injection-locked divide-by-three circuits operating in theMMW spectrum have been reported in the past [13], [36], [37].In this work, a cascode HBT-based injection-locked LC oscil-lator circuit, based on the work reported in [13] and [20], hasbeen designed to realize a division ratio of three. As mentionedbefore, a key feature of our design is its additional capabilityto act as an injection-locked oscillator for the fundamental fre-quency input. The ILC schematic is shown in Fig. 6. The circuitresembles a conventional cross-coupled LC VCO except that thetail current source has been replaced by an input pseudo-differ-ential pair consisting of two common-emitter HBT amplifiers

and . The stand-alone ILC has three modes of operationas described next. However, during proper functioning of thedual-band synthesizer, only Modes I and II are apparent. Never-theless, the third mode is critical for startup of the oscillations;we call it Mode 0.



Fig. 7. Equivalent circuit of the ILC in the free-running mode.

1) Mode 0: Free-Running Operation: If no signal is appliedat the input of the ILC, the circuit operates as a free-running os-cillator at 24 GHz. Although it may seem that the circuit will failto oscillate due to the emitter degeneration of the cross-coupledpair by the large output resistance of the HBT current sources,a closer examination proves otherwise. A simplified equivalentcircuit of the free-running ILC is shown in Fig. 7. The circuit isessentially a cross-coupled LC VCO with capacitive emitter de-generation. The capacitive degeneration, in fact, results in lowerpower consumption because it reduces the required negative re-sistance of the active cross-coupled pair [38]. The minimum re-quired transconductances for oscillation in the absence and pres-ence of capacitive degeneration are given by

(12)

and the quadratic equation

(13)

respectively [38], validating the lower required power dissipa-tion of the emitter-degenerated VCO.

2) Mode I: Injection-Locked Oscillator: If a differential 24GHz signal is applied at the ILC input, the output locks to theinput frequency, and the circuit essentially operates as a tunedbuffer. The LC tank provides the additional phase shift requiredto shift the output frequency from the free-running oscillationfrequency. The two-sided locking range of the ILC in thismode is given by [39]

(14)

where is the free-running tank frequency, is the tankquality factor, and is the injection strength.Injection-locked circuits typically suffer from a limited lockingrange. From (14), it is observed that the locking range canbe enhanced by increasing the injected signal power and byreducing the tank .

3) Mode II: Injection-Locked Divide-by-Three: In this mode,a 77 GHz differential signal is injected into the ILC input. Thisinjection signal modulates the free-running state of the LC

tank. Due to the nonlinearity of the active cross-coupled pair,several intermodulation products result from the multiplicationof the input signal and the tank oscillation. It is important tonote that the virtual ground of the differential pair in a conven-tional LC oscillator is non-existent in the ILC described here.Therefore, the even harmonics generated by the cross-coupledpair are not suppressed, enabling the divide-by-three operation(Appendix II). For a sufficiently large input signal, the ILCoutput is locked to the intermodulation product at one-thirdof the input frequency. As shown in Appendix II, the upperbound on the locking range of the divide-by-three ILC can beexpressed as

(15)

where and denote the small-signal conversion gain andthe second-order nonlinearity, respectively, of the equivalentmixer formed by the cross-coupled pair. It is noteworthy herethat the ratio is defined as the second-order interceptpoint of a circuit [40] and (15) can be recast as

(16)

It is readily inferred from (16) that lowering the (i.e., highereven-order circuit nonlinearity) of the cross-coupled pair willimprove the locking range of the divider.

As indicated by (14) and (15), the ILC has a smaller lockingrange in the divider mode than that in Mode I because istypically less than unity. To compensate for this and the lowergain at 77 GHz, higher current is drawn by the ILC in this mode.Alternatively, the current consumption in Mode I can be de-creased to obtain the same locking range as that in Mode II.Since the ILC locking range around its free-running frequencyis small, varactors are used to tune the center frequency of theILC. This necessitates the implementation of a calibration tech-nique to align the center frequency of the ILC to that of the VCO,so that the PLL can lock to the correct frequency (Section IV).

One may wonder if the ILC, operating in Mode I, would lockto the inevitable second harmonic of the 24 GHz input. Fortu-nately, the underlying differential operation of the cross-coupledpair precludes locking to the second harmonic of the input. Theeven harmonics of the input produce in-phase signals at the ILCoutput, as discussed in [41].

In accordance with the foregoing discussion, the tank , thevaractor ratio ( 1.4), and the input differential am-plifier gain have all been optimized in order to maximize thelocking range and the free-running tuning range of the ILC. Thetank inductance (200 pH) has a Q of 9 at 25 GHz and MOS var-actors (9 3 m 0.5 m) have been used to provide a tuningrange from 24.5 GHz to 28.3 GHz. The varactor finger lengthand width were optimized for a wide tuning range, at the ex-pense of a little degradation in . The ILC consumes 6 mA froma 2.5 V supply in Mode II. In Mode I, the ILC can successfullylock to the input signal with a bias current as low as 2 mA.

C. Divider Chain, PFD/CP and Loop Filter

It is clear from above that the output of the ILC is alwaysin the 24 GHz band. Static dividers can be used at these fre-



Fig. 8. Simplified schematic of the charge pump circuit.

quencies with reasonable power dissipation. In fact, static di-viders are the more suitable choice because LC-tank-based in-jection-locked dividers would be costly in terms of die area. Achain of five static emitter-coupled logic (ECL) dividers followsthe ILC and consumes only 15 mW from a 2.5 V supply. Threestatic flip-flop-based CMOS dividers further divide the signalfrequency down to the reference frequency of the synthesizer.The ECL divider chain is optimized for low power consump-tion and the voltage swing of the signal is gradually increasedthrough the cascaded ECL dividers by scaling up the load resis-tors in the latches. The output of the last ECL divider providesa differential peak-to-peak swing of 1.5 V, which is sufficientlylarge to completely switch the following CMOS divider. This, inturn, efficiently eliminates the need for an ECL-to-CMOS con-verter prior to the CMOS divider chain. The output of the en-tire divider chain provides a rail-to-rail signal at the input of thePFD, which is implemented as a standard tri-state topology.

The schematic of the charge pump circuit, inspired by thetopology in [42], is shown in Fig. 8. Cascode current sourcesreduce the effect of the VCO control voltage variation on thecharge pump UP/DOWN currents until comes within

of the supply rails, which in turn broadens the linearityof the PLL loop. Moreover, it reduces the UP/DOWN currentmismatch. The use of a dummy branch to steer the chargepump current for the duration when is not integratingany charge, in addition to the charge-injection and clockfeed-through cancellation provided by the dummy switches,significantly reduces the non-idealities of the charge pumpcircuit.

The loop filter is placed off-chip to compensate for modelingerrors in the MMW circuits. A Spectre-RF/Verilog-A co-sim-ulation methodology is adopted for closed-loop simulations ofthe frequency synthesizer. The PLL loop has been optimized fora target bandwidth of 1 MHz.

IV. EXPERIMENTAL RESULTS

The dual-band frequency synthesizer has been fabricated in a0.18 m 200/180 GHz SiGe BiCMOS process with sixmetal layers. The emitter width of the HBTs in the technology is0.15 m. The micrograph of the 1 mm 0.8 mm chip is shown

Fig. 9. Die micrograph of the 1� 0.8 mm dual-band synthesizer prototype.

in Fig. 9. The fabricated prototype also consists of a high-speeddigital baseband circuit, reported elsewhere [12], which occu-pies the top half of the die. The frequency synthesizer itself re-quires a chip area of about 0.4 mm only.

The 2.8- m-thick top metal is used to realize inductors andtransmission lines in the VCOs and the ILC. Stray couplingto the ILC tank can subdue the injection-locking phenomenonresulting in an erroneous output frequency or undesired side-bands, and can even throw the circuit out of lock [39]. Therefore,signal distribution and routing between building blocks havebeen accomplished carefully using the 1.6- m-thick penulti-mate metal layer to minimize coupling to the oscillator tanks inthe top-metal layer. Since transmission lines can provide excel-lent isolation between adjacent circuits, their use should be con-sidered when integrating injection-locked circuits in a complexsystem such as a transceiver. In this work and in [12], we havedemonstrated the functionality of the ILC in a synthesizer anda transceiver environment, respectively. All passives, includingMIM capacitors and interconnects, used in the synthesizer havebeen designed or characterized using planar 3-D electromag-netic simulations [43].

The synthesizer chip is attached to a PCB using achip-on-board assembly. All DC pads are wirebonded tothe PCB. The reference frequency input is provided by anon-board 50–125 MHz voltage controlled crystal oscillator(VCXO). With the PCB mounted on a probe station, thesynthesizer performance is characterized by on-wafer mea-surements. The 24 GHz mode is measured using a simplecoaxial setup. A WR-10 waveguide-based setup is used forthe 77 GHz mode, including an Agilent 11970 W harmonicmixer. A simplified version of the setup is shown in Fig. 10. Inorder to avoid any noise pick-up, the control voltage is isolatedfrom on-chip bias lines and the substrate using RF shieldingtechniques. The length of the wirebond from the pad tothe PCB was minimized and the control voltage wiring on thePCB was isolated from other on-board interconnects.

To measure the free-running performance of the VCOs, thedivider chain is disabled. As depicted in Fig. 11, the K-bandVCO achieves a tuning range from 23.68 GHz to 27 GHz whilethe W-band VCO can be tuned from 75.6 GHz to 78.6 GHz.



Fig. 10. Waveguide-based measurement setup for the synthesizer in theW-band mode. The basic setup for frequency calibration of the ILC is alsoshown.

Fig. 11. Measured (solid lines) and simulated (dashed lines) tuning curves ofthe free-running 24 GHz and 77 GHz VCOs.

The for the 24 GHz and 77 GHz VCOs are 3.9 GHz/Vand 1 GHz/V, respectively, in the linear portion of the tuningcurve. The error between the simulated and measured oscilla-tion frequencies is less than 2% for the 77 GHz oscillator and isslightly higher than 5% for the 24 GHz oscillator. The highererror for the 24 GHz VCO is attributed to the presence of athin but highly conductive diffusion layer on top of the siliconsubstrate, which resulted in an inaccurately modeled ground re-turn path for the spiral inductor in the tank. The 77 GHz VCOis unaffected because the base inductance is implemented asa microstrip line, which is shielded from the substrate by abottom-metal ground shield. The discrepancy for the 24 GHzVCO has been addressed in a newer version of the synthesizer,integrated within an MMW transceiver [12]. The free-runningVCOs achieve a phase noise better than 95 dBc/Hz at 1 MHzoffset from the carrier, as shown in Fig. 12.

The performance of the divide-by-three ILC is measured withthe on-chip W-band VCO as the injection-locking signal source.Fig. 13 shows the measured and simulated divider tuning range.The simulated tuning range extends from 70.1 GHz to 82.3 GHz.The measured tuning range is 75.6 to 78.6 GHz, which is limitedby the VCO tuning range. Since a circuit breakout of the ILCwas unavailable, the divider locking performance could not beverified outside this range. Nevertheless, fairly good model-to-hardware correlation is obtained within the measured tuningrange, validating the divider functionality adequately. The sim-ulated locking range is also shown in Fig. 13, as a function ofthe divider control voltage, and varies from 1.8 GHz to 2.7 GHz

Fig. 12. Measured phase noise of the free-running VCOs.

Fig. 13. Measured (dashed lines) and simulated (solid lines) tuning and lockingranges of the ILC in divide-by-three mode (Mode II). The measured dividertuning range is limited by the tuning range of the on-chip 77 GHz VCO.

Fig. 14. Simulated input sensitivity of the divide-by-three injection-locked cir-cuit at different � settings.

across the divider tuning range. The input power in the simula-tion results of Fig. 13 is set to 5 dBm, which is the designedpower level at the input of the divider. The simulated sensitivitycurves of the divider are shown in Fig. 14. With a higher inputpower, the divider achieves a locking range as high as 6.95 GHzwhich, combined with the tuning capability, results in a wide



TABLE ICOMPARISON OF STATE-OF-THE-ART MILLIMETER-WAVE DIVIDE-BY-THREE CIRCUITS

Fig. 15. Measured output spectrum of the synthesizer in (a) the W-band mode and (b) the K-band mode. Measurement setup losses have not been de-embedded.

input frequency range from 68.7 GHz to 85 GHz. The simu-lated suppression of the second harmonic of the divider outputfrequency is more than 33 dB below the fundamental. Table Icompares the performance of the divide-by-three ILC with priorart.

In frequency synthesizers that consist of an injection-lockeddivider within the PLL loop, a critical requirement for the loopto lock is that either (i) the divider locking range captures theVCO tuning range completely or, (ii) a mechanism is providedto tune the divider center frequency to within the VCO tuningrange. Prior art in the MMW domain includes driving the VCOand the injection-locked divider by the same control voltage[15], and off-chip calibration of the divider control voltage [21].Recently, on-chip digital calibration of the divider has also beenreported [16]. In this work, a software-based calibration usingMatlab and GPIB control has been employed to tune the ILCcontrol voltage until the loop is locked. As shown in the mea-surement setup of Fig. 10, the VCO control voltage is monitoredon an oscilloscope and a lock condition is detected when it set-tles to a constant voltage. Note that an on-chip calibration canbe readily implemented in a revised version.

In the locked state, the measured output spectrum of the syn-thesizer in the two bands is shown in Fig. 15. In each mode,the reference spurs at the output are 47–50 dB below the car-rier power level. The locking range of the synthesizer in theK-band is from 23.8 GHz to 26.95 GHz and in the W-band isfrom 75.67 GHz to 78.5 GHz. The synthesizer output delivers

Fig. 16. Measured closed-loop phase noise of the synthesizer in the two bands.Reference phase noise is limited by the noise floor of the measurement setup.

an output power of 9.5 dBm at 25.6 GHz and 17.8 dBm at76.8 GHz after de-embedding the losses of the waveguide probe,harmonic mixer, cables and other components of the measure-ment fixture.

The closed-loop phase noise performance of the synthesizeris depicted in Fig. 16. Phase noise of the reference input isalso plotted in the same figure. At 100 kHz, 1 MHz, and



TABLE IISUMMARY OF THE MEASURED PERFORMANCE

TABLE IIIPERFORMANCE COMPARISON OF MILLIMETER-WAVE FREQUENCY SYNTHESIZERS

10 MHz offsets from the carrier, the locked 24 GHz VCOoutput shows a phase noise of 112 dBc/Hz, 114 dBc/Hz,and 117 dBc/Hz, respectively. The corresponding phasenoise of the locked 77 GHz VCO output is 102 dBc/Hz,

103.5 dBc/Hz, and 116 dBc/Hz, respectively. Jumps inthe phase noise plots of Fig. 16 are observed at frequency offsetsslightly greater than the loop bandwidth. This behavior occursbecause the PLL output phase noise is no longer suppressed bythe closed-loop dynamics. Also note that the synthesizer phasenoise is not flat at frequency offsets less than 10 kHz, unlikethe typical PLL characteristics reported in literature. This isbecause the synthesizer output follows the phase noise of thehigh-quality (i.e., low phase noise) voltage-controlled crystaloscillator used to provide the reference signal, which exhibitssimilar phase noise behavior as shown in Fig. 16. The referencephase noise shown in Fig. 16 is limited by the measurementnoise floor.

The frequency synthesizer consumes 50 mW in the 24 GHzmode and 75 mW in the 77 GHz mode. A single 2.5 V supplyis needed for the entire synthesizer. The 77 GHz and 24 GHzVCOs require 10 mA and 4 mA, respectively. The ILC con-sumes a maximum of 6 mA.

The measured performance of the dual-band synthesizeris summarized in Table II. The authors are unaware of otherimplementations of MMW dual-band frequency synthesizers.Nevertheless, it is fair to compare the performance withsingle-frequency prior art in the MMW spectrum. Table IIIprovides a comparative list of state-of-the-art MMW frequencysynthesizers.

V. CONCLUSIONS AND FUTURE WORK

A new dual-band architecture for MMW frequency syn-thesizers utilizing multiple modes of operation of an injec-tion-locked circuit has been described. A highly-integratedsynthesizer prototype chip has been designed and implementedin a 0.18 m BiCMOS technology. The versatile synthesizerarchitecture targets 24/77 GHz automotive radars, and is alsosuitable for 94 GHz imaging applications. Measurements of thefabricated prototype demonstrate excellent results, including alocking range of 23.8-to-26.95 GHz and 75.67-to-78.5 GHz.Detailed design and analysis of a dual-mode injection-lockedcircuit, operating either as a divide-by-three or as a tuned buffer,have been described. To the authors’ best knowledge, the di-vide-by-three circuit achieves the highest operating frequency



reported to date inside a synthesizer loop. This work reveals thefirst step toward the realization of fully-integrated dual-bandMMW radar transceivers. Efforts toward generating dual-bandquadrature signals and further reducing the component-countin dual-band synthesizers and transceivers are currently inprogress.

APPENDIX IOSCILLATION AMPLITUDE AND PHASE NOISE OF COLPITTS AND

LC EMITTER-DEGENERATED OSCILLATOR TOPOLOGIES

Oscillation Amplitude: The steady-state base-to-emittervoltage for a Colpitts oscillator is given by [44]

(A.1)

where is the collector bias current and is the minimumrequired transconductance for oscillation. For the conventionalColpitts oscillator, (A.1) can be written as

(A.2)

where is the series tank resistance. Replacing by its par-allel equivalent resistor , we get

(A.3)

resulting in a peak oscillation amplitude of

(A.4)

For the LC emitter-degenerated oscillator,

(A.5)

from which we obtain

(A.6)

It is clear from (A.4) and (A.6) that for a given bias current,LC emitter degeneration provides more flexibility in setting theoscillation amplitude compared to the conventional Colpittstopology. Assuming the same for the two topologies3 andassuming that the tank capacitors are kept constant for thepurpose of comparison (which implies that the inductors in thetank are varied to obtain the same oscillation frequency for thetwo topologies), we can obtain the ratio of the two oscillationamplitudes as

(A.7)

3In our design (and for W-band silicon-based designs in general), the tankresistance is dominated by varactor loss, validating this assumption.

for the same oscillation frequencies. Since ,and therefore, is always greater than .

Phase Noise Analysis Using Leeson’s Model: From [31],the phase noise of the Colpitts oscillator can be expressedas

(A.8)

where is the element of the ABCD matrix of the feed-back network (i.e., the tank), , and is theimaginary part of the element of the matrix. For a Colpittsoscillator, and

(A.9)

Replacing by , differentiating with respect to ,and then setting , we obtain, for an LC emitter-degenerated oscillator,

(A.10)

From (3),

(A.11)

(A.12)

where is given by (7). Substituting (A.11) and (A.12) in(A.10), we obtain

(A.13)

Substituting the values of and in (A.8) and rearrangingthe result, we obtain the expression for the close-in phase noiseof an emitter-degenerated Colpitts oscillator as

(A.14)The phase noise of the conventional Colpitts topology is

readily obtained from (A.14) by replacing with 0,

(A.15)

Phase Noise Analysis Using Linear Time-Variant Model:Following the analysis in [34] for a Colpitts oscillator, the phasenoise due to collector current noise can be expressed as

(A.16)



and that due to as

(A.17)

The overall phase noise for the conventional Colpitts topologyis then given by

(A.18)

As discussed earlier, the LC degeneration impedance appearscapacitive at the oscillation frequency of the emitter-degener-ated oscillator. Therefore, the current and voltage waveformsof the emitter-degenerated oscillator are similar to those of theconventional Colpitts oscillator. This in turn implies that the de-vice noise currents are injected into the tank at the voltage peaks,thereby reducing the amount of device noise conversion to phasenoise [32]. Thus, the phase noise analysis carried out for theColpitts topology is also valid for the LC emitter-degeneratedoscillator topology.

By substituting with andwith in (A.18), the phase noise of an LC emitter-degener-ated Colpitts oscillator is readily expressed as

(A.19)

The ratio of the phase noises of the two oscillator topologiesis

(A.20)

Using the result of (A.7), and with the same assumptions, (A.20)is simplified to

(A.21)

Since , the ratio in (A.21) is always less than1, indicating that the LC emitter-degenerated topology exhibitsbetter phase noise than the conventional Colpitts oscillator.

From the foregoing analysis, the importance of using a lineartime-variant model is clearly seen. In (A.8) and (A.14), alldevice noise sources are converted to phase noise by the sametransfer function, whereas (A.16)–(A.19) indicate differenttransfer functions for different noise sources. The key conceptthat enables higher accuracy in the LTV model is the impulsesensitivity function (ISF), which is different for different noisesources and different circuit topologies [32]. Furthermore, theISF takes into account the cyclo-stationary nature of devicenoise sources, whereas the Leeson’s model treats all noisesources as stationary processes.

Fig. 17. Behavioral model of the divide-by-three injection-locked frequencydivider.

APPENDIX IILOCKING RANGE OF AN LC-TANK-BASED INJECTION-LOCKED

DIVIDE-BY-THREE CIRCUIT

Fig. 17 shows a behavioral model for the analysis of an in-jection-locked divide-by-three circuit. The mixer output currentcan be expressed as [41]

(A.22)

where are the mixer nonlinearity coefficients and is the di-vider output phase. The fundamental component of , limitingthe products to the fourth-order nonlinearity, is

(A.23)

from which the phase of the mixer output can be computed as

(A.24)

where .The phase shift introduced by the tank is given by

(A.25)

and since , we obtain

(A.26)

After converting (A.26) into exponential form and solving theresulting quadratic equation, we get

(A.27)

where . Applying the identity , ne-glecting the terms and simplifying, we obtain the relation

(A.28)



The maximum two-sided locking range is then readily com-puted as

(A.29)

ACKNOWLEDGMENT

The authors acknowledge helpful discussions withDr. M. Wiklund of FLA, Prof. B. Razavi of UCLA,S. Sundararaman of Avago Technologies, A. Goel of USC, andC.-C. Wang, Z. Chen, F. Tzeng, and L. Zhou of UCI. Theyare indebted to the anonymous reviewers for their diligentcomments and suggestions. Technical support from SonnetSoftware is highly appreciated.

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Vipul Jain (S’01) was born in India in 1983. He re-ceived the B.Tech. degree in electronics engineeringfrom the Kamla Nehru Institute of Technology(KNIT), Sultanpur, India, in 2004, and the M.S.degree in electrical engineering from the Universityof California, Irvine, CA, in 2007. He is currentlyworking toward the Ph.D. degree at UC Irvine.

He was a summer intern at Skyworks Solutions,Irvine, CA, and Fujitsu Laboratories of America,Sunnyvale, CA, in 2005 and 2006, respectively.During the summer of 2008, he was a research intern

at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where heworked on integrated circuits for millimeter-wave imaging receivers. His re-search interests include high-frequency integrated circuit design for automotiveradars, wireless communications, and imaging applications.

Mr. Jain served as the President of the IEEE student branch at KNIT in 2003.He was the recipient of the 2009 EECS Ph.D. Dissertation Fellowship and the2005 Center for Pervasive Communications and Computing Fellowship at UCIrvine. He was also a member of the team that won the 2009 Business PlanCompetition at the Paul Merage School of Business, UC Irvine.

Babak Javid received the B.Sc. degree in electricalengineering in 2004 from Sharif University ofTechnology, Tehran, Iran, and the M.A.Sc. degree inelectrical engineering in 2006 from the University ofToronto, Toronto, ON, Canada.

During the summer of 2007, he was an intern at theBosch Research and Technology Center, Palo Alto,CA, where he worked on the measurement of a high-resolution incremental ADC. From 2007 to 2008, hewas with Wilinx, Carlsbad, CA, as an RF/Analog De-sign Engineer where he was working on designing

CMOS transceiver RF front-end for UWB systems. His research interests in-clude the design of RF, analog, mixed-signal, and data conversion circuits.

Mr. Javid was a recipient of the Silver Medal in National MathematicsOlympiad in both 1998 and 1999. He was also a recipient of the Department ofElectrical and Computer Engineering Fellowship from University of Toronto.

Payam Heydari (S’98–M’00–SM’07) received theB.S. and M.S. degrees (with honors) in electrical en-gineering from the Sharif University of Technologyin 1992 and 1995, respectively. He received the Ph.D.degree in electrical engineering from the Universityof Southern California in 2001.

During the summer of 1997, he was with BellLabs, Lucent Technologies, Murray Hill, NJ, wherehe worked on noise analysis in deep submicron verylarge-scale integrated (VLSI) circuits. During thesummer of 1998, he was with IBM T. J. Watson

Research Center, Yorktown Heights, NY, where he worked on gradient-basedoptimization and sensitivity analysis of custom-integrated circuits. In August2001, he joined the University of California, Irvine, where he is currentlyan Associate Professor of Electrical Engineering and Associate Chair forGraduate Affairs. His research interests include the design of high-speedanalog, radio-frequency (RF), and mixed-signal integrated circuits. He is the(co)-author of one book and more than 70 journal and conference papers.

Dr. Heydari is the co-recipient of the 2009 Business Plan Competition FirstPlace Prize Award from Paul Merage School of Business at UC-Irvine. He isthe recipient of the 2009 School of Engineering Fariborz Maseeh Best FacultyResearch Award, the 2007 IEEE Circuits and Systems Society Guillemin-CauerAward, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005National Science Foundation (NSF) CAREER Award, the 2005 Henry SamueliSchool of Engineering Teaching Excellence Award, the Best Paper Award at the2000 IEEE International Conference on Computer Design (ICCD), and the 2001Technical Excellence Award from the Association of Professors and Scholars ofIranian Heritage (APSIH). He was recognized as the 2004 Outstanding Facultyin the EECS Department of the University of California, Irvine. His researchon novel low-power multi-purpose multi-antenna RF front-ends received theLow-Power Design Contest Award at the 2008 IEEE International Symposiumon Low-Power Electronics and Design (ISLPED).

Dr. Heydari has been a Guest Editor of IEEE JOURNAL OF SOLID-STATE

CIRCUITS. He currently serves on the Technical Program Committees ofCustom Integrated Circuits Conference (CICC) and International Symposiumon Low-Power Electronics and Design (ISLPED). He was an Associate Editorof the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - PART I from 2006 to2008. He was the Student Design Contest Judge for the DAC/ISSCC DesignContest Award in 2003, the Technical Program Committee member of theIEEE Design and Test in Europe (DATE), International Symposium on QualityElectronic Design (ISQED), and International Symposium on Physical Design(ISPD).


Documents

2100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. …newport.eecs.uci.edu/~Payam/DualBand_MMW_VCO.pdf: A BICMOS DUAL-BAND MILLIMETER-WAVE FREQUENCY SYNTHESIZER FOR AUTOMOTIVE