216b 16gb 2c0f Mobile Lpddr3

Mobile LPDDR3 SDRAMEDFA164A1PB, EDFA164A1PK

Features Ultra-low-voltage core and I/O power supplies Frequency range

800/933 MHz (data rate: 1600/1866 Mb/s/pin) 8n prefetch DDR architecture 8 internal banks for concurrent operation Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_cedge

Bidirectional/differential data strobe per byte ofdata (DQS_t/DQS_c)

Programmable READ and WRITE latencies (RL/WL) Burst length: 8 Per-bank refresh for concurrent operation Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor Partial-array self refresh (PASR) Deep power-down mode (DPD) Selectable output drive strength (DS) Clock-stop capability On-die termination (ODT) Lead-free (RoHS-compliant) and halogen-free

packaging

Options VDD1/VDD2/VDDCA/VDDQ: 1.8V/1.2V/1.2V/1.2V Array configuration

256 Meg x 64 (QDP) Packaging

15mm x 15mm, 216-ball PoP FBGA package Operating temperature range

From 30C to +85C

Table 1: Configuration Addressing

Architecture 256 Meg x 64

Density per package 16Gb

Die per package 4

Ranks (CS_n) per channel 2

Die per channel 2

Configuration 16 Meg x 32 x 8 banks x 2 rank x 2 channel

Row addressing 16K A[13:0]

Column addressing (same for each die) 1K A[9:0]

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMFeatures

PDF: 09005aef85b4b06b216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN 1

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Key Timing Parameters

SpeedGrade

Clock Rate(MHz)

Data Rate(Mb/s/pin) WRITE Latency (Set A) READ Latency

GD 800 1600 6 12

JD 933 1866 6 12

Table 3: Part Number Description

PartNumber

TotalDensity Configuration Ranks Channels

PackageSize

BallPitch

EDFA164A1PB-GD-F-DEDFA164A1PB-GD-F-R

16Gb 256 Meg x 64 2 2 15mm x 15mm(1.0 mm MAX height)

0.50mm

EDFA164A1PK-JD-F-DEDFA164A1PK-JD-F-REDFA164A1PK-GD-F-DEDFA164A1PK-GD-F-R

16Gb 256 Meg x 64 2 2 15mm x 15mm(0.8 mm MAX height)

0.50mm

Figure 1: Marketing Part Number Chart

E D F A1 64 A F

Micron Technology

TypeD = Packaged device

Product FamilyF = Mobile LPDDR3 SDRAM

Density/Chip SelectA1 = 16Gb/4-CS (2-CS/channel)

Organization64 = x64

Power Supply InterfaceA = VDD1 = 1.8V, VDD2 = VDDCA = VDDQ = 1.2V,

S8 device, HSUL_12

1 PB GD- - D

Packing MediaD = Dry Pack (Tray)R = Tape and Reel

Environment CodeF = Lead-free (RoHS-compliant)

and halogen-free

SpeedGD = 1600 MbpsJD = 1866 Mbps

PackagePB = BGA for PoPPK = BGA for Pop

Revision

-

Note: 1. The characters highlighted in gray indicate the physical part marking found on the device.




ContentsBall Assignments ............................................................................................................................................ 10Ball Descriptions ............................................................................................................................................ 10Package Block Diagrams ................................................................................................................................. 12Package Dimensions ....................................................................................................................................... 13MR0MR3, MR5MR8, MR11 Contents ............................................................................................................ 15IDD Specifications Quad Die, Dual Channel ................................................................................................... 17Pin Capacitance ............................................................................................................................................. 21AC Timing ...................................................................................................................................................... 22LPDDR3 Array Configuration .......................................................................................................................... 29

General Notes ............................................................................................................................................ 29Functional Description ................................................................................................................................... 30Simplified Bus Interface State Diagram ............................................................................................................ 32Power-Up and Initialization ............................................................................................................................ 34

Voltage Ramp and Device Initialization ....................................................................................................... 34Initialization After Reset (Without Voltage Ramp) ........................................................................................ 36

Power-Off Sequence ....................................................................................................................................... 37Uncontrolled Power-Off Sequence .............................................................................................................. 37

Standard Mode Register Definition .................................................................................................................. 38Mode Register Assignments and Definitions ................................................................................................ 38

Commands and Timing .................................................................................................................................. 47ACTIVATE Command ..................................................................................................................................... 48

8-Bank Device Operation ............................................................................................................................ 48Read and Write Access Modes ......................................................................................................................... 49Burst READ Command ................................................................................................................................... 50

tDQSCK Delta Timing ................................................................................................................................. 52Burst WRITE Command .................................................................................................................................. 56Write Data Mask ............................................................................................................................................. 60PRECHARGE Command ................................................................................................................................. 61

Burst READ Operation Followed by PRECHARGE ......................................................................................... 62Burst WRITE Followed by PRECHARGE ....................................................................................................... 63Auto Precharge ........................................................................................................................................... 64Burst READ with Auto Precharge ................................................................................................................. 64Burst WRITE with Auto Precharge ............................................................................................................... 65

REFRESH Command ...................................................................................................................................... 67REFRESH Requirements ............................................................................................................................. 70

SELF REFRESH Operation ............................................................................................................................... 72Partial-Array Self Refresh (PASR) Bank Masking ......................................................................................... 73Partial-Array Self Refresh Segment Masking .............................................................................................. 73

MODE REGISTER READ ................................................................................................................................. 75MRR Following Idle Power-Down State ........................................................................................................ 76Temperature Sensor ................................................................................................................................... 77DQ Calibration ........................................................................................................................................... 78

MODE REGISTER WRITE ................................................................................................................................ 79MRW RESET Command .............................................................................................................................. 80MRW ZQ Calibration Commands ................................................................................................................ 81ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 84MRW CA Training Mode ........................................................................................................................... 84MRW - Write Leveling Mode ........................................................................................................................ 86

On-Die Termination (ODT) ............................................................................................................................. 88ODT Mode Register .................................................................................................................................... 88




Asychronous ODT ...................................................................................................................................... 88ODT During READ Operations (READ or MRR) ............................................................................................ 89ODT During Power-Down ........................................................................................................................... 89ODT During Self Refresh ............................................................................................................................. 89ODT During Deep Power-Down .................................................................................................................. 89ODT During CA Training and Write Leveling ................................................................................................ 89

Power-Down .................................................................................................................................................. 92Deep Power-Down ......................................................................................................................................... 98Input Clock Frequency Changes and Stop Events ............................................................................................. 99

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 99Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 100

NO OPERATION Command ........................................................................................................................... 100Truth Tables .................................................................................................................................................. 101Absolute Maximum Ratings ........................................................................................................................... 108Electrical Specifications IDD Measurements and Conditions ......................................................................... 109

IDD Specifications ...................................................................................................................................... 110AC and DC Operating Conditions ................................................................................................................... 113AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 114

VREF Tolerances ......................................................................................................................................... 115Input Signal .............................................................................................................................................. 116

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 118Single-Ended Requirements for Differential Signals .................................................................................... 119Differential Input Crosspoint Voltage ......................................................................................................... 120Input Slew Rate ......................................................................................................................................... 122

Output Characteristics and Operating Conditions ........................................................................................... 123Single-Ended Output Slew Rate .................................................................................................................. 123Differential Output Slew Rate ..................................................................................................................... 125HSUL_12 Driver Output Timing Reference Load ......................................................................................... 127

Output Driver Impedance .............................................................................................................................. 128Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 129Output Driver Temperature and Voltage Sensitivity ..................................................................................... 129Output Impedance Characteristics Without ZQ Calibration ......................................................................... 130ODT Levels and I-V Characteristics ............................................................................................................ 134

Clock Specification ........................................................................................................................................ 135tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 136

Clock Period Jitter .......................................................................................................................................... 136Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 136Cycle Time Derating for Core Timing Parameters ........................................................................................ 137Clock Cycle Derating for Core Timing Parameters ....................................................................................... 137Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 137Clock Jitter Effects on Read Timing Parameters ........................................................................................... 137Clock Jitter Effects on Write Timing Parameters .......................................................................................... 138

Refresh Requirements .................................................................................................................................... 139AC Timing ..................................................................................................................................................... 140CA and CS_n Setup, Hold, and Derating .......................................................................................................... 147Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 154Revision History ............................................................................................................................................ 161

Rev. B 09/14 ............................................................................................................................................ 161Rev. A 06/14 ............................................................................................................................................ 161




List of FiguresFigure 1: Marketing Part Number Chart ............................................................................................................ 2Figure 2: 216-Ball Dual-Channel FBGA 4 x 4Gb Die ...................................................................................... 10Figure 3: Quad-Die, Dual-Channel Package Block Diagram ............................................................................. 12Figure 4: 216-Ball FBGA (15mm x 15mm) EDFA164A1PB .............................................................................. 13Figure 5: 216-Ball FBGA (15mm x 15mm) EDFA164A1PK .............................................................................. 14Figure 6: Functional Block Diagram ............................................................................................................... 31Figure 7: Simplified State Diagram ................................................................................................................. 33Figure 8: Voltage Ramp and Initialization Sequence ........................................................................................ 36Figure 9: Command and Input Setup and Hold ............................................................................................... 47Figure 10: CKE Input Setup and Hold ............................................................................................................. 47Figure 11: ACTIVATE Command .................................................................................................................... 48Figure 12: tFAW Timing .................................................................................................................................. 49Figure 13: READ Output Timing ..................................................................................................................... 50Figure 14: Burst READ RL = 12, BL = 8, tDQSCK > tCK ................................................................................... 50Figure 15: Burst READ RL = 12, BL = 8, tDQSCK < tCK ................................................................................... 51Figure 16: Burst READ Followed by Burst WRITE RL = 12, WL = 6, BL = 8 ....................................................... 51Figure 17: Seamless Burst READ RL = 6, BL = 8, tCCD = 4 .............................................................................. 52Figure 18: tDQSCKDL Timing ........................................................................................................................ 53Figure 19: tDQSCKDM Timing ....................................................................................................................... 54Figure 20: tDQSCKDS Timing ......................................................................................................................... 55Figure 21: Data Input (WRITE) Timing ........................................................................................................... 56Figure 22: Burst WRITE ................................................................................................................................. 57Figure 23: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 57Figure 24: Method for Calculating tWPST Transitions and Endpoints ............................................................... 58Figure 25: Burst WRITE Followed by Burst READ ............................................................................................ 58Figure 26: Seamless Burst WRITE WL = 4, BL = 8, tCCD = 4 ............................................................................ 59Figure 27: Data Mask Timing ......................................................................................................................... 60Figure 28: Write Data Mask Second Data Bit Masked .................................................................................... 60Figure 29: Burst READ Followed by PRECHARGE BL = 8, RU(tRTP(MIN)/tCK) = 2 ........................................... 62Figure 30: Burst WRITE Followed by PRECHARGE BL = 8 .............................................................................. 63Figure 31: LPDDR3 Burst READ with Auto Precharge .................................................................................... 64Figure 32: Burst WRITE with Auto Precharge BL = 8 ...................................................................................... 65Figure 33: REFRESH Command Timing .......................................................................................................... 69Figure 34: Postponing REFRESH Commands .................................................................................................. 69Figure 35: Pulling In REFRESH Commands .................................................................................................... 69Figure 36: All-Bank REFRESH Operation ........................................................................................................ 71Figure 37: Per-Bank REFRESH Operation ....................................................................................................... 71Figure 38: SELF REFRESH Operation .............................................................................................................. 73Figure 39: MRR Timing .................................................................................................................................. 75Figure 40: READ to MRR Timing .................................................................................................................... 76Figure 41: Burst WRITE Followed by MRR ...................................................................................................... 76Figure 42: MRR After Idle Power-Down Exit .................................................................................................... 77Figure 43: Temperature Sensor Timing ........................................................................................................... 78Figure 44: MR32 and MR40 DQ Calibration Timing ......................................................................................... 79Figure 45: MODE REGISTER WRITE Timing ................................................................................................... 80Figure 46: MODE REGISTER WRITE Timing for MRW RESET .......................................................................... 81Figure 47: ZQ Timings ................................................................................................................................... 83Figure 48: CA Training Timing ....................................................................................................................... 84Figure 49: Write-Leveling Timing ................................................................................................................... 87Figure 50: Functional Representation of On-Die Termination .......................................................................... 88




Figure 51: Asynchronous ODT Timing RL = 12 ............................................................................................. 90Figure 52: Automatic ODT Timing During READ Operation RL = m ............................................................... 91Figure 53: ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit ................................. 91Figure 54: Power-Down Entry and Exit Timing ................................................................................................ 93Figure 55: CKE Intensive Environment ........................................................................................................... 93Figure 56: REFRESH to REFRESH Timing in CKE Intensive Environments ....................................................... 94Figure 57: READ to Power-Down Entry ........................................................................................................... 94Figure 58: READ with Auto Precharge to Power-Down Entry ............................................................................ 95Figure 59: WRITE to Power-Down Entry ......................................................................................................... 95Figure 60: WRITE with Auto Precharge to Power-Down Entry .......................................................................... 96Figure 61: REFRESH Command to Power-Down Entry .................................................................................... 96Figure 62: ACTIVATE Command to Power-Down Entry ................................................................................... 97Figure 63: PRECHARGE Command to Power-Down Entry ............................................................................... 97Figure 64: MRR Power-Down Entry ................................................................................................................ 98Figure 65: MRW Command to Power-Down Entry .......................................................................................... 98Figure 66: Deep Power-Down Entry and Exit Timing ....................................................................................... 99Figure 67: VREF DC Tolerance and VREF AC Noise Limits ................................................................................. 115Figure 68: LPDDR3-1600 to LPDDR3-1333 Input Signal ................................................................................. 116Figure 69: LPDDR3-2133 to LPDDR3-1866 Input Signal ................................................................................. 117Figure 70: Differential AC Swing Time and tDVAC .......................................................................................... 118Figure 71: Single-Ended Requirements for Differential Signals ....................................................................... 119Figure 72: VIX Definition ............................................................................................................................... 121Figure 73: Differential Input Slew Rate Definition for CK and DQS .................................................................. 122Figure 74: Single-Ended Output Slew Rate Definition ..................................................................................... 124Figure 75: Differential Output Slew Rate Definition ........................................................................................ 125Figure 76: Overshoot and Undershoot Definition ........................................................................................... 126Figure 77: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 127Figure 78: Output Driver ............................................................................................................................... 128Figure 79: Output Impedance = 240, I-V Curves After ZQRESET ................................................................... 132Figure 80: Output Impedance = 240, I-V Curves After Calibration ................................................................. 133Figure 81: ODT Functional Block Diagram .................................................................................................... 134Figure 82: Typical Slew Rate and tVAC tIS for CA and CS_n Relative to Clock ................................................. 150Figure 83: Typical Slew Rate tIH for CA and CS_n Relative to Clock ............................................................... 151Figure 84: Tangent Line tIS for CA and CS_n Relative to Clock ...................................................................... 152Figure 85: Tangent Line tIH for CA and CS_n Relative to Clock ..................................................................... 153Figure 86: Typical Slew Rate and tVAC tDS for DQ Relative to Strobe ............................................................. 157Figure 87: Typical Slew Rate tDH for DQ Relative to Strobe ........................................................................... 158Figure 88: Tangent Line tDS for DQ with Respect to Strobe .......................................................................... 159Figure 89: Tangent Line tDH for DQ with Respect to Strobe .......................................................................... 160




List of TablesTable 1: Configuration Addressing ................................................................................................................... 1Table 2: Key Timing Parameters ....................................................................................................................... 2Table 3: Part Number Description .................................................................................................................... 2Table 4: Ball/Pad Descriptions ....................................................................................................................... 11Table 5: Mode Register Contents .................................................................................................................... 15Table 6: IDD Specifications ............................................................................................................................. 17Table 7: IDD6 Partial-Array Self Refresh Current at 45C .................................................................................... 20Table 8: IDD6 Partial-Array Self Refresh Current at 85C .................................................................................... 20Table 9: Input/Output Capacitance ................................................................................................................ 21Table 10: AC Timing ...................................................................................................................................... 22Table 11: Voltage Ramp Conditions ................................................................................................................ 34Table 12: Initialization Timing Parameters ...................................................................................................... 36Table 13: Power Supply Conditions ................................................................................................................ 37Table 14: Power-Off Timing ............................................................................................................................ 37Table 15: Mode Register Assignments ............................................................................................................. 38Table 16: MR0 Device Feature 0 (MA[7:0] = 00h) .............................................................................................. 39Table 17: MR0 Op-Code BIt Definitions .......................................................................................................... 39Table 18: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 40Table 19: MR1 Op-Code Bit Definitions .......................................................................................................... 40Table 20: Burst Sequence ............................................................................................................................... 40Table 21: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 40Table 22: MR2 Op-Code Bit Definitions .......................................................................................................... 41Table 23: LPDDR3 READ and WRITE Latency ................................................................................................. 41Table 24: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 42Table 25: MR3 Op-Code Bit Definitions .......................................................................................................... 42Table 26: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 42Table 27: MR4 Op-Code Bit Definitions .......................................................................................................... 42Table 28: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 43Table 29: MR5 Op-Code Bit Definitions .......................................................................................................... 43Table 30: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 43Table 31: MR6 Op-Code Bit Definitions .......................................................................................................... 43Table 32: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 43Table 33: MR7 Op-Code Bit Definitions .......................................................................................................... 43Table 34: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 43Table 35: MR8 Op-Code Bit Definitions .......................................................................................................... 44Table 36: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 44Table 37: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 44Table 38: MR10 Op-Code Bit Definitions ........................................................................................................ 44Table 39: MR11 ODT Control (MA[7:0] = 0Bh) ................................................................................................. 45Table 40: MR11 Op-Code Bit Definitions ........................................................................................................ 45Table 41: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 45Table 42: MR16 Op-Code Bit Definitions ........................................................................................................ 45Table 43: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 45Table 44: MR17 PASR Segment Mask Definitions ............................................................................................ 45Table 45: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 46Table 46: MR63 RESET (MA[7:0] = 3Fh) MRW Only ....................................................................................... 46Table 47: Reserved Mode Registers ................................................................................................................. 46Table 48: Bank Selection for PRECHARGE by Address Bits ............................................................................... 61Table 49: PRECHARGE and Auto Precharge Clarification ................................................................................. 66Table 50: REFRESH Command Scheduling Separation Requirements .............................................................. 68




Table 51: Bank- and Segment-Masking Example ............................................................................................. 74Table 52: Temperature Sensor Definitions and Operating Conditions .............................................................. 77Table 53: Data Calibration Pattern Description ............................................................................................... 79Table 54: Truth Table for MRR and MRW ........................................................................................................ 80Table 55: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b)) .................................... 85Table 56: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b)) .................................... 85Table 57: CA to DQ Mapping (CA Training Mode Enabled with MR41) ............................................................. 85Table 58: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b)) .................................... 86Table 59: CA to DQ Mapping (CA Training Mode Enabled with MR48) ............................................................. 86Table 60: DRAM Termination Function in Write-Leveling Mode ...................................................................... 90Table 61: ODT States Truth Table ................................................................................................................... 90Table 62: Command Truth Table ................................................................................................................... 101Table 63: CKE Truth Table ............................................................................................................................. 102Table 64: Current State Bank n to Command to Bank n Truth Table ................................................................ 103Table 65: Current State Bank n to Command to Bank m Truth Table ............................................................... 105Table 66: DM Truth Table .............................................................................................................................. 108Table 67: Absolute Maximum DC Ratings ...................................................................................................... 108Table 68: Switching for CA Input Signals ........................................................................................................ 109Table 69: Switching for IDD4R ......................................................................................................................... 109Table 70: Switching for IDD4W ........................................................................................................................ 110Table 71: IDD Specification Parameters and Operating Conditions .................................................................. 111Table 72: Recommended DC Operating Conditions ....................................................................................... 113Table 73: Input Leakage Current ................................................................................................................... 113Table 74: Operating Temperature Range ........................................................................................................ 113Table 75: Single-Ended AC and DC Input Levels for CA and CS_n Inputs ......................................................... 114Table 76: Single-Ended AC and DC Input Levels for CKE ................................................................................ 114Table 77: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 114Table 78: Differential AC and DC Input Levels ................................................................................................ 118Table 79: CK and DQS Time Requirements Before Ringback (tDVAC) .............................................................. 119Table 80: Single-Ended Levels for CK and DQS .............................................................................................. 120Table 81: Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c) ..................................... 121Table 82: Differential Input Slew Rate Definition ............................................................................................ 122Table 83: Single-Ended AC and DC Output Levels .......................................................................................... 123Table 84: Differential AC and DC Output Levels ............................................................................................. 123Table 85: Single-Ended Output Slew Rate Definition ...................................................................................... 123Table 86: Single-Ended Output Slew Rate ...................................................................................................... 124Table 87: Differential Output Slew Rate Definition ......................................................................................... 125Table 88: Differential Output Slew Rate ......................................................................................................... 125Table 89: AC Overshoot/Undershoot Specification ......................................................................................... 126Table 90: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 129Table 91: Output Driver Sensitivity Definition ................................................................................................ 129Table 92: Output Driver Temperature and Voltage Sensitivity ......................................................................... 130Table 93: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 130Table 94: I-V Curves ..................................................................................................................................... 130Table 95: ODT DC Electrical Characteristics (RZQ After Proper ZQ Calibration) ..................................... 134Table 96: Definitions and Calculations .......................................................................................................... 135Table 97: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 136Table 98: Refresh Requirement Parameters (Per Density) ............................................................................... 139Table 99: AC Timing ..................................................................................................................................... 140Table 100: CA Setup and Hold Base Values ..................................................................................................... 147Table 101: CS_n Setup and Hold Base Values ................................................................................................. 148Table 102: Derating Values for AC/DC-Based tIS/tIH (AC150) ......................................................................... 148




Table 103: Derating Values for AC/DC-Based tIS/tIH (AC135) ......................................................................... 148Table 104: Required Time for Valid Transition tVAC > VIH(AC) and < VIL(AC) ..................................................... 149Table 105: Data Setup and Hold Base Values .................................................................................................. 155Table 106: Derating Values for AC/DC-Based tDS/tDH (AC150) ....................................................................... 155Table 107: Derating Values for AC/DC-Based tDS/tDH (AC135) ....................................................................... 155Table 108: Required Time for Valid Transition tVAC > VIH(AC) or < VIL(AC) ....................................................... 156




Ball Assignments

Figure 2: 216-Ball Dual-Channel FBGA 4 x 4Gb Die

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

Top View (ball down)GroundSupplyChannel BChannel A

1

NC

DQ17_B

DQ18_B

DQ21_B

DQ22_B

DM2_B

DQ1_B

DQ2_B

DQ4_B

DQ6_B

DQ8_B

DQ9_B

DQ10_B

1

2

DQ16_B

DQ19_B

DQ20_B

DQ23_B

DQS2_t_B

DQS2_c_B

DQS0_t_B

DQS0_c_B

DQS1_t_B

DQS1_c_B

DQS3_t_B

DQS3_c_B

DQS2_t_A

DQS2_c_A

DQS0_t_A

DQS0_c_A

DQS1_t_A

DQS1_c_A

DQS3_t_A

DQS3_c_A

CK_c_A

CK_t_A CKE1_A

CKE0_A CS0_n_A

CS0_n_B

CK_t_B CK_c_B

CS1_n_B

CS1_n_A

DQ0_B

DQ3_B

DQ5_B

DQ7_B

DM0_B

NC

ODT_B

DM1_B

DQ11_B

2

3

VDD2_A/B

VDDCA_A/B

VDDCA_A/B

VDDCA_A/B

VDDCA_A/B

VDDCA_A/B

VDDCA_A/B

VDD1_A/B

VDDQ_A/BDQ31_A

DQ12_B

3

4

DQ30_A

DQ13_B

4

5

DQ29_A

DQ28_A

DQ14_B

5

6

DQ27_A

DQ15_B

6

7

DQ26_A

DM3_B

7

8

DQ25_A

DQ24_A

8

9

DQ24_B

9

10

DQ26_B

DQ25_B

10

11

DM3_A

DQ27_B

11

12

DQ15_A

DQ14_A

DQ28_B

12

13

DQ13_A

DQ30_B

DQ29_B

13

14

DQ12_A

DQ31_B

14

15

DQ11_A

15

28

DQ2_A

DQ1_A

DM2_A

DQ20_A

DQ19_A

DQ16_A

CA4_B

CA7_B

CA8_B

28

29

DQ0_A

DQ23_A

DQ22_A

DQ21_A

DQ18_A

DQ17_A

CA0_B

CA1_B

CA2_B

CA3_B

CKE1_B

CKE0_B

CA5_B

CA6_B

CA9_B

ZQ_B

29

20

ODT_A

CA6_A

CA5_A

20

21

21

22

NC

22

23

DM0_A

23

24

24

25

DQ7_A

CA3_A

CA4_A

25

26

DQ6_A

DQ5_A

CA2_A

26

27

DQ4_A

DQ3_A

CA1_A

CA0_A

27

16

DQ10_A

NC

16

17

DQ9_A

CA9_A

ZQ_A

17

18

DQ8_A

CA8_A

18

19

DM1_A

CA7_A

19

NC NC

NC

NC

NC

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/B VSS_A/BVSS_A/B VSS_A/B VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VSS_A/BVSS_A/B

VSS_A/BVSS_A/B

VSS_A/B

VSS_A/B

VSS_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDDQ_A/B

VDD2_A/B

VDD2_A/B

VDD2_A/B

VDD2_A/B

VDD1_A/B

VDD2_A/B

VREFCA_A

VDD1_A/B

VDD2_A/B

VDD2_A/B

VDD1_A/B

VDDQ_A/B

VDD2_A/B

VDD1_A/B

VDD2_A/B

VDD2_A/B

VREFCA_B

VREFDQ_A

VREFDQ_B

Ball DescriptionsThe ball/pad description table below is a comprehensive list of signals for the devicefamily. All signals listed may not be supported on this device. See ball assignments forinformation specific to this device.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMBall Assignments



Table 4: Ball/Pad Descriptions

Symbol Type Description

CA[9:0]_A,CA[9:0]_B

Input Command/address inputs: Provide the command and address inputs according to thecommand truth table. A separate CA[9:0] is provided for each channel (A and B).

CK_t_B, CK_t_ACK_c_B, CK_c_A

Input Clock: Differential clock inputs. All CA inputs are sampled on both rising and fallingedges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings arereferenced to clock. A separate CK_t/CK_c is provided for each channel (A and B).

CKE[1:0]_A,CKE[1:0]_B

Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,input buffers, and output drivers. Power-saving modes are entered and exited via CKEtransitions. CKE is considered part of the command code. CKE is sampled on the risingedge of CK. A separate CKE is provided for each channel (A and B).

CS[1:0]_n_A,CS[1:0]_n_B

Input Chip select: Considered part of the command code and is sampled on the rising edgeof CK. A separate CS_n is provided for each channel (A and B).

DM[3:0]_B,DM[3:0]_A

Input Input data mask: Input mask signal for write data. Although DM balls are input-only,the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for eachof the four data bytes, respectively. A separate DM[3:0] is provided for each channel (Aand B).

ODT_B, ODT_A Input On-die termination: Enables and disables termination on the DRAM DQ bus accordingto the specified mode register settings. For packages that do not support ODT, the ODTsignal may be grounded internally. A separate ODT provided for each channel (A andB).

DQ[31:0]_B,DQ[31:0]_A

I/O Data input/output: Bidirectional data bus. A separate DQ[11:0] is provided for eachchannel (A and B).

DQS[3:0]_t_B,DQS[3:0]_t_A,DQS[3:0]_c_B,DQS[3:0]_c_A

I/O Data strobe: Bidirectional (used for read and write data) and complementary (DQS_tand DQS_c). It is edge-aligned output with read data and centered input with write da-ta. DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively. A sepa-rate DQS[3:0]_t and DQS[3:0]_c is provided for each channel (A and B).

VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity.

VSSQ Supply DQ ground: Isolated on the die for improved noise immunity.

VDDCA Supply Command/address power supply: Command/address power supply.

VSSCA Supply Command/address ground: Isolated on the die for improved noise immunity.

VDD1 Supply Core power: Supply 1.

VDD2 Supply Core power: Supply 2.

VSS Supply Common ground.

VREFCA_B, VREFCA_AVREFDQ_B, VREFDQ_A

Supply Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ isreference for DQ input buffers. A separate VREFCA and VREFDQ provided for each channel(A and B).

ZQ_B, ZQ_A Reference External reference ball for output drive calibration: This ball is tied to an external240 resistor (RZQ), which is tied to VSSQ. A separate ZQ is provided for each channel (Aand B).

DNU Do not use: Must be grounded or left floating.

NC No connect: Not internally connected.

(NC) No connect: Balls indicated as (NC) are no connects; however, they could be connectedtogether internally.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMBall Descriptions



Package Block Diagrams

Figure 3: Quad-Die, Dual-Channel Package Block Diagram

LPDDR3Die 0

CS0_n_A

CKE0_A

CS1_n_A

CKE1_A

ODT_A

CK_t_A

CK_c_ADM[3:0]_A

CA[9:0]_A

DQ[31:0]_A,DQS[3:0]_t_A,DQS[3:0]_c_A

ZQ_A

LPDDR3Die 1

LPDDR3Die 2

LPDDR3Die 3

CS0_n_B

CKE0_B

ODT_B

ODT

ODT

ODT

ODT

CK_t_B

CK_c_BDM[3:0]_B

CA[9:0]_B

DQ[31:0]_B,DQS[3:0]_t_B,DQS[3:0]_c_B

ZQ_B

CS1_n_B

CKE1_B

VDD1_A/B

VDD2_A/B

VDDQ_A/B

VDDCA_A/B

VSS_A/B

VSS

VSS

VREFDQ_A, BVREFCA_A, B

Note: 1. The ODT input is connected to rank 0. The ODT input to rank 1 is connected to VSS in thepackage.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMPackage Block Diagrams



Package Dimensions

Figure 4: 216-Ball FBGA (15mm x 15mm) EDFA164A1PB

14.0

14.0

B

S

0.5

216- 0.325 0.05 0.05 M S AB

0.10 S

0.5

0.10 S

A

15.0 0.1

Index mark

0.90 0.10

Index mark

0.20 S A

0.20 S B15

.0

0.1

0.25 0.05

Notes: 1. Package drawing: ECA-TS2-0503-01.2. All dimensions are in millimeters.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMPackage Dimensions



Figure 5: 216-Ball FBGA (15mm x 15mm) EDFA164A1PK

14.0

14.0

B

S0.

5

216- 0.325 0.05 0.05 M S AB

0.10 S

0.5

0.10 S

A

15.0 0.1

Index mark

0.72 0.08

Index mark

0.20 S A

0.20 S B

15.0

0.

1

0.25 0.05

Notes: 1. Package drawing: ECA-TS2-0519-01.2. All dimensions are in millimeters.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMPackage Dimensions



MR0MR3, MR5MR8, MR11 Contents

Table 5: Mode Register Contents

Part Number OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

MR0

EDFA164A1PKEDFA164A1PB

OP6 = 0b indicates no support for WL set BOP7 = 0b indicates that the option for RL3 is not supportedOP6 and OP7 = 0b for this package

MR1


OP[7:5] If nWRE (in MR2) = 0100b: nWR = 6110b: nWR = 8 (default)111b: nWR = 9

If nWRE = 1000b: nWR =10001b: nWR = 11010b: nWR =12

All others: Reserved

MR2


OP[3:0] RL and WL0100b: RL = 6: WL = 30110b: RL = 8; WL = 4 (default)0111b: RL = 9; WL = 51000b: RL = 10; WL = 61001b: RL = 11; WL = 61010b: RL = 12; WL = 6All others: Reserved

OP4 nWRE0b: Enable nWR programming 9 (default)1b: Enable nWRE programming > 9

OP6 WL select0b: Select WL Set A (default)1b: Reserved

OP7 Write leveling0b: Write leveling mode disabled (default)1b: Write leveling mode enabled

MR3


OP[3:0] DS0000b: Reserved0001b: 34.3 Ohms TYP0010b: 40 Ohms TYP (default)0011b: 48 Ohms TYPAll others: Reserved

MR5


Manufacturer ID = 0000 0011b

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMMR0MR3, MR5MR8, MR11 Contents



Table 5: Mode Register Contents (Continued)

Part Number OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

MR6


Revision ID1 = 0000 00000b: Revision A

MR7

EDFA164A1PBEDFA164A1PK

Revision ID2 = (RFU)

MR8 I/O Width Density Type


00b: x32 0110b: 4Gb 11b: S8

MR11


OP[1:0]DQ ODT00b; Disabled (default)01b: Reserved10b: RZQ/211b: RZQ/1

OP2 PD control (power-down control)0b: ODT disabled by DRAM during power-down1b: ODT enabled by DRAM during power-down

Note: 1. The contents of MR0MR3, MR5MR8, and MR11 will reflect information specific toeach in these packages.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMMR0MR3, MR5MR8, MR11 Contents



IDD Specifications Quad Die, Dual Channel

Table 6: IDD Specifications

VDD2, VDDQ, VDDCA = 1.141.30V; VDD1 = 1.701.95V; TC = 30C to +85C

Symbol Supply

Speed

Unit Parameter/Condition1866 1600 1333

IDD01 VDD1 16 16 16 mA 2 devices in operating one bank active-precharge;2 devices in deep power-down. Conditions for op-erating devices are:tCK = tCK(avg) MIN;tRC = tRC (MIN); CKE is HIGH;CS_n is HIGH between valid commands;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD02 VDD2 120 120 120

IDD0,in VDDCA + VDDQ 6.0 6.0 6.0

IDD2P1 VDD1 1.6 1.6 1.6 mA All devices in idle power-down standby current tCK= tCK(avg) MIN; CKE is LOW; CS_n is HIGH;All banks are idle; CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD2P2 VDD2 3.6 3.6 3.6

IDD2P,in VDDCA + VDDQ 0.4 0.4 0.4

IDD2PS1 VDD1 1.6 1.6 1.6 mA All devices in idle power-down standby currentwith clock stopCK_t = LOW, CK_c = HIGH; CKE is LOW;CS_n is HIGH; All banks are idle;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

IDD2PS2 VDD2 3.6 3.6 3.6

IDD2PS,in VDDCA + VDDQ 0.4 0.4 0.4

IDD2N1 VDD1 1.6 1.6 1.6 mA All devices in idle non power-down standby cur-renttCK = tCK(avg) MIN; CKE is HIGH;CS_n is HIGH; All banks are idle;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD2N2 VDD2 60 52 44

IDD2N,in VDDCA + VDDQ 12 12 12

IDD2NS1 VDD1 1.6 1.6 1.6 mA All devices in idle non power-down standby cur-rent with clock stopCK_t = LOW, CK_c = HIGH; CKE is HIGH;CS_n is HIGH; All banks are idle;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

IDD2NS2 VDD2 16 16 16

IDD2NS,in VDDCA + VDDQ 12 12 12

IDD3P1 VDD1 2.8 2.8 2.8 mA All devices in active power-down standby currenttCK = tCK(avg) MIN; CKE is LOW;CS_n is HIGH; One bank is active;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD3P2 VDD2 22 22 22

IDD3P,in VDDCA + VDDQ 0.4 0.4 0.4

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMIDD Specifications Quad Die, Dual Channel



Table 6: IDD Specifications (Continued)


Symbol Supply

Speed


IDD3PS1 VDD1 2.8 2.8 2.8 mA All devices in active power-down standby currentwith clock stopCK_t = LOW, CK_c = HIGH; CKE is LOW;CS_n is HIGH; One bank is active;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

IDD3PS2 VDD2 22 22 22

IDD3PS,in VDDCA + VDDQ 0.4 0.4 0.4

IDD3N1 VDD1 4.0 4.0 4.0 mA All devices in active non power-down standby cur-renttCK = tCK(avg) MIN; CKE is HIGH;CS_n is HIGH; One bank is active;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD3N2 VDD2 80 68 60

IDD3N,in VDDCA + VDDQ 12 12 12

IDD3NS1 VDD1 4.0 4.0 4.0 mA All devices in active non power-down standby cur-rent with clock stopCK_t = LOW, CK_c = HIGH; CKE is HIGH;CS_n is HIGH; One bank is active;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

IDD3NS2 VDD2 32 32 32

IDD3NS,in VDDCA + VDDQ 12 12 12

IDD4R1 VDD1 4.0 4.0 4.0 mA 2 devices in operating burst read; 2 devices in deeppower-down.Conditions for operating devices are:tCK = tCK(avg) MIN; CS_n is HIGH between validcommands;One bank is active; BL = 8; RL = RL (MIN);CA bus inputs are SWITCHING;50% data change occurs at each burst transfer;ODT is disabled

IDD4R2 VDD2 540 460 400

IDD4R,in VDDCA 6.0 6.0 6.0

IDD4W1 VDD1 4.0 4.0 4.0 mA 2 devices in operating burst write; 2 devices indeep power-downConditions for operating devices are:tCK = tCK(avg) MIN; CS_n is HIGH between validcommands;One bank is active; BL = 8; WL = WL (MIN);CA bus inputs are SWITCHING;50% data change occurs at each burst transfer;ODT is disabled

IDD4W2 VDD2 560 480 420

IDD4W,in VDDCA + VDDQ 6.0 6.0 6.0




Table 6: IDD Specifications (Continued)


Symbol Supply

Speed


IDD51 VDD1 56 56 56 mA 2 devices in all bank auto-refresh; 2 devices indeep power-down.Conditions for operating devices are:tCK = tCK(avg) MIN; CKE is HIGH between validcommands;tRC = tRFCab (MIN); Burst refresh;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD52 VDD2 300 300 300

IDD5,in VDDCA + VDDQ 6.0 6.0 6.0

IDD5AB1 VDD1 4.0 4.0 4.0 mA 2 devices in all bank auto-refresh; 2 devices indeep power-down.Conditions for operating devices are:tCK = tCK(avg) MIN; CKE is HIGH between validcommands;tRC = tREFI;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD5AB2 VDD2 40 36 32

IDD5AB,in VDDCA + VDDQ 6.0 6.0 6.0

IDD5PB1 VDD1 4.0 4.0 4.0 mA 2 devices in per bank auto-refresh; 2 devices indeep power-down.Conditions for operating devices are:tCK = tCK(avg) MIN; CKE is HIGH between validcommands;tRC = tREFIpb;CA bus inputs are SWITCHING;Data bus inputs are STABLE;ODT is disabled

IDD5PB2 VDD2 40 36 32

IDD5PB,in VDDCA + VDDQ 6.0 6.0 6.0

IDD81 VDD1 64 64 64 A All devices in deep power-downCK_t = LOW, CK _c = HIGH; CKE is LOW;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

IDD82 VDD2 24 24 24

IDD8,in VDDCA + VDDQ 48 48 48

Notes: 1. Published IDD values are the maximum of the distribution of the arithmetic mean.2. IDD current specifications are tested after the device is properly initialized.




Table 7: IDD6 Partial-Array Self Refresh Current at 45C

VDD2, VDDQ, VDDCA = 1.141.30V; VDD1 = 1.701.95VPASR Supply Value Unit Parameters/Conditions

Full array VDD1 920 A All devices in self refreshCK_t = LOW, CK_c = HIGH;CKE is LOW;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

VDD2 3520

VDDCA + VDDQ 40

1/2 array VDD1 600

VDD2 2000

VDDCA + VDDQ 40

1/4 array VDD1 440

VDD2 1200

VDDCA + VDDQ 40

1/8 array VDD1 360

VDD2 840

VDDCA + VDDQ 40

Note: 1. IDD6 45C is typical of the distribution of the arithmetic mean.

Table 8: IDD6 Partial-Array Self Refresh Current at 85C

VDD2, VDDQ, VDDCA = 1.141.30V; VDD1 = 1.701.95VPASR Supply Value Unit Parameters/Conditions

Full array VDD1 3800 A All devices in self refreshCK_t = LOW, CK_c = HIGH;CKE is LOW;CA bus inputs are STABLE;Data bus inputs are STABLE;ODT is disabled

VDD2 12,000

VDDCA + VDDQ 48

1/2 array VDD1 3000

VDD2 7200

VDDCA + VDDQ 48

1/4 array VDD1 2600

VDD2 5200

VDDCA + VDDQ 48

1/8 array VDD1 2400

VDD2 4000

VDDCA + VDDQ 48

Note: 1. IDD6 85C is the maximum of the distribution of the arithmetic mean.




Pin Capacitance

Table 9: Input/Output Capacitance

Part Number Parameter Symbol Min Max Unit Notes


Input capacitance, CK_t and CK_c CCK 1.5 3.6 pF 1, 2


Input capacitance, all other input-onlypins except CS_n, CKE, and ODT

CI1 1.5 3.6 pF 1, 2


Input capacitance, CS_n, CKE, and ODT CI2 0.5 3.0 pF 1, 2


Input/output capacitance, DQ, DM,DQS_t, DQS_c

CIO 2.5 5.5 pF 1, 2, 3


Input/output capacitance, ZQ CZQ 0.0 6.0 pF 1, 2, 3

Notes: 1. This parameter is not subject to production testing. It is verified by design and character-ization.

2. These parameters are measured on f = 100 MHz, VOUT = VDDQ/2, TA = +25 C.3. DOUT circuits are disabled.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMPin Capacitance



AC Timing

Table 10: AC Timing

Notes 13 apply to all parameters and conditions

Parameter Symbol Min/MaxData Rate

Unit Notes1333 1600 1866

Maximum frequency 667 800 933 MHz

Clock Timing

Average clock period tCK(avg) MIN 1.5 1.25 1.071 ns

MAX 100

Average HIGH pulse width tCH(avg) MIN 0.45 tCK(avg)

MAX 0.55

Average LOW pulse width tCL(avg) MIN 0.45 tCK(avg)

MAX 0.55

Absolute clock period tCK(abs) MIN tCK(avg) MIN + tJIT(per) MIN ns

Absolute clock HIGH pulse width tCH(abs) MIN 0.43 tCK(avg)

MAX 0.57

Absolute clock LOW pulse width tCL(abs) MIN 0.43 tCK(avg)

MAX 0.57

Clock period jitter (with suppor-ted jitter)

tJIT(per), al-lowed

MIN 80 70 -60 ps

MAX 80 70 60

Maximum clock jitter betweentwo consecutive clock cycles(with allowed jitter)

tJIT(cc), al-lowed

MAX 160 140 120 ps

Duty cycle jitter (with supportedjitter)

tJIT(duty), al-lowed

MIN min((tCH(abs),min - tCH(avg),min),(tCL(abs),min - tCL(avg),min))

tCK(avg)

ps

MAX max((tCH(abs),max - tCH(avg),max),(tCL(abs),max - tCL(avg),max))

tCK(avg)

Cumulative errors across 2 cycles tERR(2per),allowed

MIN 118 103 -88 ps

MAX 118 103 88


MIN 140 122 -105 ps

MAX 140 122 105


MIN 155 136 -117 ps

MAX 155 136 117


MIN 168 147 -126 ps

MAX 168 147 126


MIN 177 155 -133 ps

MAX 177 155 133


MIN 186 163 -139 ps

MAX 186 163 139

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMAC Timing



Table 10: AC Timing (Continued)



Unit Notes1333 1600 1866


MIN 193 169 -145 ps

MAX 193 169 145


MIN 200 175 -150 ps

MAX 200 175 150

Cumulative errors across 10 cy-cles

tERR(10per),allowed

MIN 205 180 -154 ps

MAX 205 180 154


tERR(11per),allowed

MIN 210 184 -158 ps

MAX 210 184 158


tERR(12per),allowed

MIN 215 188 -161 ps

MAX 215 188 161

Cumulative errors across n = 13,14, 15, 19, 20 cycles

tERR(nper),allowed

MIN tERR(nper),allowed MIN = (1 +0.68ln(n)) tJIT(per), allowed MIN

ps

MAX tERR (nper), allowed MAX = (1 +0.68ln(n)) tJIT(per), allowed MAX

ZQ Calibration Parameters

Initialization calibration time tZQINIT MIN 1 s

Long calibration time tZQCL MIN MAX (360ns, 6nCK) ns

Short calibration time tZQCS MIN MAX (90ns, 6nCK) ns

Calibration RESET time tZQRESET MIN MAX (50ns, 3nCK) ns

READ Parameters4

DQS output access time from CK tDQSCK MIN 2500 ps

MAX 5500

DQSCK delta short tDQSCKDS MAX 265 220 220 ps 5

DQSCK delta medium tDQSCKDM MAX 593 511 511 ps 6

DQSCK delta long tDQSCKDL MAX 733 614 614 ps 7

DQS-DQ skew tDQSQ MAX 165 135 135 ps

DQS output HIGH pulse width tQSH MIN tCH(abs) - 0.05 tCK(avg)

DQS output LOW pulse width tQSL MIN tCL(abs) - 0.05 tCK(avg)

DQ/DQS output hold time fromDQS

tQH MIN MIN (tQSH, tQSL) ps

READ preamble tRPRE MIN 0.9 tCK(avg) 8, 9

READ postamble tRPST MIN 0.3 tCK(avg) 8, 10

DQS Low-Z from clock tLZ(DQS) MIN tDQSCK (MIN) - 300 ps 8

DQ Low-Z from clock tLZ(DQ) MIN tDQSCK (MIN) - 300 ps 8

DQS High-Z from clock tHZ(DQS) MAX tDQSCK (MAX) - 100 ps 8

DQ High-Z from clock tHZ(DQ) MAX tDQSCK (MAX) + (1.4 tDQSQ(MAX))

ps 8







Unit Notes1333 1600 1866

WRITE Parameters4

DQ and DM input hold time (VREFbased)

tDH MIN 175 150 150 ps

DQ and DM input setup time(VREF based)

tDS MIN 175 150 150 ps

DQ and DM input pulse width tDIPW MIN 0.35 tCK(avg)

Write command to first DQSlatching transition

tDQSS MIN 0.75 tCK(avg)

MAX 1.25

DQS input high-level width tDQSH MIN 0.4 tCK(avg)

DQS input low-level width tDQSL MIN 0.4 tCK(avg)

DQS rising edge to CK fallingedge and DQS falling edge to CKrising edge setup time

tDSS MIN 0.2 tCK(avg)

CK rising edge to DQS fallingedge and CK falling edge to DQSrising edge hold time

tDSH MIN 0.2 tCK(avg)

Write postamble tWPST MIN 0.4 tCK(avg)

Write preamble tWPRE MIN 0.8 tCK(avg)

CKE Input Parameters

CKE minimum pulse width (HIGHand LOW pulse width)

tCKE MIN MAX (7.5ns, 3nCK) tCK(avg)

CKE input setup time tISCKE MIN 0.25 tCK(avg) 11

CKE input hold time tIHCKE MIN 0.25 tCK(avg) 12

Command path disable delay tCPDED MIN 2 tCK(avg)

Command Address Input Parameters4

Address and control input setuptime

tISCA MIN 175 150 150 ps 13

Address and control input holdtime

tIHCA MIN 175 150 150 ps 13

CS_n input setup time tISCS MIN 290 270 270 ps 13

CS_n input hold time tIHCS MIN 290 270 270 ps 13

Address and control input pulsewidth

tIPWCA MIN 0.35 tCK(avg)

CS_n input pulse width tIPWCS MIN 0.7 tCK(avg)

Boot Parameters (1055 MHz)14, 15, 16

Clock cycle time tCKb MAX 100 ns

MIN 18

CKE input setup time tISCKEb MIN 2.5 ns







Unit Notes1333 1600 1866

CKE input hold time tIHCKEb MIN 2.5 ns

Address and control input setuptime

tISb MIN 1150 ps

Address and control input holdtime

tIHb MIN 1150 ps

DQS output data access timefrom CK

tDQSCKb MIN 2 ns

MAX 10

Data strobe edge to output dataedge

tDQSQb MAX 1.2 ns

Mode Register Parameters

MODE REGISTER WRITE com-mand period (MRW command toMRW command interval)

tMRW MIN 10 tCK(avg)

MODE REGISTER SET commanddelay (MRW command to non-MRW command interval)

tMRD MIN MAX (14ns, 10nCK) ns

MODE REGISTER READ commandperiod

tMRR MIN 4 tCK(avg)

Additional time after tXP has ex-pired until MRR command maybe issued

tMRRI MIN tRCD (MIN) ns

Core Parameters17

READ latency RL MIN 10 12 12 tCK(avg)

WRITE latency (set A) WL MIN 6 6 6 tCK(avg)

ACTIVATE-to- ACTIVATE com-mand period

tRC MIN tRAS + tRPab (with all-bank pre-charge)

tRAS + tRPpb (with per-bank pre-charge)

ns

CKE minimum pulse width dur-ing SELF REFRESH (low pulsewidth during SELF REFRESH)

tCKESR MIN MAX (15ns, 3nCK) ns

SELF REFRESH exit to next validcommand delay

tXSR MIN MAX (tRFCab + 10ns, 2nCK) ns

Exit power-down to next validcommand delay

tXP MIN MAX (7.5ns, 2nCK) ns

CAS-to-CAS delay tCCD MIN 4 tCK(avg)

Internal READ to PRECHARGEcommand delay

tRTP MIN MAX (7.5ns, 4nCK) ns

RAS-to-CAS delay tRCD MIN MAX (18ns, 3nCK) ns







Unit Notes1333 1600 1866

Row precharge time (singlebank)

tRPpb MIN MAX (18ns, 3nCK) ns

Row precharge time (all banks) tRPpab MIN MAX (21ns, 3nCK) ns

Row active time tRAS MIN MAX (42ns, 3nCK) ns

MAX 70 s

WRITE recovery time tWR MIN MAX (15ns, 3nCK) ns

Internal WRITE-to- READ com-mand delay

tWTR MIN MAX (7.5ns, 4nCK) ns

Active bank A to active bank B tRRD MIN MAX (10ns, 2nCK) ns

Four-bank ACTIVATE window tFAW MIN MAX (50ns, 8nCK) ns

Minimum deep power-downtime

tDPD MIN 500 s

ODT Parameters

Asynchronous RTT turn-on delyfrom ODT input

tODTon MIN 1.0 ns

MAX 2.25

Asynchronous RTT turn-off delayfrom ODT input

tODToff MIN 1.0 ns

MAX 2.25

Automatic RTT turn-on delay af-ter READ data

tAODTon MAX tDQSCK + 1.4 tDQSQmax +tCK(avg,min)

ps

Automatic RTT turn-off delay af-ter READ data

tAODToff MIN tDQSCKmin - 300 - 0.5tCK(avg,min) ps

RTT disable delay from power-down, self refresh, and deeppower-down entry

tODTd MAX 12 ns

RTT enable delay from power-down and self refresh exit

tODTe MAX 12 ns

CA Training Parameters

First CA calibration commandfollowing CA training entry

tCAMRD MIN 20 tCK(avg)

First CA calibration commandfollowing CKE LOW

tCAENT MIN 10 tCK(avg)

CA calibration exit command fol-lowing CKE HIGH

tCAEXT MIN 10 tCK(avg)

CKE LOW following CA calibra-tion mode entry

tCACKEL MIN 10 tCK(avg)

CKE HIGH following last CA cali-bration results

tCACKEH MIN 10 tCK(avg)

Data out delay after CA trainingcalibration command entry

tADR MAX 20 ns







Unit Notes1333 1600 1866

MRW CA exit command to DQtri-state

tMRZ MIN 3 ns

CA calibration command to CAcalibration command delay

tCACD MIN RU(tADR/tCK) + 2 tCK(avg)

Write Leveling Parameters

DQS delay after write levelingmode is programmed

tWLDQSEN MIN 25 ns

MAX

First DQS edge after write level-ing mode is programmed

tWLMRD MIN 40 ns

MAX

Write leveling output delay tWLO MIN 0 ns

MAX 20

Write leveling hold time tWLH MIN 205 175 150 ns

Write leveling setup time tWLS MIN 205 175 150 ns

Temperature Derating Parameters

DQS output access time from CK(derated)

tDQSCK MAX 5620 ps

RAS-to-CAS delay (derated) tRCD MIN tRCD + 1.875 ns

ACTIVATE-to- ACTIVATE com-mand period (derated)

tRC MIN tRC + 1.875 ns

Row active time (derated) tRAS MIN tRAS + 1.875 ns

Row precharge time (derated) tRP MIN tRP + 1.875 ns

Active bank A to active bank B(derated)

tRRD MIN tRRD + 1.875 ns

Notes: 1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine de-vice capabilities.

2. All AC timings assume an input slew rate of 2 V/ns.3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX.4. READ, WRITE, and input setup and hold values are referenced to VREF.5. tDQSCKDS is the absolute value of the difference between any two tDQSCK measure-

ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is

8. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the pointwhen the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur inthe same access time (with respect to clock) as valid data transitions. These parametersare not referenced to a specific voltage level but to the time when the device output isno longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,tLZ(DQS) and tLZ(DQ)). The figure below shows a method to calculate the point whenthe device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) andtLZ(DQ) by measuring the signal at two different voltages. The actual voltage measure-ment points are not critical as long as the calculation is consistent. The parameterstLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing pa-rameters tRPRE and tRPST are determined from the differential signal DQS.

Output Transition Timing

VOL + 2x X mV

VOL + X mV

VOH - X mV

VOH - 2x X mV

2x XX

2x Y

VOH

VOL

Y

T1 T2

VTT - Y mV

VTT VTT

VTT - 2x Y mV

VTT + 2x Y mV

VTT + Y mV tLZ(DQS), tLZ(DQ)

tHZ(DQS), tHZ(DQ)

T1 T2Start driving point = 2 T1 - T2 End driving point = 2 T1 - T2

actual wave form

9. Measured from the point when DQS begins driving the signal, to the point when DQSbegins driving the first rising strobe edge.

10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driv-ing the signal.

11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level toCK crossing.

12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltagelevel.

13. Input setup/hold time for signal (CA[9:0], CS_n).14. To ensure device operation before the device is configured, a number of AC boot timing

parameters are defined in this table. Boot parameter symbols have the letter b appen-ded (for example, tCK during boot is tCKb).

15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET(MRW) command, as specified in Mode Register Definition.

16. The output skew parameters are measured with default output impedance settings us-ing the reference load.

17. The minimum tCK column applies only when tCK is greater than 6ns.




LPDDR3 Array ConfigurationThe 4Gb Mobile Low-Power DDR3 SDRAM (LPDDR3) is a high-speed CMOS, dynamicrandom-access memory containing 4,294,967,296-bits. The device is internally config-ured as an eight-bank DRAM. Each of the x16s 536,870,912-bit banks is organized as16,384 rows by 2048 columns by 16 bits. Each of the x32s 536,870,912-bit banks is or-ganized as 16,384 rows by 1024 columns by 32 bits.

General Notes

Throughout the data sheet, figures and text refer to DQs as DQ. DQ should be inter-preted as any or all DQ collectively, unless specifically stated otherwise.

DQS and CK should be interpreted as DQS_t, DQS_c and CK_t, CK_c, respectively,unless specifically stated otherwise. BA and "CA" include all BA and CA pins, respec-tively, used for a given density.

Complete functionality may be described throughout the entire document. Any page ordiagram may have been simplified to convey a topic and may not be inclusive of all re-quirements.

Timing diagrams reflect a single-channel device.

In timing diagrams, CMD is used as an indicator only. Actual signals occur on CA[9:0].

VREF indicates VREFCA and VREFDQ.

Any specific requirement takes precedence over a general statement.

Any functionality not specifically stated herein is considered undefined, illegal, is notsupported, and will result in unknown operation.

16Gb: 216-Ball, Dual-Channel Mobile LPDDR3 SDRAMLPDDR3 Array Configuration



Functional DescriptionMobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory de-vice. LPDDR3 uses a double data rate architecture on the command/address (CA) busto reduce the number of input pins in the system. The 10-bit CA bus is used to transmitcommand, address, and bank information. Each command uses one clock cycle, duringwhich command information is transferred on both the rising and falling edges of theclock.

LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed op-eration. The double data rate architecture is essentially an 8n prefetch architecture withan interface designed to transfer two data bits per DQ every clock cycle at the I/O pins.A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide,one-clock-cycle data transfer at the internal SDRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the device are burst oriented; accesses start at a selected lo-cation and continue for a programmed number of locations in a programmed se-quence.

Accesses begin with the registration of an ACTIVATE command followed by a READ orWRITE command. The address and BA bits registered

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216b 16gb 2c0f Mobile Lpddr3