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D.Y.PATIL TECHNICAL CAMPUS D.Y.PATIL SCHOOL OF ENGINEERING ACADEMY, AMBI, PUNE 2.3.1 STUDENT CENTRIC METHOD Sr. No. Documents 1 ICT Enabled Teaching 1.1 NPTEL online Course 1.2 Khan Academy 1.3 Digital Library 1.4 YOUTUBE 2 Participative Learning 1.2.1 Group Learning Method 1.2.2 Learning through Project work 1.2.3 Co-curriculum Activity 1.2.4 Student Chapter 1.2.5 CSE (Computer) 1.2.6 ISHARE (Mechanical) 3 Problem Solving Methodology 1.3.1 Case Study Analysis 1.3.2 Interactive method Circuit Mania, MEMS (E&Tc Dept) 4 Request letter for establishing SWAYAMNPTEL Local Chapter 5 Approval Letter of NPTEL chapter 6 Number of Register courses 7 List of faculty Members Registration for NPTEL 8 List of Students Registration for NPTEL

2.3.1 STUDENT CENTRIC METHOD Sr. No. Documentsdypsoeambi.com/Criteria/Final Upload File 2.3.1.pdf · [email protected] om noc18-ce19 Matrix Method of Structural Analysis +91

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D.Y.PATIL TECHNICAL CAMPUS

D.Y.PATIL SCHOOL OF ENGINEERING ACADEMY, AMBI, PUNE

2.3.1 STUDENT CENTRIC METHOD

Sr. No. Documents 1 ICT Enabled Teaching

1.1 NPTEL online Course

1.2 Khan Academy

1.3 Digital Library

1.4 YOUTUBE

2 Participative Learning

1.2.1 Group Learning Method

1.2.2 Learning through Project work

1.2.3 Co-curriculum Activity

1.2.4 Student Chapter

1.2.5 CSE (Computer)

1.2.6 ISHARE (Mechanical)

3 Problem Solving Methodology

1.3.1 Case Study Analysis

1.3.2 Interactive method – Circuit Mania, MEMS (E&Tc Dept)

4 Request letter for establishing SWAYAMNPTEL Local Chapter

5 Approval Letter of NPTEL chapter

6 Number of Register courses

7 List of faculty Members Registration for NPTEL

8 List of Students Registration for NPTEL

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Page 3: 2.3.1 STUDENT CENTRIC METHOD Sr. No. Documentsdypsoeambi.com/Criteria/Final Upload File 2.3.1.pdf · sudhirshinde21566@gmail.c om noc18-ce19 Matrix Method of Structural Analysis +91
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National Digital Library of India

Slider Share

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Participative Learning:

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List of Mini Project Group for Learning through Project Work

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Co-curricular Activity

Project Exhibition at Texcellence

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Compititation of Lathe War

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Student Chapter : CSI of Computer Engineering Department

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Certificate of Institutional Accreditation

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ISHARE STUDENT CHAPTER: MECHANICAL ENGINEERING DEPARTMENT

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Student Membership Certificate

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ISHARE PUNE CHPTER

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Problem Solving Methodology: Case Study

D.Y.PATIL EDUCATION ACADEMY’S

D. Y. Patil School of Engineering Academy

Ambi, Talegaon, Pune-410506

Computer Engineering Department

Name of Case study: Pentium IV Cache organization

Course Name: Computer Organization and Architecture

Details

The Pentium 4 has three levels of cache as shown in figure.

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The level 1 cache is a split cache and is 8KB in size and is four-way set associative. This means

that each set is made up of four lines in cache. The replacement algorithm used for this is a “least

recently used” algorithm. The line size is 64 bytes.

The level 2 cache is a unified cache and is 256KB in size. The line size is 128 bytes and it is eight-

way set associative. This means that each set is made up of eight lines in cache. The increase in

size and set size means that it will reduce the chances of a miss occurring when accessing this

cache, increasing its effectiveness as a trade-off for its reduced speed. The increase in line size can

cause higher latency for line refills, so the Pentium 4 employs a 400MHz system bus using a

100MHz clock that delivers a data rate of 3.2GB/s to make up for the latency. The system bus has

a 64 byte access length, requiring 2 main memory accesses to fill a level 2 cache line.

The level 2 cache employs a hardware pre-fetcher to fill up 2 cache lines to take advantage of

locality of reference. The hardware monitors the history of cache misses to try to help it avoid

unnecessary pre-fetches.

The level 3 cache is eight-way set associative and has a line size of 128 bytes. All caches make

use of a “Least Recently Used (LRU)” replacement algorithm.

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9/27/2018 https://nptel.ac.in/LocalChapter/ack3/1.php

https://nptel.ac.in/LocalChapter/ack3/1.php 1/1

2018-08-10 10:08:58To The Principal D.Y.PATIL SCHOOL OF ENGINEERING ACADEMY D.Y.PATIL TECHNICAL CAMPUS,SR.NO.124 &126,A/P-AMBI,TALEGAON DHABADE,MIDC ROAD,TAL

MAHARASHTRAPUNE - 410506

Dear Sir/Madam,

Sub: Establishing NPTEL Local Chapter in your college

Greetings from the NPTEL office.

This is to acknowledge the receipt of your letter accepting to host NPTEL Local Chapter in your institution.

The Single Point of Contact (SPOC) nominated from your college is

Name of SPOC: PROF.AMOLKUMAR N.JADHAV Designation: ASSISTANT PROFESSOR Department:COMPUTER ENGINEERING Contact No(s):08208920924E-mail id: [email protected]

We wish to inform you that all future correspondence related to NPTEL contents and online courses will be made to the afore-mentioned SPOC. He/she will be routinely updated with all the latest NPTEL initiatives which then may be circulated among the students.

We are also happy to share that a dedicated NPTEL Local Chapter web page is being created and your institution will have a separate page on it (http://nptel.ac.in/LocalChapter).

Thanking you.

Sincerely

Prof. Andrew Thangaraj

NPTEL Coordinator

IIT MADRAS

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Swati Rajput [email protected] noc18-cs33

Introduction to Programming in

C +91 77090 41829 PUNE faculty masters

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Science and

Engineering Jul-Oct 2018

D.Y.Patil School of Engineering Academy, Ambi, Pune

List of faculty registered for NPTEL Courses

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priya raut [email protected] noc18-cs36 Data Base Management System +91 90969 17242 PUNE faculty masters

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Control Systems: Applications

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