234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #10 MIPS commands

234262 – © Yohai Devir 2007Technion - IIT

234262

Tutorial #10

MIPS commands


MIPS overview

MIPS is a simple processor:• All arithmetic operations are done with registers only. • Memory access is done with only two instructions –

LOAD \ STORE.

The MIPS is a 32-bit machine.• The instructions are 32-bits long.• Register file (RF), with 32 registers of 32 bits each (5 bit

for the number)• Memory address size – 32 bits.• We’ll work in resolution of words – 32bit each.


Registers

• There are registers which are denoted by R0, R1,…R31.• Register 0 is read-only and its value is 0 (R0 ≡ 0). • The PC (Program Counter) is a special register. The PC

points to the next instruction to be executed.• In some places register K is marked as $K (i.e. R8 ≡ $8)


Memory

• (maximal) size 230 words of 32 bits each.• Each word has a 32-bit address, the two LSB bits of the

address are 00.• Memory is accessed only by LOAD\STORE commands


Instructions

3 types of instructions, each kind with a fixed structure:

• Type R (Register)

• Type I (Immediate)

• Type J (Jump)


Type R

• OPeration

• Source \ Target \ Destination Register

• SHift AMounT

• FUNCtion

OP Rs Rt Rd shamt func6 bit 5 bit 5 bit 5 bit 5 bit 6 bit


ADD R11,R20,R3

• Semantic: R11 R20 + R3

• Performs addition of the values of R20 and R3 and stores the result in R11

OP Rs Rt Rd shamt func

06 bit 5 bit 5 bit 5 bit 5 bit 6 bit


ADD R11,R20,R3



0 326 bit 5 bit 5 bit 5 bit 5 bit 6 bit


ADD R11,R20,R3



0 11 326 bit 5 bit 5 bit 5 bit 5 bit 6 bit


ADD R11,R20,R3



0 20 3 11 326 bit 5 bit 5 bit 5 bit 5 bit 6 bit


ADD R11,R20,R3



0 20 3 11 0 326 bit 5 bit 5 bit 5 bit 5 bit 6 bit




OR R8,R7,R6

• Semantic: R8 R7 OR R6

• Performs bitwise logical OR between the values of R7 and R6 and stores the result in R8




SLT R10,R20,R30

Semantic:If (R20 < R30)

R10 000… …00001 (32bit)

else

R10 000… …00000 (32bit)

• Name: Set Less Than




SLL R5,R7,2

Semantic:R5 R7 << 2

Name: Shift Left LogicalExample: if R7= 11100… …01111 then

R5 = 100… …0111100SRL does the same but shifts right


Not 0 7 0 5 2 06 bit 5 bit 5 bit 5 bit 5 bit 6 bit


Type I

• OPeration

• Source \ Target Registers

• IMmediate

OP Rs Rt IM6 bit 5 bit 5 bit 16 bit


ADDI R2,R29,144

Semantic:R2 R29+144

Bigger constants?

OP Rs Rt IM

8 29 2 1446 bit 5 bit 5 bit 16 bit

OP Rs Rt IM

001000 11101 00010 0000 0000 1001 00006 bit 5 bit 5 bit 16 bit


LUI R3,0xB3A0

Load Upper Immediate

Semantic:1. Sets the 16 MSBs of R3 to 0xB3A0

2. Zero the 16 LSBs of R3

OP Rs Rt IM

15 0 3 0xB3A06 bit 5 bit 5 bit 16 bit


LUI

Example: In order to load 0x2AC0900 to R3:

R3 (before) = 0x ABCD 1234

LUI R3, 0x02AC

R3 = 0x 02AC 0000

ADDI R3, 0x0900

R3 = 0x 02AC 0900


BNE R31,R8,loop1

Branch on Not Equal

Semantic:

if R31!=R8, the next instruction to be executed is the on which is stored in the memory at label ‘loop1’

BEQ branches if EQual

OP Rs Rt IM

4 31 8 ?6 bit 5 bit 5 bit 16 bit


BNE R31,R8,loop1label Address

(decimal)instruction

gremlin: 00…000984 ADDI R5,R0,81

00…000988 SUB R7,R9,R12

00…000992 …

00…000996 ADDI R1,R0,5

Loop1: 00…001000 ADD R1,R1,R3

00…001004 …

…

00…001016 SUBI, R1,R1,1

00…001020 BNE R1,R0,loop1


(BNEaddr )

BNE

We want to branch to address 00…001000.

However, this a 32bit address while having only 16bit of IM.

• Most branches are to “nearby” addresses.

We can put address relative to the PC.

• 2 LSB bits are ’00 (Why?)

No need to specify the 2 LSBs.

• We’ll see this later: After bringing the intruction (before really reading it) the PC is incremented in 4 bytes.

PCnew (BNEaddr +4) + IM x4


BNE R31,R8,loop1Loop1: 00…001000 ADD R1,R1,R3

…

00…001020 BNE R1,R0,loop1

• BNE instruction address is 1020, branch address is 1000.

• After fetching the instruction the PC will be 1024 we need to branch to an address -24 bytes away.

• No need to store the 2 LSBs (-24)/4 = -6 IM should be -6

OP Rs Rt IM

4 31 8 -66 bit 5 bit 5 bit 16 bit


LW R2,100(R3)

Load WordSemantic:

Read the word located in the memory address of [R3] + 100 (not 103 !!!) and write it to R2

NOTE: Rs is the Base registerRt is the register to write to.

OP Rs Rt IM

35 3 2 1006 bit 5 bit 5 bit 16 bit


SW R7,200(R6)

Load WordSemantic:

Writes the word located in R7 to the memory address of [R6] + 200 (not 206!!!)

NOTE: Rs is the Base registerRt is the read from.

OP Rs Rt IM

43 6 7 2006 bit 5 bit 5 bit 16 bit


Type J

• OPeration

• eXtended Immediate

• Unconditional jump

• 2 LSBs are ’00. No need to specify them.

• 4 MSBs are taken from PC

OP XI6 bit 26 bits


J 0xEF44 4444

Jumps to a specific address

Semantic:

PCnew PC[upper 4 MSBs] || XI || 00

OP XI

2 ? 6 bit 26 bits


J 0xEF44 4444Example:

0xE044 4444 in binary is:

Without 4 MSBs and 2 LSBs:

Back to Hex:

Therefore XI = 0x3D1 1111

Address (HEX) instruction

0x E123 4568: J 0xEF44 4444

E F 4 4 4 4 4 41110 1111 0100 0100 0100 0100 0100 0100

11 1101 0001 0001 0001 0001 0001

3 D 1 1 1 1 1


JAL 0xEF44 4444

Jump And Link

Stores PC in Register 31 and then jumps to given address.

Semantic:

R31 PC

PC PC[upper 4 MSBs] || XI || 00

OP XI

3 ? 6 bit 26 bits


JR R17

Jump Register – a Type R command.

Semantic:PC R17



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234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #10 MIPS commands