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27th ICMTS
2014 IEEE International Conference on
Microelectronic Test Structures
INTERNATIO
NA
LC
ON
FERE
NCE ON MICROELECTRON
ICTE
ST
STRUCTURESIEEE
ICMTS
March 24–27, 2014Palazzo Antonini CernazaiVia Prospero Antonini
Udine, Italy
Technically sponsored by:The IEEE Electron Devices Society
ContentsWELCOME LETTER 2
GENERAL INFORMATION 3Conference Information . . . . . . . . . . . . . . . . . . . . 3Presentations . . . . . . . . . . . . . . . . . . . . . . . . . . 3Best Paper Award . . . . . . . . . . . . . . . . . . . . . . . 4Conference Proceedings . . . . . . . . . . . . . . . . . . . . 4Conference Registration . . . . . . . . . . . . . . . . . . . . 4Equipment Exhibition . . . . . . . . . . . . . . . . . . . . . 5Messages and facilities . . . . . . . . . . . . . . . . . . . . . 5Lunch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Banquet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Excursion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Udine Information . . . . . . . . . . . . . . . . . . . . . . . 7Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Climate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Accommodation . . . . . . . . . . . . . . . . . . . . . . . . 7
TUTORIALS 10Tutorial Lecturer Biographies . . . . . . . . . . . . . . . . . 10Tutorial Programme . . . . . . . . . . . . . . . . . . . . . . 12
WELCOME RECEPTION 14
TECHNICAL PROGRAMME 14Tuesday 25th March . . . . . . . . . . . . . . . . . . . . . . 14Wednesday 26th March . . . . . . . . . . . . . . . . . . . . 21Thursday 27th March . . . . . . . . . . . . . . . . . . . . . 26
CONFERENCE OFFICIALS 30Conference Committee . . . . . . . . . . . . . . . . . . . . . 30Steering Committee . . . . . . . . . . . . . . . . . . . . . . 31Technical Committee . . . . . . . . . . . . . . . . . . . . . . 32
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WELCOME LETTERDear Colleagues,
the 27th International Conference on Microelectronic Test Struc-tures will be held in Udine (Italy) at Palazzo Antonini Cernazai, viaProspero Antonini, Udine. This year it is organized by the Universitadegli Studi di Udine. It is technically co–sponsored by the IEEE Elec-tron Devices Society. The purpose is to bring together designers andusers of test structures to discuss recent developments and future di-rections. The conference will be held on March 25–27, 2011, and willbe preceded by a one–day Tutorial Short Course on microelectronictest structures on March 24.
The first ICMTS was held in Long Beach in 1988, and since thenthe conference has cycled between Europe, North America, and Asia.It will be the second time that ICMTS is held in Italy and for thefirst time in Udine. As in previous editions there will also be a re-lated equipment exhibition focused on test structure measurementsand related companies.
Venue of the Conference is the Sala Gusmani of Palazzo AntoniniCernazai, conveniently situated within walking distance of the TrainStation, in the heart of the Udine historical center. Hotels, restau-rants and tourist attractions are abundantly found in the near vicin-ity. Palazzo Antonini Cernazai itself is one of the historical buildingsowned by the Universita degli Studi di Udine and it is the seat of thehumanistic pole of the University. It was built by the noble family ofAntonini and it has been erected in the year 1595.
An attractive social programme is offered to the conference dele-gates and accompanying persons. This includes a Welcome Receptionon Monday, a short excursion at the Tiepolo Galleries in PalazzoArcivescovile and the Conference Banquet on Wednesday, and, onThursday, an excursion to Villa Manin, one of the most importantartistic monuments in Friuli Venezia Giulia.
We hope to welcome you in Udine in March!
Sincerely
Luca Selmi, General ChairmanJohan Klootwijk, Technical Program ChairGaudenzio Meneghesso, Tutorial ChairAlain Toffoli, Exhibition ChairFrancesco Driussi, Local Arrangements Chair
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GENERAL INFORMATION
Conference InformationThe 2014 International Conference on Microelectronic Test Structuresis organized by the Universita degli Studi di Udine and it is technicallyco–sponsored by the IEEE Electron Devices Society. The purpose is tobring together designers and users of test structures to discuss recentdevelopments and future directions of research on test structures orenabled by test structures. The Conference will be preceded by aone–day Tutorial Short Course covering a variety of technical areasrelated to Microelectronic Test Structures.
The Tutorials and the Technical sessions will all be held at theSala Gusmani in Palazzo Antonini Cernazai. The address is: viaProspero Antonini, Udine.
Website and Email ContactsICMTS Website:
http://icmts2014.uniud.it
General Contact:[email protected]
PresentationsThe official language of the conference is English. The ICMTS con-siders both oral and poster presentations to be of equal value andimportance to the conference. The time allowed for oral presenta-tions is 15 minutes plus 5 minutes for discussion. All those authorswho have been selected for poster presentation should be prepared tomake a 3 minute oral presentation describing their research. Therewill be no questions after the presentation as these will be followed byan opportunity to discuss the work with the author at their poster. Itis suggested these talks should be limited to three slides. We welcomethree Invited Speakers to the conference this year: Prof. Kazuo Ter-ada (Hiroshima State University), Dr. Greg Yeric (ARM) and Prof.Mark A. Reed (Yale University). The Invited Speakers are allocated35 minutes plus 5 minutes for questions.
Sala Gusmani,
venue of the Tutorial and Technical Program
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The conference hall offers up to 130 seats and all required facilitiesincluding PC, beamer, and audio equipment. All presentations will beuploaded on the Conference PC before the start of the conference, toallow a smooth transition between consecutive presentations. Hence,all presentation materials should be sent to [email protected] be-fore March the 17th 2014. Adobe PDF and PowerPoint (.ppt and.pptx) formats are accepted. In addition, all presenters are requestedto bring the original files as backup. All speakers are requested toreport to their session chairperson 10 minutes before the session be-gins. They can then familiarize themselves with the control panel,and ensure that their presentation files are correctly loaded on thecomputer system well before the session starts.
Best Paper AwardThe program committee will select one of the regular conference con-tributions for the Best Paper Award. The Best Paper will be an-nounced at the end of the conference. The award will be handedout at ICMTS 2015. Furthermore, the last year’s Best Paper Awardwill be handed out to the recipients. The Award was won last yearwith the paper entitled ”Tr Variance Evaluation induced by ProbingPressure and its Stress Extraction Methodology in 28nm High-K andMetal Gate Process” authored by T. Okagaki and coworkers.
Conference ProceedingsThe conference proceedings will be published in paper and on a USB–stick. One copy of the paper proceedings and one USB stick areincluded in the registration fee. Additional copies will be available atthe conference for 50e per copy.
Conference Registration
Registration Fees
Early Registration (Before Febrary 15st, 2014)Member* Non Member Student**
Tutorial 120e 140e 80e/100eTechnical
320e 350e 180e/210eSessions
Late Registration (After Febrary 15st, 2014)Member* Non Member Student**
Tutorial 140e 160e 100e/120eTechnical
350e 400e 210e/260eSessions
On-site Registration (Registration at the conference)On–site registration goes at the Late Registration.
* Must be a member of the IEEE
** Lower prices for student members of IEEE
Registration fees include admission to the technical sessions, equip-ment exhibits, morning and afternoon coffee breaks, the welcome re-ception, lunch (Monday – tutorial, Tuesday, Wednesday and Thursday– conference), the conference banquet and excursion to Villa Manin.It also includes one paper copy of the proceedings and a USB stick.
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Payment of Registration Fees
For payment, please follow the information reported in the Confer-ence Website: http://icmts2014.uniud.it/2014/index.html . On-site, the registration payment can be in cash, by credit card (VISA,MASTERCARD), or non–transferrable check to ”Dip. di Ing. Elet-trica Gestionale e Meccanica (DIEGM), Univ. di Udine”. The confir-mation of your IEEE Membership or Student status will be conductedduring Registration at the Conference.
Cancellation
Cancellation can only be accepted if a written notice is sent by e-mailor fax to the ICMTS 2014 Secretariat (Fax: +39 0432 558251, email:[email protected]). A charge of 20% of the total registrationfees will be withheld in order to cover administration and bankingcosts. After March 10th 2014, no refund will be possible, but a copyof the Proceedings will be delivered after the Conference. All refundswill be processed after the Conference.
Equipment ExhibitionDuring the conference an equipment exhibition will be held in Saladel Pianoforte, Palazzo Caiselli. The exhibition will display equipmentand systems closely associated with the design, fabrication, analysisand characterisation of test structures. Companies working in re-lated fields present themselves and their products. This exhibitionwill permit one–to–one discussions between exhibitors and conferenceattendees on the latest practices and test equipment. For more de-tails see the ICMTS website. The exhibition opening times are givenbelow along with a preliminary list of exhibitors. The full list will bedistributed at the conference.
March 24 8:50–17:20 Set up – TutorialMarch 25, 26 8:50–17:20 ConferenceMarch 27 9:00–12:40 Conference and Close-down
Exhibitors List (at time of press)
- Agilent Technologies
- Accretech
- JEM Europe
- Keithley
- Tokyo Electron Limited
MessagesIf you need to be contacted during the Conference Sessions, a messagecan be left at the registration desk between the hours of 9:00am and5:00pm, March 24-26, and from 9:00am to 12 noon on March 27.Messages will be placed on a Message Board beside the registrationdesk.
Messages can be posted for attendees by emailing Ms. ChiaraMacuz ([email protected]).
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Internet accessThe conference area is equipped with WiFi internet. The WiFi accesswill be guaranteed to all academic delegates through the eduroam net.If requested, credentials to access the WiFi will be provided to nonacademic delegates. Instructions for WiFi connection can be found at
http://ainf.uniud.it/fileadmin/istruzioni/wi-fi/
Istruzioni_WindowsXPeVista/convegni/WiFi-Cisco-EN.pdf.
Lunch VenueDuring ICMTS the tutorial and conference lunches will be servedat the Sala del Pianoforte of Palazzo Caiselli, just two minutes walkfrom Palazzo Antonini Cernazai. Palazzo Caiselli is situated in VicoloFlorio (2 in blue in the ICMTS Google map).
Conference BanquetThe conference banquet will be held in the Casa della Contadinanza,on the top of the Udine Castle hill.
Casa della Contadinanza, outside
Night view of the Udine Castle square
The conference registration fees include one banquet ticket. Guesttickets are available in the accompanying person package.
ExcursionThe excursion to Villa Manin will take place Thursday afternoon afterlunch, between 14:30 and 18:00 approximately. It is recommended toreserve for the excursion in order to allow the organization to arrangeall details. Transfer to Villa Manin in Passariano will be by bus.
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Details of the excursion will be announced at the conference, whereregistration will take place.
Udine Information
Getting there
• Travelling by plane
Udine is served mainly by three international airports, Venezia,Treviso and Trieste. Connections to/from Udine are served bybus (Trieste and Venezia airports) and by train (Venezia andTreviso airports).
• Travelling by car
Udine is located along Highway A23 which connects Austriawith major highway A4 travelling est to west of Italy. Moreinformations on Autostrade per l’Italia SpA. To plan a travelto Udine by car, you might refer to ViaMichelin website www.
viamichelin.it.
• Travelling by train
Udine Train Station is located 200 meters from the city center.City busses stop in front of the station. Taxis are available atthe station too. Udine is connected by train with all majorItalian cities. Schedules and prices available at Italian Rail-way website http://www.trenitalia.com. When browsing thewebsite make sure to select the ”tutti i treni” - ”all trains”option . Then, insert the stations and dates, click the searchbutton and then click the ”all solutions” option at the centerbottom of the page. Otherwise only a very limited set of highspeed trains will be displayed.
The venue is within 15 minutes walking from Udine’s Train Sta-tion. All conference hotels are within walking distance. For moreinformation on traveling to Udine and on public transport in Udine,check http://icmts2014.uniud.it/2014/logistics.html.
MapA city map with the important locations for ICMTS 2014 (including alarge list of hotel and restaurants) can be found at http://icmts2014.uniud.it/2014/logistics.html
ClimateThe Udine weather in late March may be quite variable. In thisperiod, the daily maximum temperature is around 15 C.
Accommodation
Udine offers a large number of hotels and guest houses coveringa wide range of prices and standards. A list of hotels in Udine withspecial agreements for discounted rates with the University of Udinecan be found at http://icmts2014.uniud.it/2014/hotel_bb.pdf. A
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limited amount of rooms at reduced price are available for studentsat the Residenza Universitaria Delle Grazie and at the CISM (www.cism.it). For more details please check http://icmts2014.uniud.
it/2014/logistics.html
CurrencyThe official currency in Italy is the Euro (e). Banks normally open onweekdays between 9:00am until 1:00 pm and between 2:30 pm until4:30 pm. ATMs are available throughout the city.
Electricity and telephoneThe Italian electricity net is 230 V/50 Hz and uses the L type plug.The cellular phone network is GSM 900/1800. All mobile operatorssupport GPRS and UMTS service.
National Emergency numbersFor emergencies, Police, fire brigade, ambulance: tel.: 112.
Safety and crimeUdine is considered as a safe city. Violent crimes are very rare. Alsopickpocketing is not usual.
Embassies and consulatesItalian embassies and consulates abroad and foreign embassies andconsulates in Italy can be found at www.esteri.it.
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Whether a prospective visitor requires a visa depends on his na-tionality and how long he intends to stay in Italy.
Sight-seeing UdineUdine, the Regional capital of Friuli, and its surroundings, have a lotto offer to visitors: its friendly squares, Tiepolo masterpieces and tra-ditional osterias, the Roman cities of Aquileia and Cividale del Friuli,the lagoon of Grado, the Alps and the Collio vineyards. Because ofits mixed geography, Region Friuli Venezia Giulia has both popularcoastal destinations in the summer and mountain ski resorts in thewinter, as well as year-round opportunities to enjoy this impressivescenery.
According to the legend, the hill where the Castle of Udine standswas built with the ground transported by Attila’s soldiers in their hel-mets, in order to create a rise from which their chief could see the cityof Aquileia burning after his devastating pass. Highlights to visit inthe city are: Torre dell’Orologio, The Cathedral, The medieval Castleand Santa Maria in Castello, Oratorio della Purita, Loggia del Li-onello, the Tiepolo Galleries in the Archbishop Palace, San FrancescoChurch and Piazza delle Erbe. All are within walking distance in thetown center.
You can explore Udine and its surroundings on foot, by bike,car, coach and train. Information is available at Udine Infopoint,Piazza I Maggio, 7, Tel. +39 0432 295972, [email protected], www.facebook.com/udine.turismo. For more information aboutthe city’s history and current activities, check the following websites:http://www.turismofvg.it/Home (in English, German and Italian)and http://www.udine20.it (in Italian).
The FVG Card is a chip card displaying the owner’s name. Youcan buy it on–line (www.turismofvg.it/Special-offers/FVG-Card).From the date of first use, it is valid for 48 hours (15 euros), 72 hours(20 euros) or 7 days (29 euros), and it gives you free entry to anyattraction or transportation it covers, as well as special discounts intheatres, theme parks, cultural events and spas.
Piazza Liberta, Udine historical centre.
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TUTORIALS
Tutorial Lecturer Biographies
Stewart Smith
Stewart Smith received the B. Eng. (hons) degree in Electronics andElectrical Engineering in 1997 and the Ph.D. degree in 2003 from theUniversity of Edinburgh, Scotland, UK. He has published papers atevery ICMTS conference from 1999 onwards and received the bestpaper award at ICMTS 2004 (Awaji, Japan). Stewart is a Lecturerin Electronics with the School of Engineering at the University ofEdinburgh. His research interests include the design and fabrication ofbiological and medical microsystems, integration of novel technologieswith CMOS and test structures for microsystem fabrication processes.He was recently appointed to the Royal Society of Edinburgh, YoungAcademy of Scotland and is an irregular contributor to the YAS bloghttp://researchtheheadlines.org.
Benno Ankele
Benno Ankele received the M. SC degree in applied physics from theUniversity of Technology in Graz (Austria) in 1986. He started hisprofessional career as a university researcher on organic semiconduc-tors at the IFP in Graz before he joined AMS in Unterpremstatten(Austria) as an IC design engineer. In 1994 he became process charac-terization manager of AMS. In 1998 he joined the circuit design centerof Infineon Technologies in Villach (Austria). As a principal engineerand head of the design - technology interface, Benno Ankele is in-volved in the design for manufacturing (DfM) of mixed analog/digitalcircuits.
Andrea Lacaita
Andrea Lacaita is professor of Electron Devices and Analog IC de-sign in the School of Engineering at the Politecnico di Milano. He hasbeen actively involved in the development of Single Photon AvalancheDiodes, nowadays adopted as high sensitivity sensors in various ap-plications. In the fields of mainstream microelectronics he has con-tributed to characterization and modeling of non–volatile memories,both Flash and emerging. Over the past 20 years he has served in tech-nical committees of IEDM, VLSI Symposium, ESSDERC. He has beenDepartment Chair, Member of the Academic Senate and is nowadaysmember of the Board of the Politecnico Foundation. He is now set-ting up PoliFAB, a facility for R&D and service, consisting of 450 m2
cleanrooms.
Andreas Martin
Andreas Martin received his M.Eng.Sc. in Electrical and ElectronicEngineering from the Technical University of Darmstadt, Germany,in 1992. After seven years in the silicon technology characteriza-tion group of the Tyndall Institute (former NMRC), Cork, Ireland hestarted working for the central Reliability Methodology department
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of Infineon Technologies AG in Munich, Germany in the field of fWLRMonitoring. He is involved in advanced and novel test structure de-sign, development of new stress methods and data analysis techniqueson the topics: dielectrics, plasma induced damage, metallization anddevice degradation topics. He has published and co-authored numer-ous papers, given tutorials and invited talks at conferences and servedin committees of the IEEE IRW, IEEE IRPS and of the ”Workshopon Dielectrics in Microelectronics” (WoDiM) for many years. He isa senior member of the IEEE, Infineon’s alternate of the JEDEC-subcommittee 14.2, member of the IEC WLR-workgroup TC 47 andco-chair of the German ITG-group 8.5.6 on ”WLR and reliability sim-ulations”.
Amal Chabli
Amal Chabli joined the CEA in 1983. Mainly involved in physicaland chemical characterization of materials for the micro and nan-otechnology programmes, she has been the leader of the MINATECnanocharacterization project. Since 2009, she is CEA director of re-search in the field of material characterization and she has managedseveral research programs in that field including the ”Recherche Tech-nologique de Base” French programme that supports the investmentand R&D projects on the MINATEC nanocharacterization centre.She is actively contributing to the nanocharacterization road map ofthe Technology Division of the CEA promoting in particular the 3Dnanocharacterization techniques. She has recently extended his re-search activity to the characterization of materials for photovoltaicapplications. She has more than 80 publications with peer reviewselection.
Andrew Marshall
Andrew Marshall is an analog and digital IC design expert, workingon benchmarking of leading edge and future technologies. He is aresearch professor at the University of Texas in Dallas. Dr. Marshallhas authored/co-authored approximately 80 patents and 80 papers.He is co-author of the book ’SOI Design: Analog, Memory and DigitalTechniques’ and sole author of ”Mismatch and Noise in Modern ICProcesses”. Dr. Marshall is a Fellow of both the IEEE and Instituteof Physics, and Fellow Emeritus of Texas Instruments Incorporated.
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Tutorial Programme
Monday, March 24th
Location: Palazzo Antonini Cernazai
08:00 Registration
08:50 Tutorials Opening – Gaudenzio Meneghesso, Tutorials Chair,University of Padova, Italy
09:00 Introduction to Microelectronic Test StructuresStewart Smith, University of Edinburgh, UKThis presentation will begin with a review of test structuresdetailing their history and hot topics over the past 20+ years.The presentation will include the development of test struc-tures for measuring sheet resistance, line width and contact re-sistance. Measurement and equipment developments will alsobe addressed focusing on procedures for obtaining accurate andrepeatable measurements.
10.00 Coffee break
10.20 Process Control Monitoring and Tolerance Modelingfor Analog/Mixed Signal CMOS DesignBenno Ankele, Infineon Technologies Villach, AustriaTest structures are used for process control monitoring (PCM)in IC fabrication as well as for tolerance modeling in IC de-sign. In this tutorial we compare PCM requirements fromfactories and design perspectives. We address questions suchas: which design parameters can / cannot be measured onPCM structures? How to prioritize PCM parameters? Do weneed six-sigma in fabrication / in design? How to deal withdesign parameter tolerances in concurrent engineering? CanPCM techniques support parametric design for manufactura-bility? We strive towards a PCM concept which is lean but doesnot miss the link to statistical parameter tolerances and cor-relations used in analog/mixed signal IC design. Finally, ourmethodology shall also support high-volume products whichare fabricated in a multi-factory scenario.
11:20 Advanced Non–Volatile Memories CharacterizationAndrea Lacaita, Politecnico di Milano, Italy10-years data retention is a key reliability target for non-volatilememories that should be guaranteed to all industrial prod-ucts. To this aim, accelerated qualification tests are usuallyperformed on new technologies and, to speed up data loss,Arrhenius-like time-to-temperature conversions are adopted.However, to derive reliable results a comprehensive understand-ing of the physical mechanisms responsible for data loss isneeded together with a careful assessment of their activationenergy. Moreover, a careful design of the accelerated qualifi-cation test is also essential, to account for real on-field oper-ation and to address the impact of novel unexpected effects.The tutorial will address these referring to two case studies,i.e., floating-gate Flash and Phase Change memories. Focuswill be on the physical mechanisms limiting data retention onthe typical cell, showing data from 41-nm NAND, 45-nm NOR
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and 45-nm PCM technologies and providing quantitative mod-els able to explain experimental observations and supportingaccelerated testing.
12.20 Lunch
14:00 Reliability Characterization in CMOSAndreas Martin, Infineon, Neubiberg, GermanyThis tutorial will present a brief overview of standard CMOSreliability characterization and some new and interesting de-velopments. Two main characterization areas can be distin-guished, process qualification and fWLR (fast Wafer Level Re-liability) Monitoring. Test structure design is closely connectedto the reliability stress and measurement sequence in use. ThreefWLR examples are discussed in detail for: electromigration,NBTI (negative bias temperature instability) and PID (plasmainduced damage). For any reliability data assessment and datacomparison to reliability targets, properly incorporated dataanalysis methods are of great importance. The tutorial is aimedtowards reliability engineers with some basic experience in thefield.
15.00 Coffee break
15:20 Characterization of Nanoscale Materials and DevicesAmal Chabli, CEA Leti, FranceIn the field of micro- and nano-technologies, physical and chem-ical characterization is a powerful tool to support and improvethe material choice, the analysis and correction of scaling ef-fects, the design and validation of integration processes. Im-pressive capabilities are demonstrated in terms of sensitivity,selectivity, depth resolution, and spatial resolution. They maybe based on instrumental effort including synchrotron radia-tion use or advanced configurations of probe-sample interac-tion such as scanning probe microscopy, nano-beam electrondiffraction, transmission electron holography, electron tomog-raphy, and atom probe tomography. Numerous characteriza-tion techniques are available either on full-wafer layers or atthe device level, providing complementary information. As anexample, transmission electron microscopy allows the charac-terization of devices with nanometer-scale resolution, leadingto 2D maps of electrical properties or strain distributions onnano-devices. The tutorial wills to overview how these capabil-ities allow to support the development of advanced technologiesand devices and to understand the electrical tests results.
16:20 Benchmarking and Test Methodologies for BeyondCMOS TechnologiesAndrew Marshall, University of TexasConventional silicon CMOS is approaching the point that scal-ing further will be a monumental task. It is generally assumedthat for electronics is to continue scaling nanoelectronics mustdevelop in a different direction. Some beyond CMOS devicesare charge based, so minor adaptations to test methods are ad-equate. However, others are not charge based, and need newtechniques to verify performance. Test and verification meth-ods for beyond CMOS charge-based and non-charge based de-vices are discussed.
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WELCOME RECEPTION
Monday, March 24thLocation: Sala del Pianoforte, Palazzo Caiselli
18:00-19:30 Welcome Reception
In order to welcome you to ICMTS 2014, a welcome receptionwill be held in Sala del Pianoforte of Palazzo Caiselli. Theaddress is Vicolo Florio, Udine (2 in blue in the map).
TECHNICAL PROGRAMME
Tuesday 25th MarchLocation: Palazzo Antonini Cernazai
08:00–17.00 Registration
08:50 Conference OpeningLuca Selmi, General ChairmanJohan Klootwijk, Technical Program Chairman
SESSION 1: Parameter Extraction
09:00–10:40Co-Chairs: Steward Smith, University of Edinburgh, UK
Loren W. Linholm, Consultant, USA
09:001.1 – Reconsideration of Effective MOSFET ChannelLength Extracted from Channel Resistance (Invited)Kazuo TeradaHiroshima City University, Japan”Channel Resistance Method” (CRM) to extract effective MOS-FET channel length (LEFF ) is briefly surveyed and the LEFF
data for the MOSFET having both “halo” and “extension” inits channel are presented. It is found that LEFF is stronglyaffected by the halo dose and gate voltage. As the halo doseis decreased to zero, LEFF converge to reasonable value andthat for the MOSFET having uniform channel is uniquely de-termined, even if various sample MOSFET sets are used. Tak-ing this property into consideration we propose new channellength definition, which is constant and obeys the classical cur-rent equation for the MOSFET with uniform channel, in orderto provide the common channel length interpretation for bothdesign and technology engineers.
09:401.2 – Effective Field and Universal Mobility in High-kMetal Gate UTBB- FDSOI DevicesO. Nier1,2,3,4, D. Rideau1, A. Cros1, F. Monsieur1, G.Ghibaudo2, R. Clerc5, J. C. Barbe3, C. Tavernier1 and H.Jaouen1
1ST Microelectronics, Crolles, France; 2IMEP-LAHC,MINATEC, France; 3CEA-LETI, MINATEC, France;
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4University of Udine, Italy; 5Laboratoire Hubert Curien &Institut d’Optique, Saint-Etienne, France
This paper aims to review important theoretical aspects of theeffective field (Eeff ) and parameter characterizing the “uni-versal” behavior of the mobility µeff (Eeff ) curves. Experi-mental values for η are extracted for various front and backgate biases conditions, temperatures and for devices with var-ious Equivalent Oxide Thicknesses. We demonstrated that a“nearly universal” trend for the mobility with respect to Eeff
can be obtained only in a limited range of back biases. Indeed,we showed that in reverse back bias conditions, a single value ofη does not make possible a ”universal” plot of the µeff versusEeff .
10:001.3 – Split-CV for pseudo-MOSFET characterization:experimental setups and associated parameter extrac-tion methodsLuca Pirro, Irina Ionica, Gerard Ghibaudo and SorinCristoloveanu
IMEP-LAHC, Grenoble, FranceIn this paper, we present recent advances in the split-CV mea-surement applied for direct characterization of bare SOI waferswith the pseudo-MOSFET test method. We discuss the pro-cedure and precautions needed for correct measurement of ca-pacitance and conductance versus frequency. The experimentalresults are used to illustrate the extraction of carrier mobilityand interface trap density.
10:201.4 – Extraction Procedure for Emitter Series Resis-tance Contributions in SiGeC BiCMOS TechnologiesF. Stein1,2, Z. Huszka3, N. Derrier1, C. Maneux2 and D. Celi11ST Microelectronics, Crolles, France; 2IMS, Universite Bor-deaux, France; 3ams AG, AustriaThe accurate determination of the emitter series resistanceRE has been topic for numerous investigations throughout thedevelopment of modern bipolar device technologies. A goodknowledge of the parasitic resistances of the device under testis important due to the apparent voltage drops over these re-sistors in high current operation. Opposed to the base and col-lector resistance today there are no appropriate individual teststructures that allow for a precise determination of the emitterresistance. In this work we present the application of a newextraction method to a recent SiGeC HBT device technologyfor mmW applications. The new method allows a precise pa-rameter determination of the desired resistance values withoutadding additional cost for a dedicated test structure.
10:40–11:00 Break
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SESSION 2: Memory
11:00–12:20Co-Chairs: Alan Mathewson, Tyndall National Institute, IRL
Kevin McCarthy, UC Cork, IRL
11:002.1 – Statistical Analysis of Resistive Switching Char-acteristics in ReRAM Test ArraysCristian Zambelli, Alessandro Grossi, Piero Olivo, DamianWalckzyk1, Thomas Bertaud1, Bernard Tillack1,2, ThomasSchroeder1,3, Valeriy Stikanov4, Christian Walckzyk1
Universita degli Studi di Ferrara, Italy; 1IHP, Germany;2Technische Universitat Berlin, Germany; 3BrandenburgischeTechnische Universitat, Germany; 4IASA, Kiev, Ukraine
The design and the manufacturing of ReRAM test structuresallow deeper insight in the performance of the FORMING,RESET, and SET operations at array level, providing detailson the process induced variability of the technology, and onthe potential sources of failures. Test structures allow alsodemonstrating the integration capability of the ReRAM tech-nology using a CMOS-compatible process ramping up suchnon-volatile memory to a maturity level.
11:202.2 – Understanding the Switching Mechanism ofCharge-Injection GeTe/Sb2Te3 Phase Change Mem-ory through Electrical Measurement and Analysis of1R Test StructureN. Takaura, T. Ohyanagi, M. Tai, M. Kitamura, M. Kinoshita,K. Akita, T. Morikawa, 1S. Kato, 1M. Araidai, 1K. Kamiya,1T. Yamamoto and K. Shiraishi1
Low-power Electronics Association & Project (LEAP), Japan;1University of Tsukuba, Japan
A new switching mechanism of charge-injection GeTe/Sb2Te3phase change memory was investigated. DC and AC transientanalysis provided deeper understanding of charge-injection en-hancement. Electrical TEG measurements revealed the gener-ation of resistance loop by DC sweep, reset switching of 4 ns,and MLC set with negative resistance for the first time.
11:402.3 – Common-Floating Gate Test Structure for Sep-aration of Cycling-Induced Degradation Componentsin Split-Gate Flash Memory CellsNhan Do and Yuri TkachevSilicon Storage Technology, USA
The endurance limitation in split-gate flash memory is causedby electron traps in the tunneling oxide and in the floating gatechannel silicon dioxide interface. We developed a novel teststructure to separate these two degradation mechanisms. As aresult, the amount of degradation in the floating gate channelcan be accurately measured and suppressed. This improvementenables the new split-gate memory cell concept to be used inproducts that require high endurance performance.
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12:002.4 – Accurate Modeling of Dynamic Variability ofSRAM Cells in 28nm FDSOI TechnologyJ. El Husseini1, A. Subirats1,3, X. Garros1, A. Makoseij1,O. Thomas1, V. Huard2, F. Cacho2, X. Federspiel2 and G.Reimbold1
1CEA-LETI, France; 2ST Microelectronics, Crolles, France;3IMEP-LAHC, MINATEC, France
The paper presents a new methodology to model the dynamicvariability of SRAM cell in 28nm FDSOI technology. This ap-proach can be easily integrated into SPICE and used for circuitdegradation simulation. Based on this methodology, fast BTIstress measurements were carried out on SRAMsized MOS-FETs in order to predict the bitcell’s read margin degradation.Simulations results obtained on a 0.197 µm2 SRAM cell arepresented.
12:20–14:00 Lunch
SESSION 3: Process Characterization I: ContactResistance
14:00–15:20Co-Chairs: Hans P. Tuinhout, NXP, The Netherlands
Sathoshi Habu, Agilent Technologies, Japan
14:003.1 – A Test Structure and Analysis of Contact Resis-tance in FinFET StructureMyung Gil Kang, Sang Hoon Lee, Mun Hyeon Kim, IL RyongKim, Chang Woo Oh, Dong-Won Kim, and Jong Shik YoonSemiconductor R&D Center, Samsung Electronics, KoreaIn multi-gate transistors such as FinFETs and nano-wire FETs,it is difficult to extract contact resistance and source/draindiffusion resistance with conventional test structures such asKelvin bridge. In this work, a simple and accurate extractionmethod of contact resistance and source/drain diffusion resis-tance is presented by using two MOSFET structures whichshare a common diffusion region. CMOS FinFETs on bulkSi using top-down process were used for the demonstration ofcontact resistance extraction method and we found that thecontact resistance of FinFET contributes to 23.1 % and 23 %of total resistance for NFET and PFET, respectively.
14:203.2 – An Approach to Characterize Ultra-Thin Con-ducting Films Protected Against Native Oxidation byan in-situ Capping Layer
H. Van Bui, F. B. Wiggers, M. P. de Jong and A.Y. KovalginMESA+, University of Twente, The Netherlands
We propose and demonstrate the applications of a test struc-ture to characterize electrical properties of ultra-thin TiN filmspassivated by amorphous silicon (a-Si). The a-Si is to preventthe conducting layer from oxidation. Pt-contact pads are madeon top of the a-Si. The good contact between the TiN and Pt,
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which are separated by the a-Si layer, is obtained by the silici-dation of a-Si and Pt at relatively low temperatures.
14:403.3 – Evaluation of Ultra-low Specific Contact Re-sistance Extraction by Cross-Bridge Kelvin ResistorStructure and Transmission Line Method StructureBing-Yue Tsui and Hsuan-Tzu TsengNational Chiao-Tung University, Taiwan
This work evaluates the accuracy of the specific contact resis-tance (rc) extraction by the cross-bridge Kelvin resistor (CBKR)structure and the self-aligned transmission line method (mTLM)structure considering three-dimensional effect. The mTLMstructure is more accurate than the CBKR structure in the-ory. Its sensitivity to the process variation could be eliminatedby averaging data. Nevertheless, the recessed contact interfacewould cause a complicated rc extraction problem for both teststructures at ultra-low rc ≈ 10−8Ω-cm2.
15:003.4 – Gated Contact Chains for Process Characteriza-tion in FinFET Technologies
Tomasz Brozek, Stephen Lam, Shia Yu, Nobuharu Yokoyama1,Mike Pak, Tom Liu, Rakesh ValishayeePDF Solutions, USA; 1PDF Solutions, Japan
Contact chain is a well known element of the diagnostic setof test structures used across many generations of silicon pro-cesses. Implementation of such test structures becomes chal-lenging in new technologies with 3D devices, like FinFET. Con-tacts to active regions of such devices are inherently dependenton the architecture of epitaxial raised source and drain andfor proper characterization require the presence of transistorgates, which set the environment for contacts. This paper de-scribes example of test structures for contact process devel-opment for FinFET technologies. Instead of simple chain ofcontacts, each structure contains a series of active devices withcommon gate electrode used to turn on the chain of transistorsto enable measurement of chain resistance. To discriminatebetween chain failures caused by an open contact or by othermechanism (e.g. bad transistor with very high threshold volt-age) a series of measurement under various test conditions isperformed and analysed to extract the contact failure rate. Wealso demonstrate application of the structures in FinFET pro-cess characterization.
15:20–17:20 Coffee, Poster and Exhibition Session
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SESSION 4: Poster and Exhibitor presentations
15:20–15:45Co-Chairs: Alain Toffoli, CEA-LETI, France
Anthony J. Walton, Univ. Edinburgh, UK
4.1 – A New Technique for Probing the Energy Distribu-tion of Positive Charges in Gate DielectricZ. Ji, S. W. M. Hatta, J. F. Zhang, W. Zhang, J. Niblock1, P.Bachmayr1, L. Stauffer1, K. Wright1 and S. Greer1
Liverpool John Moores University, UK; 1Keithley, Cleveland,USATo simulate impact of stress-induced positive charges in gatedielectric on devices and circuits, it is essential to know their en-ergy distribution both within and beyond substrate band-gap.A new technique is proposed. By implementing to standardparameter analyzer, it serves as a powerful tool for materialand process screening.
4.2 – Low Specific Contact Resistivity Nickel to Silicon Car-bide Determined Using a Two Contact Circular TestStructureYue Pan, Aaron M. Collins, Philip Tanner1, Patrick W. Leech,Geoffrey K. Reeves and Anthony S. Holland
RMIT University, Melbourne, Australia, 1Queensland Mi-crotechnology Facility, Brisbane, Australia
We present the experimentally determined specific contact re-sistivity of as deposited Ni to 3-C silicon carbide using a noveltest structure. The specific contact resistivity, extracted us-ing this test structure and the corresponding methodology, isbetween 0.83 µΩcm2 to 5.7 µΩcm2.
4.3 – A Novel Apparatus For The Volume Estimation of InVitro Thrombus GrowthA. Affanni, R. Specogna and F. TrevisanDIEGM, University of Udine, ItalyWe present a novel apparatus to measure the volume of throm-bus induced in a lab-on-a-chip device under blood flow. Pro-posed inversion technique allows reconstructing thrombus vol-ume versus time. This is not possible with current technologybased on confocal microscopy, where thrombus volume is esti-mated only at the end of the experiment.
4.4 – Comparison of Channel Length Extracted from GateCapacitance with That Extracted from Channel Resis-tanceKatsuhiro Tsuji and Kazuo TeradaHiroshima City University, JapanWe compare the two effective channel lengths LCAP1 andLCAP2, which are extracted from the gate capacitances withand without the fringe component, with the effective channellength extracted from channel resistance LCEF. It is found thatLCAP1 is about 30 nm longer than LCAP2 and almost coin-cides with LCEF for the samples made with 65-nm technology.It is considered that this difference is caused by the extensionregions next to source and drain regions.
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4.5 – 3D IC Testing Using a Chip Prober and a TransparentMembrane Probe Card
Naoya Watanabe, Michiyuki Eto1, Kenji Kawano1, andMasahiro Aoyagi
National Institute of Advanced Industrial Science and Tech-nology, Tsukuba-shi, Japan; 1STK Technology Co., Ltd., Oita,JapanWe performed pre- and post-bond testing of an SRAM/flashmemory chip using a chip prober with a transparent membraneprobe card. By deformation of PEN film (base material ofprobe card) during probing, low-load and damageless probingwas possible and we successfully conducted pre-bond testing of50 µm-thick SRAM/flash memory chip and post-bond testingof stacked chips.
4.6 – Characterisation of Residual Stress in Dielectric FilmsStudied by Automated Wafer Mapping
R. Walker, E. Sirotkin, G. Schiavone, J. G. Terry, S. Smith, A.R. Mount, 1M. P. Y. Desmulliez and A. J. WaltonUniversity of Edinburgh, UK; 1Heriot-Watt University, Edin-burgh, UK
SU-8 is a negative toned epoxy based photoresist, which iswidely used as a structural and dielectric layer in the fabri-cation of MEMS devices. However this material normally ex-hibits high levels of stress during processing. This paper reportsdetailed quantitative data following previous work, where wedemonstrated Parylene-C as a possible replacement for SU-8.Particularly, this paper details the characterisation of residualstress in (i) SU-8 films as a result of processing temperaturesand (ii) post processing thermal treatment of Parylene-C. Thischaracterisation includes wafer mapping strain using rotatingpointer arm test structures, and deriving the stress from inde-pendent measurements of strain and Young’s modulus.
4.7 – A Test Structure for Analysis of Temperature Distri-bution in Stacked IC with Sensing Device ArrayT. Matsuda, K. Yamada, H. Iwata, T. Hatakeyama, M. Ishizukaand T. Ohzone1
Toyama Prefectural University, Japan; 1Dawn Enterprise,Nagoya, Japan
A test structure for analysis of temperature distribution instacked IC, which has a top tier chip attached on a bottomdummy chip with adhesive layer, is presented. The deviceswith four kinds of thickness of 50 - 410 µm were fabricated.Dependences of the temperature on distance from the heaterresistor were analyzed with on-chip sensor arrays, as well as fasttransient phenomena. The thinner top tier structures showedthe higher temperature and affected the temperature distri-butions. The test structure can provide an effective way foranalysis of thermal properties in various LSIs.
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Wednesday 26th MarchLocation: Palazzo Antonini Cernazai
08:15–17.00 Registration
SESSION 5: Yield
09:00–10:40Co-Chairs: Antoine Cros, ST Microelectronics, France
Christopher Hess, PDF Solutions, USA
09:005.1 – Processor Yield at 14nm and Beyond (Invited)
Greg YericARM Holdings, Austin, USAMoore’s law was created with an understanding of yield limita-tions on integrated circuits, but as we enter the 1x logic nodes,quantifying yield loss becomes exponentially more complicated.This is due primarily to the significant process complexitiesthat are being added in an attempt to deliver historic scalingtrends. The complexity drives a need for increasingly accuratequantification of cost/area/yield trade-offs. Even with this on-slaught of process complexity, the underlying process scalingwill fall short of expected scaling. We can offset this scalinggap with increased focus on additional areas of guard-banding,such as variability modeling and reliability modeling. If all ofthe above sounds like “test structures”, it should. This pa-per will examine these technology trends and highlight areasof opportunity for test structure measurements.
09:405.2 – A Novel Compact Model of the Product MarginalYield and its Application for Performance Maximiza-tionAtsushi Tsuda, Takeshi Okagaki, Masako Fujii, Toshikazu Tsut-sui, Yoshio Takazawa, Koji Shibutani, Shigeo Ogasawara, MihoYokota, Kazunori OnozawaRenesas Electronics Corporation, JapanIn this paper, we presented a novel compact model to calculatethe product performance accurately. It becomes possible to es-timate marginal yield before pilot wafer by input of a little Siinformation to compact model. In the result, we can quantita-tively determine optimal transistor target by using our model.
10:005.3 – In-Situ Variability Characterization of IndividualTransistors using Topology-Reconfigurable Ring Oscil-lators
A.K.M Mahfuzul Islam and Hidetoshi OnoderaKyoto University, Japan
We propose a variability characterization methodology whichenables characterization of individual transistors under swith-ing condition. We use a topology-reconfigurable ring oscilla-tor (RO) where various nMOSFET and pMOSFET-sensitivetopologies can be achieved. Using the frequency measurementsof different topologies, estimation of each transistor parameters
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become possible. Measurement and estimation results from a65-nm process shows the validity of our proposed technique.We successfully characterized individual transistor static vari-ation as well as RTN induced threshold voltage fluctuation.
10:205.4 – Circuits to Measure the Delay Variability of MOS-FETsKarthik Balakrishnan and Keith JenkinsIBM T.J. Watson Research Center, USA
Two test circuits have been implemented and measured in or-der to characterize delay variability in individual MOSFETs.Measurement results show that both circuits have high sensi-tivities to gate resistance, which differentiate them from othercircuits which characterize variations in traditional DC param-eters such as threshold voltage and channel length.
10:40–11:00 Break
SESSION 6: RF Characterization
11:00–12:20Co-Chairs: Alexey Kovalgin, Univ. Twente, The Netherlands
Larg H. Weiland, PDF Solutions, USA
11:006.1 – Effect of Seed Layers on the Performance of Pla-nar Spiral Micro-InductorsR. Walker, E. Sirotkin, J. G. Terry, S. Smith, 1M. P. Y. Desmul-liez and A. J. WaltonUniversity of Edinburgh, UK; 1Heriot-Watt University, Edin-burgh, UK
This paper reports on the effect of the electrical performancerelated to magnetic seed layers used within planar powermicro-inductors. These studies involve structural and mag-netic characterisations of Ni80Fe20 films electro-deposited onnon-magnetic and magnetic seed layers (i.e. copper and nickelrespectively). Microelectronic mechanical test structures andX-ray analysis have been used to characterise the stress levelsand structural properties of Ni80Fe20 films electro-depositedon both copper and nickel seed layers. In addition, planar spi-ral micro-inductors have been fabricated in order to confirmthe improvement in the electrical performance from magneticseed layers, as a result of enhanced magnetic and resistive con-tribution.
11:206.2 – A semi-distributed method for Inductor de-embeddingJ. Dang, A. Noculak1, F. Korndorfer2, C. Jungemann1, and B.MeinerzhagenTU Braunschweig, Germany; 1Aachen University, Germany;2IHP, Frankfurt (Oder), GermanyThis paper presents a de-embedding method based on ”pad”and ”thru” test structures for on-wafer inductor characteri-zation. A transmission line model in combination with par-allel admittances describing the pads is used to describe the
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“thru” test structure. This method is compared to thestandard ”open-short”, ”open-thru” and ”pad-open-short” de-embedding methods and electromagnetic simulations. It isdemonstrated that the proposed method is more accurate orsaves chip area compared to the standard de-embedding meth-ods.
11:406.3 – Matched Test Structures for Accurate Charac-terization in Millimeter Wave Range
Rachid Hamani1,2, Cristian Andrei1, Bernard Jarry2, andJulien Lintignat2
1NXP Semiconductors, France; 1XLIM, Limoges, FranceThis paper, presents a novel methodology for small signal equiv-alent circuit extraction suitable for high frequency characteri-zation up to mm-wave range. This methodology allows the de-embedding and the extraction of RF characteristics by the useof a smart matching at 50% of the transistor connected in GSGprobe pads. The method has been validated first on a test mod-ule based on RFMOS transistor fabricated in BiCMOS 0.25 µmtechnology from NXP Semiconductors. The results of matchedRFMOS transistors at 30.5GHz are presented here and showgood agreement between measurements/extractions and calcu-lations (e.g. for ). Second, a bipolar transistor matched teststructure is investigated. An improvement of transmission gainof matched test structured from -12dB to -0.2dB has been foundusing measurements and simulated data.
12:006.4 – On Wafer Silicon Integrated Noise Source char-acterization up to 110 GHz based on Germanium-on-Silicon PhotodiodeS. Oeuvrard1,2, J.-F. Lampin2, G. Ducournau2, S. Lepilliet2,F. Danneville2, T. Quemerais1, D. Gloria1
1ST Microelectronics, France; 2IEMN, Villeneuve d’Ascq,FranceIn this work, a new concept of optical noise source has been de-veloped and characterized, based on a Germanium-on-Siliconphotodiode. Photodiodes RF output power measurements havebeen achieved up to 210 GHz, using an appropriate Opti-cal/High frequency bench, and demonstrating available powerin the range of -30dBm. It turned out that the Excess NoiseRatio of those photodiodes, after careful measurements andcalculations, was in the range of 35 dB at 110 GHz.
12:20–14:10 Lunch
14:10–14:20 ICMTS 2015 Presentation
SESSION 7: Emerging Technologies
14:20–15:40Co-Chairs: Colin McAndrew, Freescale, USA
Kazuo Terada, Hiroshima CU, Japan
14:207.1 –A Test Structure of Bypass Diodes for On-chip
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High-Voltage Silicon Photovoltaic Cell ArrayIsao Mori, Masanori Kubota and Yoshio MitaUniversity of Tokyo, Japan
A bypass diode is an effective solution for degradation issue ofa partially-shaded photovoltaic cell array. We proposed a teststructure of bypass diodes for the on-chip high voltage siliconphotovoltaic cell array we have previously proposed. It showsan appropriate diode size and whether their fabrication processwas performed successfully.
14:407.2 – A Single-Photon Avalanche Diode test chip in150nm CMOS technology
Lucio Pancheri, Leo H. C. Braga1, Hesong Xu1, David Stoppa1
and Gian-Franco Dalla BettaDII, University of Trento, Italy; 1Fondazione Bruno Kessler,Trento, ItalyThe design of Single-Photon Avalanche Diode (SPAD) arraysrequires a clear understanding of the correlation between de-vice characteristics and the geometrical and structural deviceparameters. This work presents a test chip, designed in a 150-nm CMOS technology, tailored to the extraction of the mainfeatures for SPADs of different shapes and sizes.
15:007.3 – Test Structure for Electrical Characterization ofCopper Nanowire Anisotropic Conductive Film (NW-ACF) for 3D Stacking ApplicationsJing Tao, Alan Mathewson, Kafil M. RazeebTyndall National Institute, Cork, IrelandCopper nanowire arrays (≈200 nm diameter) grown in porouspolymer template is a potential low temperature interconnec-tion technology compared with metal/metal or solder micro-bump interconnects for 3D chip stacking. To advance thistechnology, good understanding of material and process relatedelectrical properties is required. In this paper, a stacked testchip module with copper daisy chain pattern, which is finishedby ≈1 µm indium bonding layer, has been designed to extractthe resistance and capacitance data of the NW-ACF.
15:207.4 – Compressively-Stressed Test Structures forOpaque Micro-Structures Releasing VisualizationTixier-Mita A., Lebrasseur E., Takahashi T., 1Francais O., 1LePioufle B., Mita Yoshio, Fujita H., Toshiyoshi H.University of Tokyo, Japan; 1Ecole Nationale Superieure,Cachan, France
Compressively-stressed test structures have been fabricated toprecisely determine the releasing time of low stress and opaqueMEMS. These test structures will deform as soon as it is re-leased, in contrast to low stress target structures that remainsflat. Thanks to the test structure, it becomes possible to detectthe releasing with an optical microscope.
15:40–16:00 Break
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SESSION 8: Material Characterization
16:00–17:20Co-Chairs: Colin McAndrew, Freescale, USA
Greg Yeric, ARM, USA
16:008.1 – Air-CPW Test Structure for Broadband Perme-ability Spectra Measurements of Thin FerromagneticFilms
E. Sirotkin, R. Walker, J. G. Terry, S. Smith, and A. J. WaltonScottish Microelectronics Centre, University of Edinburgh, UKIn this paper we demonstrate a novel technique based on acoplanar waveguide (CPW) test structure for broadband char-acterization of the intrinsic permeability spectra of thin ferro-magnetic films. This measurement is based on the analysis ofS-parameters measured from the CPW test structure connectedto Vector Network Analyzer (VNA) in transmission. The spe-cific feature of the test structure is a small 50% ‘air-CPW’section loaded with thin layer of material under test (MUT).This principal feature allows independent measurements andcomponent separation of complex permeability and permittiv-ity spectra of conductive ferromagnetic films. The techniquecan be conveniently applied for characterization of both con-tinuous and patterned magnetic films.
16:208.2 – Process Parameter Calibration for Millimeter-Wave CMOS Back-End Device Design with Electro-magnetic Field AnalysisS. Amakawa, A. Orii, K. Katayama, K. Takano, M. Motoyoshi,T. Yoshida, and M. FujishimaHiroshima University, JapanThis paper presents a systematic procedure for calibrating pro-cess parameters for electromagnetic field analysis. A few CMOSbackend material parameters are first chosen as fitting param-eters by sensitivity analysis, and then their values are unam-biguously determined from contour maps showing electricalcharacteristics versus material parameters. Calibration withmeasured data for 1–170 GHz is shown to give a reasonableprediction even at higher frequencies.
16:408.3 – Characterization and Development of Materialsfor an Integrated High-Temperature Sensor Using Re-sistive Test Structures
A. Tabasnikov, A. S. Bunting, J. G. Terry, J. Murray, 1G. Cum-mins, 2C. Zhao, 2J. Zhou, 2R. Y. Fu, 1M. P. Y. Desmulliez,A.J. Walton and S. SmithUniversity of Edinburgh, UK; 1Heriot-Watt University, Edin-burgh, UK; 2University of the West of Scotland, Paisley, UKThis paper reports the application of test structures for theevaluation of tantalum nitride (TaN) as a material for integra-tion with high temperature electronics. The process involvesthe reactive sputtering of TaN and its consequent annealing ina vacuum to reach the target specifications of low temperature
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coefficient of resistance (TCR). The test wafer has been de-signed to both evaluate the temperature performance of thinfilms and to study the possibility of integrating different metalfilms into a single sensing device. The TaN resistors resultingfrom this work have a TCR of –150·10–6 C−1, which remainsstable after 6 hours of annealing at 600 C.
17:008.4 – Thickness Evaluation of Deposited PureB Layersin Micro-/Millimeter-Sized Windows to Si V. Moham-madi, S. Ramesh and L. K. NanverDelft University of Technology, The Netherlands
Resistance measurement structures are designed for monitor-ing thickness variations in nanometerthin pure-boron (PureB)layers deposited on Si for (photo-)diode applications whereangstrom-level variations impact performance. In millimeter-large windows a fine resolution is achieved with metal-contactarrays patterned directly on the PureB. For micron-sized win-dows Kelvin structures provide a sensitive solution.
17:20 End of Session 8
18:00 Short excursion to Tiepolo Galleries, Palazzo Ar-civescovile, Udine
20:00 Banquet, Casa della Contadinanza.
Thursday 27th MarchLocation: Palazzo Antonini Cernazai
SESSION 9: Process Characterization II: Devicesand thin layers
09:00–10:40Co-Chairs: Bing-Yue Tsui, Nat. Chiao Tung Univ., Taiwan
Yoshio Mita, University of Tokyo, Japan
09:009.1 – Calibration Methods for Silicon NanowireBioFETs (Invited)A. Vacic, J. M. Criscione, E. Stern, N. K. Rajan, T. Fahmy,and M. A. ReedInstitute for Nanoscience and Quantum Engineering, YaleUniversity, USA
Nanowire Field Effect Transistors have emerged as a promis-ing technology for point-of-care application. However, theirapplication as quantitative sensors has not been well explored.In this work we propose a calibration scheme for multiplexednanoribbon field effect sensors by utilizing the initial currentrate rather than the end point detection. A linear responseof nanosensors is observed in medically relevant range of an-alyte concentration. Moreover, we are able to show that top-down fabrication technique yields reproducible result and de-vices with uniform electrical characteristics. In addition, wedemonstrate that device calibration can be done by using eitherbaseline current or device transconductance normalization.
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09:409.2 – Effects of Metal Spacing and Poly-Silicon Layerson Pulsed-Laser Single Event Transient Testing
Jinshun Bi, Chuanbin Zeng, Linchun Gao, Duoli Li, Gang Liu,Jiajun Luo and Zhengsheng Han
Chinese Academy of Sciences, Beijing, ChinaThe influence of metal spacing and poly-crystalline silicon gateand silicide technology on single event transients occurring inpulsed laser irradiated test patterns was investigated, includingSET rise time, fall time, pulse width, pulse maximum, andcollected charge. Quantitative dependence of the transients onmetal spacing and silicide processing is reported.
10:009.3 – Test Structure to Evaluate the Impact of Neigh-boring Features on Stress of Metal Interconnects
Brad Smith and Mehul Shroff
Freescale Semiconductor, Austin, USAThe stress-inducing effects of neighboring features were studiedusing special stress migration test structures with various lay-outs of neighboring combs. The structures with narrow widthsshowed no change in stress migration, with or without nearneighbor structures. However, structures built with wider linesshowed 3X worse stress migration performance when perpen-dicular combs were present nearby, almost independent of thespacing to the combs.
10:209.4 – Direct Probing Characterization Vehicle TestChip For Wafer Level Exploration of Transistor Pat-tern on Product ChipsChristopher Hess, Kelvin Doong1, Hans Eisenmann2, ScottLin1, Larg Weiland, Amit Joag, Balasubramania Murugan andSa ZhaoPDF Solutions, San Jose, USA; 1PDF Solutions, Zhubei City,Taiwan; 2PDF Solutions, Munich, Germany
Due to recent changes in the manufacturing of FEOL (front endof line) layers it is increasingly difficult to provide rapid learn-ing cycles required to drive yield improvement on new productintroduction (NPI). The Direct Probe Characterization Vehi-cle (DPCV) Test Chips presented here provides direct accessto thousands of transistors on a product chip. Only two masksare needed (contact & metal 1) to provide access to the DUTsof the unchanged FEOL layers of a product chip. The DPCVtest chip is capable of matching the distribution of producttransistor pattern. Measurement data indicate that correctiveactions to the design and/or process recipes will reduce the gapbetween measured product chip transistors and their expectedbehavior based on SPICE simulations.
10:40–11:00 Break
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SESSION 10: Matching
11:00–12:20Co-Chairs: Colin McAndrew, Freescale, USA
Greg Yeric, ARM, USA
11:0010.1 – A Compact Array for Characterizing 32k Tran-sistors in Wafer Scribe LanesChristopher S. Chen, Liping Li, Queennie Lim, Hong Hai Teh,Noor Fadillah Binti Omar, Chun Lee Ler and Jeffrey T. WattProcess Technology Development, Altera Corporation
A new test structure was designed to enable characterization of32k transistors in a wafer scribe lane using standard paramet-ric test equipment. New methods were developed to mitigatedecoder series resistance issues. Random variations in transis-tor threshold voltage measurement data followed the expectednormal distribution up to 4.1 sigma.
11:2010.2 – Analysis of Process Impact on Local VariabilityThanks to Addressable Transistors ArraysA. Cros, T. Quemerais, A. Bajolet, Y. Carminati, P. Norman-don, F. Kergomard, N. Planes, D. Petit, F. Arnaud and J. RosaST Microelectronics, Crolles, France
We designed an addressable transistor arrays to analyse localvariability at the wafer scale. On FDSOI substrates, we mea-sure no impact of the silicon thickness variations on short chan-nel transistors, and demonstrate that the impact on large areatransistors is no more visible when the Tsi is well controlled.
11:4010.3 – Cascode Configuration as a Substitute to LDEMOSFET for Improved Electrical Mismatch Perfor-mance
L. Rahhal1,2, G. Bertrand1, A. Bajolet1, J. Rosa1 and G.Ghibaudo2
1ST Microelectronics, Crolles, France; 2IMEP-LAHC, Mi-natec, Grenoble, France
The work presented in this paper investigates the possibly of re-placing a Lateral Drain Extended MOS (LDEMOS) SOI tran-sistors by a cascode configuration to improve electrical mis-match performance. Thus, the cascode connection of two MOSdevices, known to sustain high drain voltage of LDEMOS SOItransistors, offers the same mismatch robustness of Silicon OnInsulator (SOI) MOS transistors. The individual mismatchconstants associated to Vt for the presented cascode configu-ration are shown to have similar values to those reported forindividual MOS devices.
12:0010.4 – A Cross-Coupled Common Centroid Test Struc-ture Layout Method for High Precision MIM Capaci-tor Mismatch MeasurementsHans Tuinhout and Nicole Wils
NXP Semiconductors, Eindhoven, The Netherlands
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A new layout method based on highly symmetrical quadru-ple connection rails enables much higher precision DUT-1-2-1-2 MIM capacitors mismatch characterization and gives sig-nificantly smaller systematic mismatch errors compared to ap-proaches reported before. A record low random mismatch fluc-tuation standard deviation of 20 ppm (0.002%) is shown to beattainable for large MIM capacitor pairs.
12:20 Best paper announcement and closing remarks
12:40 Lunch
14:20 Excursion
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CONFERENCE OFFICIALS
Conference CommitteeGeneral Chairman:
Luca SelmiDIEGM, Universita degli Studi di UdineVia delle Scienze 20633100 UdineItalyTel: +39 0432 558293Fax: +39 0432 558251E-mail: [email protected]
Technical Chairman:Johan KlootwijkPhilips Research EuropeHigh Tech Campus 45656AA EindhovenThe NetherlandsTel: +31-40-274-4735Fax: +31-40-274-3352E-mail: [email protected]
Local Arrangements:Francesco DriussiDIEGM, Universita degli Studi di UdineVia delle Scienze 20633100 UdineItalyTel: +39 0432 558295Fax: +39 0432 558251E-mail: [email protected]
Tutorial Chairman:Gaudenzio Meneghesso,DII, Universita di PadovaVia Gradenigo 6/B35131 PadovaItalyTel: +39-049 827 7653Fax: +39-049 827 7699E-mail: [email protected]
Equipment Exhibition:Alain ToffoliCEA/Leti – MINATEC3 parvis Louis Neel38054 F-Grenoble cedex 9FranceE-mail: [email protected]
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USA Representative:Loren W. LinholmTel: +1-301-607-6569E-mail: [email protected]
European Representative:Anthony J. WaltonScottish Microelectronics CentreSchool of Engineering and ElectronicsThe King’s Buildings, The University of EdinburghEdinburgh, EH9 3JF, UKTel: +44-(0)-131-650-5620Fax: +44-(0)-131-650-6554E-mail: [email protected]
Asian Representative:Kunihiro AsadaThe University of TokyoVLSI Design and Education Center2-11-16 Yayoi, Bunkyo-ku, Tokyo 113-8656, JapanTel: +81-3-5841-6671Fax: +81-3-5841-8911E-mail: [email protected]
Steering Committee
Anthony J. Walton University of Edinburgh ScotlandBill Verzi Agilent Technologies USAKunihiro Asada University of Tokyo JapanLoren Linholm USALuca Selmi Universita degli Studi di Udine ItalySatoshi Habu Agilent Japan
31
Technical CommitteeRichard Allen National Institute of USA
Standards and TechnologyYu Cao Arizona State University USAAntoine Cros ST Microelectronics FranceSatoshi Habu Agilent Technologies Japan
Japan, Inc.Christopher Hess Pdf Solutions Inc. USAKjell Jeppson Chalmers University Sweden
of TechnologyWon-Young Jung Dongbu Hitek Inc. KoreaChang Yong Kang Sematech USAMark Ketchen IBM T. J. Watson Research
CenterUSA
Johan Klootwijk Philips Research Europe The NetherlandsAlexey Kovalgin Mesa+ Institute For The Netherlands
NanotechnologyChoongho Lee Samsung Electronics KoreaHi-Deok Lee Chungnam National Univ. KoreaLoren W. Linholm Consultant USAEmilio Lora-Tamayo Universitat Autonoma Spain
de BarcelonaAlan Mathewson Tyndall National Institute IrelandHiroaki Matsui University of Tokyo JapanColin McAndrew Freescale Semiconductor USAKevin McCarthy University College Cork IrelandYoshio Mita University of Tokyo JapanJerome Mitard IMEC BelgiumTatsuya Ohguro Toshiba JapanMark Poulter Texas Instruments USATsuyoshi Sekitani University of Tokyo JapanLuca Selmi Universita degli Studi Italy
di UdineBrad Smith Freescale Semiconductor USAStewart Smith Scottish Microelectronics
CentreUK
Lee Stauffer Keithley Instruments Inc. USAKenichi Takeda Hitachi JapanKiysohi Takeuchi Renesas Electronics Corpo-
rationJapan
Kazuo Terada Hiroshima City University JapanAlain Toffoli Cea/Leti - Minatec FranceBing-Yue Tsui National Chiao Tung Taiwan
UniversityHans P.Tuinhout NXP Semiconductors The NetherlandsBill Verzi Agilent Technologies USAAnthony J.Walton University of Edinburgh UKLarg H.Weiland Pdf Solutions Inc. USAGreg Yeric Arm USA
32
ICM
TS
2014CONDENSED
PROGRAM
Monday
,M
arc
h24
08:0
0R
egis
trati
on
08:5
0T
uto
rial
op
enin
g
09:0
0T
est
Str
uct
ure
Fund.
10:0
0B
reak
10:2
0P
roce
ssC
ontr
ol
and
Tol-
erance
for
Analo
gD
esig
n
11:2
0N
VM
Chara
cter
izati
on
12:2
0L
unch
14:0
0R
elia
bilit
yC
hara
cter
iza-
tion
inC
MO
S
15:0
0B
reak
15:2
0N
anosc
ale
mate
rials
and
dev
ices
chara
cter
izati
on
16:2
0B
eyond
CM
OS
Ben
ch-
mark
ing
and
Tes
t
17:2
0E
nd
of
Tuto
rials
Wel
com
eR
ecep
tion
Tues
day
,M
arc
h25
08:0
0R
egis
trati
on
08:5
0C
onfe
rence
Op
enin
g
09:0
0Ses
sion
1
Para
met
erex
tract
ion
(wit
hIn
vit
ed)
10:4
0B
reak
11:0
0Ses
sion
2
Mem
ory
12:2
0L
unch
14:0
0Ses
sion
3
Pro
cess
chara
c.:
conta
ctre
sist
ance
15:2
0Ses
sion
4
Coff
ee,
Post
ers
and
Exhib
itio
n
17:2
0E
nd
of
Day
1
Wed
nes
day
,M
arc
h26
08:1
5R
egis
trati
on
09:0
0Ses
sion
5
Yie
ld(w
ith
Invit
ed)
10:4
0B
reak
11:0
0Ses
sion
6
RF
chara
cter
izati
on
12:2
0L
unch
14:1
0IC
MT
S2015
14:2
0Ses
sion
7
Em
ergin
gte
ch.
15:4
0B
reak
16:0
0Ses
sion
8
Mate
rial
chara
c.
17:2
0E
nd
of
Day
2
18:0
0Short
excu
rsio
n
20:0
0B
anquet
Thurs
day
,M
arc
h27
08:3
0R
egis
trati
on
09:0
0Ses
sion
9
Pro
cess
chara
c.:
dev
ices
and
thin
layer
s
(wit
hIn
vit
ed)
10:4
0B
reak
11:0
0Ses
sion
10
Matc
hin
g
12:2
0B
est
Pap
erand
Clo
sing
rem
ark
s
12:4
0L
unch
14:2
0E
xcu
rsio
n
