28/44-Pin, High-Performance USB MCUs with XLP Technology...Errata An errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist

PIC18F47J53 FAMILY28/44-Pin, High-Performance USB MCUs with XLP Technology

Universal Serial Bus Features:• USB V2.0 Compliant• Low Speed (1.5 Mbps) and Full Speed (12 Mbps)• Supports Control, Interrupt, Isochronous and Bulk

Transfers• Supports up to 32 Endpoints (16 bidirectional)• USB module can use any RAM Location on the

Device as USB Endpoint Buffers• On-Chip USB Transceiver with Crystal-Less Operation

Power Management with XLP• Deep Sleep mode: CPU off, Peripherals off, Currents

Down to 13 nA and 850 nA with RTCC- Able to wake-up on external triggers,

programmable WDT or RTCC alarm- Ultra Low-Power Wake-up (ULPWU)

• Sleep mode: CPU off, Peripherals off, SRAM on, Fast Wake-up, Currents Down to 105 nA Typical

• Idle: CPU off, Peripherals on, Currents Down to 2.3 A Typical

• Run: CPU on, Peripherals on, Currents Down to 6.2 A Typical

• Timer1 Oscillator w/RTCC: 1 μA, 32 kHz Typical• Watchdog Timer: 0.8 μA, 2V Typical

Special Microcontroller Features:• 5.5V Tolerant Inputs (digital-only pins)• Low-Power, High-Speed CMOS Flash Technology• C Compiler Optimized Architecture for Re-Entrant Code• Priority Levels for Interrupts• Self-Programmable under Software Control• 8 x 8 Single-Cycle Hardware Multiplier• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s• Single-Supply In-Circuit Serial Programming™

(ICSP™) via Two Pins• In-Circuit Debug with Three Breakpoints via Two Pins• Operating Voltage Range of 2.0V to 3.6V• On-Chip 2.5V Regulator• Flash Program Memory of 10,000 Erase/Write

Cycles Minimum and 20-Year Data Retention

Flexible Oscillator Structure:• High-Precision PLL for USB• Two External Clock modes, up to 48 MHz (12 MIPS)• Internal, 31-kHz Oscillator• High-Precision, Internal Oscillator for USB, 31 kHz to

8 MHz or 48 MHz w/PLL, ±.15% Typical, ±1% Max• Secondary Oscillator using Timer1 at 32 kHz• Fail-Safe Clock Monitor (FSCM):

- Allows for safe shutdown if any clock stops• Programmable Reference Clock Output Generator

Peripheral Highlights:• Peripheral Pin Select:

- Allows independent I/O mapping of many peripherals- Continuous hardware integrity checking and safety

interlocks prevent unintentional configuration changes• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions• High-Current Sink/Source 25 mA/25mA

(PORTB and PORTC)• Four Programmable External Interrupts• Four Input Change Interrupts• Three Enhanced Capture/Compare/PWM (ECCP) modules:

- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-shutdown and auto-restart- Pulse steering control

• Seven Capture/Compare/PWM (CCP) modules• Two Master Synchronous Serial Port (MSSP)

modules Supporting Three-Wire SPI (all four modes) and I2C Master and Slave modes

• Eight-Bit Parallel Master Port/Enhanced Parallel Slave Port

• Three Analog Comparators with Input Multiplexing• 10/12-Bit Analog-to-Digital (A/D) Converter

module:- Up to 13 input channels- Auto-acquisition capability- Conversion available during Sleep

• High/Low-Voltage Detect module• Charge Time Measurement Unit (CTMU):

- Supports capacitive touch sensing for touch screens and capacitive switches

- Provides precise resolution time measure-ment for flow measurement and simple tem-perature sensing

• Two Enhanced USART modules:- Supports RS-485, RS-232 and LIN/J2602- Auto-wake-up on Start bit- Auto-Baud Detect (ABD)

2009-2016 Microchip Technology Inc. DS30009964C-page 1

PIC18F47J53

TABLE 1: PIC18F47J53 FAMILY TYPES

PIC18FDevice Pi

ns

Prog

ram

M

emor

y (b

ytes

)

SRA

M (b

ytes

)

Rem

appa

ble

Pins

Tim

ers

8/16

-Bit

ECC

P/(P

WM

)

EUSA

RT

MSSP

10/1

2-B

it A

/D (C

h)

Com

para

tors

Dee

p Sl

eep

PMP/

PSP

CTM

U

RTC

C

USBSPI w/

DMA I2C

PIC18F26J53 28 64K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y YPIC18F27J53 28 128K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 Y N Y Y YPIC18F46J53 44 64K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y YPIC18F47J53 44 128K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 Y Y Y Y YPIC18LF26J53 28 64K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 N N Y Y YPIC18LF27J53 28 128K 3.8K* 16 4/4 3/7 2 2 Y Y 10 3 N N Y Y YPIC18LF46J53 44 64K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 N Y Y Y YPIC18LF47J53 44 128K 3.8K* 22 4/4 3/7 2 2 Y Y 13 3 N Y Y Y Y

* Dual access RAM for USB and/or general purpose use.

DS30009964C-page 2 2009-2016 Microchip Technology Inc.

PIC18F47J53

Pin Diagrams

PIC

18F2

XJ53

1011

23456

1

87

9

121314 15

1617181920

232425262728

2221

MCLRRA0/AN0/C1INA/ULPWU/RP0

RA1/AN1/C2INA/VBG/RP1RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF

RA3/AN3/C1INB/VREF+VDDCORE/VCAP

RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2VSS1

OSC1/CLKI/RA7OSC2/CLKO/RA6

RC0/T1OSO/T1CKI/RP11RC1/CCP8/T1OSI/UOE/RP12

RC2/AN11/C2IND/CTPLS/RP13VUSB

RB7/CCP7/KBI3/PGD/RP10RB6/CCP6/KBI2/PGC/RP9RB5/CCP5/KBI1/SDI1/SDA1/RP8RB4/CCP4/KBI0/SCK1/SCL1/RP7RB3/AN9/C3INA/CTED2/VPO/RP6RB2/AN8/C2INC/CTED1/VMO/REFO/RP5RB1/AN10/C3INC/RTCC/RP4RB0/AN12/C3IND/INT0/RP3VDDVSS2RC7/CCP10/RX1/DT1/SDO1/RP18RC6/CCP9/TX1/CK1/RP17RC5/D+/VPRC4/D-/VM

28-Pin SPDIP/SOIC/SSOP

28-Pin QFN

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

PIC18F2XJ53

RC

0/T1

OS

O/T

1CK

I/RP1

1

54

RB

7/C

CP7

/KB

I3/P

GD

/RP1

0R

B6/

CC

P6/K

BI2

/PG

C/R

P9R

B5/

CC

P5/K

BI1

/SD

I1/S

DA

1/R

P8R

B4/

CC

P4/K

BI0

/SC

K1/

SC

L1/R

P7

RB3/AN9/C3INA/CTED2/VPO/RP6RB2/AN8/C2INC/CTED1/VMO/REFO/RP5RB1/AN10/C3INC/RTCC/RP4RB0/AN12/C3IND/INT0/RP3VDDVSS2RC7/CCP10/RX1/DT1/SDO1/RP18

RC

6/C

CP9

/TX1

/CK

1/R

P17

RC

5/D

+/V

PR

C4/

D-/V

M

MC

LRR

A0/

AN

0/C

1IN

A/U

LPW

U/R

P0R

A1/A

N1/

C2I

NA

/VB

G/R

P1

RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREFRA3/AN3/C1INB/VREF+

VDDCORE/VCAPRA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2

VSS1OSC1/CLKI/RA7

OSC2/CLKO/RA6R

C1/

CC

P8/

T1O

SI/U

OE

/RP1

2R

C2/

AN

11/C

2IN

D/C

TPLS

/RP1

3V U

SB

Legend: Shaded pins are 5.5V tolerant. RPn represents remappable pins. Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS mod-ule, see Section 10.7 “Peripheral Pin Select (PPS)”.

Note: For the QFN package, it is recommended that the bottom pad be connected to VSS.


PIC18F47J53

Pin Diagrams (Continued)

44-Pin QFN

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4XJ53

37

RA3

/AN

3/C

1IN

B/V

RE

F+R

A2/

AN

2/C

2IN

B/C

1IN

D/C

3IN

B/VR

EF-

/CVR

EF

RA

1/AN

1/C

2IN

A/V

BG

/PM

A7/

RP1

RA

0/A

N0/

C1I

NA

/ULP

WU

/PM

A6/

RP0

MC

LRR

B7/C

CP

7/KB

I3/P

GD

/RP1

0R

B6/

CC

P6/

KB

I2/P

GC

/RP9

RB

5/C

CP5

/PM

A0/

KBI

1/S

DI1

/SD

A1/

RP8

RB

4/C

CP

4/P

MA

1/KB

I0/S

CK

1/S

CL1

/RP7N

CR

C6/

CC

P9/P

MA

5/TX

1/C

K1/

RP1

7R

C5/

D+/

VP

RC

4/D

-/VM

RD

3/P

MD

3/R

P20

RD

2/P

MD

2/R

P19

RD

1/P

MD

1/S

DA

2R

D0/

PM

D0/

SC

L2V U

SB

RC

2/A

N11

/C2I

ND

/CTP

LS/R

P13

RC

1/C

CP8

/T1O

SI/U

OE

/RP1

2R

C0/

T1O

SO

/T1C

KI/R

P11

OSC2/CLKO/RA6OSC1/CLKI/RA7VSS2

AVDD2RE2/AN7/PMCSRE1/AN6/PMWRRE0/AN5/PMRDRA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2VDDCORE/VCAP

RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18RD4/PMD4/RP21RD5/PMD5/RP22RD6/PMD6/RP23

VSS1

VDD1RB0/AN12/C3IND/INT0/RP3

RB1/AN10/C3INC/PMBE/RTCC/RP4RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5

RB

3/AN

9/C

3IN

A/C

TED

2/P

MA

2/VP

O/R

P6RD7/PMD7/RP24 5

4 AVSS1VDD2

AVDD1

Legend: RPn represents remappable pins.Shaded pins are 5.5V tolerant.

Note: For the QFN package, it is recommended that the bottom pad be connected to VSS.


PIC18F47J53

Pin Diagrams (Continued)

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4XJ53

37

RA

3/A

N3/

C1I

NB

/VR

EF+

RA

2/A

N2/

C2I

NB

/C1I

ND

/C3I

NB/

VRE

F-/C

VRE

FR

A1/

AN

1/C

2IN

A/V

BG

/PM

A7/

RP1

RA

0/A

N0/

C1I

NA

/ULP

WU

/PM

A6/

RP0

MC

LRNC

RB

7/C

CP

7/K

BI3

/PG

D/R

P10

RB

6/C

CP

6/K

BI2/

PG

C/R

P9R

B5/

CC

P5/

PM

A0/

KBI

1/S

DI1

/SD

A1/

RP8

RB

4/C

CP

4/P

MA

1/KB

I0/S

CK

1/S

CL1

/RP7N

CR

C6/

CC

P9/

PM

A5/

TX1/

CK1

/RP1

7R

C5/

D+/

VP

RC

4/D

-/VM

RD

3/P

MD

3/R

P20

RD

2/P

MD

2/R

P19

RD

1/P

MD

1/S

DA

2R

D0/

PM

D0/

SC

L2V U

SB

RC

2/A

N11

/C2I

ND

/CTP

LS/R

P13

RC

1/C

CP

8/T1

OS

I/UO

E /R

P12

NC

NCRC0/T1OSO/T1CKI/RP11OSC2/CLKO/RA6OSC1/CLKI/RA7VSS2VDD2RE2/AN7/PMCSRE1/AN6/PMWRRE0/AN5/PMRDRA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2VDDCORE/VCAP

RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18RD4/PMD4/RP21RD5/PMD5/RP22RD6/PMD6/RP23

VSS1VDD1

RB0/AN12/C3IND/INT0/RP3RB1/AN10/C3INC/PMBE/RTCC/RP4

RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6

44-Pin TQFP(2)

RD7/PMD7/RP24 54

Legend: RPn represents remappable pins.Shaded pins are 5.5V tolerant.

Note: Dedicated AVDD/AVSS pins are available only on the 44-pin QFN package. Other packages internally tieAVDD/AVSS to VDD/VSS.


PIC18F47J53

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 82.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 273.0 Oscillator Configurations ............................................................................................................................................................ 314.0 Low-Power Modes...................................................................................................................................................................... 435.0 Reset .......................................................................................................................................................................................... 606.0 Memory Organization ................................................................................................................................................................. 767.0 Flash Program Memory............................................................................................................................................................ 1048.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 1149.0 Interrupts .................................................................................................................................................................................. 11610.0 I/O Ports ................................................................................................................................................................................... 13611.0 Parallel Master Port (PMP)....................................................................................................................................................... 17412.0 Timer0 Module ......................................................................................................................................................................... 19913.0 Timer1 Module ......................................................................................................................................................................... 20314.0 Timer2 Module ......................................................................................................................................................................... 21315.0 Timer3/5 Module ...................................................................................................................................................................... 21716.0 Timer4/6/8 Module ................................................................................................................................................................... 22717.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 23018.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 24919.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 26120.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 28321.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 33722.0 10/12-bit Analog-to-Digital Converter (A/D) Module................................................................................................................. 35923.0 Universal Serial Bus (USB) ...................................................................................................................................................... 37124.0 Comparator Module.................................................................................................................................................................. 39825.0 Comparator Voltage Reference Module................................................................................................................................... 40526.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 40827.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 41428.0 Special Features of the CPU.................................................................................................................................................... 42929.0 Instruction Set Summary .......................................................................................................................................................... 44730.0 Development Support............................................................................................................................................................... 49731.0 Electrical Characteristics .......................................................................................................................................................... 50132.0 Packaging Information.............................................................................................................................................................. 542Appendix A: Revision History............................................................................................................................................................. 559Appendix B: Migration From PIC18F46J50 to PIC18F47J53............................................................................................................. 560The Microchip Website....................................................................................................................................................................... 561Customer Change Notification Service .............................................................................................................................................. 561Customer Support .............................................................................................................................................................................. 561Reader Response .............................................................................................................................................................................. 561Product Identification System............................................................................................................................................................. 562


PIC18F47J53

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected]. We welcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Website; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our website at www.microchip.com to receive the most current information on all of our products.


mailto:[email protected]://www.microchip.comhttp://www.microchip.com

PIC18F47J53

1.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:

This family introduces a new line of low-voltageUniversal Serial Bus (USB) microcontrollers with themain traditional advantage of all PIC18 microcontrollers,namely, high computational performance and a richfeature set at an extremely competitive price point.These features make the PIC18F47J53 family a logicalchoice for many high-performance applications, wherecost is a primary consideration.

1.1 Core Features

1.1.1 XLP TECHNOLOGYAll of the devices in the PIC18F47J53 family incorpo-rate a range of features that can significantly reducepower consumption during operation. Key features are:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operational requirements.

• On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the users to incorporate power-saving ideas into their application’s software design.

• Deep Sleep: The 2.5V internal core voltage regu-lator on F parts can be shutdown to cut power consumption to as low as 15 nA (typical). Certain features can remain operating during Deep Sleep, such as the Real-Time Clock Calendar.

• Ultra Low Power Wake-Up: Waking from Sleep or Deep Sleep modes after a period of time can be done without an oscillator/clock source, saving power for applications requiring periodic activity.

1.1.2 UNIVERSAL SERIAL BUS (USB)Devices in the PIC18F47J53 family incorporate afully-featured USB communications module with abuilt-in transceiver that is compliant with the USBSpecification Revision 2.0. The module supports bothlow-speed and full-speed communication for allsupported data transfer types.

1.1.3 OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F47J53 family offer fivedifferent oscillator options, allowing users a range ofchoices in developing application hardware. Theseinclude:

• Two Crystal modes, using crystals or ceramic resonators.

• Two External Clock modes, offering the option of a divide-by-4 clock output.

• An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approxi-mately 31 kHz, stable over temperature and VDD), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of eight clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier available to the high-speed crystal, and external and internal oscillators, providing a clock speed up to 48 MHz.

• Dual clock operation, allowing the USB module to run from a high-frequency oscillator while the rest of the microcontroller is clocked at a different frequency.

The internal oscillator block provides a stable referencesource that gives the PIC18F47J53 family additionalfeatures for robust operation:

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset (POR), or wake-up from Sleep mode, until the primary clock source is available.

1.1.4 EXPANDED MEMORYThe PIC18F47J53 family provides ample room forapplication code, from 64 Kbytes to 128 Kbytes of codespace. The Flash cells for program memory are ratedto last in excess of 10000 erase/write cycles. Dataretention without refresh is conservatively estimated tobe greater than 20 years.

The Flash program memory is readable and writableduring normal operation. The PIC18F47J53 family alsoprovides plenty of room for dynamic application datawith up to 3.8 Kbytes of data RAM.

• PIC18F26J53 • PIC18LF26J53• PIC18F27J53 • PIC18LF27J53• PIC18F46J53 • PIC18LF46J53• PIC18F47J53 • PIC18LF47J53


PIC18F47J53

1.1.5 EXTENDED INSTRUCTION SETThe PIC18F47J53 family implements the optionalextension to the PIC18 instruction set, adding eightnew instructions and an Indexed Addressing mode.Enabled as a device configuration option, the extensionhas been specifically designed to optimize re-entrantapplication code originally developed in high-levellanguages, such as C.

1.1.6 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.

The consistent pinout scheme used throughout theentire family also aids in migrating to the next largerdevice.

The PIC18F47J53 family is also pin compatible withother PIC18 families, such as the PIC18F4550,PIC18F2450 and PIC18F46J50. This allows a newdimension to the evolution of applications, allowingdevelopers to select different price points withinMicrochip’s PIC18 portfolio, while maintaining thesame feature set.

1.2 Other Special Features• Communications: The PIC18F47J53 family

incorporates a range of serial and parallel com-munication peripherals, including a fully featured USB communications module that is compliant with the USB Specification Revision 2.0. This device also includes two independent Enhanced USARTs and two Master Synchronous Serial Port (MSSP) modules, capable of both Serial Peripheral Interface (SPI) and I2C (Master and Slave) modes of operation. The device also has a parallel port and can be configured to serve as either a Parallel Master Port (PMP) or as a Parallel Slave Port (PSP).

• CCP/ECCP Modules: All devices in the family incorporate seven Capture/Compare/PWM (CCP) modules and three Enhanced Capture/Com-pare/PWM (ECCP) modules to maximize flexibility in control applications. ECCPs offer up to four PWM output signals each. The ECCPs also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes.

• 10/12-Bit A/D Converter: This module incorpo-rates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 31.0 “Electrical Characteristics” for time-out periods.

1.3 Details on Individual Family Devices

Devices in the PIC18F47J53 family are available in28-pin and 44-pin packages. Block diagrams for thetwo groups are shown in Figure 1-1 and Figure 1-2.The devices are differentiated from each other in twoways:

• Flash program memory (two sizes: 64 Kbytes for the PIC18FX6J53 and 128 Kbytes for PIC18FX-7J53)

• I/O ports (three bidirectional ports on 28-pin devices, five bidirectional ports on 44-pin devices)

All other features for devices in this family are identical.These are summarized in Table 1-1 and Table 1-2.

The pinouts for the PIC18F2XJ53 devices are listed inTable 1-3. The pinouts for the PIC18F4XJ53 devicesare shown in Table 1-4.

The PIC18F47J53 family of devices provides anon-chip voltage regulator to supply the correct voltagelevels to the core. Parts designated with an “F” partnumber (such as PIC18F47J53) have the voltageregulator enabled.

These parts can run from 2.15V-3.6V on VDD, but shouldhave the VDDCORE pin connected to VSS through alow-ESR capacitor. Parts designated with an “LF” partnumber (such as PIC18LF47J53) do not enable the volt-age regulator nor support Deep Sleep mode. For “LF”parts, an external supply of 2.0V-2.7V has to be suppliedto the VDDCORE pin while 2.0V-3.6V can be supplied toVDD (VDDCORE should never exceed VDD).

For more details about the internal voltage regulator,see Section 28.3 “On-Chip Voltage Regulator”.


PIC18F47J53

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ53 (28-PIN DEVICES)

TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ53 (44-PIN DEVICES)

Features PIC18F26J53 PIC18F27J53

Operating Frequency DC – 48 MHz DC – 48 MHzProgram Memory (Kbytes) 64 128Program Memory (Instructions) 32,768 65,536Data Memory (Kbytes) 3.8 3.8Interrupt Sources 30I/O Ports Ports A, B, CTimers 8Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCPSerial Communications MSSP (2), Enhanced USART (2), USBParallel Communications (PMP/PSP) No10/12-Bit Analog-to-Digital Module 10 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set EnabledPackages 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil)

Features PIC18F46J53 PIC18F47J53

Operating Frequency DC – 48 MHz DC – 48 MHzProgram Memory (Kbytes) 64 128Program Memory (Instructions) 32,768 65,536Data Memory (Kbytes) 3.8 3.8Interrupt Sources 30I/O Ports Ports A, B, C, D, ETimers 8Enhanced Capture/Compare/PWM Modules 3 ECCP and 7 CCPSerial Communications MSSP (2), Enhanced USART (2), USBParallel Communications (PMP/PSP) Yes10/12-Bit Analog-to-Digital Module 13 Input Channels

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set EnabledPackages 44-Pin QFN and TQFP


PIC18F47J53

FIGURE 1-1: PIC18F2XJ53 (28-PIN) BLOCK DIAGRAM

InstructionDecode and

Control

PORTAData Latch

Data Memory(3.8 Kbytes)

Address Latch

Data Address12

AccessBSR FSR0FSR1FSR2

inc/declogic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

Address Latch

Program Memory(16 Kbytes-64 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.2: BOR functionality is provided when the on-board voltage regulator is enabled.

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0ADC

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

Decode

8

8

EUSART2

ROM Latch

MSSP2

PORTC

RA0:RA7(1)

RC0:RC7(1)

PORTB

RB0:RB7(1)

Timer4

OSC1/CLKIOSC2/CLKO

VDD,

8 MHzINTOSC

VSS MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

Brown-outReset(2)

Precision

ReferenceBand Gap

INTRCOscillator

RegulatorVoltage

VDDCORE/VCAP

CTMU

TimingGeneration

USBModule

VUSB

HLVDRTCC

ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 USB

Timer5 Timer6 Timer8


PIC18F47J53

FIGURE 1-2: PIC18F4XJ53 (44-PIN) BLOCK DIAGRAM

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

8

83

W8

8

8

InstructionDecode and

Control

Data Latch

Address Latch

Data Address12

AccessBSR FSR0FSR1FSR2

inc/declogic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

Address Latch

Program Memory(16 Kbytes-64 Kbytes)

Data Latch

20

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

ROM Latch

PCLATU

PCU

Instruction Bus

STKPTR Bank

State MachineControl Signals

Decode

Syst

em B

us In

terfa

ce

AD, A(Multiplexed with PORTDand PORTE)

PORTA

PORTC

PORTD

PORTE

RA0:RA7(1)

RC0:RC7(1)

RD0:RD7(1)

RE0:RE2(1)

PORTB

RB0:RB7(1)

Note 1: See Table 1-3 for I/O port pin descriptions.2: The on-chip voltage regulator is always enabled by default.

Data Memory(3.8 Kbytes)

OSC1/CLKIOSC2/CLKO

VDD,

8 MHzINTOSC

VSS MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

Brown-outReset(2)

Precision

ReferenceBand Gap

INTRCOscillator

RegulatorVoltage

VDDCORE/VCAP

TimingGeneration

USBModule

VUSB

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0ADC

EUSART2 MSSP2

Timer4

CTMU

HLVDRTCC

ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 USB

Timer5 Timer6 Timer8


PIC18F47J53

TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS

Pin Name

Pin NumberPin

TypeBufferType Description

28-SPDIP/SSOP/SOIC

28-QFN

MCLR 1(2) 26(2) I ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

OSC1/CLKI/RA7OSC1

CLKI

RA7(1)

9 6I

I

I/O

ST

CMOS

TTL/DIG

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. Main oscillator input connection.External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins).Digital I/O.

OSC2/CLKO/RA6OSC2

CLKO

RA6(1)

10 7O

O

I/O

—

DIG

TTL/DIG

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.Main oscillator feedback output connection.In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Digital I/O.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)DIG = Digital output I2C = Open-Drain, I2C specific

Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.2: 5.5V tolerant.


PIC18F47J53

PORTA is a bidirectional I/O port.

RA0/AN0/C1INA/ULPWU/RP0RA0AN0C1INAULPWURP0

2 27I/OIII

I/O

TTL/DIGAnalogAnalogAnalogST/DIG

Digital I/O.Analog Input 0.Comparator 1 Input A.Ultra low-power wake-up input.Remappable Peripheral Pin 0 input/output.

RA1/AN1/C2INA/VBG/RP1RA1AN1C2INAVBGRP1

3 28I/OOIO

I/O

TTL/DIGAnalogAnalogAnalogST/DIG

Digital I/O.Analog Input 1.Comparator 2 Input A.Band Gap Reference Voltage (VBG) output.Remappable Peripheral Pin 1 input/output.

RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF

RA2AN2C2INBC1INDC3INBVREF-CVREF

4 1

I/OIIIIOI

TTL/DIGAnalogAnalogAnalogAnalogAnalogAnalog

Digital I/O.Analog Input 2.Comparator 2 Input B.Comparator 1 Input D.Comparator 3 Input B.A/D reference voltage (low) input.Comparator reference voltage output.

RA3/AN3/C1INB/VREF+RA3AN3C1INBVREF+

5 2I/OIII

TTL/DIGAnalogAnalogAnalog

Digital I/O.Analog Input 3.Comparator 1 Input B.A/D reference voltage (high) input.

RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2

RA5AN4C1INCSS1HLVDINRCVRP2

7 4

I/OIIIII

I/O

TTL/DIGAnalogAnalog

TTLAnalogAnalogST/DIG

Digital I/O.Analog Input 4.Comparator 1 Input C.SPI slave select input.High/Low-Voltage Detect input.External USB transceiver RCV input.Remappable Peripheral Pin 2 input/output.

RA6(1)RA7(1)

See the OSC2/CLKO/RA6 pin.See the OSC1/CLKI/RA7 pin.

TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin NumberPin


28-SPDIP/SSOP/SOIC

28-QFN




PIC18F47J53

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/AN12/C3IND/INT0/RP3RB0AN12C3INDINT0RP3

21 18I/OIII

I/O

TTL/DIGAnalogAnalog

STST/DIG

Digital I/O.Analog Input 12.Comparator 3 Input D.External Interrupt 0.Remappable Peripheral Pin 3 input/output.

RB1/AN10/C3INC/RTCC/RP4RB1AN10C3INCRTCCRP4

22 19I/OIIO

I/O

TTL/DIGAnalogAnalog

DIGST/DIG

Digital I/O.Analog Input 10.Comparator 3 input.Asynchronous serial transmit data output.Remappable Peripheral Pin 4 input/output.

RB2/AN8/C2INC/CTED1/VMO/REFO/RP5

RB2AN8C2INCCTED1VMOREFORP5

23 20

I/OIIIOO

I/O

TTL/DIGAnalogAnalog

STDIGDIG

ST/DIG

Digital I/O.Analog Input 8.Comparator 2 Input C.CTMU Edge 1 input.External USB Transceiver D- data output.Reference output clock.Remappable Peripheral Pin 5 input/output.

RB3/AN9/C3INA/CTED2/VPO/RP6

RB3AN9C3INACTED2VPORP6

24 21

I/OIIIOI

TTL/DIGAnalogAnalog

STDIG

ST/DIG

Digital I/O.Analog Input 9.Comparator 3 Input A.CTMU edge 2 Input.External USB Transceiver D+ data output.Remappable Peripheral Pin 6 input/output.


Pin Name

Pin NumberPin


28-SPDIP/SSOP/SOIC

28-QFN




PIC18F47J53

PORTB (continued)

RB4/CCP4/KBI0/SCK1/SCL1/RP7

RB4CCP4KBI0SCK1SCL1RP7

25(2) 22(2)

I/OI/OI

I/OI/OI/O

TTL/DIGST/DIG

TTLST/DIG

I2CST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.Synchronous serial clock input/output.I2C clock input/output.Remappable Peripheral Pin 7 input/output.

RB5/CCP5/KBI1/SDI1/SDA1/RP8

RB5CCP5KBI1SDI1SDA1RP8

26(2) 23(2)

I/OI/OII

I/OI/O

TTL/DIGST/DIG

TTLSTI2C

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.SPI data input.I2C data input/output.Remappable Peripheral Pin 8 input/output.

RB6/CCP6/KBI2/PGC/RP9RB6CCP6KBI2PGCRP9

27(2) 24(2) I/OI/OII

I/O

TTL/DIGST/DIG

TTLST

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.ICSP™ clock input.Remappable Peripheral Pin 9 input/output.

RB7/CCP7/KBI3/PGD/RP10RB7CCP7KBI3PGD

RP10

28(2) 25(2) I/OI/OI

I/O

I/O

TTL/DIGST/DIG

TTLST/DIG

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming data pin.Remappable Peripheral Pin 10 input/output.


Pin Name

Pin NumberPin


28-SPDIP/SSOP/SOIC

28-QFN




PIC18F47J53

PORTC is a bidirectional I/O port.

RC0/T1OSO/T1CKI/RP11RC0T1OSOT1CKIRP11

11 8I/OOI

I/O

ST/DIGAnalog

STST/DIG

Digital I/O.Timer1 oscillator output.Timer1 external digital clock input.Remappable Peripheral Pin 11 input/output.

RC1/CCP8/T1OSI/UOE/RP12RC1CCP8T1OSIUOERP12

12 9I/OI/OIO

I/O

ST/DIGST/DIGAnalog

DIGST/DIG

Digital I/O.Capture/Compare/PWM input/output.Timer1 oscillator input.External USB transceiver NOE output.Remappable Peripheral Pin 12 input/output.

RC2/AN11/C2IND/CTPLS/RP13

RC2AN11C2INDCTPLSRP13

13 10

I/OIIO

I/O

ST/DIGAnalogAnalog

DIGST/DIG

Digital I/O.Analog Input 11.Comparator 2 Input D.CTMU pulse generator output.Remappable Peripheral Pin 13 input/output.

RC4/D-/VMRC4D-VM

15 12I

I/OI

ST—ST

Digital Input.USB bus minus line input/output.External USB transceiver FM input.

RC5/D+/VPRC5D+VP

16 13I

I/OI

ST—ST

Digital Input.USB bus plus line input/output.External USB transceiver VP input.

RC6/CCP9/TX1/CK1/RP17RC6CCP9TX1CK1

RP17

17(2) 14(2) I/OI/OO

I/O

I/O

ST/DIGST/DIG

DIGST/DIG

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.EUSART1 asynchronous transmit.EUSART1 synchronous clock (see related RX1/DT1).Remappable Peripheral Pin 17 input/output.

RC7/CCP10/RX1/DT1/SDO1/RP18

RC7CCP10RX1DT1SDO1RP18

18(2) 15(2)

I/OI/OI

I/OO

I/O

ST/DIGST/DIG

STST/DIG

DIGST/DIG

Digital I/O.Asynchronous serial receive data input.Capture/Compare/PWM input/output.Synchronous serial data output/input.SPI data output.Remappable Peripheral Pin 18 input/output.


Pin Name

Pin NumberPin


28-SPDIP/SSOP/SOIC

28-QFN




PIC18F47J53

VSS1 8 5 P — Ground reference for logic and I/O pins.VSS2 19 16 — —VDD 20 17 P — Positive supply for peripheral digital logic and I/O

pins.VDDCORE/VCAP

VDDCORE

VCAP

6 3 —

P

P

—

—

—

Core logic power or external filter capacitor connection.

Positive supply for microcontroller core logic (regulator disabled).External filter capacitor connection (regulator enabled).

VUSB 14 11 P — USB voltage input pin.


Pin Name

Pin NumberPin


28-SPDIP/SSOP/SOIC

28-QFN




PIC18F47J53

TABLE 1-4: PIC18F4XJ53 PINOUT I/O DESCRIPTIONS

Pin NamePin Number

PinType

BufferType Description44-

QFN44-

TQFP

MCLR 18(3) 18 I ST Master Clear (Reset) input; this is an active-low Reset to the device.

OSC1/CLKI/RA7OSC1

CLKI

RA7(1)

32 30I

I

I/O

ST

CMOS

TTL/DIG

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. Main oscillator input connection.External clock source input; always associated with pin function OSC1 (see related OSC1/CLKI pins).Digital I/O.

OSC2/CLKO/RA6OSC2

CLKO

RA6(1)

33 31O

O

I/O

—

—

TTL/DIG

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal orresonator in Crystal Oscillator mode.Main oscillator feedback output connectionin RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Digital I/O.


Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).3: 5.5V tolerant.


PIC18F47J53

DS

PORTA is a bidirectional I/O port.

RA0/AN0/C1INA/ULPWU/PMA6/RP0

RA0AN0C1INAULPWUPMA6

RP0

19 19

I/OIII

I/O

I/O

TTL/DIGAnalogAnalogAnalogST/TTL/

DIGST/DIG

Digital I/O.Analog Input 0.Comparator 1 Input A.Ultra low-power wake-up input.Parallel Master Port digital I/O.

Remappable Peripheral Pin 0 input/output.

RA1/AN1/C2INA/VBG/PMA7/RP1RA1AN1C2INAVBGPMA7

RP1

20 20I/OOIO

I/O

I/O

TTL/DIGAnalogAnalogAnalogST/TTL/

DIGST/DIG

Digital I/O.Analog Input 1.Comparator 2 Input A.Band Gap Reference Voltage (VBG) output.Parallel Master Port digital I/O.


RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF

RA2AN2C2INBC1INDC3INBVREF-CVREF

21 21

I/OIIIIII

TTL/DIGAnalogAnalogAnalogAnalogAnalogAnalog

Digital I/O.Analog Input 2.Comparator 2 Input B.Comparator 1 Input D.Comparator 3 Input B.A/D reference voltage (low) input.Comparator reference voltage output.

RA3/AN3/C1INB/VREF+RA3AN3C1INBVREF+

22 22I/OIII

TTL/DIGAnalogAnalogAnalog

Digital I/O.Analog Input 3.Comparator 1 Input B.A/D reference voltage (high) input.

RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2

RA5AN4C1INCSS1HLVDINRCVRP2

24 24

I/OIIIII

I/O

TTL/DIGAnalogAnalog

TTLAnalog

TTLST/DIG

Digital I/O.Analog Input 4.SPI slave select input.Comparator 1 Input C.High/Low-Voltage Detect input.External USB transceiver RCV input.Remappable Peripheral Pin 2 input/output.

RA6(1)RA7(1)

See the OSC2/CLKO/RA6 pin.See the OSC1/CLKI/RA7 pin.


Pin NamePin Number

PinType


QFN44-

TQFP



30009964C-page 20 2009-2016 Microchip Technology Inc.

PIC18F47J53

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/AN12/C3IND/INT0/RP3RB0AN12C3INDINT0RP3

9 8I/OIII

I/O

TTL/DIGAnalogAnalog

STST/DIG

Digital I/O.Analog Input 12.Comparator 3 Input D.External Interrupt 0.Remappable Peripheral Pin 3 input/output.

RB1/AN10/C3INC/PMBE/RTCC/RP4

RB1AN10C3INCPMBE(2) RTCCRP4

10 9

I/OIIOO

I/O

TTL/DIGAnalogAnalog

DIGDIG

ST/DIG

Digital I/O.Analog Input 10.Comparator 3 Input C.Parallel Master Port byte enable.Asynchronous serial transmit data output.Remappable Peripheral Pin 4 input/output.

RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5

RB2AN8C2INCCTED1PMA3(2) VMOREFORP5

11 10

I/OIIIOOO

I/O

TTL/DIGAnalogAnalog

STDIGDIGDIG

ST/DIG

Digital I/O.Analog Input 8.Comparator 2 Input C.CTMU Edge 1 input.Parallel Master Port address.External USB Transceiver D- data output.Reference output clock.Remappable Peripheral Pin 5 input/output.

RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6

RB3AN9C3INACTED2PMA2(2) VPORP6

12 11

I/OIIIOO

I/O

TTL/DIGAnalogAnalog

STDIGDIG

ST/DIG

Digital I/O.Analog Input 9.Comparator 3 Input A.CTMU Edge 2 input.Parallel Master Port address.External USB Transceiver D+ data output.Remappable Peripheral Pin 6 input/output.


Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

PORTB (continued)

RB4/CCP4/PMA1/KBI0/SCK1/SCL1/RP7

RB4CCP4(2) PMA1(2)

KBI0SCK1SCL1RP7

14(3) 14(3)

I/OI/OI/O

II/OI/OI/O

TTL/DIGST/DIGST/TTL/

DIGTTL

ST/DIGI2C

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Parallel Master Port address.

Interrupt-on-change pin.Synchronous serial clock input/output.I2C clock input/output.Remappable Peripheral Pin 7 input/output.

RB5/CCP5/PMA0/KBI1/SDI1/SDA1/RP8

RB5CCP5PMA0(2)

KBI1SDI1SDA1RP8

15(3) 15(3)

I/OI/OI/O

II

I/OI/O

TTL/DIGST/DIGST/TTL/

DIGTTLSTI2C

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Parallel Master Port address.

Interrupt-on-change pin.SPI data input.I2C data input/output.Remappable Peripheral Pin 8 input/output.

RB6/CCP6/KBI2/PGC/RP9RB6CCP6KBI2PGCRP9

16(3) 16(3)I/OI/OII

I/O

TTL/DIGST/DIG

TTLST

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.ICSP™ clock input.Remappable Peripheral Pin 9 input/output.

RB7/CCP7/KBI3/PGD/RP10RB7CCP7KBI3PGD

RP10

17(3) 17(3)I/OI/OI

I/O

I/O

TTL/DIGST/DIG

TTLST/DIG

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming data pin.Remappable Peripheral Pin 10 input/output.


Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

PORTC is a bidirectional I/O port.

RC0/T1OSO/T1CKI/RP11RC0T1OSOT1CKIRP11

34 32I/OOI

I/O

STDIGAnalog

STST/DIG

Digital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input.Remappable Peripheral Pin 11 input/output.

RC1/CCP8/T1OSI/UOE/RP12RC1CCP8T1OSIUOERP12

35 35I/OI/OIO

I/O

ST/DIGST/DIGAnalog

DIGST/DIG

Digital I/O.Capture/Compare/PWM input/output.Timer1 oscillator input.External USB Transceiver NOE output.Remappable Peripheral Pin 12 input/output.

RC2/AN11/C2IND/CTPLS/RP13RC2AN11C2INDCTPLSRP13

36 36I/OIIO

I/O

ST/DIGAnalogAnalog

DIGST/DIG

Digital I/O.Analog Input 11.Comparator 2 Input D.CTMU pulse generator output.Remappable Peripheral Pin 13 input/output.

RC4/D-/VMRC4D-VM

42 42I

I/OI

ST—ST

Digital Input.USB bus minus line input/output.External USB Transceiver FM input.

RC5/D+/VPRC5D+VP

43 43I

I/OI

ST—ST

Digital Input.USB bus plus line input/output.External USB Transceiver VP input.


Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

RC6/CCP9/PMA5/TX1/CK1/RP17RC6CCP9PMA5TX1

CK1

RP17

44(3) 44(3)I/OI/OI/OO

I/O

I/O

ST/DIGST/DIG

DIGST/TTL/

DIGST/DIG

ST/DIG

Digital I/O.Capture/Compare/PWM input/output.Parallel Master Port address.EUSART1 asynchronous transmit.

EUSART1 synchronous clock (see related RX1/DT1).Remappable Peripheral Pin 17 input/output.

RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18

RC7CCP10PMA4RX1

DT1SDO1RP18

1(3) 1(3)

I/OI/OI/O

I

I/OO

I/O

ST/DIGST/DIGST/TTL/

DIG

ST

ST/DIGDIG

ST/DIG

EUSART1 asynchronous receive.Capture/Compare/PWM input/output.Parallel Master Port address.EUSART1 synchronous data (see related TX1/CK1).Synchronous serial data output/input.SPI data output.Remappable Peripheral Pin 18 input/output.


Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

PORTD is a bidirectional I/O port.

RD0/PMD0/SCL2RD0PMD0

SCL2

38(3) 38(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGI2C

Digital I/O.Parallel Master Port data.

I2C data input/output.

RD1/PMD1/SDA2RD1PMD1

SDA2

39(3) 39(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGI2C


I2C data input/output.

RD2/PMD2/RP19RD2PMD2

RP19

40(3) 40(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




RP20

41(3) 41(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




RP21

2(3) 2(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




RP22

3(3) 3(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




RP23

4(3) 4(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




RP24

5(3) 5(3)I/OI/O

I/O

ST/DIGST/TTL/

DIGST/DIG




Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

PORTE is a bidirectional I/O port.

RE0/AN5/PMRDRE0AN5PMRD

25 25I/OI

I/O

ST/DIGAnalogST/TTL/

DIG

Digital I/O.Analog Input 5.Parallel Master Port input/output.

RE1/AN6/PMWRRE1AN6PMWR

26 26I/OI

I/O

ST/DIGAnalogST/TTL/

DIG

Digital I/O.Analog Input 6.Parallel Master Port write strobe.

RE2/AN7/PMCSRE2AN7PMCS

27 27I/OIO

ST/DIGAnalog

DIG

Digital I/O.Analog Input 7.Parallel Master Port byte enable.

VSS1 6 6 P — Ground reference for logic and I/O pins.VSS2 31 29 — —AVSS1 30 — P — Ground reference for analog modules.VDD1 8 7 P — Positive supply for peripheral digital logic and

I/O pins.VDD2 29 28 P —VDDCORE/VCAP

VDDCORE

VCAP

23 23

P

P

—

—

Core logic power or external filter capacitor connection.

Positive supply for microcontroller core logic (regulator disabled).External filter capacitor connection (regulatorenabled).

AVDD1 7 — P — Positive supply for analog modules.AVDD2 28 — — — Positive supply for analog modules.VUSB 37 37 P — USB voltage input pin.


Pin NamePin Number

PinType


QFN44-

TQFP




PIC18F47J53

2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS

2.1 Basic Connection RequirementsGetting started with the PIC18F47J53 family of 8-bitmicrocontrollers requires attention to a minimal set ofdevice pin connections before proceeding withdevelopment.

The following pins must always be connected:

• All VDD and VSS pins (see Section 2.2 “Power Supply Pins”)

• All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”)

• MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”)

• VCAP/VDDCORE pins (see Section 2.4 “Voltage Regulator Pins (VCAP/VDDCORE)”)

These pins must also be connected if they are beingused in the end application:

• PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

• VREF+/VREF- pins are used when external voltage reference for analog modules is implemented

The minimum mandatory connections are shown inFigure 2-1.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS

Note: On 44-pin QFN packages, the AVDD andAVSS pins must always be connected,regardless of whether any of the analogmodules are being used. On other pack-age types, the AVDD and AVSS pins areinternally connected to the VDD/VSS pins.

PIC18FXXJXX

VD

D

VS

S

VDD

VSS

VSS

VDD

AVD

D

AVS

S

VD

D

VS

S

C1

R1

VDD

MCLRVCAP/VDDCORE

R2

C7

C2(2)

C3(2)

C4(2)C5(2)

C6(2)

Key (all values are recommendations):C1 through C6: 0.1 F, 20V ceramicC7: 10 F, 6.3V or greater, tantalum or ceramicR1: 10 kΩR2: 100Ω to 470ΩNote 1: See Section 2.4 “Voltage Regulator Pins

(VCAP/VDDCORE)” for explanation of VCAP/VDDCORE connections.

2: The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.

(1)


PIC18F47J53

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORSThe use of decoupling capacitors on every pair ofpower supply pins, such as VDD, VSS, AVDD andAVSS, is required.

Consider the following criteria when using decouplingcapacitors:

• Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capaci-tor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F).

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.

2.2.2 TANK CAPACITORSOn boards with power traces running longer thansix inches in length, it is suggested to use a tank capac-itor for integrated circuits, including microcontrollers, tosupply a local power source. The value of the tankcapacitor should be determined based on the traceresistance that connects the power supply source tothe device, and the maximum current drawn by thedevice in the application. In other words, select the tankcapacitor so that it meets the acceptable voltage sag atthe device. Typical values range from 4.7 F to 47 F.

2.3 Master Clear (MCLR) PinThe MCLR pin provides two specific devicefunctions: Device Reset, and Device Programmingand Debugging. If programming and debugging arenot required in the end application, a directconnection to VDD may be all that is required. Theaddition of other components, to help increase theapplication’s resistance to spurious Resets fromvoltage sags, may be beneficial. A typicalconfiguration is shown in Figure 2-1. Other circuitdesigns may be implemented, depending on theapplication’s requirements.

During programming and debugging, the resistanceand capacitance that can be added to the pin mustbe considered. Device programmers and debuggersdrive the MCLR pin. Consequently, specific voltagelevels (VIH and VIL) and fast signal transitions mustnot be adversely affected. Therefore, specific valuesof R1 and C1 will need to be adjusted based on theapplication and PCB requirements. For example, it isrecommended that the capacitor, C1, be isolatedfrom the MCLR pin during programming anddebugging operations by using a jumper (Figure 2-2).The jumper is replaced for normal run-timeoperations.

Any components associated with the MCLR pinshould be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

Note 1: R1 10 k is recommended. A suggestedstarting value is 10 k. Ensure that theMCLR pin VIH and VIL specifications are met.

2: R2 470 will limit any current flowing intoMCLR from the external capacitor, C, in theevent of MCLR pin breakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.

C1

R2R1

VDD

MCLR

PIC18FXXJXXJP


PIC18F47J53

2.4 Voltage Regulator Pins

(VCAP/VDDCORE)On “F” devices, a low-ESR (< 5Ω) capacitor is requiredon the VCAP/VDDCORE pin to stabilize the voltageregulator output voltage. The VCAP/VDDCORE pin mustnot be connected to VDD and must use a capacitor of 10F connected to ground. The type can be ceramic ortantalum. A suitable example is the MurataGRM21BF50J106ZE01 (10 F, 6.3V) or equivalent.Designers may use Figure 2-3 to evaluate ESRequivalence of candidate devices.

It is recommended that the trace length not exceed0.25 inch (6 mm). Refer to Section 31.0 “ElectricalCharacteristics” for additional information.On “LF” devices, the VCAP/VDDCORE pin must be tied toa voltage supply at the VDDCORE level. Refer toSection 31.0 “Electrical Characteristics” forinformation on VDD and VDDCORE.

Note that the “LF” versions of these devices areprovided with the voltage regulator permanentlydisabled; they must always be provided with a supplyvoltage on the VDDCORE pin.

FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP

2.5 ICSP PinsThe PGC and PGD pins are used for In-Circuit SerialProgramming™ (ICSP™) and debugging purposes. Itis recommended to keep the trace length between theICSP connector and the ICSP pins on the device asshort as possible. If the ICSP connector is expected toexperience an ESD event, a series resistor is recom-mended, with the value in the range of a few tens ofohms, not to exceed 100Ω.

Pull-up resistors, series diodes, and capacitors on thePGC and PGD pins are not recommended as they willinterfere with the programmer/debugger communica-tions to the device. If such discrete components are anapplication requirement, they should be removed fromthe circuit during programming and debugging. Alter-natively, refer to the AC/DC characteristics and timingrequirements information in the respective deviceFlash programming specification for information oncapacitive loading limits, and pin input voltage high(VIH) and input low (VIL) requirements.

For device emulation, ensure that the “CommunicationChannel Select” (i.e., PGCx/PGDx pins) programmedinto the device matches the physical connections forthe ICSP to the Microchip debugger/emulator tool.

For more information on available Microchipdevelopment tools connection requirements, refer toSection 30.0 “Development Support”.

10

1

0.1

0.01

0.0010.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR

()

Note: Data for Murata GRM21BF50J106ZE01 shown.Measurements at 25°C, 0V DC bias.


PIC18F47J53

2.6 External Oscillator PinsMany microcontrollers have options for at least twooscillators: a high-frequency primary oscillator and alow-frequency secondary oscillator (refer toSection 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the sameside of the board as the device. Place the oscillatorcircuit close to the respective oscillator pins with nomore than 0.5 inch (12 mm) between the circuitcomponents and the pins. The load capacitors shouldbe placed next to the oscillator itself, on the same sideof the board.

Use a grounded copper pour around the oscillator cir-cuit to isolate it from surrounding circuits. Thegrounded copper pour should be routed directly to theMCU ground. Do not run any signal traces or powertraces inside the ground pour. Also, if using a two-sidedboard, avoid any traces on the other side of the boardwhere the crystal is placed.

Layout suggestions are shown in Figure 2-4. In-linepackages may be handled with a single-sided layoutthat completely encompasses the oscillator pins. Withfine-pitch packages, it is not always possible to com-pletely surround the pins and components. A suitablesolution is to tie the broken guard sections to a mirroredground layer. In all cases, the guard trace(s) must bereturned to ground.

In planning the application’s routing and I/O assign-ments, ensure that adjacent port pins and other signalsin close proximity to the oscillator are benign (i.e., freeof high frequencies, short rise and fall times, and othersimilar noise).

For additional information and design guidance onoscillator circuits, please refer to these MicrochipApplication Notes, available at the corporate website(www.microchip.com):

• AN826, Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices

• AN849, Basic PICmicro® Oscillator Design• AN943, Practical PICmicro® Oscillator Analysis

and Design• AN949, Making Your Oscillator Work

2.7 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic low state. Alternatively, connect a 1 kΩto 10 kΩ resistor to VSS on unused pins and drive theoutput to logic low.

FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

GND

`

`

`

OSC1

OSC2

T1OSO

T1OS I

Copper Pour Primary OscillatorCrystal

Timer1 OscillatorCrystal

DEVICE PINS

PrimaryOscillator

C1

C2

T1 Oscillator: C1 T1 Oscillator: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom LayerCopper Pour

OscillatorCrystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)


PIC18F47J53

3.0 OSCILLATOR CONFIGURATIONS

3.1 OverviewDevices in the PIC18F47J53 family incorporate adifferent oscillator and microcontroller clock systemthan general purpose PIC18F devices. Besides theUSB module, with its unique requirements for a stableclock source, make it is necessary to provide aseparate clock source that is compliant with both USBlow-speed and full-speed specifications.

The PIC18F47J53 family has additional prescalers andpostscalers, which have been added to accommodatea wide range of oscillator frequencies. Figure 3-1provides an overview of the oscillator structure.

Other oscillator features used in PIC18 enhancedmicrocontrollers, such as the internal oscillator blockand clock switching, remain the same. They arediscussed later in this chapter.

3.1.1 OSCILLATOR CONTROLThe operation of the oscillator in PIC18F47J53 familydevices is controlled through three Configuration regis-ters and two control registers. Configuration registers,CONFIG1L, CONFIG1H and CONFIG2L, select theoscillator mode, PLL prescaler and CPU divideroptions. As Configuration bits, these are set when thedevice is programmed and left in that configuration untilthe device is reprogrammed.

The OSCCON register (Register 3-2) selects the ActiveClock mode; it is primarily used in controlling clockswitching in power-managed modes. Its use isdiscussed in Section 3.5.1 “Oscillator ControlRegister”.The OSCTUNE register (Register 3-1) is used to trim theINTOSC frequency source and select the low-frequencyclock source that drives several special features. TheOSCTUNE register is also used to activate or disable thePhase Locked Loop (PLL). Its use is described inSection 3.2.5.1 “OSCTUNE Register”.

3.2 Oscillator TypesPIC18F47J53 family devices can be operated in eightdistinct oscillator modes. Users can program theFOSC Configuration bits to select one of themodes listed in Table 3-1. For oscillator modes whichproduce a clock output (CLKO) on pin RA6, the outputfrequency will be one fourth of the peripheral clockfrequency. The clock output stops when in Sleep mode,but will continue during Idle mode (see Figure 3-1).

3.2.1 OSCILLATOR MODES AND USB OPERATION

Because of the unique requirements of the USB module,a different approach to clock operation is necessary. Inorder to use the USB module, a fixed 6 MHz or 48 MHzclock must be internally provided to the USB module foroperation in either Low-Speed or Full-Speed mode,respectively. The microcontroller core need not beclocked at the same frequency as the USB module.

A network of MUXes, clock dividers and a fixed 96 MHzoutput PLL have been provided, which can be used toderive various microcontroller core and USB modulefrequencies. Figure 3-1 helps in understanding theoscillator structure of the PIC18F47J53 family ofdevices.

TABLE 3-1: OSCILLATOR MODES Mode Description

ECPLL External Clock Input mode, the PLL can be enabled or disabled in software, CLKO on RA6, apply external clock signal to RA7.

EC External Clock Input mode, the PLL is always disabled, CLKO on RA6, apply external clock signal to RA7.

HSPLL High-Speed Crystal/Resonator mode, PLL can be enabled or disabled in software, crystal/resonator connected between RA6 and RA7.

HS High-Speed Crystal/Resonator mode, PLL always disabled, crystal/resonator connected between RA6 and RA7.

INTOSCPLLO Internal Oscillator mode, PLL can be enabled or disabled in software, CLKO on RA6, port function on RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock.

INTOSCPLL Internal Oscillator mode, PLL can be enabled or disabled in software, port function on RA6 and RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock.

INTOSCO Internal Oscillator mode, PLL is always disabled, CLKO on RA6, port function on RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source.

INTOSC Internal Oscillator mode, PLL is always disabled, port function on RA6 and RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source.


PIC18F47J53

FIGURE 3-1: PIC18F47J53 FAMILY CLOCK DIAGRAM

OSC1

OSC2

Primary Oscillator

CPU

Peripherals

IDLE

INTO

SC P

osts

cale

r

8 MHz

4 MHz

2 MHz

1 MHz500 kHz

125 kHz

250 kHz

11111010110001101000100031 kHz

INTRC31 kHz

InternalOscillator

Block

8 MHz8 MHz

01

OSCTUNE

PLLDIV

CPU

Div

ider

1 2 3

6

USB Module

4 MHz

WDT, PWRT, FSCMand Two-Speed Start-up

OSCCON

PLLEN

1

0

FOSC2

1

0

PLL

Pre

scal

er

96 MHzPLL(1) 2

1

0

FSEN

8 1

0 4

LS48MHZ00011011

CPDIV

(Note 2)

00

FOSC

Oth

er

0001

OSCCON

11 4

RA6

CLKOEnabled Modes

Timer1 Clock(3)

PostscaledInternal Clock

T1OSI

T1OSO

Secondary Oscillator

ClockNeeds 48 MHz for FSNeeds 6 MHz for LS

Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to trc to lock. During this time, the device continues to be clocked at the PLL bypassed frequency.

2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked at 6 MHz.

3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the reference clock of Section 3.6 “Reference Clock Output”) and PLL.

4: The USB module cannot be used to communicate unless the primary clock source is selected.

12 10 6 5 4 3 2 1

000001010011100101110111

48 MHz

Primary ClockSource(4)

CFGPLLEN


PIC18F47J53

3.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORSIn HS and HSPLL Oscillator modes, a crystal orceramic resonator is connected to the OSC1 andOSC2 pins to establish oscillation. Figure 3-2 displaysthe pin connections.

The oscillator design requires the use of a parallelresonant crystal.

FIGURE 3-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION)

TABLE 3-2: CAPACITOR SELECTION FOR CERAMIC RESONATORS

TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR

An internal postscaler allows users to select a clockfrequency other than that of the crystal or resonator.Frequency division is determined by the CPDIVConfiguration bits. Users may select a clock frequencyof the oscillator frequency, or 1/2, 1/3 or 1/6 of thefrequency.

Note: Use of a series resonant crystal may givea frequency out of the crystalmanufacturer’s specifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

HS 8.0 MHz16.0 MHz

27 pF22 pF

27 pF22 pF

Capacitor values are for design guidance only. These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following Table 3-3 for additionalinformation.

Resonators Used:

4.0 MHz8.0 MHz

16.0 MHz

Note 1: See Table 3-2 and Table 3-3 for initial values of C1 and C2.

2: RS may be required to avoid overdriving crystals with low drive level specifications.

C1(1)

C2(1)

XTAL

OSC2

OSC1

Sleep

To

Logic

RS(2)

Internal

PIC18F47J53

Osc Type Crystal Freq

Typical Capacitor Values Tested:

C1 C2

HS 4 MHz 27 pF 27 pF8 MHz 22 pF 22 pF

16 MHz 18 pF 18 pFCapacitor values are for design guidance only.These capacitors were tested with the crystals listedbelow for basic start-up and operation. These valuesare not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following this table for additionalinformation.

Crystals Used:

4 MHz8 MHz16 MHz

Note 1: Higher capacitance not only increasesthe stability of oscillator, but alsoincreases the start-up time.

2: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

3: Rs may be required to avoid overdrivingcrystals with low drive level specification.

4: Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.


PIC18F47J53

3.2.3 EXTERNAL CLOCK INPUTThe EC and ECPLL Oscillator modes require anexternal clock source to be connected to the OSC1 pin.There is no oscillator start-up time required after aPower-on Reset (POR) or after an exit from Sleepmode.

In the EC Oscillator mode, the oscillator frequencydivided by 4, is available on the OSC2 pin. In theECPLL Oscillator mode, the PLL output, divided by 4,is available on the OSC2 pin. This signal may be usedfor test purposes or to synchronize other logic.Figure 3-3 displays the pin connections for the ECOscillator mode.

FIGURE 3-3: EXTERNAL CLOCK INPUT OPERATION (EC AND ECPLL CONFIGURATION)

3.2.4 PLL FREQUENCY MULTIPLIERPIC18F47J53 family devices include a PLL circuit. Thisis provided specifically for USB applications with lowerspeed oscillators and can also be used as amicrocontroller clock source.

The PLL can be enabled in HSPLL, ECPLL,INTOSCPLL and INTOSCPLLO Oscillator modes bysetting the PLLEN bit (OSCTUNE). It is designedto produce a fixed 96 MHz reference clock from afixed 4 MHz input. The output can then be divided andused for both the USB and the microcontroller coreclock. Because the PLL has a fixed frequency inputand output, there are eight prescaling options tomatch the oscillator input frequency to the PLL. Thisprescaler allows the PLL to be used with crystals, res-onators and external clocks, which are integer multiplefrequencies of 4 MHz. For example, a 12 MHz crystalcould be used in a prescaler Divide-by-Three mode todrive the PLL.

There is also a CPU divider, which can be used to derivethe microcontroller clock from the PLL. This allows theUSB peripheral and microcontroller to use the sameoscillator input and still operate at different clock speeds.The CPU divider can reduce the incoming frequency bya factor of 1, 2, 3 or 6.

3.2.5 INTERNAL OSCILLATOR BLOCKThe PIC18F47J53 family devices include an internaloscillator block which generates two different clocksignals; either can be used as the microcontroller’sclock source. The internal oscillator may eliminate theneed for external oscillator circuits on the OSC1 and/orOSC2 pins.

The main output (INTOSC) is an 8 MHz clock sourcewhich can be used to directly drive the device clock. Italso drives the INTOSC postscaler which can provide arange of clock frequencies from 31 kHz to 8 MHz.Additionally, the INTOSC may be used in conjunctionwith the PLL to generate clock frequencies up to48 MHz.

The other clock source is the internal RC oscillator(INTRC) which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource. It is also enabled automatically when any of thefollowing are enabled:

• Power-up Timer• Fail-Safe Clock Monitor• Watchdog Timer• Two-Speed Start-up

These features are discussed in larger detail inSection 28.0 “Special Features of the CPU”.The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (page 39).

OSC1/CLKI

OSC2/CLKOFOSC/4

Clock fromExt. System PIC18F47J53


PIC18F47J53

3.2.5.1 OSCTUNE RegisterThe internal oscillator’s output has been calibrated atthe factory but can be adjusted in the user’s applica-tion. This is done by writing to the OSCTUNE register(Register 3-1). The tuning sensitivity is constantthroughout the tuning range.

When the OSCTUNE register is modified, the INTOSCfrequency will begin shifting to the new frequency. TheINTOSC clock will stabilize typically within 1 s. Codeexecution continues during this shift. There is noindication that the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.The INTSRC bit allows users to select which internaloscillator provides the clock source when the 31 kHzfrequency option is selected. This is covered in largerdetail in Section 3.5.1 “Oscillator Control Register”. The PLLEN bit, contained in the OSCTUNE register,can be used to enable or disable the internal 96 MHzPLL when running in one of the PLL type oscillatormodes (e.g., INTOSCPLL). Oscillator modes that donot contain “PLL” in their name cannot be used withthe PLL. In these modes, the PLL is always disabledregardless of the setting of the PLLEN bit. When configured for one of the PLL enabled modes, set-ting the PLLEN bit does not immediately switch thedevice clock to the PLL output. The PLL requires up toelectrical parameter, trc, to start-up and lock, duringwhich time, the device continues to be clocked. Once thePLL output is ready, the microcontroller core willautomatically switch to the PLL derived frequency.

3.2.5.2 Internal Oscillator Output Frequency and Drift

The internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.However, this frequency may drift as VDD or tempera-ture changes, which can affect the controller operationin a variety of ways.

The low-frequency INTRC oscillator operates inde-pendently of the INTOSC source. Any changes inINTOSC across voltage and temperature are not nec-essarily reflected by changes in INTRC and vice versa.

3.2.5.3 Compensating for INTOSC DriftIt is possible to adjust the INTOSC frequency bymodifying the value in the OSCTUNE register. This hasno effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. When using the EUSART, for example, anadjustment may be required when it begins to generateframing errors or receives data with errors while inAsynchronous mode. Framing errors indicate that thedevice clock frequency is too high; to adjust for this,decrement the value in OSCTUNE to reduce the clockfrequency. On the other hand, errors

Documents

28/44-Pin, High-Performance USB MCUs with XLP Technology...Errata An errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist