3 Architecture Consideration

8/7/2019 3 Architecture Consideration

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Architectural Considerations

A Review of Some Architectural Concepts


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Organization of the Computing

System

Processor

Input/

Output Memory

System

Interconnection

The Computing System Top Level Structure


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Organization of the Computing System

Processor

Controls the operation of the computing system andperforms its data processing functions.

Memory Sub-System Stores data and programs.

Input/Output Sub-System

Moves information between the computing systemand its external environment.

System Interconnection

Some mechanism that provides for communicationamong the processor, the memory and the I/O sub-systems.


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The Processor

Control

Unit

Registers

Arithmetic

and

Logic Unit

InternalInterconnection

The Processor


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The Processor

Control Unit

Controls the operation of the processor.

Arithmetic and Logic Unit (ALU)

Performs the systems data processing functions

Registers

Internal storage for the processor

Internal Interconnection

A mechanism that provides communication among

the control unit, ALU, and registers.


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The Registers

A number of registers exit within the processor and are

intended for the temporary storage of information needed

frequently and urgently.

Can be classified into:

General Purpose Registers.

Can be used as the programmer requires.

Special Purpose Registers.

Can only be used for specific functions.

Stack Pointer.

Accumulator.

Pointers.


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The Operation of the Processor

Processors mainly operate based on a 3-

state cycle:

Fetch. Bring the next instruction from memory into theprocessor.

Decode.

Determine what is required. Execute.

Do it. 0124828147 :)


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Details of the 3-State Cycle

A special register in the processor known as the program counter(PC) always holds the address of the next instruction forexecution.

During the fetch cycle, the contents of the PC are copied to anotherspecial register Memory Address Register (MAR) which isconnected to the address bus output of the processor.

When the instruction is ready, it is read in the form of a group ofbits known as an opcode using the processors data bus into yetanother special register the Instruction Register (IR).

The contents of the IR are decoded to tell the processor what

operation to perform and what the operands for the operation are. The processor uses its internal register and the ALU to perform the

required operation.


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The ALU

The ALU is made up of several functional blocks that perform

different arithmetic and logical operations on the operands.

The ALU operations may generate certain conditions that are saved

in the flags register.

Some typical flags are: sign, carry, zero and overflow.

Overflow occurs when an arithmetic operation on signed

numbers produces a wrong result because the result has

more bits than can be held by the registers.

The flags register together with the AC are collectively known as the

Program Status Word PSW.


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Memory Sub-System Memory in a computing system is used for the storage of programs

and data.

Could be temporary or permanent.

How permanent is permanent?

Memory is measured by two numbers:

The address space.

How many different locations there are.

The access width.

Maximum number of bits that can be accessed at once.

Both of these values may have different meanings depending on

whether one is looking from the point of view of the processor or

the memory.


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Memory Sub-System

Data and programs cannot co-exist.

Most computing systems treat memory as one

continuous address space.

It is up to the programmer to keep the program(s)

and data separate.

However, some systems have physicallyseparate program and data storage with

separate address spaces.


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Memory Many different types that vary in

Access speed.

Volatility.

Erasability.

Cost As a rule of thumb, the more useful the memory technology is,

the more expensive it would be.

Types:

RAM Random Access Memory

Dynamic DRAM Static SRAM

ROM Read Only Memory

Erasable EPROM

Electrically Erasable EEPROM


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Memory RAM

The proper name is Read/Write Memory.

But no one will understand what you are talking about.

Allows both read and write operations.

Both operations are performed electrically.

Volatile.

Used for temporary storage only.

If the power is disconnected, the contents become invalid. Can be made non-volatile by using a battery for backup power.


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Memory RAM DRAM

Uses only one transistor per bit.

Data is stored as charge

in capacitors. Charge on a capacitordecays naturally.

Therefore, DRAM needs refreshing even

when powered to maintain the data. Refreshing is done by reading and re-writing eachword every few milliseconds.


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Memory RAM SRAM

Consists of internal flip flop like structures

that store the binary information.

No charges to leak. No refreshing is needed.

More complex construction.

Larger cell, Less dense.

More expensive. Faster.


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Memory ROM

Read but cannot write.

Non volatile.

Manufactured with the data wired into the

chip.

No room for mistakes.

Not very effective for end-users.


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Memory EPROM

Uses MOS transistors with insulating material that changes behavior

when exposed to ultraviolet light.

Programmed electrically and erased optically.

Erasing can be repeated a relatively large but limited number of

times (~100,000 times). Erasing time ~20 minutes.

Electrically read and written.

Before writing,ALL cells must be erased by exposure to

ultraviolet light.

Non volatile.

More expensive than PROM.


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Memory EEPROM

Uses the same floating-gate transistors, except that theinsulating material is much thinner.

Its operation can be inverted using voltage.

Can be written to any time without erasing the previous

contents. Only the bytes addressed are modified.

Write takes a relatively long time (~100Qsec/byte).

Can be erased only about 10,000 times.

Non volatile.

Updatable in place.

More expensive and less dense than EPROM.


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Memory The Stack

The stack is an area of memory identified by the

programmer for temporary storage of information.

The stack is a LIFO structure.

Last In First Out. The stack normally grows backwards into memory.

In other words, the programmer

defines the bottom of the stack

and the stack grows up intoreducing address range.


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Memory The Stack

Processors usually contain a special register known as the StackPointer (SP).

This pointer is used to constantly point to the top of the stack.

Information is saved on the stack using a push operation.

The information is copied to the location pointed to by the SP,then the SP is decremented.

Information is retrieved from the stack using a pop operation.

The SP is incremented, then the information is copied from

the location pointed to by the SP.

There must be a pop for every push.


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Memory Speed

The speed of memory is measured by two

numbers:

Access Time.

How long it takes from the time the address is

ready until the data becomes ready.

Cycle Time. How soon after the previous access can the

memory be accessed again.


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The I/O Sub-System

Interface between the processor, memory and one or moreperipherals.

Can be classified into:

Serial Single wire with the data being transferred sequentially.

Parallel

Multiple wires with the data being transferred concurrently.

Several possible implementation techniques: Programmed

Interrupt driven


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Programmed I/O

Processor has direct control over I/O

Sensing status

Read/write commands

Transferring data

CPU waits for I/O module to complete operation

Wastes CPU time

Two types:

I/O port-based.

Memory-mapped


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I/O port-based I/O

I/O ports are connections consisting of groups of parallelbits connecting into and out of the computing system.

Physically, the ports are made of either tri-statebuffers for input or latches for output.

Each port is identified by a unique port number.

The processor uses special instructions to accessthese ports.

It produces the port number on its address bus outputwhen it is attempting to access the port.

The hardware uses the port number to activate(enable) the proper port.


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Memory-mapped I/O

Some systems allow memory-mapped

I/O where the I/O devices are treated like

memory locations.

The processor would use memory access

instructions to access these devices.

I/O devices and memory locations cannot

have the same address. Therefore, we lose memory area when we use

memory-mapped I/O.


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Interrupt-driven I/O

Instead of having the processor waste time constantly checking on

the I/O devices, we can have the devices interrupt the processor

when they need attention.

An interrupt is defined as an event requiring immediate attention. Extremely important in real-time environments.

When the processor is interrupted, it branches to a special routine

known as an interrupt service routine (ISR).

The ISR is written to handle the specific event that occurred.

An ISR may interrogate an I/O device to determine the required

activity and perform it.


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Measuring the Speed of a Processor

The proper way to measure the speed of a processor is not by

counting Hz.

Whats the proper way?

One aspect of the speed of a processor is throughput. Which is

defined as the number of instructions executed per second. Another aspect is how well does the processors instruction set

support the expected usage of the processor.

The match between the processor and its bus and memory can

affect the apparent overall speed of the system.

The best method for comparing processor is to compare theirperformance on standardized applications known as

benchmarks.

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3 Architecture Consideration