3 ENGN3225 Power Engineering: Semiconductor Devicespeople.physics.anu.edu.au/~bdb112/engn3225/eng_3225... · 2002. 10. 6. · ENGN3225 Power Engineering: Devices Lectures 8/2002 Boyd

ENGN3225 Power Engineering: Devices Lectures 8/2002 Boyd Blackwell: Rev G

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3 ENGN3225 Power Engineering: Semiconductor Devices

3 ENGN3225 Power Engineering: Semiconductor Devices 1

Bibliography 2

3.1 Semiconductor Physics 3

3.1.1 Conductors, Semiconductors and Insulators 3

3.1.2 The charge carriers: free electrons and holes 3

3.1.3 Extrinsic (Doped) Semiconductors, Majority and Minority Carriers. 3

3.1.4 Recombination Sites and Rates 4

3.1.5 Mobility, Drift and Diffusion, Hall Effect 5

3.2 PN Junctions 7

3.2.1 Depletion layer width 8

3.2.2 Exponential Relation of I to V 9

3.2.3 Reverse Breakdown 9

3.3 Power Diodes 11

3.3.1 Voltage Standoff for Minority and Majority Carrier devices 12

3.3.2 Switching Transients 13

3.3.3 Other Diodes 13

3.3.4 Contacts 15

3.4 Bipolar Junction Transistor (BJT) 15

Saturation in the BJT 16

Second Breakdown 17

3.5 Silicon Controlled Rectifier(SCR) 18

3.5.1 Triacs, Gate Turn-Off Thyristors 19

Field Effect Devices 19

3.6.1 Switching Considerations 20

3.6.2 MOSFET, IGBT 21

3.7 Protection Devices 22

3.7.1 Snubber Circuits 22

3.7.2 Overvoltage Protection: Varistors, Spark Gaps, Crowbars 22

3.7.3 Overcurrent Protection: Fuses and Circuit Breakers 22

4 Switching Circuits 23

4.2 23


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4.3 DC-DC Convertors – Buck Convertor 23

Aims: Basic physics of power semiconductor devices to allow understanding different device

technologies and their relative merits, failure modes, and general drive requirements. Mohan Chapter 2 is

a brief functional overview to introduce devices and highlight characteristics without physical

explanation.

Reference:

Mohan chapters 19-25 will be covered at ~50% detail. These notes are rather terse and should be read in

conjunction with Mohan. (M:19-7 means eqn. 7, ch9, Mohan, M§19-1 means section 19-1) – full details

in Bibliography. Italics are for emphasis, bold indicates extra emphasis or a definition.

Units: Note that a hybrid “practical” unit system is used – cm/�m, coulomb and volts. (neither cgs nor

SI). Consequently I will try to calculate consistently as you probably will, by converting to MKS-SI,

calculating, then converting back. One trick in dealing with electron volt energy units is to convert

temperatures (kT) to eV (1eV=11,600K) , and then terms such as eqV/kT can be evaluated with q in units of

the electronic charge e.g. q=1.6e-19, V=0.6V, room temperature=0.0258eV

� e1.6e-19�0.6/(0.026�1.6e-19) = e0.6/0.025 = 2.6e10 (e.g. forward bias current ratio)

Concepts:

Semiconductors – electrons/holes, doping, majority/minority carriers, devices

Devices: Diode, (Schottky, Power, High Speed), BJT, SCR, (GTO, Triac), MOSFET, IGBT,

Important characteristics are

carrier density � conductivity, voltage drop, power dissipation,

breakdown voltage � power handling, impact on other parameters

temperature coefficient � sharing of currents between multiple devices

stored charge � switching speed, switching power losses

Revisions: C Renumber/layout of 3.4 on; D spelling, note on j=�E , resistivity. E:2001 M19-3, Eg(T), Schottky, Darlington fig, Bib. F2002; G double spaced, fix up after giving lectures.

BIBLIOGRAPHYPrimary Reference: Mohan, Undeland and Robbins, Power Electronics.

J.J.Sparkes, Semiconductor Devices, 2nd Ed 1994, Chapman and Hall – good, detailed, physical electronics of general devices.

J.G.Kassakian, Schlect and Verghese, Addison Wesley 1992. Principles of Power Electronics – good, but too much detail. Good to follow up on

inconsistencies in Mohan introduced by his simplifications. Rates as the second most popular PE text on Amazon (after Mohan).

In general, the Power Electronics books are weaker on the physical electronics, but treat the special features of power devices more thoroughly.

D.A. Fraser The Physics of Semiconductor Devices 4th Ed, 1986 Clarendon. device physics QC611.F72 1987

J.J.Liou, Advanced Semiconductor Device Physics and Modelling. Artech House, 1994. Adv. SS physics approach, a little obscure.QC611.L473


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3.1 SEMICONDUCTOR PHYSICS

3.1.1 Conductors, Semiconductors and Insulators

Free charges (usually electrons) in solids allow conduction of current when an applied electric field causes

the unbound charges (carriers) to move (drift). Large currents can flow if the number density of carriers

is large (e.g. 1023/cm3: metallic conductors) and virtually no current can flow in an insulator with densities

as low as ~103/cm3. (resistivity range is ~1021). Intermediate densities are semiconductors, usually with

½ full valence shells [e.g. Si, Ge, C(diamond: v.good EBdown and thermal(20W/cm/K, c.f. 1.5 for Si, 3.85

for Cu, 0.5 for steel, .0016 for Kapton), but non-existent process tech.), SiC, Ga+As=3+5(v. high

mobility: �n=8500)M§26-7]. Free carrier densities are generally chosen to be intrinsically low, and can

be controlled (usu. increased) by doping, application of electric fields, and injection.

3.1.2 The charge carriers: free electrons and holes

In a pure, perfect crystal, silicon has a full set of 8 electrons

(4 pairs of shared electrons in covalent bonds with

neighbours), and free electrons are only created (and at a

very low density) by thermal agitation. A free electron

leaves behind a “hole” which itself is a charge carrier:

neighbouring bound electrons can jump into this hole, so

the hole, a positive charge, can move independently of the original electron that created it. That this is not

just a book-keeping trick can be demonstrated in two ways: – 1/ the mobility of holes is different to

electrons (usually less, as it takes more energy for a bound electron to jump into a hole than for a free

electron to move to a different lattice site, and 2/ Hall effect shows that the sign of charge carriers in P

material (defined below) is positive. Holes move about in the valence band, and free electrons in the

conduction band. These carriers may recombine when they meet (rate � nn � np: free electron density and

hole density resp.), and the equilibrium density occurs when these processes are in balance: ni2 ~ C exp(-

qEg/kT) (M:19-1), where nn=np � ni ,(intrinsic number density) and Eg is the band gap energy (~1.1eV

Si: p25 Liou - Eg is a weak function of T (Eg = 1.17V - �T2/(T+�) where � = 4.73e-4eVK-2 and �=636K).

(ni ~1010/cm3 Si, room temperature, doubles every ~5 – 10C). Eg is the energy gap between the bound

state of the covalent bond and the conduction energy band. (note: a more complete version of M19-1

contains an explicit factor of T3 (with a different numerical value of C: C1) C1 T3 exp(-qEg/kT))

3.1.3 Extrinsic (Doped) Semiconductors, Majority and Minority Carriers.

A monolithic device is made from one “block” of silicon, rather than pieces of different material bonded

together such as the original ‘point-contact’ semiconductors. Monolithic devices are made possible by

Energy band structure in a semiconductor

conductionband

Egenergy gap

1.2V Si

electron energy

valence band( o � holes)

- - - - - - - - - - - - - - - - - - - - - -

o o o o o o o oo o o o o o o o


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doping: the ability to greatly enhance the number of electrons or holes by adding very low densities of

impurities with one more (or fewer) shell electrons, from columns III and V in the periodic table. If one

boron atom replaces a silicon atom, the crystal structure remains unchanged, and the boron needs to make

one more bond(4) than it has shell electrons(3). A (thermally generated) free electron is quickly trapped

here (the impurity accepts an electron �acceptor), liberating a hole. The resulting doped semiconductor

is called P-type as there is an excess of holes, which in this case are called majority carriers, the rarer free

electrons being called minority carriers. Conversely, but more straightforwardly, a phosphorous (group-

V) impurity atom in a Si lattice would have an unbonded (free) electron, and is called a donor impurity,

and makes an N-type semiconductor, and the majority(=e)/minority(=p) carrier roles reverse.

The doped semiconductor nevertheless remains charge-neutral, as the charge at the donor/acceptor site is

equal and opposite to that of the liberated electron/holes. Eqn. M:19-1 still holds, but now as np � nn the

product of the electron and hole density appears on the LHS.:- p0n0 (= ni2) ~ exp(…)(M19-2)

where subscript 0 refers to the thermal (i.e. non-injected: see below)density. Note that the charge balance

equation, for full ionization of impurities (T > 100K), is p0+ND = n0+NA (M19-3)

obtained from N+ = N- , where N+ is the number of isolated positive charges (p0+ND: each donor leaves a

net +ve charge at its lattice site) and N- = n0+NA(acceptor atom sites end up with a net –ve charge). We

have included both acceptor and donor doping levels for generality, but as NA, ND enter only as NA-ND,

the excess dopant is the important quantity. [here NA, ND refer to the same material – beware later (e.g.

M:19-17) where NA, ND refer to different ends of a p-n junction!]

Solving (M19-2 and 3) for P-type material (acceptor doping only) and for NA>>ni � n0~ni2/NA, p0 ~

NA.(M19-4)

� hole density ~ acceptor density, but very few electrons (


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Lateral voltage due to Hall Effect

-

p

-

VD

- VHB (out)

Both these parameters are important, especially in minority carrier devices (e.g. transistors), so these

defect sites are often augmented during manufacture (e.g. controlled e-beam damage) to allow closer

control of device parameters.

3.1.5 Mobility, Drift and Diffusion, Hall Effect

Drift: In the presence of an applied electric field, charge carriers drift at the velocity at which the

acceleration from the field balances resistance to motion from collisions etc.

Vd = �E where � is the mobility

applying this to both electrons(n) and holes(p), and expressing in terms of current density, we can obtain

M: 19-7

Jdrift = �nqv = q�nnE + q�ppE (opposite charges, but opposite dirns �

same sign)

Hole movement (mobility) is different to electron mobility (usually lower), because although in both

cases, the particle that moves is actually an electron, when a hole moves, each electron has to break out of

a covalent (shared electrons) bond, and rejoin one. When considering free electron mobility, the electron

involved has already left the bond and remains free. Typically �n~1500cm2/V-s, �p ~1/3 of this in doped

Si. Note that the resistivity � can be obtained from M19-7, via j=�E, and =1/�. (Contrast with free

space, where we have dV/dt � E, as F=ma).

Diffusion: Thermal agitation causes diffusion out of regions of high density - formally diffusion currents

flow against density gradients, from higher density to lower density.

In 1D, diffusion motion causes an effective flux nv = -D dn/dx, so we can write

Jdiff = Jn + Jp = qDn dn/dx – qDp dp/dx M:19-8,

where the diffusion coeffts D are � T (Dp,n/�p,n =kT/q): M19-9

Similarly the minority carrier diffusion lengths

are Ln = sqrt(Dnn) Lp = sqrt(Dpp)

Hall Effect:

In the presence of a transvrse magnetic field, charged

particles are deflected by q(v� B). This creates a lateral

charge separation and potential difference.

Calculate transverse E from Hall voltage VH, then

qEtrans = JB/Nmaj. Then measure resistivity (~E longitudinal) ��Nmaj., from which we can measure �, and the

sign of Etrans gives the sign of the charge q on the majority carrier. Also measure mass of majority carrier


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by cyclotron resonance freq. (gyration frequency) � = qB/m. The effective mass is found to be

~1.1me(p52, Sparkes) for an electron in Si. (tidy up!!)


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3.2 PN JUNCTIONS

Concepts: step junction, depletion layer�reverse bias, forward bias�injection, variation of depletion

layer width, conductivity modulation, reverse saturation current, exponential forward conduction

equation.

Notation: np(x): electron(n) density in “p” region as fn of x. pn(x): hole(p) density in “n”

region

pn0 : intrinsic hole density? in n region x=0 is different for both sides!p+ means highly

doped p region

NA: Capitals refer to doping density (A: of acceptors)

For simplicity we study a step junction: has an abrupt change in doping density(e.g. deposited , point

contact, implanted). Graded is more realistic for diffusion-grown junctions, but more complicated to

analyse.

p n

Charge density+

-

+

++++

+

--

----

E-field

potential

depletion layer (… shows wider layer)drawn for higher doping in p than n

qNd

-xp xn

�c

metallurgical junction fixed charges

p n

np0

np(0)np(x)pn(x)

Exponential distribution of minority carriers outside thedepletion layer, which is narrower due to forward bias.

Note asymmetry: the p type region is more heavily doped

holeselectrons

+++

---

+ -

pn0

Figure 3-1 a) step junction, b) minority carrier injection under forward bias

When the p and n type materials are brought into contact, the potentials at the common surface

(metallurgical junction) have to equalise, giving rise to a contact potential, �c which is obtained by

integration across the depletion layer at I=0:

�c = kT/q ln(NaNd/ni2) M19-14. (assumptions: thermal diffusion balances drift, asymm, np0np(0) – see

below 3.2.1)

At equilibrium, for no bias (Figure 3-1a), drift due to contact potential balances diffusion. The

depletion layer (or space-charge limited region – SCL) is formed because majority carriers diffuse

across the metallurgical junction (density is much lower on the other side), and leave behind fixed charges

at the donor/acceptor impurity sites. This process continues until the E-field, which opposes this diffusive

flow, builds up to the point where drift in the E-field of the depletion layer cancels the diffusion current.


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Notes on the physical pictures in Mohan fig 19-8++:� In addition to the depicted remaining (fixed) donor charges, the diffusion of (free) carriers across the junction also results in a charge

buildup that simply doubles the net effect, even though they are not specifically identified. Later, in the calculation of depletion layer

width under reverse bias, these free carriers are in fact swept back into their original material, so best to leave them out.

� In fig 3-1b, the decay of minority density away from the junction is due to recombination. Also, it should be remembered that the

majority carrier densities are much larger than the values shown on the graphs of minority densities, but do not contribute significantly

to conduction across the critical depletion region as their charge causes motion in the wrong direction in the electric field set up there.

� In addition to the simplification of a step junction, there are some apparent anomalies in the physical picture because the choice of step

profiles of carrier and donor density that are not technically solutions of the diffusion equation because the gradients are infinite - but

they are the simplest possible representation.

� The depletion effect may be relative (i.e. carriers not totally depleted) in the equilibrium case (no connections), but application of

reverse bias will cause more and more electric field build up, until all the carriers are swept out – then the depletion of majority carriers

will be virtually complete – otherwise conduction would occur.

� Question: Is the net carrier density during forward bias increased significantly above the majority density by the presence of injected

minority carriers? If so, does this reduce the resistance? (maybe not, as the collision rate might go up?) – Answer from 3.3: yes and yes:

excess carriers DO (especially in a lightly doped material) decrease resistivity up to a point (conductivity modulation M§20-4-1), (but,

at very high levels, collisions do eventually increase, pushing resistivity back up).

3.2.1 Depletion layer width

As depicted by the dashed lines, varying the depletion layer width varies both E (� w) and the voltage (�

w2). The essential constraint is that the charge densities there are just the fixed (donor/acceptor) densities,

as the free carriers are swept away. This allows simple calculation of the contact potential from

electrostatics – dE/dx = /� = -qNa/� , and � = � E.dx = (q/2�)Naxp2 ( is the charge density/m3) from

which we can see that the total � considering both sides of the depletion layer is�c = (q/2�) (Na xp2+Nd

xn2). (Mohan 19-12).

Allowing for an arbitrary bias V by replacing �c with V + �c, and by noting that for neutrality, the widths

must be in the ratio xp/xn = Nd/Na, substitution in 19-12 shows the depletion layer width can be related

directly to bias and doping densities (-ve V being reverse bias)

W(V) = W0sqrt(1-V/�c) where W0=sqrt(2��c(Na+Nd)/qNaNd), noting �=11.7�0 in silicon,

�0=8.85e-14 in cm.

Under this simple model, the maximum electric field occurs at the interface (“metallurgical junction”) and

is

(C subscript omitted in Mohan) Emax = (2�C/W0) sqrt(1-V/�c) (Mohan:19-18)


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This simple approach relates �c to width and v.v., but is circular: Solution is to obtain contact potential

independently of the above by setting Drift and Diffusion current equal and opposite: �pEp = -Dp

dp/dx, assuming that at the p-type end of the depletion layer, the hole density p = NA and at the other end

it is ni2/Nd as per Mohan 19-4, and that the Einstein relations connect mobility and diffusion (M19-9) to

obtain �C = kT/q ln[NaNd/ni2] (Mohan:19-14)

This potential cannot be simply measured with a voltmeter, as the probes would form junctions

themselves, which would have contact potentials which together oppose the p-n contact potential.

3.2.2 Exponential Relation of I to V

In forward bias, the carriers that diffuse across the junction are not impeded by a large retarding field

(such as for no bias), and become minority carriers on the other side. With no depletion layer, the

diffusing minority density would approach the parent doping density in the other half of the junction, and

with a small depletion layer, a Boltzmann relation applies – pn(0) = p0 exp(qV/kT) where p0 = ni2/Nd,

pn(0) being the number in the thermal distribution that can cross the potential barrier – i.e. that have

energies in excess of the energy barrier presented by the retarding potential from Figure 3-1a, but reduced

by the bias voltage V. Note also that the contact potential �C does not appear in the expression with V,

because of cancellation in the end contacts; the same mechanism that prevents simple measurement of �C.

Viewed from the opposite point of view (starting from the no bias condition), the minority injection is

exponentially increasing as the barrier height is reduced by increasing V. [Note: No bias (I=0) turns out to

be equivalent to zero volts bias, also because of the cancellation of contact potentials in the contacts to the

external bias circuit.]

We obtain J (=I/A) by taking I=d/dt (q), and observing that d/dt � 1/. This avoids (j=nqv) calculating

the minority drift velocity, which must vary with x to ensure div.J=0 . Following Mohan, Q, the total

excess charge can be obtained from the area under the curves in Figure 3-1b, and J = Js [eqV/kT – 1],

(M:19-25)

where Js = qni2[Ln/(Nan) + Lp/(Ndp)], the reverse saturation current

A full calculation would take into account boundary conditions at the 4(5?) boundaries, voltage drop

outside the depletion layer, etc, but would be much more complicated.

3.2.3 Reverse Breakdown

Because the depletion layer is so narrow, the electric field in the reverse biased junction is very large, up

to ~ 200kV/cm, well above the breakdown electric field in air. The main limit to this electric field is

when a carrier obtains enough energy from the field between collisions with the crystal lattice to knock

(impact ionization) a bond electron into the conduction band. This electron will also be accelerated and


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can in turn ionise another site, and very quickly an avalanche occurs. Assuming an electron-lattice

collision time of c ~10-13 seconds, the distance travelled starting from rest is s= ½ac2, a=F/m=qE/me, and

the energy gained is qEs, equating to the band gap energy gives

EBD = sqrt[2Egm/(qtc2)] (a power of q in denominator was cancelled to put Eg into volts

M:19-26)

This ‘back-of-the-envelope’ calculation gives 3e7 V/m evaluated in MKS-SI, not far from the practical

figure of 200kV/cm.

It is instructive to calculate a few numbers assuming EBD ~ 2E7V/m, Breakdown voltage = 1kV

s = 1.8e-8m (0.02�m), depletion width = VBD/EBD ~ 5e-5m (50�m), tc ~ 10-7� recombination

time ? (recomb. time�excess carrier lifetime)

given �n = 1500cm2/V.s, = 0.15m2/V.s, then Einstein Reln� D n =kT/q � �n = 0.0038, so

assuming excess carrier lifetime of 1�s, then minority carrier diffusion length Ln =sqrt(Dnn) =

61�m

Returning to the general case, if we apply the breakdown E field, Vd= �EBD = 3e6m/s, i.e. KE=25eV, well

above the value assumed in estimation of EBD. In reality, the mobility probably falls with increasing drift

parameter, as the collision rates increases.

If we put this E-field back into the simplified step junction equation for Emax (M19-18), we estimate

breakdown voltage

VBD � �(Na + Nd)EBD2/(2qNaNd) (M:19-27)

(why both Na & Nd? – because E is affected by dopant levels on both p and n sides) from which

we see that higher voltage requires lower doping levels, on at least one side of the junction.

(�injection idea, conductivity modulation described below – also note that Na & Nd refer to

dopant densities on opposite sides of junction contrast with M19-3)

Looking ahead, for Nd


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3.3 POWER DIODESThe PN junction structure in a power diode is a good

example of a minority carrier device, representing

about half of all power devices. As we see above, lower

doping density allows higher breakdown voltage, thus

(high voltage) power diodes have a n- drift region in

between the p+ anode and n+ cathode. (note:

superscript – means lighter doping, and that heavy

doping(+) of end regions facilitate bonding to lead wires § 3.3.4 ). Low doping in the n- region means

that most of the current is carried by holes (why? less mobile? answer: in fact both p and e injected into n-

, from left and right) injected at the anode junction, the electron injection being at least Ndn-/Nap+ (num.

donors in light n/num. acceptors in heavy p) ~1e5 times smaller (reduced further because of nn.pn = nin) .

Injected carrier densities can approach 1e17/cm3, so this large injection of carriers makes the resistance of

the n- region much lower than the bulk resistance of the doped material (doped at say 1e14/cm3), a

phenomenon called “conductivity modulation” common to many minority or injection devices. This

region is often manufactured by epitaxy – evaporative deposition of ~100�m of silicon onto an existing

crystal, incorporating the doping impurities during the process for uniformity. Note that in fig 3-2, the

250�m cathode is actually the substrate in the epitaxy, as detailed in figs.20-1, 20-5 and 6 in Mohan. The

anode is formed by diffusion doping at high levels, leaving the bulk of the epitaxial layer as the n- or

‘drift’ region of length Wd. Note that this is distinct from (but contains) the depletion layer (W).

In this way, a bipolar (injection/minority carrier) device can have the best of both worlds, the injecting

region having a high doping density, but the drift/depletion region with very low doping to enhance

voltage stand-off.

This can be quantified by considering the voltage drop Vd across the drift region of a p+n–n+ junction in

forward bias, carrying current IF.

we use J = �(p,n)nqv, where J = IF/A, v(p,n) = �(p,n)E = �(p,n)Vd/Wd and we assume equal injection

from both ends so nd = na. substituting � IF = q(�n + �p)naAVd/Wd (M20-11)

Which confirms that the current increases with injected density. In forward conduction, the electric field

in the drift region is small, the carriers move slowly and the distance is “long”, so the carriers tend to

recombine before reaching the other end. If the recombination time is , the we can also say that IF

equates to the rate of disappearance of stored charge QF

IF = QF/, QF � qna� (drift volume) = qnaAWd (M20-12)

p+ n++ -n _

Na=1e19 Nd=1e14 Nd=1e1910�m Wd=50-200�m 250�manode drift cathode

Injection of holes ‘Double’ injection (e-)

Figure 3-2 Power Diode with exaggerated drift region


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which in combination with 20-11 says that Vd (and Ed) is independent of IF and is given by Vd ~ Wd2/[(�n

+ �p)] (M20-13).

This shows how both the increased drift region size of the power diode, and reduced recombination time

(attempting to combat stored charge problems) increase the losses. If we put Wd = 100�m, �n + �p = 900,

= 1e-6 then Vd = 110mV – which is fairly small, but increases with injection level as follows:

At higher current levels, higher carrier densities are injected, and M20-13 must be corrected by allowing

for reductions in mobility at high injection levels (na > nb, the critical injection level) . This restores the

more intuitive situation where Vd increases with IF.

putting �n + �p = �0/(1+na/nb) Vd ~ JFWd/(q�0nb) +3�( JF2Wd4/(q2�03nb2 0)) (M20-16)

and remembering the junction drop Vj, we finally have Vfwd = Vj + RonIF , where Ron is the

“slope of Vd vs JA from M20-16”

3.3.1 Voltage Standoff for Minority and Majority Carrier devices

For the case when voltage stand-off is important (i.e. power devices), Mohan compares current density

capability of majority (FET) and minority (BJT, SCR) technology and with reasonable simplifying

assumptions

(lower � for minority devices as carrier density is likely to be higher, substitute the breakdown estimate

of M20-3, into M20-11 obtaining

J(minor.) � 1.4e6 Vd/VBD compared to J(maj.) � 3.1e6 Vd/VBD2, (M20-18,20)

where Vd is the forward bias drift region voltage drop. The majority carrier result comes from the

majority version of M20-11 JF = q�nNdVd/Wd, and the use of n-type material for its higher mobility

~1500cm2/V-s at the typical (lower) doping of 1014 /cm3. For majority devices, Wd is less well-defined,

but may be identified with the path length of current in the device.

This shows that minority devices are clearly more efficient for high voltage stand-off. Both will suffer

higher Vd for higher stand-off voltage. (If anything, the Wd may be bigger still for a majority device to

satisfy other geometry requirements, further reducing J.) However, the huge injected charge of minority

devices becomes a problem at high frequencies as follows:


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3.3.2 Switching Transients

How long does it take for the minority charge

density to be established, and then removed?

Assume conduction � 50mV over 100�m as

estimated above ~500V/m (~1/40,000th

breakdown field) �p ~ 0.05m2/V.s, so vp=

25m/s. Time to travel 100�m is 4�s, assuming

uniform field, and longer if non-uniform. So the

time for the injected charge to leave the diode will be >4�s, or as long as the recombination time (~0.1 –

10�s). Even if a bias is applied, to sweep out the minority charge, initially the bias will tend to be shorted

out by the free carriers because of that injected charge. Similarly the turn on time would be the time to fill

the n- region with carriers. This will be shorter, as the absence of carriers allows a voltage to be applied,

creating an Efield, which sweeps the injected charge in more rapidly. The consequence is that the

resistivity (hence forward voltage drop) decreases over a period of hundreds of ns from a high value

(~10V) to the normal value. Inductance in the leads and chip only adds to this effect on turn-on. Typical

waveforms are shown in Fig 3-3. Overlap between current flow and voltage spikes produces high

instantaneous power and increases the average power dissipation with frequency. One method to

implement fast recovery diodes is increasing the recombination rate, thereby reducing the stored carrier

decay time, but this also decreases the carrier density in the low doping region, and reduces the efficiency

gain from conductivity modulation. A similar dilemma exists for Schottky diodes described below.

3.3.3 Other Diodes

Zener Diodes are designed specifically to operate in reverse breakdown as voltage limiters or “clamps”,

or as voltage references. At voltages above 5V, the mechanism is impact ionization as described above,

and the breakdown is controlled by doping. At lower VBD doping levels are so high, and the depletion

layer so thin, that quantum-mechanical tunnelling through it dominates reverse breakdown. Numerical

example: Say we want a 6V Zener. Assuming the target breakdown field is 3e7V/m, we need a depletion

layer width of 6/(3e7) = 0.2�m. M19.27 � ND, NA, ~ 4e16/cm3.

At lower voltages sizes are smaller still, the gradient in the potential is so high that over a distance of

2nm, or ~7 atom spacings, the potential changes by ~ EG (need to consider band-bending). This is close

enough so that electrons can “tunnel” from the valence band to the conduction band, causing a breakdown

that is called ‘Zener’ breakdown.

V

i forward reverse

reverserecovery

P

capacitiveenergy out

Increaseddissipation

Figure 3-3 Current, Voltage and powerwaveforms for a power diode


p14

Au n+

e-

reverse

forward�

P-I-N diodes could be likened to the structure of power

diodes §3.3 but with an Intrinsic region replacing the n-

drift region. In fact, a P-I-N structure is used to achieve

even higher breakdown strength in power diodes for the

same length of drift region (low doping section). It is in

practice, a power diode structure as above, (p+, n-, n+), but

with an even lower doping level (almost intrinsic) n- drift

section. ( Mohan refers to this as “Punch through” or

“reach through” (§20-3-1), and the advantage arises from

the electric field being almost constant in the depletion layer, rather than “triangular” as in Figure 3-1a.

The gradient in E is � charge density, which is lower in lower doped materials.)

Punch through diodes are motivated by M20-13 – the voltage drop in the drift region goes as the length

squared. The drift region could be shortened if the electric field was more evenly distributed. This

happens if the charge density in the drift region is even lower than n-. The depletion layer widens at lower

voltages to fill the drift region. After this, the charge density exposed is in higher doped material, so the

electric field builds up quickly (dE/dx = /� = -qNa/�). This appears to violate the avalanche criterion,

but if the exposed lattice ions in the p+, n+ regions are dense enough, the length of the region over the

limit is too short for an avalanche to grow. The “constant” Efield means that the integral of Edx (i.e.

BVBD) is up to twice that of a pn-n diode.

Small P-I-N diodes are used as RF modulators (conductivity modulation) and photon/particle detectors

(large sensitive volume).

In Schottky diodes, the p+ zone is replaced by a high work function metal

(electrons bound strongly – e.g. �Au ~4.75V c.f. usual metal contact �Al~4.1V and

Si �nSi16 ~4.2V), creating a potential barrier w.r.t. the n-region, so electrons

preferentially move from the n region to the metal (and falling through the barrier, become “hot”). The

physics is very different:

– holes are not involved (there are none in the metal region – no covalent band),

– the majority carriers (e-) do the conduction (low stored charge, fast switching), and

– forward (0.3V – only “half” a junction) and reverse voltages (100V) are smaller (if no minority carriers

in n region, can’t use low doping overcome by injection for low ON resistance� compromise).

In the reverse direction, that small difference in potential(


p15

Figure 3-4 Interdigitated NPN power transistor (Mohan)

i

voperatingzone

Efield in medium doped n can’t overcome this. Need to consider Fermi levels and band-bending for a

better understanding.

3.3.4 Contacts

The Schottky diode anode is an example of a rectifying contact. To make a low

resistance, non-rectifying “Ohmic” contact, a very high doping density (>>1e17) is

used under a low work function metal contact (Al), so that the depletion layer is tiny,

and tunnelling occurs at very low voltage (i.e. Zener with VBD so small it conducts in

both directions.). The contact is typically evaporated (or vacuum arc deposited) onto the silicon, and is

connected to the package either by a compression sandwich structure for power devices or a welded bond

wire. Thin bond wires can also be used in power devices if they are made up of many (100s-1000s) of

tiny devices of sufficient complexity that they can’t be contacted by a single compression structure

(IGBT).

3.4 BIPOLAR JUNCTION TRANSISTOR (BJT)

The familiar transistor is a bipolar (p and n)

junction device, in which injection of minority

carriers from the emitter to the base region enables

current flow from the emitter to collector. The

transistor has high gain (�) if the current collected

by the base is much smaller than that collected by the collector. The collector base

junction is reverse biased, and sweeps most carriers in the base region to the

collector. A much lower doping density in the base preferentially injects from

emitter� base, and the base region is kept as thin as possible for high �. The idea

is that VBE keeps potential barrier low to allow diffusion E�B, but most electrons

continue on to the collector C, not the base B if the base is thin. However high

stand-off C-E requires that the depletion layer width (and therefore the effective base width) be increased,

T1 T2

Darlington cfg

n n- +p-

ne-

IB

IE IC+

-

--

Figure 3-5 Conventional (low power) BJT, simplified


p16

n+ p n- n+

injectedexcesscharge

active region

quasi-saturationfull saturation

virtual base

+

IB+ Ic

VCE

IB1

IB2

IB3

as in a power diode. This is achieved (also as for a power diode) by making a drift n- region adjacent to

the base, as shown in fig 3-5. This conflicts with the � requirement, so for a power transistor � is lower,

typically 5-20 (overcome by Darlington cfg see figure). Another loss mechanism for � is hole current

from the base to emitter. Although kept low by low doping in the base, the holes must complete the

circuit through the base, (as the CB is reverse biased) so this increases IB, further decreasing �. The

transistor suffers from stored charge switching delays in the EB junction due to its use of minority

injection. This also may happen in the CB junction if that is permitted to forward bias, which typically

happens when used as a switch, and the transistor “saturates” (next section: VBC~0.6V~VBE�VCE~0.1V). Three-dimensional effects are quite important, as illustrated by the diagram of the

interdigitated power transistor Figure 3-4. This device would not be possible to make sufficiently large

for high power by diffusion processing (i.e. monolithic) in the simple slab geometry used for explanation

– the resistance of the base and hence the lateral voltage drop (§3.4.2) would be too high. The figure

shows both how a slab structure is achieved vertically by masked diffusion doping, and how multiple

devices can be paralleled. Disadvantages of 3D structures include locally high electric fields near corners

and edges, which often need special shaping or guard pieces for compensation (Mohan fig 20-12). An

important strategy is to “cancel” or override a weak dopant with a localised stronger dopant (e.g. the p

over the n- in fig 3-4, to make the base, and then put the n+ over the p to make the emitter fingers -

doping diagram from Williams p26 is good, also Mohan Fig21-1(simple), 21-4 (complex)).

3.4.1 Saturation in the BJT

During normal operation

(“active region”), the CB

junction is reversed biased,

and sweeps injected charge

quickly through it. As the

collector voltage falls, the

electric field in the CB

junction falls, and carriers slow

down and accumulate (j=nqv; v��n�). This charge accumulation increases the effective size of the base,

which reduces the beta (more charge escapes via the base), and the collector current consequently falls

(quasi-saturation). This is indicated graphically by the constant base current curves (IB1,2..) bunching

together(��), and those lines turning over towards the origin. In this quasi-saturated state, part of the

drift region is conductivity-modulated (low resistance), and the rest is not. In this state, quasi-neutrality

� injected n (n’) must be ~ matched by extra holes (p’), and recombination can only occur by loss of

Figure 3-6 Saturation stages of a power BJT


p17

Ic

VCE

IB3Ic Max

VCE MaxSecond BD

VI=Const(�T)

1ms10ms

numbers from each (to preserve neutrality). This co-operative recombination is termed ambipolar

lifetime �a.

The extreme case is when the collector voltage is near zero (saturation), when carriers accumulate even

more, the beta falls even more. This state however is very useful in switching circuits as the high carrier

density allows very little voltage drop and therefore reduces conduction losses. As stated above, recovery

from saturation is slow. This is because in the saturated state, the large carrier excess makes the

conductivity high, so the field to sweep carriers away is very small, which creates a vicious cycle. The

same transistor will switch must faster if saturation is avoided, but this is at the expense of higher on state

losses, and more difficulty setting the exact bias required to achieve the unsaturated on state, esp. as �

varies.

3.4.2 Second Breakdown

This is a subtle failure mode which is the main limitation of power

BJTs. The phenomenon is that a transistor may fail well inside the

rated voltage and current zone. For the purposes of this discussion,

the diagram provided is different to the usual second breakdown

safe operating area (SOA) diagram, in that the axes are linear. First,

every device has a maximum I and V, creating a rectangular SOA.

Next a hyperbolic area is excluded on the basis of power dissipation (Pmax=VI(T)). This is actually a

family of hyperbolae, because on shorter pulses, more power can be instantaneously dissipated. Finally,

at higher voltages, the collector current is even more restricted. This is the second breakdown region

(diagram). The explanation is complicated in detail, but key elements are negative temperature coefft,

current crowding and lateral voltage drop. Minority carrier devices have a negative temperature

coefficient of resistivity – the intrinsic density doubles every 10 degrees (why does this affect the injected

minority density?), so a concentration of current is likely to concentrate itself further (current crowding)

if the current is rising quickly and the local heat can’t spread– so there is danger if current turns on too

fast, near the edge of the SOA. During the switchoff phase, the base is usually driven hard to remove the

stored excess charge. This large current causes a lateral voltage drop in the base region, and as the base

is usually fed from the “side”, this means that the voltage gradient across the base turns off the transistor

in a gradient across the base, so the far side of the transistor stays on longer. This causes immediate extra

dissipation, which may escalate and cause further current crowding. Normally a log-log graph is used to

show SOA, and both the power limit and second BD regions appear as straight lines, with slopes about –1

and ~–2 respectively. Second breakdown may limit currents severely – up to 10 times less that the peak


p18

current capacity. Note that VCEO(sus) is only 50-80% of VCBO(sus), because � amplifies small,

pre-avalanche currents.

3.5 SILICON CONTROLLEDRECTIFIER(SCR)

The SCR or thyristor is a four layer

junction device that may be regarded as a

complementary (�NPN + PNP) pair of

latching transistors, although it is

constructed as a unified four layer

structure as shown. The bipolar

technology allows for simultaneous

high voltage stand-off and low forward resistance by use of long, low-doped drift regions which achieve a

good forward conductivity by the conductivity modulation characteristic of injection/minority devices. As

an injection/minority device, it suffers from reverse recovery delays, and current crowding as a transistor

does. The simple (non-interdigitated) structure allows efficient cooling and contacting – a large (>kW)

device is often one huge (~75mm) 4 layer wafer, compressed between two metal disk electrodes by large

forces (~MPa) to aid in contact and heat removal. The single gate contact if this type of structure makes

the device more rugged, but encourages current crowding near the gate terminal (due to lateral voltage

drop), so fast DI/dt at turn-on must be avoided to allow the current channel to fill the device area

uniformly. Also DV/dt at turn-off needs to be controlled, as capacitive currents (like Miller currents in

linear devices) can retrigger the device. Marginal retriggerring is very bad – only some regions switch on

� current crowding. One strategy here is a “cathode short”, an extra piece of metallisation that partially

bridges the gate and cathode. This is like a resistor between emitter and bas of Q1, and effectively sets a

minimum base current below which the device will not turn on, either directly or by dVa/dt.

There are two grades of SCR – �1 – low speed, low forward voltage, usually a simple gate, and Inverter

grade are intended for higher frequencies ~kHz, and have complex gate structures (e.g.involute) to speed

up switching at the expense of higher forward voltage drop.

Latching means that the transistors turn each other on regeneratively, so once conduction starts, it cannot

be stopped by removing the gate drive. It is a two-state device – On and Off. Only current dropping to

zero unlatches the device (the criterion is that the loop gain of the device ~�1�2 has to fall to < 1 before it

turns off). � falls at very low current, and at low voltage, so as the current goes through a zero, the device

turns off. This is known as “natural-commutation”. The high current capacity makes it ideal for phase

n+ n+p

n-

p

p+

cathode cathodegate

anode – p+ layer lowers contact R

gate

cathode

anode+rev.block SCL

fwd. SCL

Q1

Q2

cathode short

Figure 3-7 section through a cylindrical SCR – not to scalethe main dep. layers are indicated for reverse and forward blocking


p19

Depletion mode N-Channel JFET showing narrowing ofthe conduction channel

-

n

p+

p+S D

G-VGG

VDD +

controlled rectifiers, the AC naturally turning off the device every cycle. The device is switched on at

different phases in the cycle (Switching circuits §2.3) according to the average current required, hence the

name SCR (Si Controlled Rectifier).

3.5.1 Triacs, Gate Turn-Off Thyristors

A gate turn off thyristor (GTO) has many small gates meshed in between cathodes. A large reverse

current in the gate (about 20% of the anode current) can squeeze out the conduction channel until the

device turns off. Gate control is achieved by providing a highly interdigitated gate so charge can be

efficiently extracted, dramatically reducing the � of Q1 so that the regenerative base drive of Q1 is not

overwhelming, and strategic placement of anode shorts to further spoil the � when the conduction channel

is squeezed. Anode shorts also spoil the reverse voltage hold-off. A duty-cycle limit arises because the

device must be allowed a minimum time in the “off” state, so that all excess charge is removed from all

paralleled sub-devices. If some charge remains in a few devices, they will turn on preferentially in the

next cycle, and try to take all the current � failure. A similar timing criterion applies to turn on to ensure

all devices conduct equally – a minimum time of a boosted drive current is applied, during which time

anode DI/dt must be controlled, and after that, a continuous, reduced drive is applied to ensure devices

stay on. If the current ever exceeds the rating, the device must NOT be turned off: if any sub-devices did

successfully switch off, it would increase the dissipation in those that didn’t. Some type of natural

commutation, fuse or crowbar must be used. For example, in a bridge, the drive unit can command all

GTOS to switch on, sharing the overcurrent, and blowing a fuse. These complex drive requirements

mean that it is advisable to drive GTOs only with custom drive units supplied by the manufacturer.

A TRIAC is a bi-directional switch like two back-to-back complementary thyristors (complementary so

that the gates can be driven from a common (but bi-polar) source, referenced to a common terminal (the

cathodes). This is the active element in small domestic “Phase controllers” e.g. light dimmers, and in

‘solid state relays’.

3.6 FIELD EFFECT DEVICESThe explanation in Mohan is hard to understand, because it

tries to explain without going into enough detail. Let me

use even less! The FET uses electric fields from an (often

insulated) gate electrode to create and control depletion

layers which vary in width, pushing in from the sides. This

modulates the width (hence conductance) of the conduction


p20

channel between Source and Drain, while leaving the carrier concentration (mainly majority carriers)

alone. Contrast this with minority carrier devices in which conductivity modulation is achieved by

injection, varying the carrier density but not the conductor geometry. The depletion JFET diagram on

p644, based on familiar pn junction(�JFET) theory is much easier to understand, although the shape of

the output curves (constant current) is not predicted by this simple explanation. In the normal active

region, the drain current is independent of VDS, and is given by ID = K(VGS – VGS(thr))2 (M22-2)

This squared dependence on VGS is only true for low drain currents in high power FETs; at higher

currents, the transfer function is closer to linear.

Most power FETS are interdigitated, multiple devices, and use “enhancement” – (in the zero drive state,

the drain conducts very little – application of the voltage causes conduction – understanding enhancement

mode requires the inversion layer concept of Fig M22-5). Because the gate is insulating, (or reverse

biased for a JFET) the drive requirements are modest (except the gate is a large capacitor – failure to drive

this decisively will lead to excessive VDS�ID dissipation during switching transitions). The device is a

majority carrier device, so the slow recovery of injected carrier devices is avoided, and device resistance

increases with temperature, so devices are readily paralleled, and share current thermally. The SOA

curve has no restrictions due to second breakdown (majority carriers, positive temperature coefft of R).

One disadvantage is the thousands of bonding wires in a large power device (>kW) increasing mechanical

fragility, compared to the compression-mount “hockey-puck” SCR. Most power devices are insulated

gate FETs described below. Recent developments in Power FETS have concentrated on increasing the

area of the conduction channel, e.g. complex hexagonal interdigitation, or even by cutting V grooves in

the silicon to make more surface area for devices . A rough guide is 100A/cm2, arising from current

density estimates like M20-20 and power calculations obtained by multiplication by Vd.

3.6.1 Switching Considerations

Like all devices, we must respect Pavg, Vmax and Imax. The only other significant power related parameters

for a FET are RDS(on), and gate turn-on time (capacitance). If the gate terminal is driven too slowly (e.g.

gate drive impedance too high), the device spends too long in the partially conducting state, in which both

IDS and VDS are >> 0, so the average power dissipation (1/T�IDS�VDSdt) increases significantly – normally

one or the other is quite small, keeping PDS low [contrast with second breakdown, saturation, DI/dt,

DV/dt, gate drive power considerations for BJT and SCRs]. IGBTs [see below] require care to avoid

latch-up.


p21

3.6.2 MOSFET, IGBT

The MOSFET is a FET whose Metal gate is insulated by an Oxide (SiO2) layer on a Semiconductor

layer. It is the most common form of the FET, and its operation is quite similar, but different in detail e.g.

the subtle effect of ‘charge inversion layers’. The device used the DC-DC converter is an N-Channel,

enhancement-mode MOSFET.

IGBT – The Insulated Gate Bipolar

Transistor is a hybrid device with the

high input impedance of a FET, but

the superior power handling of a BJT

(and a speed in between BJT and

FET). It like a MOSFET driving the

base of a PNP transistor, but even

more effective because the structures

are integrated, the BJT injects back into the FET, conductivity-modulating the drain. It is meant to be

non-latching, so is much more versatile than an SCR, as it can be switched off easily. However, because

the structure n+, p, n-, n+, p resembles a thyristor, it can act like one in some circumstances, latching on –

this is considered a fault condition and should be avoided. This is called the “parasitic thyristor

structure” in parallel with the IGBT (in the same way as MOSFETS have a “parasitic BJT transistor

structure” in parallel). Although the parasitic BJT is shorted (B to E) by overlapping metallisation (same

principle as cathode shorts in a SCR) a lateral voltage drop may occur when the drain current is high,

overcoming the short. Both doping levels and geometry are optimised to reduce this effect, and the circuit

designer limits the maximum drain current and its rate of change to avoid latchup. A punch-through

depletion layer reduces the on resistance, but reduces the reverse-holdoff voltage. If the drift region is

made thicker so that punch through does not occur, then the reverse-holdoff is the same as the forward

holdoff, and we have a symmetric IGBT, good for AC.

SiO2 SiO2

n- (drift/standoff)

n+

p+

gate gatesource

gate

cathode

anode+rev.block SCL

FET

Q2

n+ n+p

E

B

Cpara. E-B short

channel

Fig 3-8 IGBT geometry showing integrated PNP BJT and N-Channel FET

Documents

3 ENGN3225 Power Engineering: Semiconductor Devicespeople.physics.anu.edu.au/~bdb112/engn3225/eng_3225... · 2002. 10. 6. · ENGN3225 Power Engineering: Devices Lectures 8/2002 Boyd