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05/03/23 Deapartment of Information Technology
1
Microprogram Control
CS1251Computer Organization
Carl Hamacher
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Terminology
Control Word Bits represent control signals
Microroutine Sequence of control words Control sequence of a machine instruction
Microinstruction Individual control word in a microroutine
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Example Micro Instructions
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
MAR_En_In, PC_En_Out,PC_Inc
2 MDR [MEM([MAR])] MEM_Read, MDR_En_In13 IR [MDR] MDR_En_Out2, IR_En_In1
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Example Micro Instructions
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
MAR_En_In, PC_En_Out,PC_Inc
2 MDR [MEM([MAR])] MEM_Read, MDR_En_In13 IR [MDR] MDR_En_Out2, IR_En_In1
Micro-instruction ...
PC_Inc
PC_En_Out
IR_En_In1
IR_En_Out1
MEM_Write
MEM_Read
MAR_En_In
MDR_En_In1
MDR_En_In2
MDR_En_Out2
...
1
2
3
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Example Micro Instructions
Step RTN Control Signals
1 MAR [PC],PC [PC] + 1
MAR_En_In, PC_En_Out,PC_Inc
2 MDR [MEM([MAR])] MEM_Read, MDR_En_In13 IR [MDR] MDR_En_Out2, IR_En_In1
Micro-instruction ...
PC_Inc
PC_En_Out
IR_En_In1
IR_En_Out1
MEM_Write
MEM_Read
MAR_En_In
MDR_En_In1
MDR_En_In2
MDR_En_Out2
...
1 1 1 0 0 0 0 1 0 0 0
2 0 0 0 0 0 1 0 1 0 0
3 0 0 1 0 0 0 0 0 0 1
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Control Components
Control Store Special memory which stores microinstructions
Microprogram Counter (PC) Address of next microinstruction
Microprogram Branching Next address determination for control
sequencing
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Control Unit Organization
ConditionCodes
AddressGenerator
CLK
IR
External Inputs
PC
ControlStore
ControlWord
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Microinstruction Encoding
Horizontal Organization Minimally encoded (higher speeds) Many resources controlled by a single microinstuction Parallel use of resources
Most signals not needed simultaneously Many signals mutually exclusive
Vertical Organization Highly encoded (slower speeds) Small number of control functions in each
microinstruction
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Example Encoding15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
InstructionF0 F1 F3 F4F2
F1000 NOP001 PC_En_Out010 MDR_En_Out2011 Z_En_In100 MEM_Write101 MEM_Read110 REGS_Write111 REGS_Read
F2000 NOP001 IR_En_In1010 MDR_En_In2011 Y_En_In1100 IR_En_Out1101 REGS_Sel110 PC_Inc111 Halt
F300 NOP01 MAR_En_In10 Z_En_Out11 Y_En_In2
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Microprogram Sequencing
PC with branching capability Separate microroutine for each machine instruction Considerable duplication of common parts Longer execution time due to complex branching
AR with Next Address and Bit-ORing Additional bits for address field Fewer branch microinstructions Microroutines share many common parts
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Bit-ORing
Modification of bits within a branch address by ORing them with Bits from IR
OpcodeAddressing Mode
Condition Codes External Inputs
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Example Instruction Format15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0 F1 F3 F4F2
F4 OR Fn00 Next Addr01 ORSRC 00&SRC_MODE&00
10 OROP_ 000&OPCODE
11 ORDST 000&DST_MODE&00
F0Addr of
next instr
Instruction
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Control Unit Organization
ControlStore
uIR
DCD...
ControlSignals
uAR
IR
DCD
F0 F4
ConditionCodes
External Inputs
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Example Control Flowchart
MDR [MEM([MAR])]
Start
MAR [PC]PC [PC] + 1
IR [MDR]
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
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Example Control Flowchart
Reg Direct00
Y [REGS([SRC_REG])]
Reg Indir01
MAR [REGS([SRC_REG])]
MDR [MEM([MAR])]
Y [MDR]
Y Y
NN
SRC_MODE?
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
010100
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
010100
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
010100 MAR [REGS([SRC_REG])]
010101 MDR [MEM([MAR])]
100000
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
010100 MAR [REGS([SRC_REG])]
010101 MDR [MEM([MAR])]
100000
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Microinstruction Encoding
Address F0 F1 F2 F3 F4 RTN
000000 000001 001 110 01 00 MAR [PC], PC [PC] + 1
000001 MDR [MEM([MAR])]
000010 IR [MDR]
010100 MAR [REGS([SRC_REG])]
010101 MDR [MEM([MAR])]
100000 Z [Y], Branch DST_MODE
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Example Control Flowchart
Reg Direct0
REGS([DST_REG]) [Z]
Absolute1
MAR Value
MDR [Z]
MEM([MAR]) [MDR]
Y Y
NN
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Questions?