Upload
jagadees21
View
219
Download
0
Embed Size (px)
Citation preview
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
1/29
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
2/29
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
3/29
Design Flow Chart
CIS
DesignOrCAD
PSpice
ons ra n s
PCB
Designer
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
4/29
Traditional Signal Integrity Flow
Design Reuse?etlistt
Constraints Update ?Design
Analyze / Edit TopologyoPCB
Co
nst
Editor
raints
Topology Extraction
opo ogy ssoc a on
o e ssoc a on
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
5/29
Topic
Chan e our constraints desi n flow with OrCAD SI
Determine desi n constraints from Ca ture to OrCAD SI
Back annotate ECsets and store information in Capture Directly translate design constraints from netlist files.
Enhance the smoothness for PCB design flow
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
6/29
OrCAD Schematic w/ Signal Integrity Flow
SI Model Association
na yze opo ogy
Topology Extraction
etl
ist
Topology Association
oPCB
Editor
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
7/29
Determine Hi-Speed Constraints in OrCAD SI
1. Impendence control
2. Timing control
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
8/29
SI Analysis in Capture
.
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
9/29
Assign SI Model
Assign SI model for others
Xnet
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
10/29
r gna n egr y or
-
From OrCAD Ca ture to OrCAD SI
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
11/29
Impendence Control - Terminator
=
R16 = 100 Ohm
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
12/29
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
13/29
Virtual Layer Stackup
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
14/29
Virtual Via Padstack
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
15/29
Edit & Assume Transmission Line
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
16/29
Edit & Assume Layer Stackup forTransmission Line Via Model
-
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
17/29
Define Constraints in OrCAD SigXplorer
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
18/29
Update to Capture
Reusable Schematic &Constraints
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
19/29
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
20/29
Apply Differential Pair ECSet
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
21/29
Update To Capture and Netin toAllegro/OrCAD PCB
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
22/29
Import ECSet From Constraint Manager
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
23/29
DDRx Routing Topology
RAM Chip
RAM Chip
Controller
RAM Chip
RAM Chip
23
D i R l i P i D l
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
24/29
Determine Relative Propagation DelayConstraints
Build BUS Group
Create pin-pair by each net
Match Group by pin-pair
-
Determine who is the target for each group
Is it possible to be much faster and easier ?
D t i R l ti P ti D l
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
25/29
Determine Relative Propagation DelayConstraints from OrCAD SI
D fi R l ti P ti D l
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
26/29
Define Relative Propagation DelayConstraints
A l ECS t i C t i t M
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
27/29
Apply ECSets in Constraint Manager
Auto create Pin-Pair b Each Net Auto match Group by Pin-Pair
Auto assign constraints by each Pin-Pair
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
28/29
*
DSN
One mouse clickmakes you ready for
From Processor =>
.
Topology Embedded in DSN file
SI Analysis
F A B
8/10/2019 3 OrCAD SI for Electrical Constraints Determination
29/29
F.A.B.
Enhance constraints design flow with OrCAD SI
r can e p us o e erm ne es gn cons ra n s It can back annotate ECSets and store information in Capture
Directly translate design constraints from netlist files