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LAB 2 Single-cycle MIPS Processor

Objective:The main objective of this laboratory is to design and implement a single-cycle MIPS processor

using VHDL, which can perform the following basic instructions:

R-format: Add, Sub, And, Or, Slt

I-format: Lw, Sw, Beq

Implementation guidance:

The instructions should be stored in ROM and the data memory should be stored in RAM. Only

a smaller version containing an 8-bit data path with full 32-bit instructions and control is

required in this laboratory experiment. Thus, this smaller model requires machine language test

programs that use 8-bit integer values. In addition, the address space for I-format and J-format

commands should also be limited.

Laboratory preparation:1. Be familiar with the materials related to the single-cycle MIPS processor from the

textbook, including hardware structure and instruction format. A brief review can be

found in Appendix A. Convert the test bench program in the laboratory part of this lab

manual into binary/hex format. That is format that will be stored in your instructionmemory.

2. Design the top level structure based on required instruction set. Take care of the

address/data width matching between different components, because the address/data

widths in this laboratory are different from the one in the textbook.

Note: You have to determine every functional part for each component is implemented by

combinational logics or sequential logics. They may be different for different components,

and even different functional parts within a same component. Keep in mind that we are

design a single-cycle processor. More detail information regarding VHDL coding and

hardware device refer Appendix C.

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Architecture Part:A two level hierarchy will be used.

Top level Module:

The top level is for final simulations and verifications, with the clock and the reset as inputs.

A Possible MIPS Top Level Module

The values of major busses and control signals are can be copied and output from the top level so

that they are available for easy display in simulation. Top level consists of five modules:

1. InstFetch.VHD Contains instruction memory and PC

2. CntrlUnit.VHD Logic for the control unit

3. InstDecode.VHD Dual ported register file

4. InstExe.VHD Data branch address ALU

5. DataMemory.VHD Contains data memory

Two-level hierarchical model Top level (grey), bottom level (white)

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These five behavioural modules correspond to the different stages of the MIPS. This makes it

much easier to modify the design when the model is pipelined in later laboratory experiments.

Top level could also be created using the schematic editor and simply connecting the symbols for

each of five VHDL sub modules. This might help you in your understanding of the design but

because of its complexity can become rather messy.

Control unit stage:

This module examines the instruction opcode bits and generates eight control signals used by

other stages of the processor.

MIPS Control Unit Module

Decode stage:

This module contains register file (MIPS contains thirty two 32 bits registers). To speed up

synthesis (speed of compilation) the registers were reduced to a total eight 8-bits registers (R0 to

R7). The sign extension is required for the original single-cycle MIPS processor in the textbook,

as the following figure shown. However, we only have 8 effective bits for instruction memory.

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Thus the sign extension function block has to be modified accordingly, as the symbol in the

figure shown. Please figure out its function before implementation.

MIPS Decode Module

Execute stage:

This module contains the data ALU and a branch address adder used for PC relative branch

instruction. Also it contains multiplexers that select different data for the ALU input. To speed up

synthesis the width of ALU is limited to eight bits only.

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MIPS Execute Module

Instruction Fetch stage:

This module contains the instruction memory, the program counter, and hardware to increment

the PC.

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MIPS Instruction Fetch Module

ROM / Instruction Memory: This component is used to store the predetermined instructions

that are to be executed by the processor. This unit will strictly be used as a storage unit for

instructions and will only be accessed in the instruction fetch step.

The instructions should be converted into their MIPS binary equivalents and stored in the ROM /

Instruction Memory sequentially starting at address 00. For example, if the program is to

execute the first instruction, it would have to load into register $2 the value at memory location 0

in RAM. This is translated to the following binary string:

100011 00000 00010 0000000000000000

^^^^^^ ^^^^^ ^^^^^ ^^^^^^^^^^^^^^^^^

Instruction Base memory Destination Memory offset (added to base)

[Sent to control] location (source) register [Sent to ALU]

[Sent to register block] [Sent to register block]

You are allowed to use the LPM_ROM function to implement Instruction memory. 256 by 32

bits of instruction memory is available. This requires four of the FLEX chips EAB memory

blocks. For more information on LPM_ROM function, please refer to Appendix B. Make sure an

asynchronous read is required here.

Data memory stage:

This section contains the data memory; it is limited to 256 locations

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MIPS Data Memory Module

To speed synthesis and simulation, data memory is limited to 256 locations of 8-bit memory. You

are allowed to use LPM_RAM_DQ (or LPM_RAM_DP) function to implement Data Memory.

Memory write cycle is critical in any design. The LPM_RAM_DQ function requires that the

memory address must be stable before write enable goes high. One FLEX EAB memory block

will be used for data memory. Again, an asynchronous read is required here.

RAM / Data Memory: This unit is used as a storage unit during the operations of the processor.

This unit is used during load and store operations of the processor during the memory write-back

step. A load instruction will take a value from a designated address in the RAM and place it in a

designated register in the register block. A store operation will do the opposite; it will take a

value from a designated address in the register block and place it at a designated address in

memory.

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Laboratory:1. Develop the modules outlined above and these include:

TopLevel.VHD ( or schematic representation)

CntrlUnit.VHD

InstDecode.VHDInstExe.VHD

InstFetch.VHD

DataMemory.VHD

All the components except the CntrlUnit.VHD have to developed using structural level

of modeling in VHDL. For CntrlUnit.VHD you can choose either behaviorial or

structural modeling.

The design has to be synchronous and globally reset-able. This means that global clock

and reset signals are required in all functional blocks.

2. Simulate each part individually and make sure that they operate correctly. Use different

scenarios that you think would happen to each module in the complete design.

3. Simulate the entire MIPS processor core and make sure that the whole design operates

correctly (use the Instructions in next step).

A Sample MIPS Simulation Window

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4. Examine your development by verifying the final model should correctly execute the following

instructions:

lw $2,0 ;memory(00)=55lw $3,1 ;memory(01)=AA

add $1,$2,$3sw $1,3 ;memory(03)=FFbeq $1,$2,-4beq $1,$1,-24

5. Examine the performance of your design on the board itself using the Altera boards

pushbuttons as your clock and reset signals and the LED segments for presenting the values of

the PC and ALU_result_out. Note: you have to include a clock divider if your clock cycle is

longer than the provided clock cycle.

Report Guideline:The laboratory report is an important aspect of the experiment and should not be taken lightly. It

should be understandable by an average person with an engineering background. Basically, there

are three parts to a design implementation report. They are:

1. Background information

The report should provide a brief overview of the technical aspects and terms used in this

experiment.

2. Problem to be solved

What is it that you are trying to accomplish in this lab? Again, only a brief explanation

suffices.

3. Design path

How did you come up with your design? How does your design function? Please include

relevant flow charts and diagrams if it aids the explanation of your logic. Always try to be

concise and, at the same time, be complete. Remember, some things may be obvious to thedesigner but it would take another designer quite some time to digest it.

4. Design testing

How can you prove that your implementation has met the requirements and solved the

problem? Simulation diagrams and output files should go into this section. Simply sticking

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in a simulation diagram without any explanation will not be acceptable!

5. Final design evaluation

Now that the design is proven to solve the problem, how can it be improved or modified

later?

Report reminder:

Include timing simulations with explanation for all VHDL source files

Describe and comment all your VHDL source files

Include a flowchart representation and/or block diagram of your solution to the problem

Append all VHDL source code and graphical design files to your report

Submit a soft copy of all VHDL and graphical design files with your report

Appendix A:The MIPS (Million Instructions Per Second) is an example of a RISC (Reduced Instruction Set

Computer) developed in 1980s. It has fixed length 32-bit instructions and thirty two 32-bit

registers with register zero always containing the value 0. In MIPS a memory word is 32 bits

wide. Block diagram of single-cycle MIPS is given in the following page. There are five major

components, which process the instructions from the instruction memory. They are:

Instruction fetching

Instruction decoding

Control unit

Instruction execution

Memory write back

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The MIPS has three instruction formats and only I-format LOAD and STORE instructions

reference memory operands. R-format instructions perform operation on two registers R1 and R2

and store the result in register R3. Shift and Function fields are used as extended opcode fields.

Format 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R Opcode R1 R2 R3 Shift Function

I Opcode R1 R2 Address/immediate value

J Opcode Branch target address

For in depth description of all the MIPS instructions refer to Chapter 3 and Appendix A of your

course text book. A list of basic MIPS instructions is shown in table below:

R-format Add, Addu, Sub, Subu, And, Or, Sll, Srl, Slt, Jr

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I-format Addi, Lui, Lw, Sw, Beq, Bne,

J-format J, Jal

After instruction fetch, the instructions opcode is sent to the control unit and the function code is

sent to the ALU control unit. The instructions register address fields are used to address the two-

part register file. This two-part register file can perform two independent reads and one write in

one clock cycle (i.e. Instruction decoding).

Appendix B:Embedded Array Block (EAB):

A physically grouped set of 8 embedded cells that implement memory (RAM or ROM) or

combinatorial logic in a FLEX 10K device. An EAB consists of an embedded cell array, withdata, address, and control signal inputs and data outputs that are optionally registered. A single

EAB can implement a memory block of 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1 bits. Each

embedded cell within the EAB implements up to 256 bits of memory. For memory blocks of

these sizes, an EAB has 8, 4, 2, or 1 outputs, respectively. Multiple EABs can be combined to

create larger memory blocks. The EAB is fed by row interconnect paths and a dedicated input

bus.

Memory Initialization File (.mif):

Memory initialization file is an ASCII text file (with the extension .mif) that specifies the initial

content of a memory block (RAM or ROM).

An MIF is used as an input file for memory initialization in the Compiler and Simulator. (You

can also use a Hexadecimal File (.hex) to provide memory initialization data.) An MIF contains

the initial values for each address in the memory. A separate file is required for each memory

block. In an MIF, you are also required to specify the memory depth and width values. In

addition, you can specify the radixes used to display and interpret addresses and data values. If

multiple values are specified for the same address, only the last value is used.

After simulation, one can check the content of the RAM and see if the result is correct. In order

to view the content of a .hex/.mif file, check Simulation Report, Logical Memories section:

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Simulation Report: Logical Memories

Appendix C:Students taking this course should be familiar with VHDL. If you find yourself to be

uncomfortable with VHDL itself, a review of the material is strongly recommended since the

teaching assistants will not have the time to sit down with each group and debug their VHDL

compilation errors. It is solely the responsibility of the student to review these materials prior

coming to the laboratory sessions. The following references should provide information:

Computer Organization and Design, second edition, David A. Patterson and John L.

Hennessy, chapter 5 and appendix C

Flex 10K Datasheet: http://www.altera.com/literature/ds/dsf10k.pdf

Altera board: http://www.altera.com/literature/lit-f10.jsp

Any VHDL tutorial on Internet

Acknowledgements

This Lab manual was designed by Ehsan Alivandi Farsi and modified by Xiaoyong Sun andMiodrag Bolic.