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All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
3D Plus Space Products
72b DDR2 & DDR2 TR Modules
Pierre-Xiao WANG
2014
MEWS27, Japan
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
3D PLUS patents = Focused Technology
3-D Interconnection for Bare die
3-D Interconnection for Packaged die
3-D Interconnection at wafer level
Electrical, Thermal and Environmental behaviour
3D stacking Core Technology (1/2)
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
Today’s Space Technology - 3D PLUS PID with Approval Certificate
Rev4 (1st - 2005) Rev9 (Today - 2013) Rev10 (2015)
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
MARS SCIENCE LABORATORY – Mars Mission – NASA JPL
Key Notes Flight Heritage – Curiosity Rover Landed on Mars on August
2012, 7th
ChemCam Instrument
Camera SiP
RTIMS
Computer Module SiP
Rover Avionics
and Data Recorder
256 Mb
NOR FLASH
2 Gb SDRAM
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
A Recall of 3D PLUS ECO System around FPGA
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72b DDRII module 3D2D4G72UB3652
The space community show a big interest to use the new Xilinx
RHBD V-5 (SIRF), which has more powerful computing
capabilities, and also need more speedy memory to work with.
Moreover, The SIRF V5 has built-in ECC hardware to directly
support 72b DDR2 interface with 8-bit ECC on a 64-bit
boundary.
3D2D4G72UB3652 Key Features:
Organized as 64Mx72b
4 chips of 1Gbit + 1 chip for ECC
Jedec standard 1.8V I/0 (SSTL_18 compatible)
Guaranteed Frequency = 333 MHz
8 internal banks per die for concurrent operation
On-Die Termination
191 leaded or lead-free balls.
Available temperature range :
0°C to +70°C
-40°C to +85°C
Or Specific temperature range
Radiation Tolerance:
TID > 75 krad(Si)
SEL LET Threshold > 60MeV.cm²/mg
SEU and SEFI characterized
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
Key Benefits
The 3D2D4G72UB3478 is packaged in a 191 balls BGA with 1.27mm pitch and leaded balls option for Space application.
Using the 3D2D4G72UB3652 will bring the benefits:
-All boards components can be procured in space grade
-ITAR free to guarantee worldwide delivery
-Qualified radiation tolerant die
-Easy assembly process thanks to space grade BGA with 1.27mm pitch and leaded balls
-Better signal integrity and space saving on the board!
Board area
savings!
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
The DDR2+DDR2 TR concept
Functional diagram:
Module supply (VDD, VAUX)
Comparators (VTT, VTT sense)
Command and protection
(Enable)
Switches and filter (VTT)
The DDR2 TR is a sink/source Double Data Rate
(DDR) termination regulator specifically designed for
low input voltage, low-noise and high reliability
systems.
Provide a VTT termination voltage to reference DDR2
(3D2D4G72UB3478: 4 chips of 1Gb + 1 chip for ECC)
3D PLUS module.
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
Source and Sink Current capability up to ±1A
Tight regulation of VTT to REF_IN (ripple ±40mV) – within DDR2 operating frequency limits
Reference voltage can be set externally (REF_IN) and buffered inside the module (REF_OUT)
Standby mode for low-power consumption (Enable)
Thermal protection (in case of internal over temperature or short circuit)
No external input/output filters needed
Compliant with JEDEC standard (JESD8-15A)
Main Features
Radiation Hardened by design:
Total Dose : >50Krad(Si)
SEL,SET Threshold >
80MeV.cm²/mg
Temperature Range -40°C / +105°C
Package SOP24, Size 20x20x14mm
ITAR Free
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
Key Benefits
First space grade Termination Regulator
Designed to work with DDR2 module
Compliant with JEDEC standard (JESD8-15A)
Simplified and optimized design for High-Reliability systems
All-in-one component
Thermally-efficient package
High performances
Tight regulated VTT – ripple (±40mV)
Suspend-to-RAM mode
Thermal protection
Suitable for any Space application:
ESA qualified stacking Technology for Space Applications
Radiation Hardened by designTotal Dose : >50Krad(Si)
SEL,SET Threshold > 80MeV.cm²/mg
Worldwide Delivery Guarantee:
Made in France – ITAR Free
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
Conclusion
As the first Space grade wide bus DDR2 & DDR2 Termination Regulator provider,
3D PLUS already starts to deliver this solution world wide thanks to its 4 key
advantages:
- Completed space grade solution for high performance space data processing
- 75% board area saving thanks to ESA qualified stacking technology
- Radiation tolerance to meet most missions’ requirement
- Worldwide delivery Guarantee – ITAR FREE
All Rights Reserved © 3D PLUS 2012 Only For Internal Presentation
www.3d-plus.com
Thanks for your attention
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