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3D TSV Test: Myths, Challenges, and Solutions
Dr. Erik VolkerinkCTO
Verigy
Outline• Introduction• Problems and Solutions Framework• Solution Directions• Economic Model• Test Challenges & Solutions• Conclusions
3D TSV: Its Happening beyond MEMS & Sensors!
Various Wide I/O Announcements
Xilinx use of 3D silicon interposers28nm FPGAs in Virtex 7
3D TSV Test Challenges, Solutions and Myths
How about Test?Level 1 - Initial (Chaotic)
The starting point for use of a new or undocumented repeat
test process.
Level 2 - Repeatable
The process is at least documented sufficiently such that
repeating the same steps may be attempted.
Level 3 - Defined
The process is defined/confirmed as a standard business
process.
Level 4 - Managed
The process is quantitatively managed in accordance with
agreed-upon metrics.
Level 5 - Optimizing
Process management includes deliberate process
optimization/improvement.
?
?
?
?
?
15%
70%
15%
0%
0%From: ATE Vision2020 Event
From Hype to Productivity
Gartner Hype Cycle
TIME
WideningScope
Narrowing Scope
DeepeningUnderstanding
2009-2011
Capabilities Cost Optimization Standards
Sol
utio
n C
once
pts
3D TSV Test Research Life Cycle
• KG-TSV• KG-CORE• KG-DIE• KG-STACK• KG-PRODUCT
MythsSolutions
3D TSV Problem & Solution Framework: Research Prioritization
NewUnique 3D
Test Problems(“New problems only due to 3D”)
ProblemsDue to
Accelerationof Heterogeneous
Integration Roadmap(“Foreseen problems”)
Existing Solutions(“Solutions can be leveraged to
address new problem”)
New Solutions(“Solutions being developed
for new problems”)
• Partial stack test• Stack sockets• Wafer partial stack• 3d software (concurrent test, adaptive test, yield, material flow)
• Inspection • …
• Concurrent Test• Protocol Aware• Heterogeneous StackTest
• …
• Test point insertion• DFx• BISx• …
• BIST / Compression• Direct probing• Accuracy• Signal Integrity• Parametric Test• Yield Learning• …
Pro
blem
s
Solutions
Identify & Accelerate Leverage
Identify & Leverage 3D TSV Test Research
Identify & Research
3D TSV Test Solution Menu
No Die Traceability Thermal Monitor & StressDFY
No Test Pads BISx Access Standards DFT / BIST
Normal pA & small capMeasurement technology
Normal Direct ProbeCommunication path
No Normal 3D OptimizedConcurrent Test
No TSV CubeRedundancy
All TSV double-sided All uBumps Select Test padsProbecard resolution
KGD PGD TraditionalWafer Quality
High-end Medium Low endPost-bond ATE
Stack Sampling Stack Interposer Pre-bond Inspection Test Insertions
Inspection Capacitance ContactProbing mechanisms
Simulation Sampling & AdaptiveTest generation
No Access DFT Wafer carrier Sockets Post-bond (partial stack)
Options *Topic
* This doesn’t imply all options are developed. Some require more research.
More Traditional Example Flow • Design for test and yield
– Test infrastructure (1149, 1500, etc)– Define and build test points/port: EDA, strong driver, etc– Define and build RA as required– Define and design temperature monitoring/control as required
• Test to Pretty-Good Die/KGD level– Find “sweet-spot” based on an economic analysis – Use traditional probe card technology and dedicated test port
• Build stack– Test incomplete stack at critical step(s) during building if needed
• Final stack test in traditional ATE– RA helps improve yield
Die 1
Die 2
Die 5
Die 6
Die 7
1. Pre-bond Die Test 2. Post-bond test
Die 4
3. Post-bond test
(Before Package)
4. Post-bond test
(Final Test)
Die 7
Die 6Die 5Die 4
Die 7
Die 6Die 5Die 4
Die 1Die 2Die 3
Die 7
Die 6Die 5Die 4
Die 1Die 2Die 3
Die 3Die 3
Test Cell
Building capital
People
Test Equipment
DUT Interface
Handling Tools
Factory Automation
Test Cell/tester utilization
Spares/support
Power consumption
Etc.
NRE
DFT design and validation
Test development
Untested
Units
Pre-bond Die Test
Test Cell
Building capital
People
Test Equipment
DUT Interface
Handling Tools
Factory Automation
Test Cell/tester utilization
Spares/support
Power consumption
Etc.
NRE
DFT design and validation
Test development
Final Stack Test
Good Units +
Escapes (PPM)
Good Units +
Escapes (PPM)
3D TSV Test Economic Model
Co
st
of
Reje
ct
Sta
ck
s
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Homogenous Memory StackResults
KGD
Number of Dies
NormalTest
100%
90%
2 4 6 8 10
% W
afer
Tes
t
Optimum % Wafer Test as function of Number of Dies
PGD Line • Assume no cube redundancy• Assume no partial stack test• Assume no TSV redundancy• Assume homogenous stack
(die cost, quality and type)
More discussion on this topic in cost of test sectionof ITRS roadmap
Unn
eces
sary
$$ A
TE
Does not imply partial stacktest is never required
% Wafer Test
Ove
rall
Cos
t (N
orm
aliz
ed to
KG
D)
2.5x
2x
1.5x
1x
.5x
Homogenous Memory StackResults (cont)
100% 95% 90%Normal TestsPGDKGD
“Wafer Test Cost
Exceeds Benefits
of Yieldloss
Reduction”
“ Cost of Y
ieldloss
Exceeds Cost of
more Wafer T
es” t
3D TSV Test Economic Model
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Partial Stack Test Optimization
Number of Tests / Insertion
Num
ber
of T
est I
nser
tions
$10$5
$4
$3
$2
InitialApproach
• Not all failure modes predictable
• Test coverage changesover yield learning curve
• Characterization different than HVM
• Potentially automatedusing statistical analysis
Equal Test Cost lines for different test insertions andnumber of tests per insertions
HVMApproach
• Optimized tests per insertion• Optimized insertions points• Minimum overall costs
DFx for 3D TSV• Process control monitors• Vias and serpentine wires near TSVs• Thermal aware design and test to avoid
thermal problems and hot spots• Temperature sensors• Monitor other stress• Intra-die variability's • Multiple-clock domains• Subsystem isolation• Standards
- DDR 4 3D support (JC-42)-MCP (JC-63)
- Low Power (JC-42.6) wide I/O- P1838- Pad locations?
Smart ReportsVisualizationTransforms
Smart DataCollection
Analysis Prioritization & Root Cause
Yield Issue!
Advanced Diagnostics Software
• Advantages for 3D TSV Technology– Rapid Yield Learning– Topological Information
• Die tracability
3D TSV Test Economic Model
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
BISx: Built-In-Self-Everything
Samsung
Analog Devices
Built-in-self-testBuilt-in-self-repairBuilt-in-self-stressBuilt-in-self-diagnostics
RF, Analog, High-speed IO, and DRAM BIST
The RF BIST is arranged in a loop-back configuration, where the base-band (BB) processor serves both as a
stimulus generator and response analyzer
Jerzy Dąbrowski, Linköping University
Ken Ferguson et.al., PMC-Sierra, Inc., Built in Self Test (BIST) for High-speed Serial Transceivers, 07756197 Cl. 375-224.
High-speed Transceiver Test
Analog Devices
MosaidSamsung
TSMC
DFT for 3D TSV
Testing TSV-Based Three-Dimensional Stacked ICs, Erik Jan Marinissen, IMEC, DATE 2010, and P1838 "3D IC Test Standard"
3D TSV Test Economic Model
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Challenge: Sensitive Instruments with High Parallelism
• Testing for pinholes in the TSV oxide, cracked TSV liner, interposers – Pico-Amperes with high parallelism – Very accurate capacity measurements with high parellism
• This requires a breakthrough in measurement electronics. – Bench top Femto-Amp solutions lack the parallelism and
sophisticated digital test capabilities.– ATE that provides per-pin parametric capabilities often shares the
measurement engine and is not truly parallel and the DC measurement engines that are built into the digital cards are not accurate enough.
Solution: picoAmpere Meter• Example measurement solution suitable for 3D TSV test
and characterization–see ITC 2011 Paper for more details
Example Protocol Aware Test for 3D• Assume one die in a 3D circuit-stack contains the
processing unit and the memory is located in different die.
• How do you test the processor unit alone, in mission mode?
• Protocol aware helps overcome this problem and allows system like test eventhough the system is not yet complete
Processor
Memory
TSV
Processor
ATE
Memory Emulator
Signal Integrity Challenge: Direct Probe• Providing high performance test at
wafer level• Moved probes to rectangular load
board eliminating pogo tower• Eliminates 2 of the 4 transitions and
provides a shorter signal path– Fewer signal reflections– More reproducible impedance
• More component area for multi-site
Pogo Tower Wafer Probe Interface (WPI)
Signal Path
TransitionTransition
Direct-ProbeTM
Improved
Transition
Transition
Signal Path
Transition
Transition
Signal Path Signal Path
10 Gbps Performance ComparisonDirect Probe17” Pogo Tower
Software: 3D Everything
• 3D Bitmaps• 3D Redundancy Analysis• 3D Shmoo plots• 3D Silicon Debug• 3D Adaptive Test• 3D Yield learning• 3D Margins• 3D TBD
From Low cost TSV process using electroless Ni plating for 3D StackedDRAM, Electronic Components and Technology Conference 2010 IEEE
Redundant rows, columns, and pillars
EDA Challenges and Solutions and Integration with Test strategies
Method and Apparatus for performing RLC Modeling and Extraction for 3DIC Designs, Qiushi Chen, et.al.Synopsys, US 2010/0199236 A1, August 5, 2010
3D TSV Test Economic Model
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Challenge: TSV Yield ImprovementDie Yield as function of TSV Yield for various number of Die Yield as function of TSV Yield for various number of Die Yield as function of TSV Yield for various number of Die Yield as function of TSV Yield for various number of TSVsTSVsTSVsTSVs
Required TSV Yield for Die Required TSV Yield for Die Required TSV Yield for Die Required TSV Yield for Die Yield TargetYield TargetYield TargetYield Target
KnownGoodTSV?No!
Solution: TSV Redundancy Analysis• EDA tools embed
redundant TSVs• Defective TSVs are
replaced by redundant TSVs
• Algorithms required to optimize repair
• Algorithms executed by ATE
• Open ATE redundancy repair platform required
Ang-Chih Hsieh; et.al “TSV redundancy: Architecture and design issues in 3D IC”, Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010
Redundancy in Cube Testing
Consequences on KGD requirements similaras redundant TSVs on know-good TSV requirements?
Example Distributed Test Architecture for stack test
TSV SpeedScan•Pinched or unfilled TSV can cause latent defects (e.g., electro migration)
•Detection during production test required•Punched or unfilled TSVs impacted by temperature – Size changes causes impendence changes
•Detection through measuring small impendence changes (e.g., frequency measurement)– Use parametric test equipment or use a
new TSV SpeedScan technique
• Identify TSVs between flip-flops that show a shift in the passing frequency at high temperature
•Needs more experiments
Assume, that the expected frequency delta is about -20MHzFor six patterns the highest passing frequency are shown in Table 2Then pattern 1 and pattern 2 represent outliers
TSV RoomTemperature
TSV HighTemperature
Void
New concurrent test opportunities & challenges
Res. ADie 1
Partial Stack 1
Die 2
Die 1
Partial Stack 2
Die 2
Cross-talkwith die 1 res B
Res. A
Res. A
Res. A
Res. B
Res. B
Res. C
Res. C
Resource A is shared Across partial stack 1 and partial stack 2
Resource B is shared across die B1 and die B2 but not across partialstacks
Cross-talk increasesLevel of constraints to concurrent test program
3D TSV Test Economic Model
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Solutions: Micro bump TSV Inspection / Test
• Inspection techniques– 2D/3D macro inspection– Front/back/edge inspection– Laser measurement of
bump co planarity
•Planarity modeling through capacitance and resistance measurements– Monitor TSV parametrics
and compare to model
IBM
Summary
StackPost-bond
Test
Pre-bondTest
Die 1
StackPost-bond
Test
Pre-bondTest
Die 2
StackPost-bond
Test
Pre-bondTest
Die n
AssemblyPackaging
FinalTest
…
DFX DFX DFX
Potential Dynamic Test Strategy Optimization
Conclusions• Moving from creating capabilities to cost
optimization – Different chips require different portfolios of
techniques– Not everything known during test
development time– Economic modeling to identify best
approaches
• Various techniques offer significant value to 3D TSV test – Direct Probe, picoAmp meter
