3D Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin MEMS Accelerometer Packages Lutz Hofmann Fraunhofer ENAS (Germany)

3D Wafer Level Packaging By Using Cu-Through Silicon Vias For

Thin MEMS Accelerometer Packages

Lutz Hofmann

Fraunhofer ENAS (Germany)

Motivation and Objective

Selection of TSV approaches

Via Last approach: TSV in MEMS-wafer

TSV fabrication

Demonstrator

Via Last approach: TSV in cap-wafer

Technology

Investigation of silicon direct bonding

Conclusion

OUTLINE

Conventional MEMS modules

Lateral or vertical integration

Based on wire bonds

Integration based on MEMS with TSVs No wire bonds / bond pad cavities

Small size (foot print and height)

Short signal paths

Direct mechanical contact

(nearly) full chip area

Improved functionality

Driver for Smart Systems (Mobile devices,

medical devices, …)

Motivation

CMOS

MEMS

MEMS

CMOS

MEMS

CMOS

TSV in one device

TSV in both

CMOS

Wire BondsMEMS

TSV

Wearable devices, smart cards, … limited package height

Increased functionality: electronics, MEMS, radio, power,... e.g. MEMS accelerometers ( motion detection )

Integration concept : 2.5D integration (Si - interposer)

MEMS height < 400 µm thin 3D-WLP: TSVs, flip chip contact

Objective - Thin Package Applications

ElectronicsMEMS

Wiring layerCarrier/ Interposer

Thin package (~0.8 mm)

~350…400 µm

Example: Smart Card




TSV fabrication

Demonstrator


Technology


Conclusion

OUTLINE

AR ... Aspect ratio

General TSV Technology Approaches

+ No temp. limit. for TSV process

- Restricted to (Poly)-Si; complete filling

- (very) high aspect ratiosTSV MEMS + Cap Thinning &

Back end

TSV & Back end processesMEMS + Cap

(a: in MEMS) (b: in cap)

TSV in capMEMS Bonding & Back end

+ Nearly independent from device-history

+ (b) Lower AR (for direct bond interface)

+ Use metals (Cu) for TSVs

- Restricted to T < 400…450ºC

+ Decoupled from device

+ No limitations (temp.)

- Bonding: electrical + mech. contact

- Bond must withstand further processes

Via First

Via Last

Via Middle

Via Last Approaches

TSV in MEMS wafer

+ Independent from WLB technique (for glass frit, etc.)

+ Flexible, nearly any device

- Ends up with HAR TSVs

- Limits of glass frit (sealing, contamination)

TSV in Cap wafer

+ Direct interface: hermetic seal

+ Thinner caps possible

+ Decoupling from MEMS device (TSV isolation)

- Direct bonding required

WLB ... Wafer level bonding




TSV fabrication

Demonstrator


Technology


Conclusion

OUTLINE

e) Spacer etching f) ECD: RDL, UBM d) TSV isolation

a) Wafer bonding b) Deep Si-etching c) BOX etching

g) Seed/barrier strip h) Passivation i) Bump formation

Via Last – Technology Flow

RDL ... Redistribution layer

BOX ... Buried oxide

UBM ... Under bump metallisation

ECD ... Electrochemical deposition

DRIE ... Deep reactive ion etching

TSV Etching Processes

TSV formation by deep Si etching

Using DRIE (BOSCH process)

Aspect ratio: 5:1 (50 µm diameter / 250 µm depth)

Stop at buried oxide

Notching effect due to over-etching(account for non uniformity)

Optimisation (partial LF-bias) reduced effect

50 µm

51 µm

250 µm

Glass frit:9…10 µm

715 nm

~5 µm

~13-23 µm

TSV profile after optimisation

Severe notching

Reducednotching

ICP ... Inductively coupled plasma


BOX etching

Contact opening at TSV bottom

Dielectric at TSV bottom: 500 nm SiO/SiN

Anisotropic RIE process

Low pressure, ICP source

Al: ~450 nm

SiO / SiN (250/250 nm)

Al: ~350 nm

(Center of TSV)

(Edge of TSV)

RIE process for BOX etching

SACVD ... Sub atmospheric chemical vapour deposition

790 nm

402 nm

335 nm

(99%)

(50%)

(42%)

TSV Isolation

SiO2 via SACVD-TEOS process

Good step coverage

Good adhesion, compatibility

Poor dielectric properties

Parylene F

Good dielectric properties

Good step coverage

Deposition @ room temp.

Post process limited

Still under investigation

SA-TEOS / O3

t=270 µm

850 nm( ~85 %)

t=230 µm

450 nm( ~45 %)

depth: 270 / 230 µm : 50 µm

Nominal values(target thickness): TEOS: 800 nmParylene: 1000 nm

Parylene F


“Spacer”-etching

Re-opening of contact (Al) at TSV bottom

Protection of sidewall/surface through non-conformal PECVD SiO2

RIE process with low pressure,and ICP

BOX: ~1000 nm

SiO2 (SATEOS): ~260 nm

Removed SiO2

SOI- wafer as test vehicle

Protection of TSV entrance

PE-SiO2

SATEOS-SiO2

TSV Metallisation – Deposition

MOCVD TixNy/ Cu:

Cu - seed layer

TiN - Barrier- / adhesion layer

Very high aspect ratios (up to 20:1)

Independent from TSV shape:

Coverage of negative slopes/undercuts

Electrochemical Deposition (ECD)

Enhancing seed layer to 5…10 µm

Conformal deposition Reduction of

stress (CTE: Cu - Si)

process complexity (Process time/ Additive control)

(Smearing from sample preparation)

TSV: 50x420 µm; 5 µm Cu

Conformal deposition even on undercut

Undercut (TSV-etching)

1 µm

MOCVD ... Metal organic CVD

Open TSVs challenge for following processes (patterning, CMP)

Residues, particles inside the TSV

Approach: Pattern plating

TSV and RDL in one step

No subsequent patterning or CMP

Principle layout for Pattern Plating

Si waferTSVSeed-Layer

Resist

RDL

TSV Metallisation – Pattern Plating

RDL ... redistribution layerCMP ... chemical mechanical polishing

Open TSVs: 80 x 400 µm;Cu ECD by pattern plating

Dry film resist

Easy coverage of cavities

Fast/easy lamination, development

Lower resolution (~30 µm) !!!

Extra equipment required

Spin on process

Standard litho tools

Negative resist (no exposure in TSVs)

High viscosity “tenting” of TSVs

Small process window (soft bake) residues can occur in TSV

SEM image before ECD

Residues of resist in TSVs

Seed layer

Spin on resist - mask

TSV10 µm

TSV

residues

Resist pattern

100 µm

TSV Metallisation – Plating Mask

Under Bump Metallisation

Layers: Cu / Ni / Au – 3-5 µm / 3 µm / 100-500 nm

Deposition via pattern plating (same mask as Cu RDL)

Critical: selective removal of seed and barrier

High undercut for standard Cu-etchant (up to 10 µm)

Adjusted etchant reduces this effect ( <2 µm)

As deposited Standard seed etchant large undercut

After TiN etching No additional effect

Adjusted seed etchant / same TiN etchant

2 µm

Cu

Ni

Au

2 µm

Solder Bumps

Deposition via pattern plating (nominal: 40 µm)

Using standard SnAg alloy bath (~3% Ag)

Reflow at 225ºC, 30” formation of ball structure

2 µm2 µm20 µm 20 µm

As deposited After reflow (225ºC)

Au-Sn phase

SnAg

2-axis MEMS accelerometer based on AIM technology

Using existing device not adapted to TSVs

TSVs placed at bonding pad area

Principle of AIM Layout

Air gap

Metal bridge

Moveable element (mass)

Spring

Glass frit

TSV

Demonstrator – MEMS Layout

AIM ... Air gap insulated microstructures

MEMS250 µm

TSV: 50 µm

Cap 400 µm

Actual Bond pad

Cross section

Sample prep.: cross sectional polishing (resin embedding)

Curvature at TSV-bottom due to porous glass frit layer

Spacer etch: TSV area not completely exposed ( SiO2 residues)

SEM image after cross sectional polishing

200 µm

MEMS

Cap

TSV

RDL

Glass frit (some pores)

5 µm

Cu

50 µm

Al

Glass frit

Liner SiO2

SiO2 residues

Enlarged single TSV

Demonstrator – Fabricated MEMS With TSVs

Thinning cap to 80/82 µm (edge/center)

Non uniformity due non optimised stress release etch (RIE)

Final thickness: 346 µm (without RDL, bumps)

No defects/cracks detectable in cap/MEMS wafer

Cap: 400 µm

Thinning

Demonstrator – MEMS After Thinning

Cap: 80 µm

200 µm 2 µm20 µm

Device after thinning/dicing

Measured before and after thinning / dicing of MEMS

Electrostatic excitation (sinus, Vpp=2 V)

Response curve: output current vs. excitation

No obvious deviation in both curves

Proof of functionality after final harsh processes

Demonstrator – Functional Test

15 150 15000.0

0.2

0.4

0.6

0.8

1.0 before thin-ning

Excitation frequency [Hz]

No

rmal

ized

ou

tpu

t cu

rren

t




TSV fabrication

Demonstrator


Technology


Conclusion

OUTLINE

Via Last Approach: TSV in Cap wafer

Challenges

Silicon direct bonding required: low roughness (<1 nm)

Not achievable by deposition of bonding SiO2 (e.g. PECVD)

Post treatment of MEMS not possible (CMP, wet cleaning, …)

This approach:

Pre-preparation of bonding surface

Protection of surface duringMEMS fabrication

b) Planarisation (CMP) c) protective cover film (PCF)

e) Selective PCF removal

g) Wafer level bondingh) Wafer thinning, TSV fabrication, contact metallisation

d) HARMS fabrication

a) Thick PECVD SiO2

f) Plasma pre-treatment

Technology For Direct Bonding And Cap TSV

A

B

C

B

A

Base wafer: 525 µm

Cap: 175 µm

Frame

Direct Bonding – Test Vehicle

SiO2 bonding frames defined by cavity etching

Frame widths:

A: 250 µmB: 450 µmC: 650 µm

Chip size: 3x3 mm

Wafer Layout (150 mm)Cross section after WLB and thinning

Direct Bonding – Pre Treatments

All cap wafers: wet (SC1) + plasma (O2/N2)

Reference wafers:

Wet cavity etching before CMP; no protective cover film

Reference 1: wet (SC1) + plasma (O2/N2)

Reference 2: plasma (O2/N2)

MEMS-Dummy:

protective cover film used during cavity etching by RIE

Pre treatment: plasma (O2/N2)

SC1 ... standard clean 1

Patterning of protective cover film (PCF)

Direct Bonding – Cavity patterning

Critical issues:

Defects in protective cover

Particles, e.g. resist residues

Transfer of defect to bonding surface

Cavities etched; PCF removed

Particles

Defects

Defects

Final bond surface

Protective cover film

Cavity area

Cavity etched

Dry Reference MEMS-DummyWet Reference

Direct Bonding – Bonding Process

Hand alignment, no defined pressure

Inspection by IR transmission imaging

Newton’s rings and darker areas no bond contact

Failure at reference: most likely dishing from CMP

Point failures: particles, local damage of bonding surface

Direct Bonding – Annealing

Furnace annealing: 400ºC, 5h, N2

No major change in bonding quality


Direct Bonding – Thinning


Grinding: Edge trimming (~8 mm)

Coarse / fine grinding: 400/100 µm

No degradation visible

Direct Bonding – Dicing


Dicing: chip raster 3x3 mm²

Falling apart of chips with bonding defects

Major part unaffected indirect proof of bonding strength

Defective chips

250 450 650 blanket0

20406080

100120140160180

wet-RefPCF

Frame width [µm]S

hea

r st

ren

gth

[N

/mm

²]

Direct Bonding – Shear Test

Reference: blanket chips without frames (i.e. 9 mm² area)

No distinct dependency visible

Differences most likely due to deviation in frame width (miscalculation of shear strength)

Mainly cohesive failure (i.e. Si fracture)

Overall: good bonding strength

Proof of principle feasibility for “protective cover film” - approach

Conclusion

Two Via Last approaches for MEMS TSVs

TSV-fabrication demonstrated for MEMS-wafer-TSVs

Functional device fabricated with 350 µm final thickness (w/o bumps)

Approach based on glass frit: limited in hermiticity, final thickness

Approach using cap wafer TSVs: based on silicon direct bonding

Method: pre-preparation and protection of bonding surface

Test vehicles fabricated with good bonding quality

Optimization required: defect free patterning of protection film

Further investigations on real MEMS with TSVs are ongoing

Thank you for your attention!

Documents

3D Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin MEMS Accelerometer Packages Lutz Hofmann Fraunhofer ENAS (Germany)