3DIC & 2.5D Interposer markettrends and …server.semiconchina.org/downloadFile/1365732442704.pdfWafer Level Packaging « Middle -end » Silicon Manufacturing « Front-end » Package

© 2013

Copyrights © Yole Developpement SA. All rights reserved.

3DIC & 2.5D Interposer market trends and technological evolutions

Pascal Viaud, CTOInfineon

Micron

SynopsysVTI

CEA LETI

Xilinx

© 2013 • 2Copyrights © Yole Developpement SA. All rights reserved.

Outline

• Introduction

• Global 3D TSV market forecast

• Infrastructure & Supply Chain

• Market & Applications

• Conclusions and perspectives

© 2013


Introduction


Fields of research activity• Yole Développement is a market , technology and strategy consulting

company, founded in 1998. We are involved in the following areas:

MEMS &Imaging sensors

Photovoltaic

Advanced Packaging

Microfluidic& Med Tech

Power Electronics

HB LED, LED &OLED

Wafers & SubstratesCompound Semi


Moore is less… Transition to 3D

Cost ?

Performance ?

Size ?

Despite “no more Moore” the quest remains

The rapid evolution of 3D thinking in the IC community is astonishing– Two years ago, the big question was “Why 3D?”– One year ago, the questions were “When 3D?” and “How 3D?”– In less than a decade from now, we will wonder “Why 2D?”

Which will determine “when” and “how” 3D happens


3DTSV: 3 platformsAdvanced Packaging Platforms

RDL

BumpingBalling

Wafer Bonding

TSV

WL-Optics

WL-Capping

2.5D Interposer3DIC

Balling

WLCSP FOWLP

Embedded IC

Flip Chip

MEMS IC

CappingIC

Sensor

MemoryLogic

3DWLCSP

Die 1 Die 2 Die 3 Die 4

Middle-End Process Steps


2012 Global Middle-end installed capacities

WLCSP2,029,203

11%

FO-WLP420,067

2%3D WLCSP539,867

3%

2.5D Interposers96,604

1%3DIC

234,9161%

WLOptics92,043

1%

FC Solder + Cu (C4NP included)10,246,277

57%

FC Au (Stud + Plated)4,234,900

24%

2012 Global "Mid-end" installed capacitiesBreakdown by advanced packaging platform (12''eq. wspy)

• In 2012, total installed capacity in the middle-end area for advanced packagingplatform was ~ 18 million (12’’eq wafers)

Yole Developpement © February 2013

© 2013


Global 3D TSV Market Forecast


-

2,000,000

4,000,000

6,000,000

8,000,000

10,000,000

2010 2011 2012 2013 2014 2015 2016 2017

Waf

er c

ount

(12’

’eq.

)

Global 3D TSV Chip Wafer Forecast (All 3D Platforms)Breakdown by Segment (12''eq wafers)

3D Stacked NAND Flash

3D Wide IO Memory

Logic 3D SiP / SoC

3D Stacked DRAM

MEMS / Sensors

LED

RF, Power, Analog &Mixed signal

Imaging &Optoelectronics

Yole Developpement © July 2012

Global 3D TSV Chip Wafer ForecastBreakdown by segment (12’’eq. Wafers)

© 2013 • 10Copyrights © Yole Développement SA. All rights reserved.

0

20

40

60

80

100

120

140

Reve

nues

(M$)

2011 global 3D TSV revenues*- Including internal production lines -

Breakdown by top players (M$)

3DIC

2.5D Interposer

3D WLCSP

*Other Nemotek, Q-Tech, ITRI, Toyota, Honda Research Institute, Sematech, UMC, Toshiba, TI

2011 Global 3D TSV RevenuesBreakdown by top players

• As of 2011, the top three players for 3D TSV revenues were involved in 3D WLCSP activity. However, this picture will change soon as important revenues are generated over the next few years with 3DIC and 2.5D Interposer products

* Middle-end activity revenues including TSV etching, Filling, RDL, Bumping,

wafer test & wafer level assembly

2011 total 3D TSV activityrevenues ~ $344 Million


3D WLCSP: the most mature 3D TSV platform

• Market size: ~ $270M in 2011 for the “middle-end” processing factories serving this specificmarket (mainly for small-size optoelectronic chip like CMOS image sensors - CIS).

• More than 90% of the revenuescome from low-end CISmanufacturing (up to 2MPx).

• 3D WLCSP Services mainlyprovided on 200mm WLP.

• Important investments are stillexpected to move to 300mm(necessary for >8MPx resolutionand “3D BSI” architecture)

Xintec$130.0M

48%

China WLCSP$66.0M

24%

Toshiba$26.7M

10%

JCET/JCAP$21.6M

8%

Samsung$18.2M

7%

STMicroelectronics$2.3M

1% Others*$5.3M

2%

2011 3D WLCSP platform Middle-End revenues*Including internal production lines

Breakdown by top players (M$)

Yole Developpement© July 2012

* Middle End activity revenues including TSV

etching, Filling, RDL, Bumping, wafer test & wafer level assembly

Total = $272M

*Others = Oki, G-MEMS, Nemotek, Q-Tech


2.5D interposer 2010-2017 wafer forecastsbreakdown by component/IC type

-

500,000

1,000,000

1,500,000

2,000,000

2,500,000

3,000,000

2010 2011 2012 2013 2014 2015 2016 2017APE/BB (Smartphone) - - - - - - - 59,641CIS & Camera Module - - - - - - 19,585 41,889CPU - - - - 34,184 62,089 98,244 146,623APE (Tablet) - - - 17,274 59,865 117,049 202,125 308,461GPU - - - 54,435 171,382 284,538 464,144 662,037Other Logic (ASIC, FPGA, ASSP …) - - 9,734 89,273 223,832 438,331 670,290 970,722MEMS (3D Capping) - 1,241 1,899 8,048 31,411 59,825 92,521 127,943High Power LED (3D Silicon Substrate) 4,395 8,759 18,890 45,188 91,101 159,569 232,887 237,715RF Devices (Filtering, IPD etc.) 10,952 13,863 18,869 26,534 35,753 46,422 58,540 77,706

Waf

er co

unt (

12''e

q. w

afer

s)2.5D Interposer platform wafer forecast

breakdown by IC type (12''eq.wafers)


TOTAL (12''eq. Wafers) 15 347 23 863 49 392 240 753 647 527 1 167 823 1 838 337 2 632 736

• 2.5D Interposer with system partitioning applications are expected to be thebiggest driver for the volume adoption of 3DTSV technology in the next fiveyears

• The motivations to adopt the “partitioning approach” using 2.5D Interposersare:

– Better electrical performance– Better yield– Reduced cost


The Future 3DIC Market is Driven by Stacked Memories & Logic SOC Applications

– 3D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for thevolume adoption of 3DIC technology followed by CMOS image sensors, power devices and MEMS

DRAM$363 M

22%

Wide IO Memory$325 M

19%

Logic SoC (APE, BB/APE)$404 M

24%

NAND Flash Memory$66 M

4%

CIS$63 M

4%

Low-End ASIC$110 M

7%

Power Devices (IGBT, PA, PMU)

$172 M10%

Other Logic (ASIC, FPGA, ASSP …)$76 M

5%

MEMS/Sensor$87 M

5%

3DIC Platform Middle-End Revenues by 2017 (M. US$)Breakdown by IC type

* Middle-end activity revenues including TSV,

Filling, RDL, Bumping, wafer test & wafer level

assembly


Total = $1.7B

© 2012

Copyrights © Yole Développement SA. All rights reserved.

Infrastructure andSupply Chain


Traditional IC Packaging Supply Chain*

System / Product

Sub-Module /Sub-systems

Design & Assembly

Design of chip & package

Wafer Level Packaging

« Middle -end »

SiliconManufacturing« Front-end »

Package Assembly & Final test« Back-end »

Front-end relatedmaterials suppliers

OEMs(Original

Equipment Makers)

FE relatedequipment suppliers

BE Packaging materials suppliers

BE Packaging equipment suppliers

Fab-lessIC players

IDMs (Integrated Device Manufacturers)

Wafer foundries

OSATs

housesWafer Bumping

houses

BE assembly & Test houses

PWB suppliers(motherboard)

ODM / EMS / DMS(electronic design &

manufacturing services)

SiP module houses

Passive comp. & SMT materials

SMT equipment suppliers

SiP design houses

Test houses

Package substratelaminate suppliers

Substrate material suppliers(FR4, BT resin, Cu clad, etc…)

* Main business models represented in red

WLP houses (no need for traditional substrate)


Transforming IC Packaging Supply Chain*

System / Product


Design & Assembly



« Middle -end »




OEMs(Original

Equipment Makers)




Fab-lessIC players

IDMs (Integrated Device Manufacturers)IDMs (Integrated Device Manufacturers)

Integrated wafer / package manufacturing foundries

OSATs







SiP design houses



* Existing business models represented in red, new business models in orange

Wafer foundries

Fab-light players Fab-light players (foundry services + focused internal investment in manufacturing & critical IP)

Wafer Bumping houses PCB / PWB houses with Embedded die capability


Transforming IC Packaging Supply Chain*

System / Product


Design & Assembly



« Middle -end »




OEMs(Original

Equipment Makers)




Fab-lessIC players

IDMs (Integrated Device Manufacturers)IDMs (Integrated Device Manufacturers)

Integrated wafer / package manufacturing foundries

OSATs (Open Source Assembly & Test houses)







SiP design houses



* Existing business models represented in red, new business models in orange

Wafer foundries

Fab-light players Fab-light players (outsourcing + focused investment in manufacturing & critical IP)

Wafer Bumping houses PCB / PWB houses with Embedded die capability

© 2013


3D TSVMarket & Applications


What are the Markets for 3D integrated ICs?

• 3D integrated ICs will be introduced in a variety of applications, all with their own specifications, challenges and individual roadmaps!

High Volumes

Lower Volumes

3DIC opportunities

High-end MultimediaSmart-phones / PMP

High-densitySolid State

Storage & µ-CardsNotebooks / MID

‘connectivity’ devices

Gaming / Graphic application engines

High-performance computers / Network & Storage components / Green Data servers

High-performance Digital Video

Wireless Connectivity /

Network Center

AutomotiveMedical


Opportunities for 3D TSV in Mobile Phones

in orange: these devices can be currently found with 3D TSV

in yellow, parts which can be found in 3DIC’s future

Discrete passives in grey, parts that won’t be found in 3DIC for the next 10 years


PA

CappingIPD Sapphire or

Silicon 3D IPD MOSFET

IGBT & Power MOSFET Power GaN

2012 2014 2016 2018

CISDSPSOC CIS

BSI CISDSP + mem

DSPmem

CIS

SOC CIS

2010 2011 2013 2015 2017 2019

3D WLCSP

FSI

BSI

< 2009 2009

MEMS

ASICMEMS

Capping

MEMSASIC

Analog/RF

MEMSLogicMEMS

Capping

FBAR

Capping

DDR3 stackHybrid Memory Cube

NAND Flash stackWide IO stack

LEDDriver

LED

Driver

LED LEDLED LEDLED IPD

FPGA FPGA FPGA FPGA

AnalogDigitalRF Mem.Analog

DigitalASICMEMS

Analog

Digital

RFMem.

Wide IOFPGA

Wide IOAPE

Wide IOAPE

CPU

DDR3 stack

GPUDDR3

LogicLogic

Logic 3D SiP/SoC

Global 3DTSV roadmap

MEMS & Sensors

Imaging & Opto

Power, Analog & RF

Stacked Memories

HB-LED modules

3D SoC

3D SiP Ultimate Heterogeneous

3DIC

SOC CIS

SOC CIS


2012 hottest topic: 2.5D « System-Partitioning » Interposers

• « System-partitioning » Interposers enable the integration of at least one logic IC with one or several memory Ics, and possible even mixed signal or analog ICs

• They will progressively replace monolithic SoC, or SiP

• Adoption of « system-partitioning » Interposers is driven by– Performance– Cost – Yield

• Lead applications for« system-partitioning » are GPUs, FPGAs, large ASICs andAPE+memory for tablets

• « System-partitioning » Interposers are generally large (exceeding 20x20mm²)

PCB

Memory Logic AnalogueSilicon

interposer

BGA Laminate


Interposers for FPGAFocus on Xilinx Virtex 7 HT

• Last fall, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 seriesFPGAs

• Key features– Two million logic cells for a high level of computational performance ,and high bandwidth– Four slice processed in 28 nm– 25 x 31mm, 100 µm thick silicon Interposer– 45 um pitch microbumps and 10 µm TSV– 35 x 35 mm BGA with 180 µm pitch C4 bumps

• Even if the infrastructurehad been ready for full 3Dstacking, the 2.5DInterposer would still havebeen the right choice forFPGAs since the “10,000routing connections” wouldhave used up valuable chiparea, making the chip sliceslarger and more costly thanthey are now

• Virtex 7 HT consists of three FPGA slices and two 28 gbps SerDes chips on an Interposercapable of operating at 2.8 Tb/sec! Source: Yole Developpement & Phil Garrou for iMicronews

Courtesy of Xilinx


Interposers for Large CPUs and GPUs• Limitation/Bottleneck in conventional 2D architecture

– Beyond eight cores, processors will lose performance benefits in a 2D configuration. This is afundamental bottleneck that IBM and Intel are working on 2D SoC partitioning and use of 2.5D Interposers will be soon be mandatory for increasing the

performance of high-performance computers!

• Power 8 by IBM will be based on 2.5D Interposers• Haswel, Intel GPU on 2.5D Interposers for laptops, with lots of on-board memory

and an ultra-large data bus

IBM Power 7+: four 32nm CMOS multi-core CPU dies are placed side by side on a silicon Interposer. (Courtesy of SemiAccurate.com)

Cross-section pictures of an IBM 3D stacked module demonstrator with TSVs in the thinner die(courtesy of Chipworks)


GPU for Gaming• Sony’s PS4 (2013) will have its GPU and memory stacked on a 2.5D Silicon Interposer with a

512-wide data bus. This will likely be an AMD chip• Future gaming platforms will offer 3D imagery, which requires fast & high bandwidth

computing power• 2.5D is unanimously praised as the solution for this purpose

• “GPU-RAM bandwidth is the key factorfor rendering performance” – Sept 2011, Teiji Yutaka , SVP Technology Platform, Sony Computer Entertainment

An Interposer module for (Yole’s assumption) an AMD GPUdemonstrator, Courtesy of Global Foundries, 2012


Networking ApplicationsCisco seriously considering silicon Interposers

• Because higher memory bandwidth is neededfor networking applications, and becausesteppers limit the size of silicon Interposers toa max. of 26x32mm (as estimated by Cisco),Cisco proposes a new architecture: the 3D SiP,with naked dies mounted on both sides of theInterposer

The 3D SiP architecture hosts bare dice on both sides of the Interposer(cross-section drawing and top view) , Source: Cisco and ITRI, ECTC 2012


Interposers technical and marketing segmentation and statusTechnical segments

“System partitioning” interposers

MEMS and sensor 3D capping interposers

Interposers for CMOS image

sensors

3D LED siliconsubstrates

3D IntegratedPassive Devices

(IPDs)

Miscellaneous interposers

Mobile/wireless Application processor + memory for tablets in

2013

HVM since 2011 BSI with interposer in 2012

Emerging Emerging for RF front-end and

DC/DC converters

Silicon PoP?

Gaming GPUs in 2013. CPUs in 2015

HVM since 2011

Industrial and medical

FPGA in 2012, High perf processors in 2014

Silicon substrates & IPDs for medical?

PCs GPUs in 2013, CPUs in 2015

Voltage regulators.In research phase

Data centers & servers

CPUs in 2014 Voltage regulators.In research phase

Wired telecominfrastructure

FPGA in 2012, ASICs in 2015

Wireless telecominfrastructure

? ?

Home consumer (DSC, MP3, TV, white

goods)

FPGA 2012 in smart TV BSI with interposer in 2012

Aerospace/mil/hi reliability

ASICs in 2017 Silicon substratesfor high temp

operation?

Automotive FPGA and ASICs in 2018 Emerging ?

General lighting Emerging

End

App

licat

ion


2.5D Summary and Roadmap

2010 2011 2012 2013 2014 2015 2016 2017 2018

BAW filters, RF devices

LED silicon substrates

FPGAs, networking, & storage & HDTV ASICs

GPUs

APEs (in tablets)

CPUs

CMOSimage sensors

APEs(smartphones)

?

© 2013


Conclusions & Perspectives


Main ConclusionsSupply Chain

• Many supply-chain possibilities for 2.5D/3DIC integration

• Innovative business model evolutions– Leading wafer foundries are now extending to package, assembly & test integrated

services– Large IDMs have now opened full turnkey manufacturing services to bring key design

wins and manufacturing volume from leading IC fabless/fab-light companies in-house– Leading packaging, assembly & test houses have the possibility of developing their own

2.5D / 3DIC technology ecosystems

• For the players unable to develop vertically into front / middle / back-endassembly & test, there is an urgent need to settle a genuine collaborativeecosystem

• Key challenge for these future ‘virtual IDM’ ecosystems To determine the ownership and responsibilities between each party involved in themanufacturing process flow To develop several different flexible supply chains with fair value distribution


Main ConclusionsMarket & Applications

• 3DTSV technology is considered today as a new paradigm for the future of thesemiconductor industry!

• 3D stacked DRAM & 3D Logic SOC = biggest drivers for volume adoption of 3DICtechnology

• In terms of value, the 3D TSV market will reach $40B in 2017, growing more than10 times faster than the global semiconductor industry!

Cost

Performance

Size


2013-2015 PerspectivesMarket & Applications

• We will probably have to wait until the end of 2013 to see application processorsand wide IO stacked on a 2.5D Silicon Interposer implemented in a tablet

– This « hybrid » 3D SiP/SoC will take advantage of the two approaches, mixing thetechnologies using the system partitioning and the wide IO interface

– The initiative may be taken by Apple for the next iPad– Moving from hybrid 3DSiP/SoC to « real » 3DIC, complex 3D systems should appear in

2015 First in high-end Smart phones for APE + Wide IO stacking (expected in 2015) Then for logic + logic stacking

• 2013 will likely be the key turning point for the first true implementation of 3DICtechnology in significant volume, driven by the commercialization of HMC


Yole Advanced Packaging Reports

© 2013


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Mei-Ling Tsai蔡美玲

M +886 9 3757 6016E [email protected] www.i-micronews.com

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Documents

3DIC & 2.5D Interposer markettrends and …server.semiconchina.org/downloadFile/1365732442704.pdfWafer Level Packaging « Middle -end » Silicon Manufacturing « Front-end » Package