3TA Diff Amps 2010

University of KwaZulu-Natal Analogue Electronics 1 ENEL3TA Differential Amplifiers

H Jay Page 1 Jan 2010

Differential Amplifiers Differential amplifiers, the concepts of differential and common-mode signals and gains, and common-mode rejection ratio (CMRR) have been introduced previously.1 Differential amplifiers are widely used for their ability to reject common-mode noise. The input stage of every op-amp is a differential amplifier and we shall now consider some typical circuits used to produce differential amplifiers and their associated biasing.

1. The BJT Differential Pair (Emitter-coupled Pair, Long-tailed Pair) • This (and its FET counterpart) forms the most widely used circuit building block in

analogue ICs; • This forms the basis for a very high-speed logic family (ECL: emitter-coupled logic); • It is widely used in ICs such as op-amps, voltage comparators, voltage regulators etc.

The basic BJT differential pair is shown in Fig. 1 where the BJTs are assumed identical (matched) and the dc biasing is controlled by a constant current source which is usually a transistor current source such as a current mirror (studied later), or in the simplest case just a resistor.

Figure 1 The dc transfer characteristic which gives the relation between the input and output voltages can be determined from the large-signal analysis. The large-signal analysis can be simplified by making the following assumptions:

1. The output resistances of the BJTs are infinite: ∞=or , 2. The output resistance of the current source is infinite: ∞=EER (the current source is ideal).

Common-mode operation Consider first the operation of the circuit with the two bases joined and a pure common-mode voltage vCM applied to both inputs i.e. 2B1BCM vvv == . Following the above assumptions, the tail current IT will remain constant and from symmetry will divide equally between the two BJTs so that

2Iii T2E1E == .

1 Electrical Principles 2 (ENEL2EB), Op-amp notes: p7,8 etc.

Q1 Q2

vC2

RC

IT

RC

+VCC

vC1

REE

vB1 vB2

−VEE

VEiE1 iE2

iC1 iC2



Assuming the BJTs are biased into the active region, 2Iiiii T2E1E2C1C ⋅α=⋅α=⋅α== thus the

voltage at each collector will be CT

CCCCCC2C1C R2

IVRiVvv ⋅⋅α−=⋅−== .

If the common-mode input signal is varied, as long as the BJTs remain in the active region, the tail current will still divide equally and the collector voltages will not change. Thus the differential pair does not respond to (i.e. it rejects) common-mode input signals.

Large-signal operation

Recall that for a BJT in active mode: TBETBE VvSCE

VvSC e

Iii eIi ⋅

α=

α=∴⋅= , so for the

differential pair: ( ) ( ) TE2BTE1B VvvSE2

VvvSE1 e

Ii and e

Ii −− ⋅

α=⋅

α= …(1)

Also T2E1E Iii =+ , and hence after some manipulation we obtain:

( ) ( ) T2B1BT1B2B VvvT

E2VvvT

E1e1

Ii and

e1

Ii −− +

=+

= …(2)

( ) ( ) T2B1BT1B2B VvvT

C2VvvT

C1e1

Ii and

e1

Ii −− +

⋅α=+

⋅α= …(3)

Using equation 3 and substituting 2B1Bid vvv −= we may thus plot the transfer characteristics of the BJT differential pair as shown in Fig. 2.

Figure 2 Note from Fig. 2 that a relatively small difference voltage of about 4VT (approx. 100 mV) is sufficient to switch the current almost entirely to one side of the BJT pair and is one reason this circuit can be used as a fast current switch. We are here concerned specifically with the application of the BJT differential pair as a linear small-signal amplifier and thus as seen from Fig. 2 the differential input voltage should thus be limited to less than about ±VT/2 ( 12 mV) in order to operate in the linear region of the characteristics around the midpoint x.

0

0.5

1.0

Nor

mal

ised

col

lect

or c

urre

nt, i

C/I T

Normalised differential input voltage, v id / VT = (vBE1-vBE2) / VT

0-10 -8 -6 -4 -2 2 4 6 8 10

Linear region

T

1CIi

T

2CIi

x



Often to extend the linear region of operation, small equal value resistances (RE1 & RE2) are included in series with the emitters of BJTs Q1 & Q2 as shown in Figure 3.

Figure 3 This is termed “emitter degeneration” since the emitter resistances introduce some negative feedback to the circuit. This has the effect of increasing the differential input voltage that may be applied while keeping the operation in the linear region, but reducing the gm (which is the slope of the transfer curve at vid = 0) as seen (dotted) in Fig. 4. The differential input resistance is also increased (“resistance reflection” of RE into the base circuit).

Figure 4 Thus the linearity is improved, (i.e. distortion reduced), the gm and hence the voltage gain is reduced, and the input resistance is increased. (This is the same effect that the addition of an unbypassed emitter resistance has to a single stage BJT common-emitter amplifier.)

Differential or Single-ended output The output of the differential pair may be taken differentially between the two collectors (by feeding this difference into another differential stage), hence the differential output is

2C1Cod vvv −= . The output may also be taken “single-ended” from just one collector with respect to ground, hence the single-ended output is 2Cos1Cos vvor vv == .

Q1 Q2

vC2

RC

IT

RC

+VCC

vC1

REE

vB1 vB2

−VEE

iC1 iC2

RE1 RE2

0

0.5

1.0

Nor

mal

ised

col

lect

or c

urre

nt,

i C/I T

Normalised differential input voltage, v id / VT = (vBE1-vBE2) / VT

0-10 -8 -6 -4 -2 2 4 6 8 10

T

1CIi

x

0R2

IE

T =

TET V5R2

I ⋅=



Small-signal operation The small-signal operation is easiest analysed by considering the circuit response to the differential and common-mode components of the signals separately and working with the relevant “half -circuit” model for each case (as shown below). In the following analysis external load resistance RL has been omitted for simplicity, hence where necessary replace RC by LCL R//RR =′ etc. as appropriate.

a. Pure differential signals: Consider the BJT differential pair of Fig. 3 with differential signals applied as in Fig. 5. For “pure” differential signals (i.e. signals with zero common-mode component), points on the line of symmetry are “virtual grounds”. (The dc supply rails are signal grounds, and at points such as “x” in Fig. 5, by symmetry, the increase in signal current in one BJT is exactly matched by the decrease in signal current in the other BJT hence the signal voltage at x is zero.)

Figure 5 Hence for differential signals, the circuit is effectively two identical “half-circuits” each comprising a single BJT (in common-emitter) with opposite polarity differential signal components applied. We may thus draw an equivalent “half-circuit” and replace the BJT by an appropriate model (e.g. “T” model) as in Fig. 6:

Figure 6

Hence the small-signal equivalent circuit has been simplified to effectively two “half-circuits” each of which is a simple familiar BJT CE circuit (with or without RE) and can thus be simply analysed.

Q1 Q2

vC2

RC

RE RE

IT

RC

+VCC

vC1

2Vid+

2Vid−

line ofsymmetry

REE

−VEE

x

Q1 RC

RE

vC1

2Vid+ RC

RE

2Vid+

re

ei⋅α

T-model

eibivC1



From the equivalent half-circuit: ...(4) ...(5)

...(6)

(…as expected using the familiar “resistance reflection” rule) Thus, without RE: (substitute RE = 0 in (4),(5),(6))

…(7)

b. Pure common-mode signals: Consider the BJT differential pair of Fig. 3 redrawn in fully-symmetric form with identical common-mode signals applied as in Fig. 7. For “pure” common-mode signals (i.e. signals with zero differential component), points on the line of symmetry are “open circuits” since no current flows in these links. (By symmetry with equal common-mode signals applied, the signal voltages at x and y will be equal.)

Figure 7 Hence for common-mode signals, the circuit is effectively two identical “half-circuits” each comprising a single BJT (common-emitter with RE) with equal common-mode signal components applied. We may thus draw an equivalent “half-circuit” and replace the BJT by an appropriate model (e.g. “T” model) as in Fig. 8:

)Rr(2R

)Rr(2R

)Rr(i2Ri

vv

vv

o/p) ended-(singleA

)Rr(R

)Rr(R

)Rr(iRiv

vv2

vvv

vv

o/p) (diff.A

Ee

C

Ee

C

Eee

Ce

id

C1

id

osVds

Ee

C

Ee

C

Eee

Ce

2v

1C

id

1C

id

2CC1

id

odVd

id

+⋅−≈

+⋅⋅α−=

+⋅⋅⋅⋅α−==≡

+−≈

+⋅α−=

+⋅⋅⋅α−===−=≡

)Rr()1(2i

)Rr()1(i2iv

R Hence

)Rr()1(i2)Rr(i2v )Rr(i2

v

Eeb

Eeb

b

idid

EebEeeidEeeid

+⋅+β⋅=+⋅+β⋅=≡

+⋅+β⋅=+⋅⋅=∴+⋅=

π⋅=⋅+β⋅=⋅−=⋅−=⋅α−= r2r)1(2R ; 2Rg

A and RgrR

A eidCm

VdsCme

CVd

Q1 Q2

vC2

RC

RE RE

RC

+VCC

vC1

icv

line ofsymmetry

2REE 2IT

2IT

−VEE

icv

2REE

x y



Figure 8 If the output is taken single-endedly, then from the equivalent half-circuit in Fig. 8:

( )( ) ( )

( ) ( ) ...(9) Rr

RRr2

R2RrR

R2RrRr2

RAA

CMRR hence, and

...(8) ] )R(r2Rusually since [ R2R

)R2Rr(R

)R2Rr(R

)R2Rr(iRi

vv

ended)-(single A

Ee

EE

Ee

EEEe

C

EEEe

Ee

C

Vcs

Vds

EeEEEE

C

EEEe

C

EEEe

C

EEEee

Ce

ic

1CVcs

+≈

+++

=⋅α

++⋅

+⋅α

≈≡

+>>−≈

++−≈

++⋅α

−=++⋅

⋅⋅α−=≡

EEme

EEE Rg

rR

CMRR then 0, R if Also, ⋅≈≈=

If the output is taken differentially, then assuming perfect symmetry, the output common-mode voltage 2C1Coc vvv −= will be zero, and hence the common-mode voltage gain will also be zero and the CMRR will be infinite. In practice circuits are not perfectly symmetrical hence even if the output is taken differentially, the common-mode gain will not be zero. For example, consider the case where the circuit is symmetric except for a mismatch RC in the collector resistances i.e. Q1 has load resistance RC but Q2 has load resistance RC + RC. Hence, using (8):

( )

...(10) RR

AA :(8) from and ; RR

R2R

A :asrewritten becan This

R2R

)R2Rr(R

vv

A

v)R2Rr(

Rvv v:be loutput wil mode-common the

v)R2Rr(

RR v;v

)R2Rr(R

v

C

CVcsVcd

C

C

EE

CVcd

EE

C

EEEe

C

ic

ocVcd

icEEEe

C2C1Coc

icEEEe

CC2Cic

EEEe

C1C

∆⋅≈∆⋅≈

∆≈++

∆⋅α==∴

++∆⋅α=−=∴

++∆+⋅α−=

++⋅α−=

From (10) it can be seen that the common-mode gain is much smaller with differential output than with single-ended output. Thus, for example, to achieve maximum CMRR for an op-amp, the input differential stage is often a balanced one with the output taken differentially.

Q1 RC

RE

vC1

icv RC

RE

re

ei⋅α

T-model

eibi

2REE

icv

vC1

2REE



Common-mode Input Resistance

Following Fig. 7, the common-mode input resistance b

iccmi i2

vR

⋅≡ . Adding the BJT output

resistance ro to the equivalent half-circuit of Fig. 8 and omitting RE, we obtain Fig. 9. Since the common-mode gain is very small (<<1, ideally zero) the output voltage will be close to zero and hence effectively grounded. Using this simplification, we obtain the equivalent circuit of Fig. 10.

Figure 9 Figure 10 From Fig. 10, neglecting re (since re << 2REE // ro),

( ) ( ) ( ) ( )oEEb

oEEb

b

iccmi r//R21

ir//R2i1

iv

R2 ⋅+β=⋅⋅+β≈= ( )

⋅+β≈∴2r

//R1R oEEcmi …(11)

This should be obvious from Fig. 10 using resistance reflection (neglecting re). Since REE & ro are usually large, Ri cm typically will be very large.

Exercise 1 The differential amplifier in Fig. 11 uses BJTs with = 100. Evaluate the following: (a) The input differential resistance Rid. (b) The differential voltage gains:

id

ovv

and sig

ovv

(neglecting ro).

(c) The worst-case common-mode gain if the collector resistors are matched to within ±1%.

(d) The CMRR, in dB. (e) The common-mode input resistance

Ri cm (assuming VA = 100 V). Figure 11 With the output voltage reference polarity as shown, identify the inverting and non-inverting inputs.

RC

2.Ri cm re

ei⋅α

T-model

eibi

icv

2REE

ro

V0v 1C ≈

2.Ri cm re

ei⋅α

eibi

icv

2REE ro

+15 V

Q1 Q2

vORS5kΩ

RC10k

RE150Ω

RE150Ω

RS5kΩ

RC10k

REE200kΩIT = 1mA

2

vsig

2

vsig

+

−

+−vC1 vC2

vid

Rid



2. Biasing of BJT and MOS Integrated Circuits Integrated circuit technology does not allow for fabrication of high-value resistors (e.g. > 30 k) or high-value capacitors (e.g. > 50 pF). Hence the biasing techniques used for discrete BJT circuits (such as in Electrical Principles 2) which typically required high-valued resistors ( > 100 k) and high-value coupling and bypass capacitors ( > 1 F) cannot be implemented in ICs. The biasing in IC design is based on the use of constant-current sources. On an IC chip with several amplifier stages, typically a constant dc reference current is generated at one location and this is then replicated at other locations to bias the various amplifier stages through a process known as current-steering. The amplifier stages in ICs are direct-coupled (dc-coupled). The current sources used in ICs are formed from interconnected transistors known as current mirrors. There are many different current mirror circuits of varying complexity and these can be combined in various ways to form current-steering circuits. Current mirrors are used to implement the biasing current source (IT, REE) such as in the BJT differential pair of Fig. 1 and they are also used to replace load (collector) resistances (RC) in “active loads”.

Current Mirrors

2.1 Basic 2-BJT current mirror

Figure 12 Fig. 12 shows the basic 2-BJT current mirror circuit with input reference current Iref and output current Io. In this npn version both currents flow into the mirror producing a current sink. From the circuit connection BE2BE1BE VVV == , thus for identical (matched) BJTs: Assuming 2CE1CE VV = then OC2C1CB2B1B IIII and III =====

β+

⋅=∴

β+=

β+=

β+=⋅+=

21

1II

21I

21I

I2II2II refOOC

CCBCref …(12)

Usually 2>>β , hence refO II ≈ so the output current “mirrors” the reference, hence the name.

The output resistance RO is determined by BJT Q2 : O

A

O

2CEA2oO I

VI

VV)Q(rR ≈+== …(13)

+ VCC

Rref

Q1 Q2

Iref

IC = IOIC

IB IB

2.IB

VBE

VCE1= VBE

VCE2

-VEE

RO



The input current Iref may be a current source (or signal), or, as usual in bias circuits, a constant reference current, typically produced via +VCC and Rref as in Fig. 12 giving:

( )ref

BEEECC

ref

BEEECCref R

VVVR

VVVI

−+=−−−= …(14)

Mirror Ratio: We define the ratio of output current IO to input current Iref to be the mirror ratio (MR).

Hence from (12) assuming identical (matched) BJTs: ] 2for 1 [ 2

1

1II

MRref

O >>β≈

β+

=≡

Mirror ratio scaling: A very useful modification of the basic current mirror results if the mirror ratio can be changed from unity. To alter the BJT mirror ratio we use the fact that the reverse saturation current (IS) of the BJT is proportional to emitter area. Hence by changing the relative areas of the emitters (emitter area scaling) of the BJTs, the IC designer can modify the mirror ratio.

Assume in Fig. 12 the emitter areas AE1 for Q1 and AE2 for Q2 are scaled such that mAA

1E

2E = .

Then 1B2B1C2C ImI ; ImI ⋅=⋅= and from (12):

β++

=

β++

⋅⋅=1m

1

mMR and

1m1

1ImI refO thus if refO ImI )1m( ⋅≈∴+>>β …(15)

Early Effect: The above analysis has assumed the BJTs have the same VCE. Usually )V(VV BE1CE2CE => and thus due to the Early effect2 and hence the finite output resistance of Q2 there will be a mismatch between IO and Iref with refO II > as shown in Fig. 13.

Figure 13 This may be accounted for by modifying (12) or (15) as follows:

−+⋅

β+

⋅=A

BE2CErefO V

VV1

21

1II or

−+⋅

β++

⋅⋅=A

BE2CErefO V

VV1

1m1

1ImI …(16)

Current mirror sources and sinks: The mirror circuit in Fig. 12 uses npn BJTs producing a current mirror sink. A similar circuit in inverted form using pnp BJTs may be used to create a current mirror source with both currents flowing out of the BJT collectors (see texts). 2 Electrical Principles 2: Notes on BJTs: p4.

-VA 0 VCE2VCE

IC

IC1

IO = IC2

VCE1= VBE



2.2 Multiple-output mirror (“repeated” mirror, or “current repeater”)

Figure 14 The basic 2-BJT mirror may be simply extended to have multiple identical current outputs by connecting several identical output BJTs to the diode-connected biasing BJT Q1 as shown above.

Hence replacing 2IB by (n+1)IB equation (12) becomes:

β++

⋅====1n

1

1I..... III ref3O2O1O …(17)

Obviously, this may be developed further by scaling the areas of the output BJTs so that, for example, area Q3 is m times area Q1, Q2 and hence .etc ... ImI 1O2O ⋅= Thus multiple output currents of different ratios to the reference current may easily be generated and this is used extensively in the biasing circuits of ICs 3 (e.g. in current steering circuits – see later).

Improved Current Mirrors

2.3 Buffered current mirror (mirror with base-current compensation) 4 The error caused by finite in the above current mirrors may become substantial if is low. This error may be greatly reduced by adding a BJT buffer (Q3) as in the circuit of Fig. 15.

Figure 15

3 Sedra & Smith: 4th Ed: p513-514, 5th Ed: p570-571; Jaeger & Blalock: 2nd Ed: p333-335, 1186-1189, 3rd Ed: p899-902 4 Sedra & Smith: 4th Ed: p515-516, 5th Ed: p650-651; Jaeger & Blalock: 2nd Ed: p1189-90, 3rd Ed: p902

+ VCC

Rref

Q1 Q2

Iref

IC = IOIB IB

2.IB

VBE

VCE1= 2.VBE VCE2

-VEE

RO

Q3

IB3

IC = IO

+ VCC

Rref

Q1Q2

Iref

IO1ICIB nIB

(n+1)IB

VBE

VCE1= VBE

-VEE

IO2 IO3

Q3 Q4

n outputs



From the circuit in Fig. 15: BE2BE1BE VVV ==

Hence for matched BJTs 1

I2I I2I also III III B

3BB3EO2C1CB2B1B +β⋅=∴⋅===∴==

β+β+

⋅=∴

β+β+=

+ββ⋅+=

+β⋅+=+=

2

refO2OO

OB

OB3Oref2

1

1II

21I

1I2

I1

I2IIII ...(18)

Hence the circuit provides refO II ≈ even for relatively low β values. Also O

A)2Q(oO I

VrR ≈=

2.4 Wilson current mirror 5

Figure 16 The Wilson current mirror of Fig. 16 is a clever modification to the buffered current mirror. It also achieves base-current compensation and hence provides refO II ≈ even for relatively low β values.

In addition, it also provides a much greater output resistance: )3Q(oO r2

R ⋅β≈ ...(19)

The disadvantage is that output voltage cannot go as close to the negative supply rail as in the previous circuits: V1VVV )3Q(CEsatBEO ≈+> (to keep Q3 in active mode).

Exercise 2

Show that for the Wilson current mirror:

β+β+

⋅=

2

21

1II

2

refO …(20)

5 Sedra & Smith: 4th Ed: p516-517, 5th Ed: p651-652; Jaeger & Blalock: 2nd Ed: p1198-1201, 3rd Ed: p909-912

+ VCC

Rref

Q1 Q2

Iref

IC

IC

IB IB

2.IB

VBE

VCE1=2.VBE

VO

-VEE

IO

IE3

IB3Q3

)3Q(oO r2

R ⋅β≈



2.5 Widlar current mirror 6 Scaling of BJT areas can provide mirror ratios of at most about 10:1 or 1:10. When much larger mirror ratios are required, the Widlar current mirror provides output current that can typically be several orders of magnitude smaller than the input reference current. This is achieved by including a small series resistance in the emitter of the output BJT that reduces VBE. Since IC is exponentially related to VBE a small reduction in VBE can produce a very large reduction in IC. It also provides a much larger output resistance oEmO r)Rg1(R ⋅′+≈ where π=′ r//RR EE

Figure 17 Recall for a BJT: TBE VV

SC eII = and thus ( )SCTBE IIlnVV ⋅= . Hence in Figure 17, neglecting base currents and assuming matched BJTs: …(21) Thus the introduction of RE reduces the current IO and the value of the resistor required can be determined using equation (21). The design and advantages of the Widlar current mirror are illustrated in the following example.

Example 1 Figure 18 shows two circuits for generating a constant current sink of 10 A which operate from a 10 V supply. Determine the value of the resistors required assuming that VBE = 0,7 V at IC = 1 mA and neglecting the effect of finite .

6 Sedra & Smith: 4th Ed: p517-520, 5th Ed: p653-656, 611-612; Jaeger & Blalock: 2nd Ed: p1194-1196, 3rd Ed. p906-907

+ VCC

Rref

Q1 Q2

Iref

IO

VBE2VBE1

-VEE

RO

REVRE

( )( )

( )

( )OREFTEOR

R2BE1BE

OREFT2BE1BE

SOT2BE

SREFT1BE

IIlnVRIV

VVVBut

IIlnVVV

IIlnVV

IIlnVV

E

E

=⋅=∴

+=⋅=−∴

⋅=⋅=



(a) (b)

Figure 18 For circuit (a) we need to find VBE1 for Iref = 10 A. We know VBE = 0,7 V at IC = 1 mA. Hence

Thus Ω=µ

−= k942A10

V585,010R1 (which is rather large, unsuitable for IC design).

For the Widlar circuit (b) we first select a suitable Iref .

Choosing Iref = 1 mA requires Ω=−= k3,9mA1

V7,010R 2 which is suitable for IC design.

Using (21): ( ) Ω=∴µ⋅=⋅µ k5,11R A10mA1ln025,0RA10 33 which is now also suitably small. An additional advantage of the Widlar mirror is that the output resistance is large. To determine an expression for the output resistance, replace Q2 in Figure 17 with its small-signal -model and apply a test voltage vx to the collector as shown in Figure 19. The base of Q2 is connected to signal ground (−VEE) via the diode-connected BJT Q1which has a small incremental resistance (re). Since

π<< rre the base of Q2 is thus assumed to be grounded.

Figure 19

R2

Q1 Q2

Iref

IO

VBE2VBE1 R3

+ 10 V

R1

Q1 Q2

Iref

IO

VBE1

+ 10 V

( ) ( ) V585,010ln025,07,0mA1A10lnV7,0V

eImA1

eIA10

2T1BE

V7,0S

VVS

T

T1BE

=⋅+=µ⋅+=

⋅=

⋅=µ

−

ro

RE

πrπ⋅vgm

πv

xi

xv

cb

e

πv



In Figure 19 RE and r are in parallel hence let π=′ r//RR EE To determine the output resistance RO apply vx and determine ix then xxO ivR =

E

x Rv

i′

−= π …(22)

o

xmx r

vvvgi π

π++= …(23)

( ) omxx rvgivv ⋅−+−= ππ …(24)

Subst. (22) into (24): oE

momoE

x rvR1

gvrvgrRv

vv ππππ

π ⋅

′+−−=⋅−⋅

′−−= ...(25)

Subst. ( )π+ vvx from (25) into (23):

ππ ⋅

′+−= v

R1

gvgiE

mmx ...(26)

Now

( ) oEmE

E

oE

m

Emm

oE

m

x

xO

rRg1R

R1

rR1

g1

vR1

gvg

rvR1

gv

iv

R

⋅′++′=

′

⋅

′++

=⋅

′+−

⋅

′+−−

==

ππ

ππ

Since R'E is small: ( ) oEmO rRg1R ⋅′+≈ ...(27)

Example 2 Find the output resistance of each of the current mirror circuits in Example 1. Use VA = 100 V and = 100.

(a) No RE and A10IO µ= : Ω=µ

== M10A10V100

IV

RO

AO

(b) A10I and k5,11R OE µ=Ω= :

( ) Ω=Ω⋅⋅⋅⋅+=

Ω===′

Ω==β=

=µ==

Ω=µ

==

−π

π

M54M101011104,01R

k11k250//k5,11r//RR

k250V/mA4,0

100g

r

V/mA4,0mV25

A10VI

g

M10A10V100

IV

r

33O

EE

m

T

Om

O

Ao



Multiple output mirrors (“current repeaters” or “current steering circuits”) as outlined in section 2.2 (p.10) may also be extended using the Widlar principle (i.e. adding emitter resistances) to produce multiple output currents with ratios to the reference current much larger than possible by area ratios. The high output resistance may be another reason for using the Widlar principle in such current steering circuits.

2.6 MOS current mirrors 7 MOS current mirrors may be implemented in similar fashion to most of the BJT current mirrors, but inaccuracy in mirror ratio due to finite β has no counterpart in MOS mirrors, hence there is no need for buffering. The simple basic MOS current mirror sink using n-channel MOSFETs is shown in Fig. 20.

Figure 20 Q1 is in saturation by connection; hence assuming matched MOSFETs with identical λ′ and,k ,V nt and providing Q2 is in saturation, then:

( )( ) ( )[ ]GS2DS

1

2refO VV1

LWLW

II −⋅λ+⋅⋅= provided ( )tGS2DS VVV −≥ . ...(28)

The output resistance is: OO

AO I

1IV

R⋅λ

=≈ …(29)

In similar fashion to BJT mirrors, multiple outputs may be connected to form current repeaters, and using p-channel MOSFETs, mirror sources may be produced. The Widlar technique may be implemented in MOS mirrors, and the Wilson mirror may be implemented in MOS form to provide increased output resistance.

7 Notes (MOSFETs): p81-82; Sedra & Smith: 4th Ed: p402-408, 533-535; 5th Ed: p562-567, 649-650, 652-653; Jaeger & Blalock: 2nd Ed: p1181-1184, 3rd Ed: p894-897

Rref

VDD

Q2Q1

Iref

IO

VO

VGS−VSS

VDS2



2.7 Current-Steering Circuits (using current mirrors) Once a constant current is generated it can replicated to provide dc bias currents for various stages in an IC, and this is easily achieved using current mirrors.

2.7.1 BJT current-steering circuit

A simple example using BJT current repeaters to produce current sources and sinks is shown in Fig. 21. In IC form, the “paralleled” BJTs would be implemented by varying the junction areas, e.g. Q5 & Q6 would be one BJT twice the area of Q1 and Q7, Q8 & Q9 would be one BJT three times the area of Q2. Hence in Fig. 21, neglecting the effect and assuming ∞ AV , ;I2I ;III REF3REF21 ⋅===

REF4 I3I ⋅= The Widlar principle may also be used, by including emitter resistances to produce current ratios much larger than possible with variation in junction areas.

Figure 21

2.7.2 MOS current-steering circuit

A similar example using CMOS technology is shown in Fig. 22. Q1, Q2 & Q3 form a two-output current mirror where Q2, Q3 sink currents I2, I3. I4 = I3 is the input of the PMOS mirror Q4 & Q5 where Q5 sources current I5. Assuming :0=λ

( )( )

( )( )

( )( )4

54534

1

3REF3

1

2REF2

LWLW

II ; II

LW

LWII ;

LWLW

II

==

==

Figure 22 To keep Q2, Q3 in saturation: 1OVSS3D2DtnGSSS3D2D VVV,V i.e. VVVV,V +−≥−+−≥

Similarly to keep Q5 in saturation: 5OVDD5D VVV −≤

Exercise 3 Sedra & Smith: Exercise 5.25 p408 4th Ed. or Exercise 6.5 p567 5th Ed.

R

IREF

+VCC

−VEE

I1 I3

I2 I4

Q1

Q2

Q3

Q4

Q5 Q6

Q7 Q8 Q9

R Q5Q4

Q1 Q2

I5I2

IREF

I4 = I3

source

sink

+VDD

−VSS

Q3

VGS1

VSG5



3. The BJT Differential Amplifier with Active Load 8

Figure 23 An important application of a current mirror is as a replacement for the load resistors of differential amplifier stages in an IC op-amp. The basic circuit using a BJT differential amplifier is shown in Fig. 23 where the current mirror is said to be an active load. The signal output current (and hence the voltage gain) is effectively doubled by the active load mirror action, thus although the output is single ended, the voltage gain is the same as would be obtained for a differential output with the same loading conditions without an active load. Drawing a small-signal equivalent circuit:

Figure 24

]R//r//r[gV

]R//r//r[Vg

VV

A L)4Q(o)2Q(omd

L)4Q(o)2Q(odm

d

OVd ⋅=

⋅⋅=≡

To determine the maximum differential voltage gain achievable, assume RL is very large, hence:

2/IV

IV

r ,r ;V

2/IVI

gT

A

C

A(Q4)o(Q2)o

T

T

T

Cm ====

T

A

T

A

T

T)4Q(o)2Q(om

d

OVd V2

V2/I

V21

V2/I

]r//r[gVV

A⋅

=

⋅=⋅=≡∴

Thus, for example, if 2000mV252V100

A ;V100V VdA =⋅

≈=

Self-study Consider the MOS equivalent: a CMOS Differential Amplifier with Active Load 9 8 Sedra & Smith: 4th Ed. p522 - 525; 5th Ed. p733 - 736; Jaeger & Blalock: p1228 – 1232, 3rd Ed. P931 - 935 9 Sedra & Smith: 4th Ed. p536 - 537; 5th Ed. p728 - 731; Jaeger & Blalock: p1221 – 1226, 3rd Ed. P924 - 928

Q1 Q2

IT

+VCC

RO

−

+

dV

Q3 Q4

2v

g dm ⋅

2v

g dm ⋅

2v

g dm ⋅

RL

VO

Riddm vg ⋅

−

+

dVrO

(Q2)

VO

RL

rO(Q4)



4. Multistage Amplifiers

4.1 Simple four-stage BJT op-amp As an example of a multistage amplifier consider the four-stage BJT op-amp shown in Fig. 25. The input stage of Q1 & Q2 is biased by the current source Q3 and is differential-in, differential-out to give maximum common-mode rejection. The second stage of Q4 & Q5 is biased by the current source Q6 and is also differential-in but the output is taken single-endedly which results in a factor of 2 loss of gain. An alternative would be to use an active load (as described in section 3 above) which would avoid the loss of gain. The third stage comprising the pnp Q7 provides some voltage gain and dc level shifting to produce zero output when the inputs are zero. The fourth and output stage comprises the emitter-follower Q8 which provides the desired low output resistance and current drive capability.

Figure 25

Exercise 4 4.1 Taking the inputs as grounded, perform an approximate dc analysis of the circuit of Fig. 25

assuming is large, V7,0VBE = , ∞ AV and calculate the dc currents and voltages

everywhere in the circuit. Note that Q6 has four times the area of Q9 and Q3. 4.2 Calculate the quiescent power dissipation in this circuit. 4.3 If Q1 and Q2 have = 100, calculate the input bias current of this op-amp. 4.4 What is the common-mode range of this op-amp? Exercise 5

Using the dc bias quantities determined in Exercise 4 to analyse the circuit in Fig. 25 to determine the differential input resistance, differential voltage gain and output resistance. Assume = 100.

IREF

Q1 Q2

VO

R120k

Q3

Q4

RREF28.6k

R33k

R220k

Q5

Q6

Q7

Q8

Q9

+15 V

−15 V

R42.3k

R515.7k

R63k

A6 = 4X

+Vid−



5. The MOSFET Differential Pair The basic MOSFET differential pair is shown in Fig. 26 where the MOSFETs are assumed identical (matched) and the dc biasing is controlled by a constant current source in similar fashion to the BJT differential pair studied in section 1.

Figure 26

DC analysis The dc analysis can be simplified by making the following assumptions:

1. The output resistances of the MOSFETs are infinite: ∞=or , 2. The output resistance of the current source is infinite: ∞=SSR (the current source is ideal).

Assume 0VV 2G1G == . From the symmetry of the circuit it is obvious that the bias tail current

divides equally between the two MOSFETs so 2III T2D1D == . Assuming the MOSFETs are biased into the saturation region, the voltage at each drain will be DDDD2D1D RIVVV ⋅−== . VGS may be determined using the usual MOSFET saturation mode equation:

( ) 2tGSL

WD )V(Vk

21

I −′= and hence ( ) ( )LWT

tLWD

tGSk

IV

k

I2VV

′+=

′⋅+=

GSS VV −= hence GSDDDDSDDS VRIVVVV +⋅−=−= and for saturation tGSDS VVV −≥ .

Small-signal operation As for BJTs, the small-signal operation is easiest analysed by considering the circuit response to the differential and common-mode components of the signals separately and working with the relevant “half -circuit” model for each case. In the following analysis external load resistance RL has been omitted for simplicity, hence where necessary replace RD by LDL R//RR =′ etc. as appropriate.

a. Pure differential signals: Consider the MOSFET differential pair with differential signals applied as in Fig. 27. For “pure” differential signals (i.e. signals with zero common-mode component), points on the line of symmetry are “virtual grounds”. (The dc supply rails are signal grounds, and at points such as “x” in Fig. 27, by symmetry, the increase in signal current in one MOSFET is exactly matched by the decrease in signal current in the other MOSFET hence the signal voltage at x is zero.)

Q1 Q2

VD2

RD

IT

+VDD

VD1

RSS

vG1 vG2

−VSS

VS

ID1 ID2

RD



Figure 27 Hence for differential signals, the circuit is effectively two identical “half-circuits” each comprising a single MOSFET (in common-source) with opposite polarity differential signal components applied. We may thus draw an equivalent “half-circuit” and replace the MOSFET by an appropriate model (e.g. “” model) as in Fig. 28:

Figure 28

The small-signal equivalent circuit has been simplified to effectively two “half-circuits” each of which is a simple familiar MOSFET CS circuit. From the equivalent half-circuit:

...(30) ...(31)

and obviously ∞=idR

b. Pure common-mode signals: Consider the MOSFET differential pair redrawn in fully-symmetric form with identical common-mode signals applied as in Fig. 29. For “pure” common-mode signals (i.e. signals with zero differential component), points on the line of symmetry are “open circuits” since no current flows in these links.

( )Dm

2v

D2v

m

2v1D

id

D1

id

osVds

Dm

2v

D2v

m

2v

1D

id

1D

id

2DD1

id

odVd

Rg21

2

Rg

2

vvv

vv

o/p) ended-(singleA

RgRgv

vv2

vvv

vv

o/p) (diff.A

id

id

id

id

id

id

⋅−=⋅

⋅⋅−=

⋅==≡

⋅−=⋅⋅−

==⋅=−=≡

2v

g idm ⋅

vD1

RD2

vid+

g d

s

Q1 Q2

vD2

RD

IT

+VDD

vD1

RSS

−VSS

RD

2vid+

2vid−

line ofsymmetry

x

iD1 iD2



Figure 29 Hence for common-mode signals, the circuit is effectively two identical “half-circuits” each comprising a single MOSFET (common-source with RS) with equal common-mode signal components applied. We may thus draw an equivalent “half-circuit” and replace the MOSFET by an appropriate model (e.g. “” model) as in Fig. 30:

Figure 30 If the output is taken single-endedly, then from the equivalent half-circuit in Fig. 30:

...(32) ...(33)

( )

RgRR2

2Rg

AA

CMRR hence, and

1)2Rg (if R2R

R2g1Rg

R2vgvRvg

vv

ended)-(single A

SSmD

SSDm

Vcs

Vds

SSmSS

D

SSm

Dm

SSGSmGS

DGSm

ic

1DVcs

⋅=⋅⋅≈≡

>>⋅−≈

⋅+⋅−=

⋅⋅+⋅⋅−=≡

gsm vg ⋅

vD1

RD

icv

2RSS

gsv

g d

s

Q1 Q2

vD2

RD

+VDD

vD1

−VSS

RD

line ofsymmetry

icv icv

2IT

2IT2RSS

2RSS

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3TA Diff Amps 2010