40-Gb/s All-Optical Processing Systems Using Hybrid

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 12, DECEMBER 2006 4903

40-Gb/s All-Optical Processing Systems UsingHybrid Photonic Integration Technology

Efstratios Kehayas, Student Member, IEEE, Dimitris Tsiokos, Student Member, IEEE, Paraskevas Bakopoulos,Dimitris Apostolopoulos, Dimitrios Petrantonakis, Leontios Stampoulidis, Alistair Poustie, Rob McDougall,

Graeme Maxwell, Yong Liu, Shaoxian Zhang, Harmen J. S. Dorren, Member, IEEE, Jorge Seoane, Member, IEEE,Pablo Van Holm-Nielsen, Palle Jeppesen, Member, IEEE, and Hercules Avramopoulos

Abstract—This paper presents an experimental performancecharacterization of all-optical subsystems at 40 Gb/s using in-terconnected hybrid integrated all-optical semiconductor opticalamplifier (SOA) Mach–Zehnder interferometer (MZI) gates andflip-flop prototypes. It was shown that optical gates can be treatedas generic switching elements and, when efficiently interconnected,can form larger and more functional network subsystems. Specif-ically, this paper reports on all-optical subsystems capable of per-forming on-the-fly packet clock recovery, 3R regeneration, label/payload separation, and packet routing using the wavelength do-main. The all-optical subsystems are capable of operating withpacket-mode traffic and are suitable for all-optical label-switchedand self-routed network nodes. The intelligent functionality of-fered, combined with the compactness and stability of the opticalgates, verifies the potential that all-optical technology can findapplication in future data-centric networks with efficient anddynamic bandwidth utilization. This paper also reports on thelatest photonic integration breakthroughs as a potential migrationpath for reducing fabrication cost by developing photonic systems-on-chip utilizing multiple SOA-MZI optical gates on a single chip.

Index Terms—Hybrid integrated circuits, label swapping, op-tical fiber communication, optical logic devices, optical memories,optical packet switching (OPS), optical signal processing, semicon-ductor optical amplifiers (SOAs).

I. INTRODUCTION

M IGRATION scenarios from circuit-switchedwavelength-division-multiplexing (WDM) networks to

optical packet-switched (OPS) networks have been introducedin view of next-generation high-speed optical networks that

Manuscript received May 22, 2006; revised September 7, 2006. This workwas supported by the European Commission through project IST-LASAGNEunder Grant FP6-507509 and project IST-MUFINS under Grant FP6-004222and by the Greek General Secretariat for Research and Technology throughproject “PENED 03.”

E. Kehayas, D. Tsiokos, P. Bakopoulos, D. Apostolopoulos,D. Petrantonakis, L. Stampoulidis, and H. Avramopoulos are with the PhotonicsCommunications Research Laboratory, National Technical University ofAthens, 15773 Athens, Greece (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected];[email protected]; [email protected]).

A. Poustie, R. McDougall, and G. Maxwell are with the Centre for IntegratedPhotonics, IP5 3RE Ipswich, U.K. (e-mail: [email protected];[email protected]; [email protected]).

Y. Liu, S. Zhang, and H. J. S. Dorren are with the COBRA Research Insti-tute, Eindhoven University of Technology, 5600 Eindhoven, The Netherlands(e-mail: [email protected]; [email protected]; [email protected]).

J. Seoane, P. V. Holm-Nielsen, and P. Jeppesen are with COM-DTU,Department of Communications, Optics and Materials, Technical Universityof Denmark, 2800 Kgs. Lyngby, Denmark (e-mail: [email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/JLT.2006.884994

will transfer voice, video, and data in an efficient and cost-effective method. In parallel, new communication standardssuch as multiprotocol label swapping (MPLS) [1] have beenreported, attempting to solve the mismatch between fibercapacity and router packet forwarding capacity by forwardingpackets within Layer-2 rather than routing them within Layer-3.In this context, significant research has been devoted in orderto identify the basic networking functions required in suchOPS scenarios, and key technologies have been developed fortheir realization including packet-mode optical switch fabrics[2], [3], optical label swapping (OLS) employing optical labelrecovery, erasure, and rewrite, wavelength conversion [4], [5],and data regeneration [6]. The current research thrust takes thenext step toward all-optical routing, and within the EuropeanIST-LASAGNE project, an all-optical label swapping (AOLS)photonic router is being designed, performing switching andforwarding functionalities in the optical layer [7]. A crucialparameter counteracting the deployment of all-optical routersis the high cost of photonic integration technology and, morespecifically, the high cost associated with packaging. Hence,the use of a generic building block to build the complete nodeis critical as this avoids the requirement for custom-made tech-nological solutions within the node and allows for a commonfabrication procedure for all node subsystems, reducing theoverall cost. Integration of arrays of such optical switches ontothe same photonic chip, which is currently researched withinthe European IST-MUFINS project,1 further reduces the costof photonic devices by sharing the packaging and pigtailingcosts over all the switches in the array. Based on the aboverationale, the scope of this paper is to report on interconnectionpotential all-optical gates, looking beyond the obvious advan-tage of high-speed operation offered by optical technology,and on all-optical network subsystems as a roadmap towardachieving higher intelligence in the optical layer. We alsodemonstrate that these subsystems are suitable for packet-modeprocessing and compatible with MPLS and OLS, showingtheir applicability to currently researched all-optical nodearchitectures such as LASAGNE [7] and ARTEMIS nodes [8].Moreover, we report on photonic integration progress, demon-strating new prototype arrays of quadruple semiconductoroptical amplifier (SOA) Mach–Zehnder interferometer (MZI)optical gates and achieving integration scale increase whileeffectively reducing cost per SOA-MZI gate.

1[Online]. Available: http://mufins.cti.gr

0733-8724/$20.00 © 2006 IEEE

4904 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 24, NO. 12, DECEMBER 2006

Fig. 1. All-optical switching elements based on (a) and (b) semiconductor and(c) optical fiber.

II. ALL-OPTICAL SWITCHING GATES

The design and implementation of all-optical devices capableof controlling light with light [9] at very high speeds have beena major research thrust during the last years as an attempt torealize the equivalent of the electronic transistor. All-opticalgates using either semiconductor [Fig. 1(a) and (b)] or fiber[Fig. 1(c)] as their active switching element, which exploit thegain or phase dynamics within the active nonlinear medium,have been reported. Interferometric switches based on opticalfibers were among the first attempts to build such high-speeddigital gates, which were fuelled by ultrafast response times al-lowing for operational bandwidth exceeding 100 Gb/s. Exploit-ing Kerr nonlinearity in optical fibers, interferometric opticalgates were built leading to the nonlinear optical loop mirror[10] or Sagnac [11] and the ultrafast nonlinear interferometer(UNI) [12]. However, disadvantages related to requirementsin optical power and fiber length stimulated the research anddevelopment of compact semiconductor-based switching de-vices using gain or phase modulation within an SOA [13]. Firstattempts using SOA-based switches were reported exploitingcross-gain modulation [14] in SOAs or cross-phase modulationin interferometric gates, such as the polarization-discriminatingMach–Zehnder [15] or SOA-UNI [16] and the semiconductoroptical loop mirror [17] or terahertz optical asymmetric demul-tiplexer [18]. In these gates, bulk components were used to re-alize the interferometer, and the SOA was used as the nonlinearelement. Recently, advances in integration technology have ledto the development and commercialization of waveguide-based40-Gb/s switches based on the Mach–Zehnder structure [19].

III. ALL-OPTICAL PROCESSING SUBSYSTEMS

All-optical signal processing using fiber- or semiconductor-based devices has been the focus of research groups duringthe last years. These experiments primarily concern single-gateexperiments reporting all-optical logic [20], [21], wavelengthconversion [22]–[25], 3R regeneration [26], and demultiplexing[27]–[29] at bit rates ranging from 10 up to 320 Gb/s [30] inlaboratory experiments and, more recently, in field transmis-sion experiments [31], verifying the potential for high-speedoperation offered by photonic technology. On the other hand,pioneering work on all-optical processing subsystems reported

in [32] and [33] involved multiple interconnected gates, butthe complexity of the implementation involving fiber-basedand bulky all-optical logic gates counteracted the evolution ofthese all-optical subsystems. This section reports on the imple-mentation of interconnected all-optical processing subsystemsrequired within an all-optical network node. These subsystemsexploit integrated generic SOA-MZI optical gates developedusing a unified fabrication technology based on hybrid in-tegration. The subsystems are capable of performing diverseprocessing functionalities for regenerating data, controlling op-tical gates, extracting optical labels, and routing packets withinthe switching matrix of a network node.

A. All-Optical 3R Regenerator

3R regeneration is employed at the input of an optical nodein order improve the quality of the incoming data traffic. Inthe case of a packet switch that employs all-optical signalprocessing, it is advantageous that the 3R regenerator operatesefficiently with packet-mode traffic and avoids optoelectronicconversion, allowing for direct interconnection with subse-quent node subsystems. Previous experiments report optical3R regeneration at 40 Gb/s by employing electro-absorptionmodulator (EAM) and highly nonlinear fiber [34], or an SOAwith an MZI [35]. In these cases, a high-frequency electri-cal circuitry has been employed for the clock acquisition inwhich case an optoelectronic conversion becomes inevitable.An optically clocked 40-Gb/s 3R regenerator has been proposedin [36], where regeneration was accomplished through a self-pulsating laser and an SOA-MZI gate. In this case, althoughthe self-pulsating laser generates a very high quality clock, thesinusoidal signal can be a limitation for the switching windowoptimization of the cascaded optical gates within the node. Inthis experiment, an all-optical 3R regenerator of different lengthpackets at 40 Gb/s is demonstrated by using three integratedSOA-MZI gates and a fiber Fabry–Pérot (FFP) filter.

The experimental setup is shown in Fig. 2 and consists ofthe 40-Gb/s optical packet generator, the wavelength converter(WC) operated as an adaptation interface stage, and the 3Rregenerator circuit employing an FFP filter and two SOA-MZIgates. A 40 :10 demultiplexing circuit was also employed inorder to obtain bit error rate (BER) measurements of 10 Gb/s.The first stage is included as an adaptation interface thatassigns local physical conditions to the incoming signal bywavelength converting it, such as polarization and phase [37].Such module is adopted at the front end of the regenerator inorder to enhance the system robustness in different incomingsignal conditions and to make it inherently transparent to datapackets arriving from different sources and through differentroutes. Most importantly, the conversion to a local continuouswave (CW) signal with known polarization state makes the3R regenerator and consequently the optical node polarizationinsensitive due to the use of SOAs with very low polarizationgain dependence.

The original return-to-zero (RZ) pulse train was producedby a semiconductor mode-locked laser operating at a repetitionrate of 10.025 GHz and a wavelength of 1556 nm. An electricalcircuitry was built to introduce a 4-ps root-mean-square (rms)

KEHAYAS et al.: 40-Gb/s ALL-OPTICAL PROCESSING SYSTEMS USING PHOTONIC INTEGRATION TECHNOLOGY 4905

Fig. 2. Experimental setup of 3R regenerator subsystem interconnecting SOA-MZI optical gates.

phase jitter at the generated short pulses. A sinusoidal variationwas imposed on the electrical signal through a variable phaseshifter driven by a 10-MHz function generator [38]. A LiNbO3

electrooptic modulator (MOD) was employed in order to mod-ulate 27 − 1 pseudorandom bit sequence (PRBS) data, and40-Gb/s pulse trains were generated using a fiber bit interleaver.The packets were then generated by modulating the continuouscodeword through an EAM. The 40-Gb/s test signal was thensplit and fed to the WC section as well as to the decision gateof the regenerator. The signal was then wavelength converted to1548 nm through the first SOA-MZI operating with a push–pullcontrol scheme. The signal was amplified and injected intothe clock recovery (CR) circuit to achieve all-optical timingextraction. The CR employed a low-Q FFP filter with freespectral range equal to the line rate (40.1 GHz) and Finesse of27 as well as an SOA-MZI powered by a CW signal at 1552 nm(LD 2), operating as a holding beam using the principle de-scribed in [39]. The recovered clock was then used as the inputsignal to the third SOA-MZI, where the incoming data servedas the two differential controls. Retiming and reshaping areachieved through optical sampling of the degraded data ontothe retimed optical recovered clock pulses. In order to measurethe BER for each multiplexed 10-Gb/s channel, an EAM setupwas built for demultiplexing each channel.

The 3R regenerator performance was tested with short datapackets of different durations, and the results obtained aresummarized in Fig. 3. In particular, the oscilloscope tracesof the incoming degraded 40-Gb/s packets are illustrated inparallel to the respective eye diagrams. The incoming packetlengths are 3.6 and 1.6 ns for the left-hand side and the right-hand side packet, respectively. The recovered clock packetsare obtained at the output of the CR stage ensuring clockpersistence for the duration equal to the corresponding datapacket length increased by 100 and 350 ps due to the riseand fall times of the clock, respectively. The former valueindicates the time taken by the CR to acquire the clock fromthe incoming data packet, while the latter value determines thetime required by the CR to lose synchronization after eachpacket. Identical values were measured for the short packet.The rise and fall times of the clock are the necessary inter-packet guardbands to avoid overlapping of successive clockpackets. The regenerated data packets are obtained at the outputof the third SOA-MZI, as shown in Fig. 4, along with therespective eye diagrams. The eye opening of the regeneratedsignal demonstrates phase and amplitude jitter reduction whencompared to the eyes of the incoming data. Phase jitter re-duction was confirmed after performing jitter measurements on

Fig. 3. Results obtained through the 3R regenerator subsystem.

the second microwave harmonic of the demultiplexed 10-Gb/schannel at each stage of the regenerator. The single sideband(SSB) noise spectra of the input, recovered clock, and regener-ated signals were integrated from an offset frequency of 1 kHzto 10 MHz from the 20-GHz component, as depicted inFig. 4(a). The rms values were 4 ps for the input, 900 fs forthe recovered clock, and 1 ps for the regenerated signal. Phasereduction originates from the FFP filter transfer function, whichis centered to the carrier, suppressing the data harmonics andthus reducing the phase jitter of the recovered clock. Amplitudenoise reduction is achieved by operating the second SOA-MZIin the deep saturation regime, forcing the switch to operate as ahard limiter and thus suppressing pulse amplitude fluctuations.BER measurements were carried out after demultiplexing eachdegraded incoming 10-Gb/s and corresponding regeneratedchannels. Fig. 4(b) shows the BER curves for each demulti-plexed 10-Gb/s channel at the input and output of the circuit. Anegative power penalty of more than 2.5 dB is demonstratedfor all four data channels. The SOAs within the MZIs wereinsensitive to control signal polarization as confirmed experi-mentally. The latter fact, in combination with the WC operation(adaptation interface stage), verifies the independency of the 3Rregenerator to the incoming signal polarization.


Fig. 4. (a) SSB integration to measure phase jitter. (b) BER measurements.

Fig. 5. Experimental setup of interconnected all-optical subsystems performing wavelength conversion, packet CR, label/payload separation, and demultiplexingof 40-Gb/s packets.

B. Packet Address Extraction and Payload Separation

This section describes a method for separating the payloadfrom the label of incoming data packets using the packet CRcircuit and an additional optical gate. The main difference inthe subsystem reported here is that the label is serially encodedto the payload and shares the same physical state [40], a fact thatallows for transmitter simplicity and high bandwidth utilizationefficiency [7]. Previous header/label extraction techniques useeither subcarrier-multiplexed [41] headers at lower rate [42],labels that are in a different state of polarization [43], or differ-ent modulations [44], [45]. As shown in Fig. 5, the incomingdata packets are wavelength converted, and the packet clockis recovered according the principle of operation describedin the previous section. The incoming data packets enter theSOA-MZI gate as input, and the packet clock is inserted asthe control signal defining the switching state of the gate thatis configured as a 1 × 2 crossbar switch. The packet clockis temporally synchronized only with the payload bits of thepackets at the input of the optical gate. As such, the payloadbits are switched (cross state), whereas the label bits remainunswitched (bar state), appearing separated at the output portof the SOA-MZI. Fig. 5(b) shows the experimental setup usedfor demonstrating the label/payload separation of 40-Gb/s shortoptical packets with variable length. A gain-switched DFB laserdiode emitting at 1553 nm was used to generate RZ pulsetrains with 2.5-ps temporal width after linear and nonlinearcompression stages. The pulse train was then modulated with

27 − 1 PRBS data into a Ti : LiNbO3 modulator (MOD 1).The data signal was multiplexed to 40 Gb/s using a two-stagecustom-made fiber multiplier (x4). 40-Gb/s wavelength con-version and all-optical CR are performed using the integratedSOA-MZI gates. The data packets and recovered clock signalsthen enter the third SOA-MZI switch with a temporal delay(ODL) equal to the label length. An additional CW laser source(LD1) was used as a pump signal to saturate the SOAs withinthe Mach–Zehnder structure in order to enhance the speed andnoise characteristics of the switch. Following label extraction,the separated payload and label signals were inserted into anEAM device configured as a demultiplexer in order to measurethe BER of each 10-Gb/s channel. Optical filters with 2-nmwidth were used at the output of the gates to remove out-of-band amplified spontaneous emission noise emitted by theSOAs, and the polarization of the signal was controlled foroptimum performance. Fig. 6 shows typical pulse traces andeye diagrams obtained using a 50-GHz sampling oscilloscope.Fig. 6(a) shows the incoming packet stream and correspondingeye diagram consisting of two short packets with payload lengthof 4.7 and 1.775 ns, respectively. Each packet has an 11-bitlabel including two preamble bits and 3 bits guard time betweenlabel and payload so as to take into account the rise time ofthe packet clock. Fig. 6(b) shows the corresponding recoveredclock packets that have a sharp rise time of 4 bits and a decaytime of 16 bits. Fig. 6(b) and (c) shows the extracted labeland payload bits along with the corresponding eye diagrams,


Fig. 6. (a), (b), (d), and (e) Traces and eye diagrams of input, wavelength-converted packets, extracted label, and forwarded payload, respectively.(c) Recovered clock packets with the beginning of the packet magnified to theinset on the right.

revealing contrast ratios of 8.4 and 8.6 dB, respectively. Theinput powers of the data packets and the packet clock were −17and −4 dBm, respectively. Fig. 7 shows the BER measurementsof the payload and label after demultiplexing in the EAM,triggered by a 10-GHz sinusoid signal.

Error-free operation was achieved for all the demultiplexedchannels, showing 1.2- and 1.8-dB normalized power penaltyfor the payload and label compared to the optical back-to-backcase, and no error floor is present. The power penalty is dueto the reduced extinction ratio in the third SOA-MZI gate dueto the simultaneous use of both output ports. This can be effec-tively removed using a simple SOA-MZI-based 2R regeneratorat the output of the AOLS node.

C. Optically Controlled Gating

Following 3R regeneration and label/payload separation, thelabel section enters the processing part of the network node,where routing decisions are made. Depending on the destina-tion address of each incoming data, suitable optical controlsignals are generated and used to drive the node switchingmatrix. Depending on the specific architecture of each OPS,

Fig. 7. BER measurements for each channel of incoming packets, respectiveswitched payload, and label.

Fig. 8. Block diagram of optically controlled (a) WC and (b) 1 × 2 crossbarswitch.

the switching matrix is constructed using either optically con-trolled WCs or optically controlled 1 × 2 space switches. Theblock diagram in Fig. 8 shows two different interconnectionsof an all-optical subsystem capable of optically controllingthe output state of an SOA-MZI gate. An optically controlledWC is shown in Fig. 8(a). The subsystem consists of an all-optical flip-flop cascaded with a WC. The specific subsystem iscapable of dynamically selecting the wavelength to which theoptical signal will be converted to with the help of the opticalflip-flop. The specific subsystem can operate as an all-opticalwavelength-based router, when the flip-flop is interconnected tothe processing core of an AOLS node such as the LASAGNE[7]. In the specific node, an array of label processors, configuredas XOR gates, compares the incoming label with the locallygenerated labels and produces a single matching pulse [46].This pulse is used to trigger the flip-flop and select the outputwavelength. Another application of the subsystem is towardall-optical contention resolution, as reported in [47]. In thisapproach, the concept of optically controlled WC is exploitedin order to detect two contenting packets and take the decisionon whether to buffer the lower-priority packet. Fig. 8(b) showsa different functionality, implemented by altering the intercon-nection of the flip-flop and the SOA-MZI optical gate. In thiscase, the WC is configured as a spatial 1 × 2 all-optical switchby inserting the flip-flop output as a control signal and theincoming data as input, as shown in Fig. 8(b). The subsystemfinds application to node designs where the switching matrix isconstructed using interconnected space switches, as reported inthe ARTEMIS node [8].


Fig. 9. Developed flip-flop using hybrid technology. (a) Schematic of flip-flop. (b) Planar silica motherboard. (c) Daughterboard with twin SOAs flippedchipped and wirebonded. (d) Packaged and pigtailed prototype. (Color versionavailable online at http://ieeexplore.ieee.org.)

1) All-Optical MZI Flip-Flop: The flip-flop device is basedon two coupled MZI gates, as shown in Fig. 9(a), in order toobtain very fast switching time. Each gate is powered by oneCW signal, forming a bistable element with two wavelengthstates. Toggling between states is achieved by injecting a pulsedsignal to one of the two gates to “set” the device and a delayedversion to “reset” to the previous state. The delay between setand reset pulses defines the duration for which the device isin the set state, and for the AOLS scenario, it is equal to thepacket length. A prototype device comprising two flip-flops ona single chip was fabricated by C.I.P. U.K. Fig. 9(b) shows thesilica waveguide motherboard showing the two MZI structuresused for flip-flop operation. Fig. 9(c) shows the precision-diced daughterboard with flip-chipped twin SOA devices, andFig. 9(d) shows the pigtailed and packaged device used in thesystem experiment.

2) All-Optical Wavelength Routing: Fig. 10 shows the ex-perimental setup for the optically controlled WC used todemonstrate the concept of all-optical routing. The flip-flopprototype was interconnected with an SOA-MZI optical gateconfigured as a WC. Two CW optical sources emitting at 1559and 1562 nm were used for providing the two states to the opti-cal flip-flop prototype. A pulsed signal (TX) was also generatedby modulating a CW laser emitting at 1565 nm that acted as thecontrol pulse providing the SET and RESET signals. The signalhad a pulse width of 400 ps and a period of 13 ns. The flip-flop output was connected to the WC, which was realized usingan SOA-MZI gate operated in push–pull mode. A counter-propagating holding beam (CW3) was also used for removingtransients within the SOAs and reshaping the generated CWsignal from the flip-flop. Finally, a 40-Gb/s pattern generatorwas used to modulate PRBS data on short pulses providedby a pulse generating laser. Depending on the measurement

required, the pattern generator was programmed to producecontinuous or packet-mode 40-Gb/s data. Figs. 11 and 12 showthe experimental results of the subsystem for demonstrating theall-optical routing functionality. In order to assess the qualityof the CW signal provided by the flip-flop, static BER mea-surements were carried out using continuous 40-Gb/s PRBSdata. Specifically, the flip-flop state was controlled so as eitherthe 1559 or 1562 nm was the dominant state. Fig. 11 showsthe BER measurements for wavelength conversion using CWlight from a tunable laser source and from CW light providedby the flip-flop for both wavelengths. The power penalty wasmeasured to be less than 1.6 dB for both cases. The flip-flopwas also operated using the pulsed signal to achieve dynamicswitching between states. The RESET pulse was delayed 2 nswith respect to the SET pulse, corresponding to the durationof a single packet. Data packets were produced by program-ming the 40-Gb/s pattern generator to produce 1.6-ns packetsseparated by 2.7 ns. Fig. 12 shows oscilloscope traces show-ing all-optical routing. Fig. 12(a) shows the incoming datapackets, and Fig. 12(b) shows the generated CW block fromthe optical flip-flop, when triggered by the SET and RESETpulses. Finally, Fig. 12(c) shows the corresponding wavelength-converted packets. The flip-flop exhibited an extinction ratio of8.5 dB, which was the main reason of crosstalk from the re-maining packets. The SOAs were driven with 150 and 340 mAin the flip-flop and the WC, respectively.

IV. PHOTONIC INTEGRATION PROGRESS

The evolution from single-gate experiments to more complexall-optical subsystems was made possible due to the devel-opment of compact SOA-MZI-based optical gates and flip-flops, exploiting a unified integration platform based on hybridtechnology [19]. The photonic platform relies on the designand development of a planar silica waveguide acting as amotherboard, which is capable of hosting active and passivedevices, similar to the electronic printed circuit board used inelectronics. The active elements of the device are independentlydeveloped on precision-machined silicon submounts or “daugh-terboards.” In the case of the development of SOA-MZI opticalgates, the daughterboards are designed to host monolithic SOAchips and provide all suitable alignment stops. Fig. 13 showsphotographs of photonic integrated prototype devices alongwith the corresponding schematic designs. The single pigtailedSOA-MZI optical gate is shown in Fig. 13(a) along with themotherboard design shown in Fig. 13(b). The daughterboardconsists of a double SOA array and is flip chipped onto themotherboard. The first milestone on the development of all-optical subsystems is reached by verifying that discrete, yetintegrated and compact, all-optical gates can be interconnected,producing all-optical circuits with increased functionality andintelligence. The next milestone involves the integration ofgeneric optical gates on the same hybrid platform in order toreduce packaging costs and increase photonic integration level.Fig. 13(d) shows the photograph of a quadruple array of opticalgates recently integrated using hybrid integration technology.The corresponding motherboard design is shown in Fig. 13(e)with two daughterboards clearly marked. In this case, each


Fig. 10. Experimental setup of 40-Gb/s optically controlled WC.

Fig. 11. BER measurements for static flip-flop operation.

daughterboard hosts a quad array of SOAs, forming two SOA-MZI optical gates. The next logical step, on this migration path,lies at the photonic integration level. Next-generation photonicintegrated devices must include on-chip interconnections andintegration of different optical components on a single chip.These devices will pave the way toward the development oftrue all-optical systems-on-chip, reducing both packaging andpigtailing costs while retaining cost effectiveness by exploitinga unified integration platform for a variety of all-optical devices.Toward this milestone, research work has already commencedreporting devices for WDM applications containing SOA-MZIregenerator and a passband filter [48] on single chip. Theachievable photonic integration level at any given time willbe defined through the interplay between the monolithic tech-nology developed and the hybrid platform capabilities. Hybridintegration is used for increasing integration scale and func-tionality while maintaining high yield and cost effectivenessthrough integration of passive elements such as filters, isolators,and arrayed waveguide gratings onto a single platform. Theadvent of monolithic technology toward the development oflarger monolithic chips will allow for constantly upgrading the

Fig. 12. Eye patterns showing all-optical routing. (a) Incoming packets.(b) Flip-flop output. (c) Routed packets.

fundamental active element of the developed photonic plat-forms and thus increasing chip integration scale and density.As the monolithic scale of integration increases and acceptableyields are achieved, the penetration of monolithic technologyon the hybrid platform will be increased. This will eventuallylead to an increase of integration density and more complex on-chip functionality while maintaining high yield and further costreduction.

V. CONCLUSION

We have demonstrated 40-Gb/s all-optical network subsys-tems showing that intelligent functionalities can be performeddirectly in the optical layer by functional interconnection of in-tegrated SOA-MZI optical gates. Successful 40-Gb/s all-optical


Fig. 13. (a) Packaged and pigtailed SOA-MZI optical gate. (b) Corresponding motherboard design and (c) twin SOA silicon submounts. (d) Packaged andpigtailed prototype device containing four SOA-MZI optical gates on a single photonic chip. (e) Motherboard design and (f) quad array of SOAs used forconstructing each double SOA-MZI gate within the chip. (Color version available online at http://ieeexplore.ieee.org.)

3R regeneration, label/payload separation, and all-opticalpacket routing were shown operating with packet-mode trafficexploiting fast switching prototypes based on hybrid integrationtechnology. The intelligence offered by the proposed networksubsystems combined with the flexibility and adaptability ofthe photonic integration platform can pave the way towardcost-optimized high-speed photonic systems-on-chip.

ACKNOWLEDGMENT

The authors would like to thank the technical staff at C.I.P.for fabrication, testing, and packaging of the SOAs, SOA-MZIs,flip-flops, and EAMs.

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Efstratios Kehayas (S’03) received the B.Eng.degree in electronic engineering from the Schoolof Electronics and Computer Science, University ofSouthampton, Southampton, U.K., in 2001 and theM.Sc. degree in optics and photonics from ImperialCollege, London, U.K., in 2002.

Since 2002, he has been with the Photonics Com-munications Research Laboratory, National Tech-nical University of Athens, Athens, Greece. Hisresearch field includes implementation of all-opticallogic devices, development of advanced optical sig-

nal processing subsystems, and high-speed optical/dense time-division multi-plexing (OTDM/DWDM) optical sources.

Dimitris Tsiokos (S’03) received the B.Eng. de-gree in electronics engineering from the School ofElectronics and Computer Science, University ofSouthampton, Southampton, U.K., in 2001 and theM.Sc. degree in photonics from Imperial College,London, U.K., in 2002. He is currently workingtoward the Ph.D. degree at the Photonics Commu-nications Research Laboratory, Athens, Greece.

His research interests involve the design and de-velopment of novel all-optical circuits for ultrahigh-speed photonic networks.

Paraskevas Bakopoulos, photograph and biography not available at the timeof publication.

Dimitris Apostolopoulos, photograph and biography not available at the timeof publication.

Dimitrios Petrantonakis, photograph and biography not available at the timeof publication.

Leontios Stampoulidis, photograph and biography not available at the time ofpublication.

Alistair Poustie, photograph and biography not available at the time of publi-cation.

Rob McDougall, photograph and biography not available at the time ofpublication.

Graeme Maxwell, photograph and biography not available at the time ofpublication.

Yong Liu, photograph and biography not available at the time of publication.

Shaoxian Zhang, photograph and biography not available at the time ofpublication.

Harmen J. S. Dorren (M’04), photograph and biography not available at thetime of publication.

Jorge Seoane (S’97–M’99), photograph and biography not available at the timeof publication.

Pablo Van Holm-Nielsen, photograph and biography not available at the timeof publication.

Palle Jeppesen (M’69), photograph and biography not available at the time ofpublication.

Hercules Avramopoulos, photograph and biography not available at the timeof publication.

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40-Gb/s All-Optical Processing Systems Using Hybrid