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7725 N. Orange Blossom Trail • Orlando, FL 32810 • 407.298.7100 • [email protected] • www.micross.com
February 4, 2016 • Rev is ion 1.1
Form #: CSI-D-686 Document: 020
Features•Tin-leadballmetalurgy•VDD=VDDQ=1.2V±60mV•VPP=2.5V,–125mV/+250mV•On-die,internal,adjustableVREFDQgeneration•1.2Vpseudoopen-drainI/O•TCof0°Cto95°C
–64ms,8192-cyclerefreshat0°Cto85°C–32msat85°Cto95°C
•8internalbanks(x16):2groupsof4bankseach•8n-bitprefetcharchitecture•Programmabledatastrobepreambles•Datastrobepreambletraining•Command/Addresslatency(CAL)•MultipurposeregisterREADandWRITEcapability•Writeandreadleveling•Selfrefreshmode•Low-powerautoselfrefresh(LPASR)•Temperaturecontrolledrefresh(TCR)•Finegranularityrefresh•Selfrefreshabort•Maximumpowersaving•Outputdrivercalibration•Nominal,park,anddynamicon-dietermination(ODT)•Databusinversion(DBI)fordatabus•Command/Address(CA)parity•Databuswritecyclicredundancycheck(CRC)
Options Code
• Configuration •256Mx16 256M16
• Package:FBGA(Sn63Pb37solder) BG •Foorprint:96-ball(9mmx14mm) GE
• Timing-cycletime •0.750ns@CL=18(DDR4-2666) 75E
• Operatingtemperature •Industrial(-40°C≤TC≤+95°C) IT
• PartMarking:Label(L),Dot(D)
4Gb - 256M x 16 DDR4 SDRAMAdvanced information. Subject to change without notice.
*Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-75E 2666 18-18-18 13.5
MYX4DDR4256M16GE
Form #: CSI-D-686 Document 007
Micross US (Americas) 407.298.7100 • Micross UK (EMEA & ROW) +44 (0) 1603 788967 • [email protected] • www.micross.com
November 16, 2015 • Revision 2.1
MYX4DDR364M16JT
Features• Tin-lead ball metallurgy
• VDD = VDDQ = 1.35V (1.283-1.45V)
• Backward-compatible to VCC = VCCQ = 1.5V ±0.075V
• 1.35V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• Programmable CAS ADDITIVE latency (AL)
• Programmable CAS WRITE latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of -40°C to 105°C
� 64ms, 8192 cycle refresh at -40°C to 85°C
� 32ms, 8192 cycle refresh at 85°C to 105°C
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options Code
• Configuration
� 64M x 16 64M16
• Package: FBGA (Sn63 Pb37 solder) BG
� Footprint: 96-ball (8mm x 14mm) TW
• Timing - cycle time
� 1.5ns @ CL = 13 (DDR3-1866) -107
• Operating temperature
� Industrial (-40°C ≤ TC ≤ +95°C) IT
� Enhanced (-40°C ≤ TC ≤ +105°C) ET
• Part Marking: Label (L), Dot (D)
1Gb - 64M x 16 DDR3 SDRAMAdvanced information. Subject to change without notice.
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-107 1866 13-13-13 13.91
Micron Part. No. MT41K64M16TW-107AIT:J for the IT temp version
Micron Part No. MT41K64M16TW-107AAT:J for the ET temp versionMicron Part No. MT40A256M16GE-075E IT:B
•Per-DRAMaddressability•Connectivitytest(x16)•Postpackagerepair(PPR)andsoftpostpackage
repair(sPPR)modes• JEDECJESD-79-4compliant
7725 N. Orange Blossom Trail, Orlando, FL 32810407.298.7100 • [email protected] • www.micross.com
4Gb - 256M x 16 DDR4 SDRAMAdvanced information. Subject to change without notice.
Figure 1: 96-Ball FBGA (Top View), TW
Figure 2: Package Dimensions 96-Ball FBGA Package - x16 (TW)
Notes: 1. All dimensions are in millimeters. 2. Solder ball material: Sn63/Pb37 3. Micron – MT40A256M16
Figure 2: 96-Ball x16 Ball Assignments
1 2 3 4 6 7 8 95
VDDQ
VPP
VDDQ
VDD
VSS
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VREFCA
VSS
RESET_n
VDD
VSS
VSSQ
VSS
DQ12
VSSQ
VDDQ
DQ0
DQ4
VDDQ
CKE
WE_n/A14
BG0
BA0
A6
A8
A11
DQ8
VDD
DQ10
DQ14
VSSQ
LDQS_c
LDQS_t
DQ2
DQ6
ODT
ACT_n
A10/AP
A4
A0
A2
PAR
UDQS_c
UDQS_t
DQ11
DQ15
DQ1
VDD
DQ3
DQ7
CK_t
CS_n
A12/BC_n
A3
A1
A9
NC
VSSQ
DQ9
DQ13
VSSQ
VSSQ
VDDQ
VSS
DQ5
VDDQ
CK_c
RAS_n/A16
CAS-n/A15
BA1
A5
A7
A13
VDDQ
VDD
VSSQ
VDDQ
VSS
ZQ
VDDQ
VSSQ
VDD
VSS
VDD
VSS
TEN
VPP
VDD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
NF/LDM_n/LDBI_n
ALERT_n
NF/UDM_n/UDBI_n
Notes: 1. See Ball Descriptions.2. A slash “/” defines a selectable function. For example: Ball E7 = NF/LDM_n. If data mask
is enabled via the MRS, ball E7 = LDM_n. If data mask is disabled in the MRS, E7 = NF (nofunction).
3. Address bits (including bank groups) are density- and configuration-dependent (see Ad-dressing).
4Gb: x4, x8, x16 DDR4 SDRAMBall Assignments
PDF: 09005aef84af6dd04gb_ddr4_dram.pdf - Rev. E 11/15 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Figure 6: 96-Ball FBGA – x16 "GE"
1.8 CTRNonconductive
overmold
0.155
Seating plane
0.12 A
Ball A1 ID(covered by SR)
Ball A1 ID
A
0.29 MIN
1.1 ±0.1
6.4 CTR
9 ±0.1
0.8 TYP
12 CTR
14 ±0.1
96X Ø0.47Dimensions applyto solder balls post-reflow on Ø0.42 SMDball pads.
0.8 TYP
123789
ABCDEFGHJKLMNPRT
Notes: 1. All dimensions are in millimeters.2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
4Gb: x4, x8, x16 DDR4 SDRAMPackage Dimensions
PDF: 09005aef84af6dd04gb_ddr4_dram.pdf - Rev. E 11/15 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Figure 6: 96-Ball FBGA – x16 "GE"
1.8 CTRNonconductive
overmold
0.155
Seating plane
0.12 A
Ball A1 ID(covered by SR)
Ball A1 ID
A
0.29 MIN
1.1 ±0.1
6.4 CTR
9 ±0.1
0.8 TYP
12 CTR
14 ±0.1
96X Ø0.47Dimensions applyto solder balls post-reflow on Ø0.42 SMDball pads.
0.8 TYP
123789
ABCDEFGHJKLMNPRT
Notes: 1. All dimensions are in millimeters.2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu).
4Gb: x4, x8, x16 DDR4 SDRAMPackage Dimensions
PDF: 09005aef84af6dd04gb_ddr4_dram.pdf - Rev. E 11/15 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.