5 4 3 2 1 D D DJ1 Montevina UMA Schematics Document uFCPGA … · 2014. 1. 7. · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Wistron Corporation

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Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

DJ1 Montevina UMA A00Cover Page

A3

1 88Wednesday, February 24, 2010

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DJ1

Intel GM45+ICH9M

2010-02-10

REV : A00

DJ1 Montevina UMA Schematics Document

uFCPGA Mobile Penryn

DY : Nopop Component

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DJ1 Montevina UMA A00

Block Diagram


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Block Diagram


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Block Diagram


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26

DJ1 Montevina UMA Block Diagram

+0.75V_DDR_VTT

+3.3V_RTC_LDO

TPS51620INPUTS

+VCC_CORE

OUTPUTS

SYSTEM DC/DCTPS51116

+V_DDR_REF

OUTPUTS

CPU DC/DC

+PWR_SRC

+1.5V_SUS

INPUTS

TPS51125

+PWR_SRC+5V_ALW

OUTPUTS

+3.3V_ALW

TPS51218

+1.05V_VCCP

OUTPUTS

SYSTEM DC/DC

INPUTS

+PWR_SRC

INPUTS

SYSTEM DC/DC

+1.5V_RUN

OUTPUTSBQ24745

INPUTS

MAXIM CHARGER

+PWR_SRC+PBATT

+5V_ALW2

+DC_IN

+5V_RUN

26

+5V_ALW+3.3V_RUN+3.3V_ALW

L6: Bottom

L5: GND

+PWR_SRC

PCB LAYER

L3: Signal

L4: Signal

L2: VCC

L1: Top

+1.5V_SUS

SYSTEM DC/DCSwitches

INPUTS OUTPUTS

+15V_ALW

46

47

49

50

42

Project code : 91.4EK01.001PCB P/N : 48.4EK06.0SARevision : 09275-SA

IDT92HD79B1

EMC2102

DMIx4 C-LINK10/100 NIC

PCIE x 2

Atheros RJ45CONN

I/O Board

Connector

Left Side:USB x 1

60

70

60

60

60

AR8132

KBC

ThermalInt. KB

LPC Bus

2MBFlash ROM

Intel Mobile CPU

DDRIII800/1066

DDRIII 800/1066 Channel A Slot 0

8,9

Slot 119

18

Socket P

Intel

10,11,12,13,14,15

75

FSB800/1066MHz

AGTL + CPU I/FDDR Memory I/F

PCIE

External Graphics

63

CAMERA 54

Right Side:USB x 2

USB 2.0 x 1

USB 2.0 x 2

USB 2.0

CRT

LVDS(Dual Channel)LCD

Penryn

RGB CRT

Intel

5959

SATA

ODD

USB 2.0/1.1 ports (12)

ICH9-MSATA

High Definition AudioSATA ports (4)

LPC I/FACPI 1.1

HDD

PCI/PCI BRIDGE

32

CardReader

RealtekRTS5138

SD/MMC/MS/MS Pro/xD

USB2.0

AzaliaCODEC

AZALIA

2CH SPEAKER

30HP1

MIC IN

Internal Analog MIC

55

NPCE781BA0DXNUVOTON

SPI

39

PCI Express ports (8)

USB 2.0 x 1

58Fan

DDRIII 800/1066 Channel B DDRIII800/1066

Clock Generator

54

7

SLG8SP513VTR

37

6267 25

20,21,22,23

67

TouchPAD

GM45

SATA

Bluetooth 72USB 2.0 x 1

802.11a/b/gMini-Card

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5

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4

3

3

2

2

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B B

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DJ1 Montevina UMA A00Power Block Diagram

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Charger

BQ24745

+VCHGR

Adapter

Battery

TPS51125

50

+5V_ALW2

Regulator LDO Switch

+5V_ALW+3.3V_RTC_LDO

SI4800

+5V_RUN

G547F2P81U

+5V_USB1

+3.3V_ALW

TPS51620

47

+VCC_CORE

46 46

TPS51218

+1.05V_VCCP

+PWR_SRC

TPS51116

+0.75V_DDR_VTT+V_DDR_REF

+1.5V_RUN

+1.5V_SUS

63

Power Shape

63

DJ1 Montevina UMA Power Block Diagram

46

42

G547F2P81U

+5V_USB2

G9091

+3.3V_CRT_LDO

FDS8880

+3.3V_RUN

RTS5159

+3.3V_RUN_CARD

G5285T11U

+LCDVDD

49

50

FSD8880

15

50

46+15V_ALW

46

42

42

5432

RT9198

+1.8V_NB_S0

15

PA102

+3.3V_LAN

RTL8103T

+1.2V_LOM

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

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DJ1 Montevina UMA A00SMBUS Block Diagram

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LDDC_CLK

LDDC_DATA

+3.3V_RUN

�

�

�

TPDATA

TPCLK

+5V_RUN

�

�

�

TouchPad Conn.TPDATA

TPCLKPSCLK1

PSDAT1

VGA

LCD CONN

ICH SMBus Block Diagram

ICHSMBCLK

SMBDATA

GPIO62/SDA2

GPIO61/SCL2

KBC

CLK_SMB

ThermalSCL

SDA

+3.3V_RUN

�

SRN4K7J-8-GP

+3.3V_ALW

�

�

�

SRN4K7J-8-GP

+3.3V_RUN

2N7002SPT

�

�

�

DAT_SMB

KBC_SCL1

KBC_SDA1

DDC1DATA

DDC1CLK

MinicardWLANSMB_DATA

SMB_CLK

SCL1

SDA1

BAT_SCL

BAT_SDA

SMBus address:D2

SMBus Address:A0

SMBus Address:A4

DIMM 1SCL

SDA

+KBC_PWR

�DIMM 2SCL

SDA

SMBus address:16

SMB_CLK

SMB_DATA

ICH_SMBCLK

ICH_SMBDATA

PBAT_SMBCLK1

PBAT_SMBDAT1

KBC SMBus Block Diagram

Battery Conn.

ICH_SMBCLK

ICH_SMBDATA

ClockGeneratorSCLK

SDATA

ICH_SMBCLK

ICH_SMBDATA BQ24745SCL

SDA

TPDATA

TPCLK

+3.3V_RUN

2N7002DW-1-GP

�

THERM_SCL

THERM_SDA

SMBus address:7A

ICH_SMBDATA

ICH_SMBCLK

�

�

SMBus address:12

+3.3V_RUN

�

�

�

+3.3V_RUN

2N7002DW-1-GP

�

�

�

+3.3V_RUN

�

SRN2K2J-1-GP

�

�

+5V_CRT_RUN

�

SRN2K2J-1-GP

CRT CONNDDC_CLK_CONDDC_DATA_CONGMCH_DDCCLK

GMCH_DDCDATA

DDC2CLK

DDC2DATA

SRN10KJ-5-GP

SRN4K7J-8-GP

SRN4K7J-8-GP

+KBC_PWR

�

SRN4K7J-8-GP

SRN2K2J-1-GP

NPCE781BA0DX

SRN100J-3-GP

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

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DJ1 Montevina UMA A00Thermal/Audio Block Diagram

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Thermal Block Diagram

ThermalEMC2102

DP1

DN1

SC470P50V3JN-2GP

DP2

DN2

DP3

DN3

Audio Block Diagram

Codec

92HD79B1

HP

OUT

MIC

IN

2CH SPEAKERS

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

SPKR_PORT_D_L-/L+

EMC2102_DP3

EMC2102_DN3

PMBS3904-1-GP

HP1_PORT_B_L

HP1_PORT_B_R

AnalogMIC

PORTC_L

PORTC_R

VREFOUT_C

SC470P50V3JN-2GP

HW T8 sensor

EMC2102_DP2

EMC2102_DN2

H_THERMDA

H_THERMDC

SC470P50V3JN-2GP

THRMDC

THRMDACPU

SC470P50V3JN-2GPPMBS3904-1-GP

Put between CPU and NB

SPKR_PORT_D_R-/R+

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

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DJ1 Montevina UMA A00Table of Content

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USB Table

PCIE Routing

LANE2

LANE3 LAN

MiniCard WLAN

LANE1

10

11

RESERVED

USB3

CAMERA

WLAN

USB1 (I/O Board 17")

USB Pair

4

5

0

2

3

1

Device

6

7

8

9

USB0 (I/O Board)

Card Reader

RESERVED

RESERVED

USB2

This signal has a weak internal pull-down.NOTE: This signal should not be pulled high

GNT1#/GPIO51

ESI Strap (Server Only),Rising Edge of PWROK.

Tying this strap low configures DMI for ESIcompatibleoperation. This signal has a weak internalpull-up.NOTE: ESI compatible mode is for server platformsonly. This signal should not be pulled low fordesktop and mobile.

GNT3#/GPIO55

Top-Block Swap override. Rising Edgeof PWROK.

Sampled low: this indicates that the system is strapped to the “top-block swap”mode (IntelR ICH9 inverts A16 for all cycles targeting BIOS space). The status of this strap is readable via the Top Swap bit(Chipset Config Registers:Offset 3414h:bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

GNT0#Boot BIOS DestinationSelection 1,Rising Edge of PWROK.

Controllable via Boot BIOS Destinationbit (Chipset Config Registers:Offset 3410h:bit 11).This strap is used in conjunction with Boot BIOSDestination Selection 0 strap.

SPI_CS1#/GPIO58

Boot BIOS DestinationSelection 0,Rising Edge of CLPWROK.

Controllable via Boot BIOS Destinationbit (Chipset Config Registers:Offset 3410h:bit 10).This strap is used in conjunction with Boot BIOSDestination Selection 1 strap.

GPIO49DMI TerminationVoltage. Rising Edgeof CLPWROK.

The signal is required to be high for mobile applications.

Bit11(GNT0#)

Bit 10(SPI_CS1#)

Boot BIOSDestination

0 1 SPI1 0 PCI1 1 LPC0 0 Reserved

SPI_MOSI(Moble Only)

Integrated TPMEnable. Rising Edgeof CLPWROK.

Sampled low: the Integrated TPM will be disabled.Sampled high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enabled.NOTE: This signal is required to be floating or pulledlow for desktop applications.

Bit11(GNT0#)

Bit 10(SPI_CS1#)

Boot BIOSDestination

0 1 SPI1 0 PCI1 1 LPC0 0 Reserved

HDA_SDOUT

SignalXOR Chain Entrance / PCI Express* Port Config 1 bit 1 (Port 1-4), Rising Edge of PWROK

Usage/When Sampled

Allows entrance to XOR Chain testing when TP3pulled low at rising edge of PWROK. When TP3 not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Config Registers: Offset 224h).This signal has a weak internal pull-down.

Comment

SATALED# PCI Express Lane Reversal (Lanes 1-4). Rising Edge of PWROK.

Signal has weak internal pull-up. Sets bit 27 ofMPC.LR (Device 28: Function 0: Offset D8)

SPKRNo Reboot, Rising Edge of PWROK.

Sampled high: this indicates that the systemis strapped to the “No Reboot” mode (ICH9 willdisable the TCO Timer system reboot feature). Thestatus of this strap is readable via the NO REBOOTbit (Chipset Config Registers:Offset 3410h:bit 5).

TP3

ICH9 EDS 642879 Rev.2.3

HDA_SYNC PCI Express Port Config 1 bit 0 (Port 1-4),Rising Edge of PWROK.

This signal has a weak internal pull-down.Sets bit 0 of RPC.PC (Chipset Config Registers:Offset 224h)

GNT2#/GPIO53

PCI Express Port Config 2 bit 2 (Port 5-6), Rising Edge of PWROK

This signal has a weak internal pull-up.Sets bit 2 of RPC.PC2 (Chipset ConfigRegisters:Offset 0224h) when sampled low.

GPIO20 Reserved, Rising Edge of PWROK

GPIO33 /HDA_DOCK_EN# (Mobile Only)

Flash DescriptorSecurity Override Strap. Rising Edge of PWROK.

Sampled low: the Flash Descriptor Security will beoverridden. Sampled high: the security measures will bein effect. This strap should only be enabled inmanufacturing environments.

ICH9M Functional Strap Definitions

XOR Chain Entrance.Rising Edge of PWROK.

This signal should not be pull low unless usingXOR Chain testing.

LDRQ1 / GPIO23

LAN_RXD[2:0]

SATALED#

PWRBTN#

PME#

SPI_MOSI

USB[11:0][P,N]

SPI_CS1# / GPIO58 (Desktop Only) /CLGPIO6 (Digital Office Only)

SPKR

TP3

PULL-UP 20K

PULL-DOWN 15K

PULL-DOWN 20K

TACH[3:0]

SPI_MISO

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 15K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-UP 20K

ICH9 EDS 642879 Rev.2.3

CL_CLK[1:0]

DPRSLPVR/GPIO16

CL_RST0#

CL_DATA[1:0]

HDA_DOCK_EN#/GPIO33

PULL-UP 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

GPIO49

PULL-DOWN 20K

PULL-DOWN 20K

SIGNAL

ICH9 Integrated pull-upand pull-down Resistors

PULL-UP 10K

HDA_SDIN[3:0]

HDA_RST#

HDA_BIT_CLK

Resistor Type/Value

LDRQ0

LAD[3:0]# / FHW[3:0]#

GPIO20

GNT0#, GNT[3:1]#/GPIO[55,53,51]

HDA_SYNC

HDA_SDOUT

Montevina Platform Design guide 355648 Rev.2.3

CFG10 PCIE Loopback enable 0 = Enable (Note 3)1 = Disable (Default)

NOTE:

1. All strap signals are sampled with respect to the leading edge of the GMCH Power OK(PWROK) signal.2. iTPM can be disabled by a ‘Soft-Strap’ option in the Flash-descriptor section of theFirmware. This ‘Soft-Strap’ is activated only after enabling iTPM via CFG6.3. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.4. DDPC_CTRL_DATA & SDVO_CTRL_DATA straps should both be high to enable Display Port.

000 = FSB1066010 = FSB800011 = FSB667Others = Reserved

CFG4:3CFG8CFG11CFG14CFG15CFG17CFG18

CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled1 = Dynamic ODT Enabled (Default)

Pin Name Strap Description Configuration

0 = The iTPM Host Interface is enabled (Note 2)

CFG2:0 FSB Frequency

Reserved

CFG5 DMI x2 Select 0 = DMI x21 = DMI x4 (Default)

CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered inOrder

1 = Reverse LanesDMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)DMI x2 mode [MCH->ICH]: (3->0, 2->1)

CFG6 ITPM Host Interface1 = The iTPM Host Interface is disabled (default)

CFG7 Intel Managementengine crypto strap

CFG9

CFG20Digital Display Port(SDVO/DP/HDMI)Concurrent with PCIe

0 = Only digital DisplayPort (SDVO/DP/HDMI) orPCIe is operational (default)1 = Digital DisplayPort (SDVO/DP/HDMI) andPCIe are operating simultaneously via the PEG port

SDVO_CTRLDATA(Note4)

SDVO Present

Cantiga chipset and ICH9M I/O controllerHub strapping configuration

0 = Intel Management Engine Crypto TransportLayer Security (TLS) cipher suite with no confidentiality1 = Intel Management Engine Crypto TLS ciphersuite with confidentiality (default)

PCIE Graphics Lane

0 = No SDVO/HDMI/DP interface disabled (default)1 = SDVO/HDMI/DP interface enabled

L_DDC_DATA Local Flat Panel(LFP) Present

0 = LFP Disabled (Default)

1 = LFP Card Present; PCIE disabled

0 = Reverse Lanes, 15->0, 14->1 etc.1 = Normal operation (default): Lane Numberedin Order

CFG12 ALLZ 0 =ALLZ mode enabled (Note 3)

1 = Disable (Default)

CFG13 XOR0 = XOR mode enabled (Note 3)1 = Disable (Default)

DDPC_CTRLDATA(Note4)

Digital DisplayPresent

0 = Digital display (HDMI/DP) device absent (default)1 = Digital display (HDMI/DP) Device Present

RESERVED

BLUETOOTH

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MINI1_CLKREQ#

CLK_PCIE_MINI1

CLK_CPU_BCLK#

CLK_MCH_BCLK#

CLK_CPU_BCLK

CLK_PCIE_ICH#

CLK_PCIE_LAN

CLK_PCIE_SATA

PCI2_TME

FSB

FSA

PCI2_TME

CLK_XTAL_OUT

CLKSATAREQ#

27_SELITP_EN

FSB

FSA

FSC

ITP_EN

CLK_XTAL_IN

CLKREQ#_1

FSC

CLK_MCH_DREFCLK#

MCH_SSCDREFCLK#

CLK_MCH_DREFCLK

27_SEL

MCH_SSCDREFCLKMCH_SSCDREFCLK

CLK_PCIE_LAN#CLK_PCIE_LAN#

CLK_MCH_BCLKCLK_MCH_BCLK

CLK_PCIE_MINI1#CLK_PCIE_MINI1#

CLK_MCH_3GPLL#CLK_MCH_3GPLL#

CLK_PCIE_SATA#CLK_PCIE_SATA#

CLK_MCH_3GPLLCLK_MCH_3GPLL

CLK_PCIE_ICHCLK_PCIE_ICH

3D3V_S0_CK505

+3.3V_RUN 3D3V_S0_CK505

1D05V_CK505_IO

3D3V_S0_CK505

1D05V_CK505_IO3D3V_S0_CK505+1.05V_VCCP +3.3V_RUN

CLK_PCIE_MINI1# 76CLK_PCIE_MINI1 76

CLK_48M_CARD32

PCLK_FWH58

CLK_CPU_BCLK 8CLK_CPU_BCLK# 8

CLK_MCH_BCLK# 10CLK_MCH_BCLK 10

CLK_48M_ICH22

H_STP_PCI#22H_STP_CPU#22

ICH_SMBCLK18,19,22,76ICH_SMBDATA18,19,22,76

CK_PWRGD22

CLKSATAREQ#22CLKREQ#_B11

PCLK_KBC37CLK_PCI_ICH21

CLK_14M_ICH22

CPU_BSEL28

CPU_BSEL18

CPU_BSEL08

MCH_CLKSEL0 11

MCH_CLKSEL1 11

MCH_CLKSEL2 11

CLK_PCIE_ICH# 21CLK_PCIE_ICH 21

CLK_MCH_3GPLL# 11CLK_MCH_3GPLL 11

CLK_PCIE_SATA# 20CLK_PCIE_SATA 20

CLK_PCIE_LAN 76CLK_PCIE_LAN# 76

MINI1_CLKREQ# 76

MCH_SSCDREFCLK# 11MCH_SSCDREFCLK 11

CLK_MCH_DREFCLK# 11CLK_MCH_DREFCLK 11

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DJ1 Montevina UMA A00Clock Generator SLG8SP513VTR

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PCI2_TME Output

0

1

Overclocking of CPU and SRC allowed

Overclocking of CPU and SRC not allowed

ITP_EN Output

0 SRC81 CPU_ITP

SSID = CLOCK

SEL1FSB

SEL0FSA

133M100M

166M800M

0 101 X

667M200M

0 1

CPUSEL2FSC

FSB

0 10

101

1067M266M0 0 0

533M

100M1 27M

27_SEL PIN24/25

96M0 100M

PIN20/21

12

R715Do Not StuffDY R715Do Not StuffDY

1 2R711 33R2J-2-GPR711 33R2J-2-GP

1 2C712 Do Not StuffDYC712 Do Not StuffDY

1 2R709 33R2J-2-GPR709 33R2J-2-GP

12

C70

8SC

D1U

16V2

KX-3

GP

C70

8SC

D1U

16V2

KX-3

GP

12

C71

3SC

1U10

V3KX

-3G

PC

713

SC1U

10V3

KX-3

GP

12

C70

9SC

D1U

16V2

KX-3

GP

C70

9SC

D1U

16V2

KX-3

GP

1 2X701

X-14D31818M-37GP

X701

X-14D31818M-37GP 12

C711

SC15P50V2JN-2-GP

C711

SC15P50V2JN-2-GP1

2

C71

5SC

D1U

16V2

KX-3

GP

C71

5SC

D1U

16V2

KX-3

GP

VSS_

REF

1

XOUT2XN3

VDD_

REF

4

REF0/FSC/TEST_SEL5

SDATA6SCLK7

PCI0/CR#_A8

VDD_

PCI

9

PCI1/CR#_B10PCI2/TME11PCI312PCI4/GCLK_SEL13PCIF0/ITP_EN14

VSS_

PCI

15VD

D_48

16

USB_48/FSA17

VSS_

4818

VDD_

IO19

VSS_

IO22

VDD_

PLL3

23

VSS_

PLL3

26VD

D_PL

L3_I

O27

VSS_

SRC

30

VDD_

SRC_

IO33

VSS_

SRC

36

SRCC1/CR#_G 39SRCT1/CR#_H 40

SRCT10 41SRCC10 42

VDD_

SRC_

IO43

CPU_STOP#44PC_STOP#45

VDD_

SRC

46

SRCC6 47SRCT6 48

VSS_

SRC

49

SRCC7/CR#_E 50SRCT7/CR#_F 51

VDD_

SRC_

IO52

SRCC8/CPU2_ITPC 53SRCT8/CPU2_ITPT 54

NC#5555

VDD_

CPU_

IO56

CPUC1 57CPUT1 58

VSS_

CPU

59

CPUC0 60CPUT0 61

VDD_

CPU

62

CKPWRGD/PWRDWN#63

FSB/TEST_MODE64

GND

65

SRCT9 37SRCC9 38

SRCT4 34SRCC4 35

SRCT3/CR#_C 31SRCC3/CR#_D 32

SRCT2/SATAT 28SRCC2/SATAC 29

SRCT1/LCDT_100/27M_NSS 24SRCC1/LCDT_100/27M_SS 25

SRCT0/DOT96T 20SRCC0/DOT96C 21

U701

SLG8SP513VTR-GP

Main = 71.08513.003(SLG)Second = 71.09356.00W(ICS)

U701

SLG8SP513VTR-GP

Main = 71.08513.003(SLG)Second = 71.09356.00W(ICS)

12

C70

6SC

D1U

16V2

KX-3

GP

C70

6SC

D1U

16V2

KX-3

GP

12

C72

2D

o N

ot S

tuff

DY C722

Do

Not

Stu

ff

DY

1 2R707 475R2F-L1-GPR707 475R2F-L1-GP

12

C71

4SC

10U

6D3V

5KX-

1GP

C71

4SC

10U

6D3V

5KX-

1GP

12

C710

SC15P50V2JN-2-GP

C710

SC15P50V2JN-2-GP

12

C72

0D

o N

ot S

tuff

DY C720

Do

Not

Stu

ff

DY

1 2

R704

Do Not Stuff

R704

Do Not Stuff

12

R716Do Not StuffDYR716Do Not StuffDY

12

C71

8SC

D1U

16V2

KX-3

GP

C71

8SC

D1U

16V2

KX-3

GP

12

C70

2SC

1U10

V3KX

-3G

PC

702

SC1U

10V3

KX-3

GP

12

R71210KR2J-3-GPR71210KR2J-3-GP

1 2R722 1KR2J-1-GPR722 1KR2J-1-GP

1 2R705 22R2J-2-GPR705 22R2J-2-GP

1 2R720 1KR2J-1-GPR720 1KR2J-1-GP

12

C70

4SC

D1U

16V2

KX-3

GP

C70

4SC

D1U

16V2

KX-3

GP

1 2R702 10KR2J-3-GPR702 10KR2J-3-GP

1 2R719 2K2R2J-2-GPR719 2K2R2J-2-GP

12

C70

1SC

D1U

16V2

KX-3

GP

C70

1SC

D1U

16V2

KX-3

GP

12


1 2R721 1KR2J-1-GPR721 1KR2J-1-GP

12


1 2R710 33R2J-2-GPR710 33R2J-2-GP

12

C72

1D

o N

ot S

tuff

DY C721

Do

Not

Stu

ff

DY

1 2R717 10KR2J-3-GPR717 10KR2J-3-GP

12

C70

7SC

D1U

16V2

KX-3

GP

C70

7SC

D1U

16V2

KX-3

GP

1 2R718 Do Not StuffR718 Do Not Stuff

12

C71

9D

o N

ot S

tuff

DY C719

Do

Not

Stu

ff

DY

12

C70

5SC

D1U

16V2

KX-3

GP

C70

5SC

D1U

16V2

KX-3

GP

12

C71

7SC

D1U

16V2

KX-3

GP

C71

7SC

D1U

16V2

KX-3

GP

12R708 Do Not StuffDY

R708 Do Not StuffDY

12

C71

6SC

D1U

16V2

KX-3

GP

C71

6SC

D1U

16V2

KX-3

GP 1 2R701

22R2J-2-GPR701

22R2J-2-GP

1 2

R706

Do Not Stuff

R706

Do Not Stuff

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16

H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4

H_A#[35..3]

ITP_TCKITP_TDI

ITP_TMSITP_TRST#

ITP_TDO

ITP_BPM#5

RSVD_CPU_4

RSVD_CPU_1

RSVD_CPU_8

RSVD_CPU_5RSVD_CPU_6RSVD_CPU_7

RSVD_CPU_2RSVD_CPU_3

H_A#35

H_A#33

RSVD_CPU_9RSVD_CPU_10

H_A#18

H_A#20H_A#21H_A#22

H_A#17

H_A#19

H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28H_A#29H_A#30H_A#31

H_RS#1H_RS#0

H_RS#2

H_CPURST#

RSVD_CPU_11

H_A#34

H_A#32

CPU_IERR#

H_THERMDCH_THERMDA

CPU_TEST3

H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39

H_D#41H_D#40

H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47

TEST1TEST2

COMP0COMP1COMP2COMP3

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15

CPU_GTLREF0

H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31

H_D#48H_D#49

H_D#51H_D#50

H_D#52H_D#53H_D#54H_D#55

H_D#57H_D#56

H_D#58H_D#59H_D#60H_D#61

H_D#63H_D#62

CPU_TEST5

H_D#[63..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_DINV#[3..0]

ITP_TDO

ITP_TDI

ITP_TMS

ITP_TRST#

ITP_TCK

ITP_BPM#5

H_THERMDC

H_THERMDA

ITP_DBRESET#

ITP_DBRESET#

H_CPURST#

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+3.3V_RUN

H_RS#[2..0] 10

H_ADSTB#110

H_FERR#20H_IGNNE#20

H_A20M#20

H_LOCK# 10

H_INIT# 20

H_ADS# 10H_BNR# 10

H_DRDY# 10H_DBSY# 10

H_BREQ#0 10

H_BPRI# 10

H_DEFER# 10

H_STPCLK#20H_INTR20H_NMI20H_SMI#20

H_HIT# 10H_HITM# 10

H_TRDY# 10

H_ADSTB#010H_REQ#[4..0]10

H_A#[35..3]10

H_CPURST# 10

H_THRMTRIP# 11,20,37,42

CLK_CPU_BCLK 7CLK_CPU_BCLK# 7

CPU_PROCHOT# 47

H_DSTBN#2 10H_DSTBP#2 10H_DINV#2 10

H_DSTBN#3 10H_DSTBP#3 10H_DINV#3 10

H_DPRSTP# 11,20,47H_DPSLP# 20H_DPWR# 10H_PWRGOOD 20,42H_CPUSLP# 10

H_D#[63..0] 10

H_DINV#[3..0] 10

H_DSTBN#[3..0] 10

H_DSTBP#[3..0] 10

H_DSTBN#010H_DSTBP#010H_DINV#010

H_DSTBN#110H_DSTBP#110H_DINV#110

CPU_BSEL27

CPU_BSEL07CPU_BSEL17

PSI# 47

H_THERMDA 39H_THERMDC 39

Title


Date: Sheet of


DJ1 Montevina UMA A00CPU-FSB(1/2)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

TEST7

SSID = CPU

Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0 62.10079.001

Layout Note:Comp0, 2 connect with Zo=27.4 ohm, maketrace length shorter than 0.5".Comp1, 3 connect with Zo=55 ohm, maketrace length shorter than 0.5".

H_THRMTRIP# should connect toICH9 and MCH without T-ing.

All place within 2" to CPU

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

62.10079.001

TP804TP804

1 2R804 56R2J-4-GPR804 56R2J-4-GP

1 2R803 Do Not StuffDYR803 Do Not StuffDY

TP807TP807

12

C849Do Not StuffDY C849Do Not StuffDY

1 2R819 51R2F-2-GPR819 51R2F-2-GP

1 2R817 51R2F-2-GPR817 51R2F-2-GP

12

R8061KR2F-3-GPR8061KR2F-3-GP

1 2R809 54D9R2F-L1-GPR809 54D9R2F-L1-GP

TP809TP809

TP805TP805



TP810TP810


12

R8122KR2F-3-GP

R8122KR2F-3-GP

1 2R818 51R2F-2-GPR818 51R2F-2-GP

1 2R820 51R2F-2-GPR820 51R2F-2-GP



TP811TP811

TP802TP802TP803TP803

A3#J4A4#L5A5#L4A6#K5A7#M3A8#N2A9#J1A10#N3A11#P5A12#P2A13#L2A14#P4A15#P1A16#R1

A20M#A6

ADS# H1

ADSTB0#M1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L1

A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5

A30#U2

A24#R4A25#T5A26#T3

A32#W3

A28#W5A29#Y4A27#W2

A31#V4

A33#AA4A34#AB2A35#AA3

FERR#A5IGNNE#C4

RSVD#M4M4RSVD#N5N5RSVD#T2T2RSVD#V3V3RSVD#B2B2RSVD#C3C3

BNR# E2BPRI# G5

DEFER# H5

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2

HIT# G6HITM# E4

BPM0# AD4BPM1# AD3BPM2# AD1BPM3# AC4PRDY# AC2PREQ# AC1

TCK AC5TDI AA6

TDO AB3TMS AB5

TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2D2

RSVD#F6F6RSVD#D3D3RSVD#D22D22

STPCLK#D5LINT0C6LINT1B4SMI#A3

A23#U1

ADSTB1#V1

RESET# C1

KEY_NCB1

THRMDC B25

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

CPU1A

BGA479-SKT6-GPU7

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

CPU1A

BGA479-SKT6-GPU71 2R811 27D4R2F-L1-GPR811 27D4R2F-L1-GP1 2R810 Do Not StuffDYR810 Do Not StuffDY

D16#N22D17#K25D18#P26D19#R23D20#L23D21#M24D22#L22D23#M23D24#P25D25#P23D26#P22D27#T24D28#R24D29#L25D30#T25D31#N25

DINV0#H25

DINV1#N24

DSTBN0#J26

DSTBN1#L26

DSTBP0#H26

DSTBP1#M26

D0#E22D1#F24D2#E26D3#G22D4#F23D5#G25D6#E25D7#E23D8#K24D9#G24D10#J24D11#J23D12#H22D13#F26D14#K22D15#H23

D53# AC26

D60# AC22

D63# AC23

GTLREFAD26

TEST2D25

BSEL0B22BSEL1B23BSEL2C21

DINV2# U22

D32# Y22D33# AB24D34# V24D35# V26D36# V23

D38# U25D39# U23D40# Y25D41# W22D42# Y23D43# W24D44# W25D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20D55# AE22D56# AF23D57# AC25D58# AE21D59# AD21

D61# AD23

DINV3# AC20DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5DPSLP# B5DPWR# D24

PWRGOOD D6SLP# D7PSI# AE6

TEST1C23

TEST6A26

TEST3C24

TEST5AF1TEST4AF26

D37# T22

DSTBP3# AF24

COMP2 AA1COMP3 Y1

2 OF 4DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

CPU1B

BGA479-SKT6-GPU7

2 OF 4DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

CPU1B

BGA479-SKT6-GPU7


TP812TP8121 2R807 27D4R2F-L1-GPR807 27D4R2F-L1-GP

TP806TP806

TP808TP808

1 2R814 54D9R2F-L1-GPR814 54D9R2F-L1-GP

1 TP801TP801

12

C801SC1KP50V2KX-1GPC801SC1KP50V2KX-1GP

1 2R816 51R2F-2-GPR816 51R2F-2-GP

1 2R802 56R2J-4-GPR802 56R2J-4-GP

1TP813TP813

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_VID6

CPU_VID0CPU_VID1CPU_VID2CPU_VID3CPU_VID4CPU_VID5

CPU_GND3CPU_GND2

CPU_GND4

CPU_GND1

+VCC_CORE

+1.5V_RUN+1.5V_VCCA

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

CPU_VID[6..0] 47

VCC_SENSE 47

VSS_SENSE 47

Title


Date: Sheet of


DJ1 Montevina UMA A00CPU-Power(2/2)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

layout note: "+1.5V_VCCA"as short as possible

VCC_SENSE and VSS_SENSE linesshould be of equal length.

Layout Note:Place as close as possibleto the CPU VCCA pin.

NCTFPIN

62.10079.001

62.10079.001

SSID = CPU

12

C92

6SC

22U

6D3V

5MX-

2GP

C92

6SC

22U

6D3V

5MX-

2GP

12

C91

8SC

22U

6D3V

5MX-

2GP

C91

8SC

22U

6D3V

5MX-

2GP

12

C92

4SC

10U

6D3V

5KX-

1GP

C92

4SC

10U

6D3V

5KX-

1GP

12

C92

7SC

22U

6D3V

5MX-

2GP

C92

7SC

22U

6D3V

5MX-

2GP

1 2R902100R2F-L1-GP-U

R902100R2F-L1-GP-U

TP902TP902

12

C90

3D

o N

ot S

tuff

DY C903

Do

Not

Stu

ff

DY

12

C939SCD01U16V2KX-3GP


12

C90

6D

o N

ot S

tuff

DY C906

Do

Not

Stu

ff

DY

12

C90

5D

o N

ot S

tuff

DY C905

Do

Not

Stu

ff

DY

12

C90

4D

o N

ot S

tuff

DY C904

Do

Not

Stu

ff

DY

TP903TP903

12

C932SC22U6D3V5MX-2GPC932SC22U6D3V5MX-2GP

12

C92

1SC

22U

6D3V

5MX-

2GP

C92

1SC

22U

6D3V

5MX-

2GP

12

C91

4D

o N

ot S

tuff

DY C914

Do

Not

Stu

ff

DY

TP901TP901

12

C91

2D

o N

ot S

tuff

DY C912

Do

Not

Stu

ff

DY

1 2

PG902

Do Not Stuff

PG902

Do Not Stuff

12 T

C90

1D

o N

ot S

tuff

DY

TC90

1D

o N

ot S

tuff

DY

12

C90

9SC

22U

6D3V

5MX-

2GP

C90

9SC

22U

6D3V

5MX-

2GP

12

C92

3SC

22U

6D3V

5MX-

2GP

C92

3SC

22U

6D3V

5MX-

2GP

12

C93

5SC

D1U

10V2

KX-5

GP

C93

5SC

D1U

10V2

KX-5

GP

12

C91

3D

o N

ot S

tuff

DY C913

Do

Not

Stu

ff

DY

1 2

PG901

Do Not Stuff

PG901

Do Not Stuff

12

C93

8SC

D1U

10V2

KX-5

GP

C93

8SC

D1U

10V2

KX-5

GP

12

C92

8SC

10U

6D3V

5KX-

1GP

C92

8SC

10U

6D3V

5KX-

1GP

12

C93

0SC

22U

6D3V

5MX-

2GP

C93

0SC

22U

6D3V

5MX-

2GP

12

C90

8D

o N

ot S

tuff

DY C908

Do

Not

Stu

ff

DY

TP904TP904

12

C91

5SC

22U

6D3V

5MX-

2GP

C91

5SC

22U

6D3V

5MX-

2GP

VSSAF2

VSSA4VSSA8VSSA11VSSA14VSSA16VSSA19VSSA23

VSSB6VSSB8VSSB11VSSB13VSSB16VSSB19VSSB21VSSB24VSSC5VSSC8VSSC11VSSC14VSSC16VSSC19VSSC2VSSC22VSSC25VSSD1VSSD4VSSD8VSSD11VSSD13VSSD16VSSD19VSSD23VSSD26VSSE3VSSE6VSSE8VSSE11VSSE14VSSE16VSSE19VSSE21VSSE24VSSF5VSSF8VSSF11VSSF13VSSF16VSSF19VSSF2VSSF22VSSF25VSSG4VSSG1VSSG23VSSG26VSSH3VSSH6VSSH21VSSH24VSSJ2VSSJ5VSSJ22VSSJ25VSSK1VSSK4VSSK23VSSK26VSSL3VSSL6VSSL21VSSL24VSSM2VSSM5VSSM22VSSM25VSSN1VSSN4VSSN23VSSN26VSSP3

VSS P6VSS P21VSS P24VSS R2VSS R5VSS R22VSS R25VSS T1VSS T4VSS T23VSS T26VSS U3VSS U6VSS U21VSS U24VSS V2VSS V5VSS V22VSS V25VSS W1VSS W4VSS W23VSS W26VSS Y3VSS Y6VSS Y21VSS Y24VSS AA2VSS AA5VSS AA8VSS AA11VSS AA14VSS AA16VSS AA19VSS AA22VSS AA25VSS AB1VSS AB4VSS AB8VSS AB11VSS AB13VSS AB16VSS AB19VSS AB23VSS AB26VSS AC3VSS AC6VSS AC8VSS AC11VSS AC14VSS AC16VSS AC19VSS AC21VSS AC24VSS AD2VSS AD5VSS AD8VSS AD11VSS AD13VSS AD16VSS AD19VSS AD22VSS AD25VSS AE1VSS AE4VSS AE8VSS AE11VSS AE14VSS AE16VSS AE19VSS AE23VSS AE26VSS A2VSS AF6VSS AF8VSS AF11VSS AF13VSS AF16VSS AF19VSS AF21VSS A25VSS AF25

4 OF 4CPU1D

BGA479-SKT6-GPU7

4 OF 4CPU1D

BGA479-SKT6-GPU7

VCCA7VCCA9

VCCAC10

VCCA10VCCA12VCCA13VCCA15VCCA17VCCA18VCCA20VCCB7VCCB9VCCB10VCCB12VCCB14VCCB15VCCB17VCCB18VCCB20VCCC9VCCC10VCCC12VCCC13VCCC15VCCC17VCCC18VCCD9VCCD10VCCD12VCCD14VCCD15VCCD17VCCD18VCCE7VCCE9VCCE10VCCE12VCCE13VCCE15

VCCAA7VCCAA9VCCAA10VCCAA12VCCAA13VCCAA15VCCAA17VCCAA18VCCAA20VCCAB9

VCCAB12VCCAB14VCCAB15VCCAB17VCCAB18

VCCE17VCCE18VCCE20VCCF7VCCF9VCCF10VCCF12VCCF14VCCF15VCCF17VCCF18VCCF20

VCC AB20VCC AB7VCC AC7VCC AC9VCC AC12VCC AC13VCC AC15VCC AC17VCC AC18VCC AD7VCC AD9VCC AD10VCC AD12VCC AD14VCC AD15VCC AD17VCC AD18VCC AE9VCC AE10VCC AE12VCC AE13VCC AE15VCC AE17VCC AE18VCC AE20VCC AF9VCC AF10VCC AF12VCC AF14VCC AF15VCC AF17VCC AF18VCC AF20

VCCP G21

VCCP J6

VCCP J21VCCP K6

VCCP K21VCCP M6

VCCP M21

VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6VCCP T21

VCCP V6

VCCP V21VCCP W21

VCCA B26VCCA C26

VID0 AD6

VID6 AE2VID4 AE3VID2 AE5

VID5 AF3VID3 AF4VID1 AF5

VSSSENSE AE7

VCCSENSE AF7VCCAB10

3 OF 4CPU1C

BGA479-SKT6-GPU7

3 OF 4CPU1C

BGA479-SKT6-GPU7

12

C92

2D

o N

ot S

tuff

DY C922

Do

Not

Stu

ff

DY

12

C91

7SC

10U

6D3V

5KX-

1GP

C91

7SC

10U

6D3V

5KX-

1GP

12

C92

5D

o N

ot S

tuff

DY C925

Do

Not

Stu

ff

DY

12

C93

3

SCD

1U10

V2KX

-5G

P

C93

3

SCD

1U10

V2KX

-5G

P

12

C90

7SC

22U

6D3V

5MX-

2GP

C90

7SC

22U

6D3V

5MX-

2GP

12

C910SC10U6D3V5KX-1GPC910SC10U6D3V5KX-1GP

12

C93

7SC

1U6D

3V2K

X-G

PC

937

SC1U

6D3V

2KX-

GP

12


12

C91

1D

o N

ot S

tuff

DY C911

Do

Not

Stu

ff

DY

12


1 2R901Do Not Stuff

R901Do Not Stuff

12

C90

2D

o N

ot S

tuff

DY C902

Do

Not

Stu

ff

DY

12

C92

0D

o N

ot S

tuff

DY C920

Do

Not

Stu

ff

DY

12

C93

6SC

D1U

16V2

KX-3

GP

C93

6SC

D1U

16V2

KX-3

GP

12

C93

4SC

D1U

16V2

KX-3

GP

C93

4SC

D1U

16V2

KX-3

GP

12

C91

6D

o N

ot S

tuff

DY C916

Do

Not

Stu

ff

DY

1 2R903100R2F-L1-GP-U

R903100R2F-L1-GP-U

12

C90

1D

o N

ot S

tuff

DY C901

Do

Not

Stu

ff

DY

12

C92

9D

o N

ot S

tuff

DY C929

Do

Not

Stu

ff

DY

12

C93

1SC

22U

6D3V

5MX-

2GP

C93

1SC

22U

6D3V

5MX-

2GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_D#[63..0]H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63

H_AVREF

H_RCOMP

H_SWING

H_SWINGH_RCOMP

H_DINV#0

H_RS#1

H_DSTBN#0

H_REQ#2

H_DSTBP#0

H_REQ#4H_REQ#3

H_RS#0

H_DINV#3

H_DSTBN#3

H_DSTBP#3

H_REQ#1

H_DINV#2

H_DSTBN#2

H_DSTBP#2

H_REQ#0

H_DINV#1

H_RS#2

H_DSTBN#[3..0]

H_DSTBN#1

H_DSTBP#[3..0]

H_DSTBP#1

H_DINV#[3..0]

H_A#6

H_A#16

H_A#34

H_A#32

H_A#22

H_A#20

H_A#26

H_A#11

H_A#5

H_A#31

H_A#3

H_A#9

H_A#15

H_A#21

H_A#19

H_A#25

H_A#4

H_A#30H_A#29

H_A#8

H_A#14

H_A#18

H_A#24

H_A#28

H_A#7

H_A#13

H_A#17

H_A#12

H_A#35

H_A#33

H_A#23

H_A#27

H_A#10

H_A#[35..3]

H_REQ#[4..0]

H_RS#[2..0]

+1.05V_VCCP

+1.05V_VCCP

H_D#[63..0]8

H_CPURST#8H_CPUSLP#8

H_DINV#[3..0] 8

H_DSTBN#[3..0] 8

H_DSTBP#[3..0] 8

H_REQ#[4..0] 8

H_RS#[2..0] 8

H_BNR# 8

H_BREQ#0 8

H_ADS# 8H_ADSTB#0 8H_ADSTB#1 8

H_DBSY# 8

H_DRDY# 8H_HIT# 8H_HITM# 8H_LOCK# 8

H_BPRI# 8

H_DEFER# 8

H_DPWR# 8

H_TRDY# 8

H_A#[35..3] 8

CLK_MCH_BCLK 7CLK_MCH_BCLK# 7

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-Host(1/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Place R1001 near to the chip ( < 0.5")

H_RCOMP routing Trace width andSpacing use 10 / 20 mil

H_SWING routing Trace width andSpacing use 10 / 20 mil

H_SWING Resistors andCapacitors close MCH500 mil ( MAX )

SSID = MCH

1 2R1003 24D9R2F-L-GPR1003 24D9R2F-L-GP

12

R1002221R2F-2-GPR1002221R2F-2-GP

12

C1001Do Not StuffDY C1001Do Not StuffDY

12

C1002SCD1U10V2KX-5GPC1002SCD1U10V2KX-5GP

12

R1001100R2F-L1-GP-UR1001100R2F-L1-GP-U

H_A#_10 P16H_A#_11 R16H_A#_12 N17H_A#_13 M13H_A#_14 E17H_A#_15 P17H_A#_16 F17H_A#_17 G20H_A#_18 B19H_A#_19 J16H_A#_20 E20H_A#_21 H16H_A#_22 J20H_A#_23 L17H_A#_24 A17H_A#_25 B17H_A#_26 L16H_A#_27 C21H_A#_28 J17H_A#_29 H20

H_A#_3 A14

H_A#_30 B18H_A#_31 K17

H_A#_4 C15H_A#_5 F16H_A#_6 H13H_A#_7 C18H_A#_8 M16H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16H_ADSTB#_1 G17

H_BNR# A9H_BPRI# F11

H_BREQ# G12

HPLL_CLK# AH6

H_CPURST#C12

HPLL_CLK AH7

H_D#_0F2

H_REQ#_2 F13H_REQ#_3 B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4H_D#_9H3

H_DBSY# B10

H_D#_11M11H_D#_12J1H_D#_13J2H_D#_14N12H_D#_15J6H_D#_16P2H_D#_17L2H_D#_18R2H_D#_19N9

H_D#_2F8

H_D#_21M5H_D#_22J3H_D#_23N2H_D#_24R1H_D#_25N5H_D#_26N6H_D#_27P13H_D#_28N8H_D#_29L7

H_D#_3E6

H_D#_31M3H_D#_32Y3H_D#_33AD14H_D#_34Y6H_D#_35Y10H_D#_36Y12H_D#_37Y14H_D#_38Y7H_D#_39W2

H_D#_4G2

H_D#_41Y9H_D#_42AA13H_D#_43AA9H_D#_44AA11H_D#_45AD11H_D#_46AD10H_D#_47AD13H_D#_48AE12H_D#_49AE9

H_D#_5H6

H_D#_51AD8H_D#_52AA3H_D#_53AD3H_D#_54AD7H_D#_55AE14H_D#_56AF3H_D#_57AC1H_D#_58AE3H_D#_59AC3

H_D#_6H2

H_D#_61AE8H_D#_62AG2H_D#_63AD6

H_D#_7F6

H_DEFER# E9

H_DINV#_0 J8H_DINV#_1 L3H_DINV#_2 Y13H_DINV#_3 Y1

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10H_DSTBN#_1 M7H_DSTBN#_2 AA5H_DSTBN#_3 AE6

H_DSTBP#_0 L9H_DSTBP#_1 M8H_DSTBP#_2 AA6H_DSTBP#_3 AE5

H_AVREFA11H_DVREFB11

H_TRDY# C9

H_HIT# H9H_HITM# E12

H_LOCK# H11

H_REQ#_0 B15H_REQ#_1 K13

H_REQ#_4 B14

H_A#_32 B20H_A#_33 F21H_A#_34 K21H_A#_35 L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0 B6H_RS#_1 F12H_RS#_2 C8

HOST

1 OF 10NB1A

CANTIGA-GM-GP-U-NF

HOST

1 OF 10NB1A

CANTIGA-GM-GP-U-NF12


12


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DMI_ITXP3_MRXP3

DMI_ITXN2_MRXN2DMI_ITXN1_MRXN1DMI_ITXN0_MRXN0

TSATN#

DMI_ITXN3_MRXN3

DMI_ITXP2_MRXP2DMI_ITXP1_MRXP1DMI_ITXP0_MRXP0

SM_RCOMP_VOHSM_RCOMP_VOL

CFG9CFG10

CFG16

CFG20CFG19

MCH_CLVREF

SM_REXT

PWROK_RRSTIN#

M_RCOMPPM_RCOMPN

CFG9

CFG16

CFG10

CFG19

PM_EXTTS#1PM_EXTTS#0

TSATN#_KBC

TSATN#

SM_RCOMP_VOH

SM_RCOMP_VOL

CLK_MCH_3GPLL#CLK_MCH_3GPLL

CANTIGA_SM_VREF

CLKREQ#_B

CFG3CFG4

CFG14CFG15

CFG17

CFG20

DMI_IRXN3_MTXN3

DMI_IRXP3_MTXP3DMI_IRXP2_MTXP2DMI_IRXP1_MTXP1DMI_IRXP0_MTXP0

DMI_IRXN2_MTXN2DMI_IRXN1_MTXN1DMI_IRXN0_MTXN0

CLK_MCH_DREFCLK#CLK_MCH_DREFCLK

MCH_SSCDREFCLK#MCH_SSCDREFCLK

GMCH_HDMI_DATA

DDR3_DRAMRST#

SM_PWROK

+1.05V_VCCP

+3.3V_RUN

+3.3V_RUN+1.05V_VCCP

+3.3V_RUN

+1.5V_SUS

+1.5V_SUS

+V_DDR_REF

MCH_CLKSEL17MCH_CLKSEL27

MCH_CLKSEL07

M_CLK_DDR#2 19M_CLK_DDR#3 19

M_CLK_DDR0 18M_CLK_DDR1 18

M_CKE0 18M_CKE1 18M_CKE2 19M_CKE3 19

M_CLK_DDR2 19M_CLK_DDR3 19

M_CS#1 18M_CS#2 19M_CS#3 19

M_CS#0 18

M_CLK_DDR#0 18M_CLK_DDR#1 18

M_ODT0 18M_ODT1 18M_ODT2 19M_ODT3 19

CL_CLK0 22CL_DATA0 22

H_DPRSTP#8,20,47PM_SYNC#22

PLT_RST#21,37,58,76PM_PWROK22,37

DPRSLPVR22,47

H_THRMTRIP#8,20,37,42

MCH_ICH_SYNC# 22

PM_EXTTS#018PM_EXTTS#119

TSATN#_KBC 37

M_PWROK 22CL_RST#0 22

CLK_MCH_3GPLL 7CLK_MCH_3GPLL# 7

CLKREQ#_B 7

DMI_IRXN0_MTXN0 21DMI_IRXN1_MTXN1 21DMI_IRXN2_MTXN2 21DMI_IRXN3_MTXN3 21

DMI_IRXP0_MTXP0 21

DMI_IRXP2_MTXP2 21DMI_IRXP3_MTXP3 21

DMI_IRXP1_MTXP1 21

DMI_ITXN0_MRXN0 21

DMI_ITXP0_MRXP0 21

DMI_ITXN1_MRXN1 21

DMI_ITXP1_MRXP1 21

DMI_ITXN2_MRXN2 21

DMI_ITXP2_MRXP2 21

DMI_ITXN3_MRXN3 21

DMI_ITXP3_MRXP3 21

CLK_MCH_DREFCLK 7CLK_MCH_DREFCLK# 7MCH_SSCDREFCLK 7MCH_SSCDREFCLK# 7

DDR3_DRAMRST# 18,19

SM_PWROK 41

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-DMI/CFG(2/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

FSB setting

MCH_CLVREF ~= 0.35V

SDVO/iHDMI/DP interface disabled

SDVO/iHDMI/DP interface enabled

DDPC_CTRLDATA

TLS cipher suite with confidentiality

CFG 16 FSB dynamic ODT disable

CFG Strap HighLow

DMI X 2

CFG 9 PCIE GFX lane reversed

CFG 19DMI Lane Reserved

DMI X 4

Normal operation Reverse DMI lanes

ITPM enable

Only PCIE or SDVO is operational

ITPM disable

CFG 20SDVO concurrent with PCIE

PCIE and SDVO areoperatiing simultaneously via the PEG port

SDVO_CTRLDATA

CFG 5

CFG 6

SDVO interface disable

CFG 7TLS cipher suite with no confidentiality

FSB Dynamic ODT enable

CFG 10 PCIE loopback enable PCIE loopback disable

CFG 12 ALLZ mode enable ALLZ mode disable

CFG 13 XOR mode enable XOR mode disable

PCIE GFX lanenumbered in oder

SDVO interface enable

L_DDC_DATA LFP disable LFP card present

SSID = MCH

* is current setting

****

****

**

***

12

C1107Do Not Stuff DYC1107Do Not Stuff DY

12

R112256R2J-4-GPR112256R2J-4-GP

1 TP1106TP1106

12

R110

43K

01R2

F-3-

GP

R110

43K

01R2

F-3-

GP

12



12

R110580D6R2F-L-GP

R110580D6R2F-L-GP

1 2R1125Do Not Stuff

R1125Do Not Stuff


TP1104TP1104

12

R1128499R2F-2-GPR1128499R2F-2-GP


12


1 2R1129

10KR2J-3-GP

R1129

10KR2J-3-GP


12

C1104

SC2D2U6D3V3KX-GP

C1104

SC2D2U6D3V3KX-GP

TP1101TP1101

12

R110380D6R2F-L-GP

R110380D6R2F-L-GP

SA_CK_0 AP24SA_CK_1 AT21SB_CK_0 AV24

SA_CK#_0 AR24SA_CK#_1 AR21SB_CK#_0 AU24

SA_CKE_0 BC28SA_CKE_1 AY28SB_CKE_0 AY36SB_CKE_1 BB36

SA_CS#_0 BA17SA_CS#_1 AY16SB_CS#_0 AV16SB_CS#_1 AR13

SM_DRAMRST# BC36

SA_ODT_0 BD17SA_ODT_1 AY17SB_ODT_0 BF15SB_ODT_1 AY13

SM_RCOMP BG22SM_RCOMP# BH21

CFG_18P29CFG_19R28

CFG_2P25CFG_0T25CFG_1R25

CFG_20T28

CFG_3P20CFG_4P24CFG_5C25CFG_6N24CFG_7M24CFG_8E21CFG_9C23CFG_10C24CFG_11N21CFG_12P21CFG_13T21CFG_14R20CFG_15M20CFG_16L21CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33PM_EXT_TS#_1P32PWROKAT40RSTIN#AT11

DPLL_REF_CLK B38DPLL_REF_CLK# A38

DPLL_REF_SSCLK E41DPLL_REF_SSCLK# F41

DMI_RXN_0 AE41DMI_RXN_1 AE37DMI_RXN_2 AE47DMI_RXN_3 AH39

DMI_RXP_0 AE40DMI_RXP_1 AE38DMI_RXP_2 AE48DMI_RXP_3 AH40

DMI_TXN_0 AE35DMI_TXN_1 AE43DMI_TXN_2 AE46DMI_TXN_3 AH42

DMI_TXP_0 AD35DMI_TXP_1 AE44DMI_TXP_2 AF46DMI_TXP_3 AH43

RESERVED#AL34AL34

RESERVED#AN35AN35RESERVED#AK34AK34

RESERVED#AM35AM35

RESERVED#BG23BG23RESERVED#BF23BF23RESERVED#BH18BH18RESERVED#BF18BF18

PM_DPRSTP#B7

SB_CK_1 AU20

SB_CK#_1 AV20

RESERVED#AY21AY21

RESERVED#AH9AH9RESERVED#AH10AH10RESERVED#AH12AH12RESERVED#AH13AH13

RESERVED#M36M36RESERVED#N36N36RESERVED#R33R33RESERVED#T33T33

GFX_VID_0 B33GFX_VID_1 B32GFX_VID_2 G33GFX_VID_3 F33

GFX_VR_EN C34

SM_RCOMP_VOH BF28SM_RCOMP_VOL BH28

THERMTRIP#T20DPRSLPVRR32

RESERVED#K12K12

CL_CLK AH37CL_DATA AH36

CL_PWROK AN36CL_RST# AJ35CL_VREF AH34

NC#A47A47

NC#BG48BG48NC#BF48BF48NC#BD48BD48NC#BC48BC48NC#BH47BH47NC#BG47BG47NC#BE47BE47NC#BH46BH46NC#BF46BF46NC#BG45BG45NC#BH44BH44NC#BH43BH43NC#BH6BH6NC#BH5BH5NC#BG4BG4

SDVO_CTRLCLK G36SDVO_CTRLDATA E36

CLKREQ# K36

RESERVED#T24T24

ICH_SYNC# H36

TSATN# B12

PEG_CLK# E43PEG_CLK F43

NC#BH3BH3

GFX_VID_4 E33

RESERVED#B31B31

DDPC_CTRLCLK N28

NC#BF3BF3NC#BH2BH2NC#BG2BG2NC#BE2BE2NC#BG1BG1NC#BF1BF1NC#BD1BD1NC#BC1BC1NC#F1F1

SM_VREF AV42SM_PWROK AR36

SM_REXT BF17

RESERVED#M1M1

HDA_BCLK B28HDA_RST# B30

HDA_SDI B29HDA_SDO C29

HDA_SYNC A28

DDPC_CTRLDATA M28

RESERVED#B2B2

PM

MISC

NC

DDR CLK/ CONTROL/COMPENSATION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

2 OF 10NB1B

CANTIGA-GM-GP-U-NF

PM

MISC

NC

DDR CLK/ CONTROL/COMPENSATION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

2 OF 10NB1B

CANTIGA-GM-GP-U-NF


12


TP1102TP1102

TP1105TP1105

123

4RN1102

SRN10KJ-5-GP

RN1102

SRN10KJ-5-GP

C

B

E

Q1101Do Not StuffDY Q1101Do Not StuffDY

TP1103TP1103


12



1 2R1127100R2J-2-GP R1127100R2J-2-GP

12

C1102SC2D2U6D3V3KX-GP

C1102SC2D2U6D3V3KX-GP

12

R1123Do Not StuffDY R1123Do Not StuffDY

1 2R1109499R2F-2-GPR1109499R2F-2-GP

1 2

R1108

Do Not Stuff

R1108

Do Not Stuff

12 C

1105

Do N

ot S

tuff

DY C110

5Do

Not

Stu

ff

DY

12 C

1108

SCD1

U10V

2KX-

5GP

C110

8SC

D1U1

0V2K

X-5G

P

12


12 C

1106

Do N

ot S

tuff

DY C110

6Do

Not

Stu

ff

DY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQS#3

M_A_DQS#0

M_A_DQS#6

M_A_DQS#4

M_A_DQS#1M_A_DQS#2

M_A_DQS#5

M_A_DQS#7

M_A_A0

M_A_A6

M_A_A3

M_A_A5

M_A_A7

M_A_A1M_A_A2

M_A_A4

M_A_A10

M_A_A8

M_A_A13

M_A_A11

M_A_A9

M_A_A12

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_DM[7..0]M_A_DM0M_A_DM1M_A_DM2M_A_DM3M_A_DM4M_A_DM5M_A_DM6M_A_DM7

M_A_DQS[7..0]

M_A_DQS5

M_A_DQS7

M_A_DQS2M_A_DQS3M_A_DQS4

M_A_DQS0M_A_DQS1

M_A_DQS6

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63..0]

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63..0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQS#[7..0]M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7

M_B_DQS[7..0]M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_A12

M_B_A9

M_B_A11

M_B_A13

M_B_A8

M_B_A10

M_B_A[14..0]M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7

M_B_DM[7..0]M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7

M_A_A14M_B_A14

M_A_DQS#[7..0] 18

M_A_DQS[7..0] 18

M_A_A[14..0] 18

M_A_DM[7..0] 18

M_B_BS0 19M_B_BS1 19M_B_BS2 19

M_B_CAS# 19M_B_RAS# 19

M_A_BS0 18M_A_BS1 18M_A_BS2 18

M_A_CAS# 18

M_B_DQ[63..0]19

M_A_RAS# 18

M_A_DQ[63..0]18

M_B_DQS#[7..0] 19

M_B_DQS[7..0] 19

M_B_A[14..0] 19

M_B_DM[7..0] 19

M_A_WE# 18M_B_WE# 19

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-DDR(3/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

SSID = MCH

SB_DQ_0AK47SB_DQ_1AH46

SB_DQ_10BA48SB_DQ_11AY48SB_DQ_12AT47SB_DQ_13AR47SB_DQ_14BA47SB_DQ_15BC47SB_DQ_16BC46SB_DQ_17BC44SB_DQ_18BG43SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45SB_DQ_21BC41SB_DQ_22BF40SB_DQ_23BF41SB_DQ_24BG38SB_DQ_25BF38SB_DQ_26BH35SB_DQ_27BG35SB_DQ_28BH40SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34SB_DQ_31BH34SB_DQ_32BH14SB_DQ_33BG12SB_DQ_34BH11SB_DQ_35BG8SB_DQ_36BH12SB_DQ_37BF11SB_DQ_38BF8SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5SB_DQ_41BC6SB_DQ_42AY3SB_DQ_43AY1SB_DQ_44BF6SB_DQ_45BF5SB_DQ_46BA1SB_DQ_47BD3SB_DQ_48AV2SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3SB_DQ_51AN2SB_DQ_52AY2SB_DQ_53AV1SB_DQ_54AP3SB_DQ_55AR1SB_DQ_56AL1SB_DQ_57AL2SB_DQ_58AJ1SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2SB_DQ_61AM3SB_DQ_62AH3SB_DQ_63AJ3

SB_DQ_7AP48SB_DQ_8AU47SB_DQ_9AU46

SB_BS_0 BC16SB_BS_1 BB17SB_BS_2 BB33

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47SB_DM_2 BD40SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3SB_DM_6 AP1SB_DM_7 AK2

SB_DQS_0 AL47SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1SB_DQS_7 AN6

SB_DQS#_0 AL46SB_DQS#_1 AV47SB_DQS#_2 BH41SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2SB_DQS#_6 AT2SB_DQS#_7 AN5

SB_MA_0 AV17SB_MA_1 BA25

SB_MA_10 BB16SB_MA_11 AW33SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28SB_MA_7 AW28SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33

SB_RAS# AU17

SB_WE# BF14

DDR SYSTEM MEMORY B

5 OF 10NB1E

CANTIGA-GM-GP-U-NF

DDR SYSTEM MEMORY B

5 OF 10NB1E

CANTIGA-GM-GP-U-NF

SA_DQ_0AJ38SA_DQ_1AJ41

SA_DQ_10AU40SA_DQ_11AT38SA_DQ_12AN41SA_DQ_13AN39SA_DQ_14AU44SA_DQ_15AU42SA_DQ_16AV39SA_DQ_17AY44SA_DQ_18BA40SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41SA_DQ_21AY43SA_DQ_22BB41SA_DQ_23BC40SA_DQ_24AY37SA_DQ_25BD38SA_DQ_26AV37SA_DQ_27AT36SA_DQ_28AY38SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36SA_DQ_31AW36SA_DQ_32BD13SA_DQ_33AU11SA_DQ_34BC11SA_DQ_35BA12SA_DQ_36AU13SA_DQ_37AV13SA_DQ_38BD12SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9SA_DQ_41BA9SA_DQ_42AU10SA_DQ_43AV9SA_DQ_44BA11SA_DQ_45BD9SA_DQ_46AY8SA_DQ_47BA6SA_DQ_48AV5SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9SA_DQ_51AN8SA_DQ_52AU5SA_DQ_53AU6SA_DQ_54AT5SA_DQ_55AN10SA_DQ_56AM11SA_DQ_57AM5SA_DQ_58AJ9SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12SA_DQ_61AM13SA_DQ_62AJ11SA_DQ_63AJ12

SA_DQ_7AM42SA_DQ_8AN43SA_DQ_9AN44

SA_BS_0 BD21SA_BS_1 BG18SA_BS_2 AT25

SA_CAS# BD20

SA_DM_0 AM37SA_DM_1 AT41SA_DM_2 AY41SA_DM_3 AU39SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44SA_DQS_1 AT44SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7

SA_DM_7 AJ5

SA_DQS#_0 AJ43SA_DQS#_1 AT43SA_DQS#_2 BA44SA_DQS#_3 BD37SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9SA_DQS#_7 AM8

SA_MA_0 BA21SA_MA_1 BC24

SA_MA_10 BC21SA_MA_11 BG26SA_MA_12 BH26SA_MA_13 BH17

SA_MA_2 BG24SA_MA_3 BH24SA_MA_4 BG25SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27SA_MA_8 BF25SA_MA_9 AW24

SA_RAS# BB20

SA_WE# AY20

SA_MA_14 AY25DDR SYSTEM MEMORY A

4 OF 10NB1D

CANTIGA-GM-GP-U-NF

DDR SYSTEM MEMORY A

4 OF 10NB1D

CANTIGA-GM-GP-U-NF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GMCH_GND4

GMCH_GND1GMCH_GND2GMCH_GND3

PEG_CMPL_CTRL_DATA

GMCH_DDCCLK

L_CTRL_CLK

GMCH_DDCDATAGMCH_DDCCLK

LDDC_DATALDDC_CLK

GMCH_DDCDATA

DDC_CLK_CON

DDC_DATA_CON

CRT_IREFGMCH_VS

GMCH_HS

LVDS_VBGLIBG

TV_DACBTV_DACC

TV_DACA

M_GREEN

M_RED

M_BLUE

+1.05V_VCCP

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

M_BLUE55

M_GREEN55

LCDVDD_EN54

M_RED55

DDC_CLK_CON55

DDC_DATA_CON 55

VGA_TXAOUT0+54VGA_TXAOUT1+54VGA_TXAOUT2+54

VGA_TXAOUT0-54VGA_TXAOUT1-54VGA_TXAOUT2-54

VGA_TXACLK-54VGA_TXACLK+54

LBKLT_CTL54

LDDC_CLK54LDDC_DATA54

GMCH_BL_ON37

GMCH_HSYNC55

GMCH_VSYNC55

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-GND/LVDS/VGA(4/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

NCTFPIN

Place R1303close toMCH within500 mils.

SSID = MCH

CRT_IREFrouting Tracewidth use 20 mil.

VSSBG21

VSSAW21VSSAU21VSSAP21VSSAN21VSSAH21VSSAF21VSSAB21VSSR21VSSM21VSSJ21VSSG21VSSBC20VSSBA20VSSAW20VSSAT20VSSAJ20VSSAG20VSSY20VSSN20VSSK20VSSF20VSSC20VSSA20VSSBG19VSSA18VSSBG17VSSBC17VSSAW17VSSAT17VSSR17VSSM17VSSH17VSSC17

VSSBA16

VSSAU16VSSAN16VSSN16VSSK16VSSG16VSSE16VSSBG15

VSSW15VSSA15VSSBG14VSSAA14VSSC14VSSBG13VSSBC13VSSBA13

VSSAN13VSSAJ13VSSAE13VSSN13VSSL13VSSG13VSSE13VSSBF12VSSAV12VSSAT12VSSAM12VSSAA12VSSJ12VSSA12VSSBD11VSSBB11VSSAY11VSSAN11VSSAH11

VSSY11VSSN11VSSG11VSSC11VSSBG10VSSAV10VSSAT10VSSAJ10VSSAE10VSSAA10

VSSBH8VSSB9VSSG9VSSAD9VSSAM9VSSAN9VSSBC9VSSM10VSSBF9

VSS AH8VSS Y8VSS L8VSS E8VSS B8VSS AY7VSS AU7VSS AN7VSS AJ7VSS AE7VSS AA7VSS N7VSS J7VSS BG6VSS BD6VSS AV6VSS AT6

VSSAC15

VSS AM6VSS M6VSS C6VSS BA5VSS AH5VSS AD5VSS Y5VSS L5VSS J5VSS H5VSS F5VSS BE4

VSS BC3VSS AV3VSS AL3

VSS_NCTF AF32VSS_NCTF AB32VSS_NCTF V32VSS_NCTF AJ30VSS_NCTF AM29VSS_NCTF AF29VSS_NCTF AB29VSS_NCTF U26VSS_NCTF U23VSS_NCTF AL20VSS_NCTF V20VSS_NCTF AC19VSS_NCTF AL17VSS_NCTF AJ17VSS_NCTF AA17VSS_NCTF U17

VSS_SCB BH48VSS_SCB BH1VSS_SCB A48VSS_SCB C1VSS_SCB A3

NC#E1 E1NC#D2 D2NC#C3 C3NC#B4 B4NC#A5 A5NC#A6 A6

NC#A43 A43NC#A44 A44NC#B45 B45NC#C46 C46NC#D47 D47NC#B47 B47NC#A46 A46NC#F48 F48NC#E48 E48NC#C48 C48NC#B48 B48

VSS R3VSS P3

VSS BA2

VSS AR2VSS AU2

VSS AP2

VSS F3

VSS AW2

VSS AE2VSS AF2VSS AH2VSS AJ2

VSS AD2VSS AC2VSS Y2VSS M2VSS K2VSS AM1VSS AA1VSS P1VSS H1

VSSBB8VSSAV8VSSAT8

VSS U24VSS U28VSS U25VSS U29

VSSL12

VSS

VSS NCTF

VSS SCB

NC

10 OF 10NB1J

CANTIGA-GM-GP-U-NF

VSS

VSS NCTF

VSS SCB

NC

10 OF 10NB1J

CANTIGA-GM-GP-U-NF

1 2R1306 75R2F-2-GPR1306 75R2F-2-GP

TP1305TP1305

1 2R13111K02R2F-1-GP R13111K02R2F-1-GP

TP1303TP1303

1 2R1309 150R2F-1-GPR1309 150R2F-1-GP

PEG_COMPI T37PEG_COMPO T36

PEG_RX#_0 H44PEG_RX#_1 J46PEG_RX#_2 L44PEG_RX#_3 L40PEG_RX#_4 N41PEG_RX#_5 P48PEG_RX#_6 N44PEG_RX#_7 T43PEG_RX#_8 U43PEG_RX#_9 Y43

PEG_RX#_10 Y48PEG_RX#_11 Y36PEG_RX#_12 AA43PEG_RX#_13 AD37PEG_RX#_14 AC47PEG_RX#_15 AD39

PEG_RX_0 H43PEG_RX_1 J44PEG_RX_2 L43PEG_RX_3 L41PEG_RX_4 N40PEG_RX_5 P47PEG_RX_6 N43PEG_RX_7 T42PEG_RX_8 U42PEG_RX_9 Y42

PEG_RX_10 W47PEG_RX_11 Y37PEG_RX_12 AA42PEG_RX_13 AD36PEG_RX_14 AC48PEG_RX_15 AD40

PEG_TX#_0 J41

PEG_TX#_10 Y40

PEG_TX#_3 M40PEG_TX#_4 M42PEG_TX#_5 R48PEG_TX#_6 N38PEG_TX#_7 T40PEG_TX#_8 U37PEG_TX#_9 U40

PEG_TX#_1 M46

PEG_TX#_11 AA46PEG_TX#_12 AA37PEG_TX#_13 AA40PEG_TX#_14 AD43PEG_TX#_15 AC46

PEG_TX#_2 M47

PEG_TX_0 J42PEG_TX_1 L46PEG_TX_2 M48PEG_TX_3 M39PEG_TX_4 M43PEG_TX_5 R47PEG_TX_6 N37PEG_TX_7 T39PEG_TX_8 U36PEG_TX_9 U39

PEG_TX_10 Y39PEG_TX_11 Y46PEG_TX_12 AA36PEG_TX_13 AA39PEG_TX_14 AD42PEG_TX_15 AD46

L_CTRL_CLKM32

L_CTRL_DATAM33L_DDC_CLKK33L_DDC_DATAJ33

L_VDD_ENM29LVDS_IBGC44LVDS_VBGB43LVDS_VREFHE37LVDS_VREFLE38LVDSA_CLK#C41LVDSA_CLKC40

LVDSA_DATA#_0H47LVDSA_DATA#_1E46LVDSA_DATA#_2G40

LVDSA_DATA_1D45LVDSA_DATA_2F40

LVDSB_CLK#B37LVDSB_CLKA37

LVDSB_DATA#_0A41LVDSB_DATA#_1H38LVDSB_DATA#_2G37

LVDSB_DATA_1G38LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25TVB_DACH25TVC_DACK25

TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29CRT_TVO_IREFE29

CRT_REDJ28

CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

3 OF 10NB1C

CANTIGA-GM-GP-U-NF

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

3 OF 10NB1C

CANTIGA-GM-GP-U-NF

123

4

RN1303

SRN2K2J-1-GP

RN1303

SRN2K2J-1-GP

TP1304TP1304

12 R13022K37R2F-GP

R13022K37R2F-GP 1TP1302

Do Not StuffTP1302

Do Not Stuff

12 3

4RN1301

SRN2K2J-1-GP

RN1301

SRN2K2J-1-GP

TP1301TP1301

VSSAU48

VSS A23

VSSAR48VSSAL48VSSBB47VSSAW47VSSAN47VSSAJ47VSSAF47VSSAD47VSSAB47VSSY47VSST47VSSN47VSSL47VSSG47VSSBD46VSSBA46

VSSAV46VSSAR46VSSAM46VSSV46VSSR46VSSP46VSSH46VSSF46VSSBF44VSSAH44VSSAD44VSSAA44VSSY44VSSU44VSST44VSSM44VSSF44VSSBC43VSSAV43VSSAU43VSSAM43VSSJ43VSSC43VSSBG42VSSAY42VSSAT42VSSAN42VSSAJ42VSSAE42VSSN42VSSL42VSSBD41VSSAU41VSSAM41VSSAH41VSSAD41VSSAA41VSSY41VSSU41VSST41VSSM41VSSG41VSSB41VSSBG40VSSBB40VSSAV40VSSAN40VSSH40VSSE40VSSAT39VSSAM39VSSAJ39VSSAE39VSSN39VSSL39VSSB39VSSBH38VSSBC38VSSBA38VSSAU38VSSAH38VSSAD38VSSAA38VSSY38VSSU38VSST38VSSJ38VSSF38VSSC38

VSSBD36

VSS AM36VSS AE36VSS P36VSS L36VSS J36VSS F36VSS B36VSS AH35VSS AA35VSS Y35VSS U35VSS T35VSS BF34VSS AM34VSS AJ34VSS AF34VSS AE34VSS W34VSS B34VSS A34VSS BG33VSS BC33VSS BA33VSS AV33VSS AR33VSS AL33VSS AH33VSS AB33VSS P33VSS L33VSS H33VSS N32VSS K32VSS F32VSS C32VSS A31VSS AN29VSS T29VSS N29VSS K29VSS H29VSS F29VSS A29VSS BG28VSS BD28VSS BA28VSS AV28VSS AT28VSS AR28VSS AJ28VSS AG28VSS AE28VSS AB28VSS Y28VSS P28VSS K28VSS H28VSS F28VSS C28VSS BF26VSS AH26VSS AF26VSS AB26VSS AA26VSS C26VSS B26VSS BH25VSS BD25VSS BB25VSS AV25VSS AR25VSS AJ25VSS AC25VSS Y25VSS N25VSS L25VSS J25VSS G25VSS E25VSS BF24

VSSBF37VSSBB37VSSAW37VSSAT37VSSAN37VSSAJ37VSSH37VSSC37VSSBG36

VSSAU36

VSS AT24

VSS AH24

VSS AB24

VSS L24

VSSAY46

VSS G24

VSS E24

VSS AG23

VSS B23

VSS AY24

VSS AJ24

VSS AF24

VSS R24

VSS K24VSS J24

VSS F24

VSS BH23

VSS Y23VSSAK15

VSS AD12

VSS AJ6

VSS

9 OF 10NB1I

CANTIGA-GM-GP-U-NF

VSS

9 OF 10NB1I

CANTIGA-GM-GP-U-NF

123

4RN1302

SRN10KJ-5-GP

RN1302

SRN10KJ-5-GP

1 2R1301 75R2F-2-GPR1301 75R2F-2-GP

1 2R1307 150R2F-1-GPR1307 150R2F-1-GP

1

2

34

5

6

U1301

2N7002EDW-GP

U1301

2N7002EDW-GP

12

R130349D9R2F-GPR130349D9R2F-GP

1 2R1305 75R2F-2-GPR1305 75R2F-2-GP

1 2R131233R2J-2-GP R131233R2J-2-GP

1 2R1308 150R2F-1-GPR1308 150R2F-1-GP

1 2R131033R2J-2-GP R131033R2J-2-GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A ASM_LF7_GMCHSM_LF6_GMCH

SM_LF3_GMCHSM_LF2_GMCHSM_LF1_GMCH

SM_LF5_GMCHSM_LF4_GMCH

VCC_AXG_SENSEVSS_AXG_SENSE

+1.05V_VCCP

+1.5V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-Power(5/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

8700mA

3060mA

3000mA

SSID = MCH

Close to (G)MCH

On the edge

+1.05V_VCCP 50mA

VCC_AXF+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

157.2mAVCCD_HPLL

VCCA_SM_CK 26mA

139.2mAVCCA_MPLL

VCCA_HPLL 24mA

720mA+1.05V_VCCP

+1.05V_VCCP

VCCA_SM

+1.05V_VCCP

50mAVCCA_PEG_PLL

+1.8V_SUS

+1.8V_SUS 124mA

Supply Signal Group

3060mAVCC+1.05V_VCCP

Imax

1782mAVCC_PEG

852mAVTT

3000mAVCC_SM

456mAVCC_DMI

VCC_SM_CK

+1.05V_VCCP

+1.5V_RUN VCCD_TVDAC 35mA

+1.5V_RUN VCCA_PEG_BG 414uA

+1.05V_VCCP

+3.3V_RUN VCC_HV 105.3mA

321.35mA

VCCD_PEG_PLL

Coupling CAP

Coupling CAP

12 C

1414

SCD

1U10

V2KX

-5G

PC

1414

SCD

1U10

V2KX

-5G

P

12C

1408

SC1U

6D3V

2KX-

GP

C14

08SC

1U6D

3V2K

X-G

P

12 C

1421

SC1U

10V3

KX-3

GP

C14

21SC

1U10

V3KX

-3G

P

12

C14

12SC

10U

6D3V

5KX-

1GP

C14

12SC

10U

6D3V

5KX-

1GP

12

C14

13SC

1U10

V3KX

-3G

PC

1413

SC1U

10V3

KX-3

GP

12 C

1405

SC1U

6D3V

2KX-

GP

C14

05SC

1U6D

3V2K

X-G

P

12

C1415

SC22U

6D3V5M

X-2GP

C1415

SC22U

6D3V5M

X-2GP

12 C

1419

SCD

22U

10V2

KX-1

GP

C14

19SC

D22

U10

V2KX

-1G

P

12 C

1423

SCD

1U16

V2KX

-3G

PC

1423

SCD

1U16

V2KX

-3G

P

12 C

1428

SC4D

7U6D

3V5K

X-3G

PC

1428

SC4D

7U6D

3V5K

X-3G

P

12 C

1402

SCD

1U10

V2KX

-5G

PC

1402

SCD

1U10

V2KX

-5G

P

2

1

C14

20SC

D47

U6D

3V2K

X-G

P

2

1

C14

20SC

D47

U6D

3V2K

X-G

P

12

C1416

SC22U

6D3V5M

X-2GP

C1416

SC22U

6D3V5M

X-2GP

12 C

1425

SCD

1U16

V2KX

-3G

PC

1425

SCD

1U16

V2KX

-3G

P

12 C

1426

SCD

1U16

V2KX

-3G

PC

1426

SCD

1U16

V2KX

-3G

P

12 C

1429

SCD

1U16

V2KX

-3G

PC

1429

SCD

1U16

V2KX

-3G

P

TP1401TP1401

12 C

1403

SC1U

6D3V

2KX-

GP

C14

03SC

1U6D

3V2K

X-G

P

12C1

417

SCD

1U10

V2KX

-5G

P

C14

17

SCD

1U10

V2KX

-5G

P

12 C

1427

SC10

U6D

3V5K

X-1G

PC

1427

SC10

U6D

3V5K

X-1G

P

12 C

1430

SCD

1U10

V2KX

-5G

PC

1430

SCD

1U10

V2KX

-5G

P

12

C14

11SC

D1U

10V2

KX-5

GP

C14

11SC

D1U

10V2

KX-5

GP

12 C

1401

SCD

22U

10V2

KX-1

GP

C14

01SC

D22

U10

V2KX

-1G

P

12

TC14

01D

o N

ot S

tuff

DY TC14

01D

o N

ot S

tuff

DY

TP1402TP1402

VCC_NCTF AM32

VCC_NCTF AC30

VCC_NCTF AJ29

VCC_NCTF AK25

VCC_NCTF AA32VCC_NCTF Y32VCC_NCTF W32VCC_NCTF U32VCC_NCTF AM30VCC_NCTF AL30VCC_NCTF AK30

VCC_NCTF AG30VCC_NCTF AF30VCC_NCTF AE30

VCC_NCTF AL32

VCC_NCTF W30VCC_NCTF V30

VCC_NCTF AK32

VCC_NCTF AH29VCC_NCTF AG29VCC_NCTF AE29

VCC_NCTF AL28VCC_NCTF AK28VCC_NCTF AL26VCC_NCTF AK26

VCC_NCTF AJ32

VCC_NCTF AK24

VCC_NCTF AH32VCC_NCTF AG32VCC_NCTF AE32VCC_NCTF AC32

VCC_NCTF AC29VCC_NCTF AA29VCC_NCTF Y29VCC_NCTF W29VCC_NCTF V29

VCC_NCTF U30VCC_NCTF AL29VCC_NCTF AK29

VCC_NCTF AH30

VCC_NCTF AB30VCC_NCTF AA30VCC_NCTF Y30

VCCAG34VCCAC34VCCAB34VCCAA34VCCY34VCCV34VCCU34VCCAM33VCCAK33VCCAJ33VCCAG33VCCAF33

VCCAE33VCCAC33VCCAA33VCCY33VCCW33VCCV33VCCU33VCCAH28VCCAF28VCCAC28VCCAA28VCCAJ26VCCAG26VCCAE26VCCAC26VCCAH25VCCAG25VCCAF25VCCAG24VCCAJ23VCCAH23VCCAF23

VCCT32

VCC_NCTF AK23

POWER

VCC NCTF

VCC CORE

6 OF 10NB1F

CANTIGA-GM-GP-U-NF

POWER

VCC NCTF

VCC CORE

6 OF 10NB1F

CANTIGA-GM-GP-U-NF

12 C

1424

SC10

U6D

3V5K

X-1G

PC

1424

SC10

U6D

3V5K

X-1G

P

12C1

418

SCD

1U10

V2KX

-5G

P

C14

18

SCD

1U10

V2KX

-5G

P

VCC_SMAY32

VCC_SMBF31

VCC_SMAW29

VCC_SMBD32VCC_SMBC32VCC_SMBB32VCC_SMBA32

VCC_SMAW32VCC_SMAV32VCC_SMAU32VCC_SMAT32VCC_SMAR32VCC_SMAP32VCC_SMAN32VCC_SMBH31VCC_SMBG31

VCC_SMAN33

VCC_SMBG30VCC_SMBH29VCC_SMBG29VCC_SMBF29VCC_SMBD29VCC_SMBC29VCC_SMBB29VCC_SMBA29VCC_SMAY29

VCC_SMBH32

VCC_SMAV29VCC_SMAU29VCC_SMAT29VCC_SMAR29

VCC_AXG_NCTF V23VCC_AXG_NCTF AM21VCC_AXG_NCTF AL21VCC_AXG_NCTF AK21VCC_AXG_NCTF W21VCC_AXG_NCTF V21VCC_AXG_NCTF U21VCC_AXG_NCTF AM20VCC_AXG_NCTF AK20VCC_AXG_NCTF W20

VCC_AXG_NCTF V28

VCC_AXG_NCTF U20VCC_AXG_NCTF AM19VCC_AXG_NCTF AL19VCC_AXG_NCTF AK19VCC_AXG_NCTF AJ19VCC_AXG_NCTF AH19VCC_AXG_NCTF AG19VCC_AXG_NCTF AF19VCC_AXG_NCTF AE19VCC_AXG_NCTF AB19

VCC_AXG_NCTF W26

VCC_AXG_NCTF AA19VCC_AXG_NCTF Y19VCC_AXG_NCTF W19VCC_AXG_NCTF V19VCC_AXG_NCTF U19VCC_AXG_NCTF AM17VCC_AXG_NCTF AK17VCC_AXG_NCTF AH17VCC_AXG_NCTF AG17VCC_AXG_NCTF AF17

VCC_AXG_NCTF V26

VCC_AXG_NCTF AE17VCC_AXG_NCTF AC17VCC_AXG_NCTF AB17VCC_AXG_NCTF Y17VCC_AXG_NCTF W17VCC_AXG_NCTF V17VCC_AXG_NCTF AM16VCC_AXG_NCTF AL16VCC_AXG_NCTF AK16VCC_AXG_NCTF AJ16

VCC_AXG_NCTF W25

VCC_AXG_NCTF AH16VCC_AXG_NCTF AG16VCC_AXG_NCTF AF16VCC_AXG_NCTF AE16VCC_AXG_NCTF AC16VCC_AXG_NCTF AB16VCC_AXG_NCTF AA16

VCC_AXG_NCTF V25VCC_AXG_NCTF W24VCC_AXG_NCTF V24VCC_AXG_NCTF W23

VCC_SMAP29

VCC_SMBG32VCC_SMBF32

VCC_AXG_NCTF W28VCC_SMAP33

VCC_AXGY26VCC_AXGAE25VCC_AXGAB25VCC_AXGAA25VCC_AXGAE24VCC_AXGAC24VCC_AXGAA24VCC_AXGY24VCC_AXGAE23VCC_AXGAC23VCC_AXGAB23VCC_AXGAA23VCC_AXGAJ21VCC_AXGAG21VCC_AXGAE21VCC_AXGAC21VCC_AXGAA21VCC_AXGY21VCC_AXGAH20VCC_AXGAF20VCC_AXGAE20VCC_AXGAC20VCC_AXGAB20VCC_AXGAA20VCC_AXGT17

VCC_AXGAM15VCC_AXGAL15

VCC_AXGAJ15VCC_AXGAH15

VCC_AXGAF15VCC_AXGAB15

VCC_SM_LF AV44VCC_SM_LF BA37VCC_SM_LF AM40VCC_SM_LF AV21VCC_SM_LF AY5VCC_SM_LF AM10VCC_SM_LF BB13

VCC_AXGT16

VCC_AXGAG15

VCC_AXGAA15VCC_AXGY15VCC_AXGV15VCC_AXGU15VCC_AXGAN14VCC_AXGAM14VCC_AXGU14VCC_AXGT14

VCC_AXG_SENSEAJ14VSS_AXG_SENSEAH14

VCC_AXG_NCTF Y16VCC_AXG_NCTF W16VCC_AXG_NCTF V16VCC_AXG_NCTF U16

VCC_SM/NCBA36VCC_SM/NCBB24VCC_SM/NCBD16VCC_SM/NCBB21VCC_SM/NCAW16VCC_SM/NCAW13VCC_SM/NCAT13

VCC_AXGAE15

POWER

VCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

7 OF 10NB1G

CANTIGA-GM-GP-U-NF

POWER

VCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

7 OF 10NB1G

CANTIGA-GM-GP-U-NF

12 C

1422

SC1U

10V3

KX-3

GP

C14

22SC

1U10

V3KX

-3G

P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1D8V_VCC_SM_CK

1D05V_VCC_DMI

1D5VRUN_QDAC

1D05V_RUN_HPLL

1D05V_RUN_PEGPLL

M_VCCA_MPLL

M_VCCA_HPLL

1D05V_SM_CK

1D5VRUN_QDAC

1D05V_SM

VCCA_PEG_BG

1D05V_RUN_PEGPLL

M_VCCA_HPLL

M_VCCA_MPLL

1D05V_VCC_AXF

VTTLF1VTTLF2VTTLF3

1D05V_RUN_PEGPLL

VCC_HDA

M_VCCA_DAC_BG

3D3V_CRTDAC_S0

M_VCCA_DPLLA

M_VCCA_DPLLB

M_VCCA_DPLLA

M_VCCA_DPLLB

1D8V_TXLVDS_S3

1D8V_SUS_DLVDS

VCC_HDA

VCCD_TVDAC

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

+1.05V_VCCP

+1.5V_SUS

+3.3V_VCC_HV

+1.5V_RUN

+3.3V_CRT_LDO

+3.3V_CRT_LDO

+1.05V_VCCP

+3.3V_TV_DAC+3.3V_CRT_LDO

+3.3V_CRT_LDO

+5V_RUN

+1.8V_NB_S0

+1.8V_NB_S0

1D8V_TXLVDS_S3

+3.3V_RUN +3.3V_VCC_HV

+1.05V_VCCP

+3.3V_RUN +1.8V_NB_S0

Title


Date: Sheet of


DJ1 Montevina UMA A00Cantiga-Power/Filter(6/6)

Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

Title


Date: Sheet of



Custom


DJ1

220ohm 100MHz

120ohm 100MHz

120ohm 100MHz

852mA

1782mA

456mA

414uA

720mA

37.5mA

24mA

139.2mA

157.2mA

50mA

50mA321.35mA

50mA

35mA

60.31mA

124mA

105.3mA

64.8mA

13.2mA

79mA

2mA

118.8mA

SSID = MCH

Reserved for CRT ripple

I=300mA

NB:180mA

12

C1535SC10U6D3V3MX-GPC1535SC10U6D3V3MX-GP

12

C1518SC1KP50V2KX-1GPC1518SC1KP50V2KX-1GP

12C

1532

SCD

1U10

V2KX

-5G

P

C15

32

SCD

1U10

V2KX

-5G

P

1 2

R1514

Do Not Stuff

R1514

Do Not Stuff

12

C15

01D

o N

ot S

tuff

DY C15

01D

o N

ot S

tuff

DY

12

C1523Do Not StuffDYC1523Do Not StuffDY

12

C15

03SC

D1U

16V2

KX-3

GP

C15

03SC

D1U

16V2

KX-3

GP

12

C15

57

SC1U

6D3V

2KX-

GP

C15

57

SC1U

6D3V

2KX-

GP

1 2

R1515

Do Not Stuff

R1515

Do Not Stuff

12

EC15

01SC

1U10

V3KX

-3G

PEC

1501

SC1U

10V3

KX-3

GP

12 C

1545

SC10

U6D

3V5K

X-1G

PC

1545

SC10

U6D

3V5K

X-1G

P

12

C1533

SC10

U6D

3V5K

X-1G

P

C1533

SC10

U6D

3V5K

X-1G

P

1 2L1501

BLM18PG121SN1D-GP

L1501

BLM18PG121SN1D-GP

12

C1539SC22U6D3V5MX-2GPC1539SC22U6D3V5MX-2GP

12


12 C1

529

SCD

1U10

V2KX

-5G

PC

1529

SCD

1U10

V2KX

-5G

P

12 C

1514

SCD

01U

16V2

KX-3

GP

C15

14SC

D01

U16

V2KX

-3G

P

12

C15

16SC

4D7U

6D3V

3KX-

GP

C15

16SC

4D7U

6D3V

3KX-

GP

1 2

R1508

Do Not Stuff

R1508

Do Not Stuff

12

C15

12SC

D1U

16V2

KX-3

GP

C15

12SC

D1U

16V2

KX-3

GP

12 C

1548

SCD

1U10

V2KX

-5G

P

C15

48

SCD

1U10

V2KX

-5G

P

1 2L1503

BLM18BB221SN1D-GP

L1503

BLM18BB221SN1D-GP

1 2

R1510

Do Not Stuff

R1510

Do Not Stuff

1 2

R1520

Do Not Stuff

R1520

Do Not Stuff

1 2

R1511

Do Not Stuff

R1511

Do Not Stuff

1 2

R1502

Do Not Stuff

R1502

Do Not Stuff

1 2L1502

BLM18PG121SN1D-GP

L1502

BLM18PG121SN1D-GP

2

1

C15

51SC

D47

U6D

3V2K

X-G

P

2

1

C15

51SC

D47

U6D

3V2K

X-G

P

12


12 C

1544

SC10

U6D

3V5K

X-1G

PC

1544

SC10

U6D

3V5K

X-1G

P

12 C

1537

Do

Not

Stu

ff

DY C153

7

Do

Not

Stu

ff

DY

1 2

R1521

Do Not Stuff

R1521

Do Not Stuff

12 C

1505

SCD

01U

16V2

KX-3

GP

C15

05SC

D01

U16

V2KX

-3G

P

1 2

R1513

Do Not Stuff

R1513

Do Not Stuff

12 C

1542

SCD

1U10

V2KX

-5G

PC

1542

SCD

1U10

V2KX

-5G

P

1 2

R1504

Do Not Stuff

R1504

Do Not Stuff

12

C1549SC1U10V3KX-3GP

C1549SC1U10V3KX-3GP

12

TC15

01D

o N

ot S

tuff

DY TC15

01D

o N

ot S

tuff

DY

12C1

559

SCD

1U10

V2KX

-5G

P

C15

59

SCD

1U10

V2KX

-5G

P

12

C15

09SC

1U10

V3KX

-3G

PC

1509

SC1U

10V3

KX-3

GP

12

C15

11SC

D1U

16V2

KX-3

GP

C15

11SC

D1U

16V2

KX-3

GP

2

1

C15

53SC

D47

U6D

3V2K

X-G

P

2

1

C15

53SC

D47

U6D

3V2K

X-G

P

1 2

R1509

Do Not Stuff

R1509

Do Not Stuff

12

C15

10SC

1U10

V3KX

-3G

PC

1510

SC1U

10V3

KX-3

GP

12 C

1560

SCD

01U

16V2

KX-3

GP

C15

60SC

D01

U16

V2KX

-3G

P

12


12 C

1543

SC4D

7U6D

3V3K

X-G

Documents

5 4 3 2 1 D D DJ1 Montevina UMA Schematics Document uFCPGA … · 2014. 1. 7. · 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Wistron Corporation