5 Controller Area Networks

8/2/2019 5 Controller Area Networks

1/55

Controller Area Network

(CAN) StandardEmbedded Systems CMP 445

Spring 2011

Computer EngineeringCairo University


2/55

Outline

Introduction

Brief History

Design Objectives

CAN Architecture

Basic Concepts


3/55

Brief History

1986 CAN v1.0 by Robert Bosch GmbH.

1991 CAN v2.0 by Bosch.

1993 ISO 11898 CAN 1993 Mercedes S-class first car with CAN

2003 ISO 11898-1, 11898-2 revised CAN with

physical layer characteristics 2008 US OBD-II automotive diagnostic

standard mandates use of CAN


4/55

Design Objectives

Reliable communication To deal with bit errors

Fault tolerance

To deal with hardware faults Low development cost

Low cost components, interconnect, andprogramming

Data rates up to 1Mbps (a big deal in the 1980s) Expandability

Open systems, nodes can be added with noreconfiguration cost


5/55

ISO 11898: Architecture

Transceiver implements

most of the PhL

Controller implements

Phy signaling and DLL Controller can be

integrated or separate

Application is not partof the standard


6/55

RT = 120

node

1

node

2

node

3

node

n

A typical CAN bus setup using cable

CAN_H

CAN_L

RT(120

Physical CAN Bus Connection

CAN is designed for data communication over a shortdistance.

CAN protocol does not specify what medium to use for datacommunication.

Using a shielded or unshielded cable is recommended for ashort distance communication.

A typical CAN bus setup using a cable is shown.


7/55

The Physical Layer

Physical signal specifications

Electrical specifications

Bit encoding

Bit timing

Bit synchronization


8/55

The Data-Link Layer

Logical Link Control

Message acceptance filtering

Overload notification (flow control)

Error recovery management

Medium Access Control

Message framing

Arbitration

Error detection

Frame coding (Bit-stuffing)


9/55

Basic Concepts

Acceptance Filtering

Bus Arbitration

Bit Synchronization Error Detection and Signaling

Fault Confinement

Bus Length vs. Bit Rate


10/55

Acceptance Filtering

Broadcast system: all nodes can hear a transmission

To avoid wasting processing power listening to

uninteresting transmissions Nodes implement a filter, to pass on messages based on their

identification which usually represent their content

all other messages are ignored.


11/55

Bus Arbitration

Physical Characteristics

NRZ Coding Scheme

Differential Signaling

CSMA

Collision Detection

Contention Resolution


12/55

NRZ Coding

Non-Return-to-Zero NRZ encoding scheme

0 and 1 are encoded as a voltage levels

A transition in signal level occurs only when a 0

is followed by 1 or vice-versa.


13/55

Differential Signaling

1 encoded asrecessive

0 encoded as

dominant


14/55

CSMA

Carrier Sense Multi-Access

Every node must sense the channel and make

sure it is idle for a minimum period of time

(intermission period) before starting a frame

transmission.

Avoids collision with on-going transmissions

Problem: if two node start transmitting at the

exact same time


15/55

Collision Detection

CAN bus behaves likean AND gate. If anynode writes adominant bit 0, the

bus will have adominant state 0.Otherwise, the bus willhave a recessive state1.

Each transmittingnode samples the busduring each bit. Ifwritten sampled, acollision is detected


16/55

Contention Resolution

Frame starts with an11-bit id fieldtransmitted mostsignificant bit first

A node detecting acollision (busdominant whiletransmittingrecessive) stops

Messages with lowbinary value id win

Losing node retriesafter bus is idle


17/55

Synchronization

No global clock signal, nodes use local oscillators

Local bit time vary slightly from nominal bit time

Periodic errors accumulate and synch is lost


18/55

Synchronization Mechanism

A receiver synchronizes to the transmitter clock bydetecting transitions and compensating local clock

Hard synchronization with first recessive-to-dominant edge(=dominant Start Of Frame (SOF)bit) after bus idle

Continuous re-synchronization at every recessive-to-dominant edge transition


19/55

Bit Stuffing

NRZ has not enough edges for resynchronization

After 5 consecutive bits with same polarity

(dominant or recessive), a bit with

complementary polarity will be inserted

Receiver filters the complementary bit away


20/55

Nominal bit time

sync_seg prop_seg phase_seg1 phase_seg2

Sample point

Nominal Bit Time

The inverse of the nominal bit rate is the

nominal bit time.

A nominal bit time is divided into four

segments


21/55

sync_seg Segment

A synchronized receiver expects a falling edge

transition to occur only within this segment.

When the receiver is slower the falling edge

will tend to occur earlier in phase_seg2 of the

previous bit time.

When the receiver is faster the falling edge

will tend to occur later in the prop_seg or

phase_seg1 of the same bit time.


22/55

prop_seg Segment

Equals twice the sum of the signals

propagation time on the CAN bus line, the

input comparator delay, and the output driver

delay.

A transmitter expects acknowledgement bit to

arrive from a synchronized receiver right after

prop_seg


23/55

CAN Message Bit Timing

Clock of receiver Bis shifted byprop_seg/2

Acknowledgementbit will arrive rightafter prop_seg

The sampling must

occur within theremaining phasesegments


24/55

phase_seg1 and phase_seg2

Used for compensating for edge phase errors

phase_seg1 can be lengthened to compensate

for a fast receiver, when an edge occurs after

the sync_seg and before the sample point

phase_seg2 can be shortened to compensate

for a slow receiver, when an edge occurs after

the sample point and before the sync_seg of

the next bit


25/55

Sample Point

At the end ofphase_seg1 segment.

Users can choose to take three samplesinstead of one.

A majority function determines the bit value whenthree samples are taken.

Each sample is separated by half time quantumfrom the next sample.

The time spent on determining the bit value isthe information processing time.


26/55

Time Quantum (TQ)

A fixed time unit for measuring thelength of segments within the bit timesync_seg = 1 TQ

1 TQ prop_seg 8 TQ1 TQ phase_seg1 8 TQ

max(phase_seg1, IPT) phase_seg2 8

Derived from local oscillator by divisionover a prescale value


27/55

Resynchronization Jump Width

The maximum amount by which phase_seg1can be lengthened (in case of fast receiver) orphase_seg2 can be shortened (in case of slow

receiver). 1 TQ SJW min(4, phase_seg1) TQ


28/55

Bus Length vs. Signaling Rate

The nominal bit time shouldbe long enough to allow thesignal has to propagate tothe most remote node and

back again (round trip)before the bit is sampled

Propagation velocity (0.1-0.2 m/ns); depends on cableand node impedance

Further considerationinclude: transceiver delay,sample time tolerance, etc.

Bus Length

(m)

Signaling Rate

(Kbps)

40 1000

100 500

200 250500 100

1000 50

<

2


29/55

Setting the CAN Timing Parameters

Nominal bit time (NBT)NBT = 1 / bitrate (1)

The worst-case value for tPROP_SEG istPROP_SEG = 2 (tBUS + tTX + tRX) (2)

In units of time quantum,prop_seg = round_up (tPROP_SEG TQ) (3)

In the absence of bus errors, bit stuffing guarantees amaximum 12-bit between resynchronization edges.

The accumulated phase errors are due to the tolerance inthe CAN system clock. This requirement can be expressed

as(2 f) 12 NBT < tSJW (4)where, f is the largest absolute relative error in

oscillator frequency (usu. < 0.5%)


30/55

Procedure for Determining

the Optimum Bit Timing Parameters

1. Determine the NBT = 1/bitrate (eq. 1)

2. Determine the minimum tPROP_SEG (eq. 2)

3. Choose a prescale factor to generate the CAN

system clock frequency. The chosen clockfrequency must make the NBT an integralmultiple of TQ, where 8 NBT/TQ 25

4. Calculate the prop_seg duration (eq. 3) If the

resultant value is greater than 8, go back to Step3 and choose a lower CAN system clockfrequency.


31/55

Procedure for Determining

the Optimum Bit Timing Parameters

5. phase_seg1 + phase_seg2 = (NBT/TQ) - (prop_segvalue+1) If < ceil(IPT/TO) +1 , go back to Step 3 and select a higher CAN

system clock frequency.

6. Determine phase_seg1 and phase_seg2 to satisfy thefollowing constraints 8 phase_seg1 1

8 phase_seg2 max( ceil(IPT/TQ), phase_seg1)

To maximize SJW, phase_seg2 = phase_seg1 or phase_seg1+1

7. Determine the resynchronization jump width (SJW) SJW = min (4, phase_seg1)

8. Calculate the oscillator tolerance (eq. 4).


32/55

Example: Problem

Calculate the CAN bit segments for the followingconstraints:

Bit rate = 1 Mbps

Bus length = 25 m Bus propagation delay = 5 10-9 sec/m

Output driver plus input comparator propagationdelay = 150 ns at 85oC

CPU oscillator frequency = 24 MHz IPT = 2 TQ

Find the oscillator frequency error tolerance


33/55

Example: Solution

1. NBT = 1/1 Mbps = 1 s

2. Physical delay of the CAN bus = 25 5 = 125 nstPROP_SEG = 2 (125 + 150) = 550 ns

3. A prescaler of 1 for 24 MHz gives a time quantum of 41.67 ns.

4. Prop_seg = round_up (550 ns 41.67) = 14 > 8. Set prescaler to 2.

Then one time quantum is 83.33 ns and one bit time is 12 timequanta. The new prop_seg = 7.

5. NBT prop_seg1 sync_seg = 12 7 1 = 4.

6. phase_seg1 = 2, phase_seg2 = 4 phase_seg1phase_seg2 = 2

7. SJW = min (4, phase_seg1)SJW = 2

8. f < SJW (2 12 NBT) = 2 (2 12 12) = 0.69%

The oscillator tolerance is 0.69%.


34/55

Example 13.2 Calculate the CAN bit segments for the following constraints: Bit rate = 500 Kbps Bus length = 50 m Bus propagation delay = 5 10-9 sec/m

CAN transceiver plus receiver propagation delay = 150 ns at 85oC CPU oscillator frequency = 16 MHz

Solution: Step 1

Physical delay of the bus = 50 5 10-9 sec/m = 250 nstPROP_SEG = 2 (250 + 150) = 800 ns Step 2Use 2 as the prescaler.The resultant TQ is 125 ns. A normal bit time is 2 ms.

Quanta per bit = 2,000 /125 = 16Step 3Prop_seg = round_up (800 125) = 7.Step 4Subtract 7 and 1 from 16 time quanta per bit gives 8. Since this number iseven and greater than 4, divide it by 2 and assign it to phase_seg1 andphase_seg2.


35/55

Step 5RJW = min (4, phase_seg1) = 4

Step 6From equation 13.6,

f < RJW (2 12 NBT) = 4 (24 16) = 1.04% In summary,

Prescaler = 2Nominal bit time = 16Prop_seg = 7Sync_seg = 1Phase_seg1 = 4Phase_seg2 = 4

RJW = 4Oscillator tolerance = 1.04%


36/55

CAN DLL Protocol

Types of CAN Messages

Frame Format


37/55


38/55

Types of CAN Messages (2 of 2)

Two states of CAN bus

Recessive: high or logic 1

Dominant: low or logic 0


39/55

Start of

frame

Arbitration

field

Control

field

Data

field

CRC

field

ACK

field

End of

frame

Data FrameInterframe

space

Interframe

space or

overload

frame

CAN Data frame

Data Frame

A data frame consists of seven fields: start-of-

frame, arbitration, control, data, CRC, ACK,

and end-of-frame.


40/55

Start of Frame

A single dominant bit to mark the beginning of

a data frame.

All nodes have to synchronize to the leading

edge caused by this field.


41/55

There are two formats for this field: standard format and extended format.

The identifier of the standard format corresponds to the base ID in the extendedformat.

The RTR bit is the remote transmission request and must be 0 in a data frame. The SRR bit is the substitute remote request and is recessive.

The IDE field indicates whether the identifier is extended and should be recessivein the extended format.

The extended format also contains the 18-bit extended identifier.

Start of frame 11 bit Identifier RTR

Arbitration field Control fieldInterframe

space

IDE r0 DLC

(a) standard format

Start of

frame 11-bit identifier

(b) extended format

SRR IDE 18-bit identifier RTR r0 r1 DLC

Arbitration field Control field

Arbitration Field


42/55

Control FieldArbitration

field

Data field

or CRC field

IDE/r1 r0 DLC3 DLC2 DLC1 DLC0

reserved bits Data length code

Figure 13.4 Control field

Control Field

Contents are shown in figure 13.4.

The first bit is IDE bit for the standard format butis used as reserved bit r1 in extended format.

r0 is reserved bit.

DLC3DLC0 stands for data length and can befrom 0000 (0) to 1000 (8).


43/55

Data Field

May contain 0 to 8 bytes of data


44/55

CRC field

CRC sequence CRC delimiter

Data or

Control field ACK

Figure 13.5 CRC field

CRC Field

It contains the 16-bit CRC sequence and a CRC

delimiter.

The CRC delimiter is a single recessive bit.


45/55

ACK Field

Consists of two bits

The first bit is the acknowledgement bit.

This bit is set to recessive by the transmitter, but

will be reset to dominant if a receiver

acknowledges the data frame.

The second bit is the ACK delimiter and is

recessive.


46/55

Remote frame

Start of

frame

arbitration

field

Control

field

CRC

field

ACK

field

End of

frame

Interframe

space

Interframe

space or

overload

frame

Figure 13.7 Remote frame

Remote Frame

Used by a node to request other nodes to

send certain type of messages

Has six fields as shown in Figure 13.7 These fields are identical to those of a data frame

with the exception that the RTR bit in the

arbitration field is recessive in the remote frame.


47/55

Error frame

error flag

Superposition of

error flags

error delimiter

Interframe space

or

Overload frame

Data

frame

Figure 13.8 Error frame

Error Frame

This frame consists of two fields. The first field is given by the superposition of error flags contributed from

different nodes.

The second field is the error delimiter.

Error flag can be either active-error flag or passive-error flag. Active error flag consists of six consecutive dominant bits.

Passive error flag consists of six consecutive recessive bits.

The error delimiter consists of eight recessive bits.


48/55

Overload flag

Superposition of

overload flags

Overload delimiter

Overload frame

Interframe space

orOverload frame

End of frame or

Error demiliter orOverload

delimiter

Figure 13.9 Overload frame

Overload Frame

Consists of two bit fields: overload flag and overload delimiter

Three different overload conditions lead to the transmission of theoverload frame: Internal conditions of a receiver require a delay of the next data frame or

remote frame.

At least one node detects a dominant bit during intermission.

A CAN node samples a dominant bit at the eighth bit (i.e., the last bit) of anerror delimiter or overload delimiter.

Format of the overload frame is shown in Figure 13.9.

The overload flag consists of six dominant bits.

The overload delimiter consists of eight recessive bits.


49/55

Interframe space

Intermission bus idle

FrameFrame

Interframe space for non error-passive nodes or receiver of

previous message

Interframe Space (1 of 2)

Data frames and remote frames are separated frompreceding frames by the interframe space.

Overload frames and error frames are not precededby an interframe space (higher priority)


50/55

Interframe Space (2 of 2)

The intermission subfield consists of three recessive bits. During intermission no node is allowed to start

transmission of the data frame or remote frame. The period of bus idle may be of arbitrary length. After an error-passive node has transmitted a frame, it

sends eight recessive bits following intermission (lowerpriority), before starting to transmit a new message orrecognizing the bus as idle.

Interframe space

IntermissionSuspend

TransmissionBus Idle

FrameFrame

Interframe space for error-passive nodes


51/55

Bit Stream Encoding

The frame segments including start-of-frame, arbitration field, controlfield, data field, and CRC sequence are encoded by bit stuffing.

Whenever a transmitter detects five consecutive bits of identical value inthe bit stream to be transmitted, it inserts a complementary bit in theactual transmitted bit stream.

The remaining bit fields of the data frame or remote frame (CRC delimiter,

ACK field and end of frame) are of fixed form and not stuffed. The error frame and overload frame are also of fixed form and are not

encoded by the method of bit stuffing.

The bit stream in a message is encoded using the non-return-to-zero (NRZ)method.

In the non-return-to-zero encoding method, a bit is either recessive ordominant.


52/55

Errors (1 of 3)

Error handling

CAN recognizes five types of errors.

Bit error

A node that is sending a bit on the bus also monitors the bus.

When the bit value monitored is different from the bit value being

sent, the node interprets the situation as an error.

There are two exceptions to this rule:

A node that sends a recessive bit during the stuffed bit-stream of the

arbitration field or during the ACK slot detects a dominant bit.

A transmitter that sends a passive-error flag detects a dominant bit.


53/55

Errors (2 of 3)

Stuff error

Six consecutive dominant or six consecutive recessive levels occurs in

a message field.

CRC error

CRC sequence in the transmitted message consists of the result of theCRC calculation by the transmitter.

The receiver recalculates the CRC sequence using the same method

but resulted in a different value. This is detected as a CRC error.


54/55

Errors (3 of 3)

Form error Detected when a fixed-form bit field contains one or more illegal bits

Acknowledgement error

Detected whenever the transmitter does not monitor a dominant bitin the ACK slot

Error Signaling

A node that detects an error condition and signals the error bytransmitting an error flag

An error-active node will transmit an active-error flag.

An error-passive node will transmit a passive-error flag.


55/55

Fault Confinement

A node may be in one of thethree states: error-active, error-passive, and bus-off.

A node keeps count of receiveand transmit errors (REC, TEC)

An error-active node will transmit

an active-error frame (dominant)when detecting an error.

An error-passive node willtransmit a passive-error frame(recessive) when detecting anerror.

A bus-off node is not allowed totake part in bus communication.

Documents

5 Controller Area Networks