521.36 - RGB LIN Controller with Current Source - … · RGB LIN Controller with Current Source E521.36 PRODUCTION DATA – May 23, 2017 Pin Configuration Figure 1: Pin Configuration

RGB LIN Controller with Current Source E521.36 PRODUCTION DATA – May 23, 2017

Features• Integrated 16 bit microcontroller• 32kByte OTP• 128Byte customer usable non-volatile memory• 1.25kByte RAM• 16kByte SysROM containing standard LIN routines

and boot loader• 4 PWM generators with 48MHz and 16bit resolution• 2 Timer with 16bit resolution• ADC 12Bit / fS = 400kSa/s• JTAG debug interface usable as GPIO and/or analog

input• Hardware divider / multiplier• LIN-Bus transceiver (V2.2a) with integrated slave

node position detection (SNPD)• LIN UART with automatic bit rate detection (accuracy

< 0.15%)• 3 high-precision current mode LED drivers with cur-

rents up to 40mA and fast slopes• Full range voltage sense inputs• Battery supply range 5V to 28V• Full automotive qualification AEC-Q100• Package SO8EP

ApplicationsInterior light modules

General DescriptionThe E521.36 is a one chip solution for RGB ambient light application. It provides an integrated 16-bit micro-controller with 32kByte memory, EEPROM, a LIN trans-ceiver supporting LIN auto-addressing. The integrated current sources can be controlled by a 16bit PWM with a48MHz clock. This enables PWM cycle frequencies up to 700Hz with full resolution. Each driver can be used to drive external loads with currents up to 40mA.For power management and temperature compensation the device provides an integrated temperature sensor aswell as an supply voltage sensing circuitry. Furthermore,with the ADC in the measurement system and the differ-ential measurement of the forward voltage an effective compensation for ageing and temperature can be imple-mented.

Ordering InformationProduct ID Temp. Range Package

E52136B80D -40°C to +125°C SO8EP

Typical Operating Circuit

Figure 1: Typical application with low side current sources

ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Elmos Semiconductor AG Data Sheet QM-Nr.: 25DS0160E.02 1 / 129


Functional Diagram

Figure 1: Functional Diagram




Pin Configuration

Figure 1: Pin Configuration

Pin DescriptionNo Name Type Description

1 GND HV_S Analog groundLIN groundLED ground

2 LIN_M HV_A_IO LIN bus line (direction towards master)

3 LIN_S HV_A_IO LIN bus line (direction away from master)

4 VS HV_S Battery supply voltage

5 OUT0 AD_IO LED driver channel 0 & GPIO0



8 DB AD_IO Debug interface (GPIO3 and analog input)

EP ExposedPad

Connect to ground

Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage




Typical Operating Characteristics

Figure 1: Typical leakage current IOUTn,LEAK at pins OUTn.The IC is in normal mode and the pull-up and pull-down

resistors as well as the LED driver are disabled.

Figure 2: Typical current in sleep mode at pin VS




1 Absolute Maximum RatingsStresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages referred to Ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.

Table 1-1: Absolute Maximum Ratings

No. Description Condition Symbol Min Max Unit

1 Junction temperature TJ -40 125 °C

2 DC voltage at pin VS continuous VS -0.3 40 V

3 Voltage at pins OUTn n= 0,1,2 VOUT_n -0.3 VS +0.3

V

4 Voltage at pins LINM and LINS continuous VLIN_M/S -27 40 V

5 Current through pins LINM and LINS continuous ILIN_M,LIN_S -200 200 mA

6 Input voltage at pin DB VIO,DB -0.3 5.5 V




2 Recommended Operating ConditionsTable 2-1: Recommended Operating Conditions

No. Description Condition Symbol Min Typ Max Unit

1 Ambient temperature TAMB -40 - 125 °C

2 Ambient temperature for programming the OTP

TAMB,prog 0 - 40 °C

3 Functional range, besides LIN VS,FUNC 5.0 28 V

4 Functional range LIN transceiver VLIN,VS 7 18 V

5 Voltage applied to pin DB VS≥5V VDB -0.3 3.6 V




3 Electrical Characteristics(5.0V < VVS < 28V, -40°C < TAMB < +125°C, unless otherwise noted. Typical values are at VVS = 12.0V and TAMB = +25°C. Positive currents flow into the device pins.)

3.1 Power Supply and References; pin VS

Table 3.1-1: Power Supply: Electrical Parameters


1 Current in sleep mode at temperatures lessthan 40°C

Sleep mode,VS=VOUT,n=VLIN=13.5V,TAMB<40°C

IVS,SLEEP_LT 15 20 µA

2 Current in sleep mode at temperatures higher than 40°C

Sleep mode,VS=VOUT,n=VLIN=13.5V,TAMB>40°C

IVS,SLEEP_HT 25 30 µA

3 Power on threshold according to pin VS (rising edge)

VS,PU 4.5 5.0 V

4 Power down threshold according to pin VS (falling edge)

VS,PD 4.2 4.9 V

5 Hysteresis between power on and power down threshold*)

VS,Phys 0.3 V

*) Not tested in production

3.2 Current Mode LED Drivers; pin OUTn

Table 3.2-1: Current Mode LED Drivers: Electrical Parameters


1 Input current at pins OUTn, selectable in 5mA Steps

PWMLEDn=H, ENLEDn=H, VOUT_n > 0.5V

IOUT_n 5 40 mA

2 Output current accuracy at pins OUTn PWMLED_n=H, ENLED=H,VOUT_n > 0.5V

ACCIOUT_n -6 6 %

3 Output current accuracy at pins OUTn con-figured to sink 20mA

PWMLED_n=H, ENLED=H,VOUT_n > 0.5V, T = 25°C, IOUT_n = 20mA

ACCIOUT_n,20mA -3 3 %

4 10% to 90% rise time of the output current at pins OUTn

*)PWMLED_n=L->H, ENLED=H

trise,IOUT_n 150 ns

5 Pull up resistor at pins OUTn to pin VS dur-ing PWM-Low(off state), if configured

PWMLED_n=L, RPU,OUT_n enabled

RPU,OUT_n 100 kΩ

6 Pull-up resistance at LED drivers in low power states

Sleep mode or standby mode

RPU,sleep,OUT_n 30 kΩ

7 HIGH to LOW threshold at input stage of OUTn

VGPIO,n,th_L 2.0 V

8 LOW to HIGH threshold at input stage of OUTn

VGPIO,n,th_H 2.8 V





9 Pull down resistor at pins OUTn to pin GND, if digital input is enabled

Digital input enabled

RPD,OUT_n 120 kΩ


3.3 LIN Transceiver with Slave Node Position Detection (SNPD)

3.3.1 LIN Transceiver; pins LIN_M, LIN_S, GND

3.3.1.1 Characteristics

Table 3.3.1.1-1: LIN DC Characteristics


1 Recessive output voltage driver in recess-ive state

VLIN,REC - VS -1 0 V

2 Dominant output voltage driver in domin-ant state, VS = 7.0V, RLIN = 0.5kΩ to VS

VLIN,DOM 1.2 V

3 Dominant output voltage driver in domin-ant state, VS = 18V, RLIN = 0.5kΩ to VS

VLIN,DOM1 2.0 V

4 Receiver dominant level VLIN,THDOM / VS 0.4

5 Receiver recessive level VLIN,THREC / VS 0.6

6 LIN bus center voltage VLIN,BUSCNT = (VLIN,THDOM + VLIN,THREC) / 2

VLIN,BUSCNT / VS 0.475 0.525

7 Receiver hysteresis VLIN,THREC - VLIN,THDOM

VLIN,HYS / VS 0.175

8 Output current limitation VLIN = VVS,MAX = 18V

ILIN,LIM 40 200 mA

9 Pull up resistance RLIN,SLAVE 27.66 33.00 40.00 kΩ

10 Leakage current flowing into pin LIN transmitter pass-ive, 7V < VS < 18V, 7V < VLIN < 18V, VLIN > VS

ILIN,BUSREC 20 μA

11 Pull up current flowing out of pin LIN transmitter pass-ive, VS = 12, VLIN = 0V

ILIN,BUSDOM -1 mA

12 Leakage current, ground disconnected (VGND = VVS)

VS = 13.5V, 0V <VLIN < 18V

ILIN,NOGND -1 0.1 mA

13 Leakage current, supply disconnected VS = 0V, 0V < VLIN < 18V

ILIN 20 μA

Table 3.3.1.1-2: LIN AC Characteristics


1 BUS input capacitance*) 7V < VS < 18V CLIN,PIN 30 pF

2 Receive propagation delay tRXD,PDR 6 μs

3 Receive propagation delay symmetry tRXD,SYM -2 2 μs





4 Wake up debounce time1) tLIN,WU 70 150 μs

5 Duty cycle 12) VLIN,THREC(max) = 0.744*VS, VLIN,THDOM(max) = 0.581*VS, VS = 7V-18V, TBIT = 50us, DLIN,1 = tBUS-

REC(min)/(2*TBIT)

DLIN,1 0.396 -

6 Duty cycle 22) VLIN,THREC(min) = 0.422*VS, VLIN,THDOM(min) = 0.284*VS, VS = 7.6V-18V, TBIT = 50us, DLIN,2 = tBUS-

REC(max)/(2*TBIT)

DLIN,2 0.581 -

7 Duty cycle 32) V,LIN,THREC(max) = 0.778*VS, VLIN,THDOM(max) = 0.616*VS, VS = 7V-18V, TBIT = 96us, DLIN,3 = tBUS-

REC(min)/(2*TBIT)

DLIN,3 0.417 -

8 Duty cycle 42) VLIN,THREC(min) = 0.389*VS, VLIN,THDOM(min) = 0.251*VS, VS = 7.6V-18V, TBIT = 96us, DLIN,4 = tBUS-

REC(max)/(2*TBIT)

DLIN,4 0.590 -

9 Receive data baud rate in kBd/s high speed mode,VS = 13.5V

BLIN,RXD 115

10 Transmit data baud rate in kBd/s high speed mode,VS = 13.5V

BLIN,TXD 115

*) Not tested in production1) Defined digitally, tested via scan test2) for definition of TBIT see Figure 4.1.1.1-1,bus load conditions (CLIN,RLIN): 1nF, 1kΩ/6.8nF, 660Ω/10nF, 500Ω

3.3.1.2 LIN Failure detection and recovery

Table 3.3.1.2-1: LIN Failure detection and Recovery: Parameters


1 time out for TXD dominant clamping failure TxD dominant timeout detectionenabled

tLIN,TXD,DOM 8 12 16 ms




3.3.2 LIN Auto-addressing; pins LIN_M, LIN_S

Table 3.3.2-1: LIN Auto-addressing: Electrical Parameters


1 Bus pull-up current source for auto-ad-dressing

LIN_PHY.LIN_AA_CONFIG_MODESx.lin_ipu_sel_xxx=16

IPU,AA,2mA -2.16 -2.0 -1.84 mA

2 Bus shunt resistor*) 1) RSHUNT 0.65 1.22 Ω

3 Transimpedance of the AA amplifier in LSB/mA2)

-0.5V < VLIN_M < 2.5V, -5mA < ILIN_S < 25mA

GAA_DIFF 105

*) Not tested in production1) Parameter not individually tested in production. Total gain of auto-addressing path will be tested.2) The total transimpedance of auto-addressing path is determined by RSHUNT and ADIFF

Note: The auto-addressing functions have limited ground shift tolerance compared to normal LIN operation.

3.4 Measurement System

3.4.1 12Bit SAR ADC

Table 3.4.1-1: 12Bit SAR ADC: Electrical Parameters


1 Resolution (bit)*) N 12 Bit*) Not tested in production

3.4.2 Analog Multiplexer (AMUX)

Table 3.4.2-1: Analog Multiplexer: Electrical Parameters


1 Leakage current into pins OUTn (not selec-ted)

0V ≤ VOUTn ≤ VVS, channel OUTn not selected, pulldown resistor notselected,T=125°C

IOUTn,LEAK 120 nA

2 Input resistance of pin OUTn (selected, absolute voltage measurement at OUTn)

0V ≤ VOUTn ≤ VVS, Channel OUTn selected, pull up resistor not selected

ROUTn,ACT 500 kΩ

3 Settling time of the buffer*) 1) tbuf,settle 5 µs

4 A to D conversion factor of supply voltage measurement in LSB/V

AVS 135 146.25 156

5 A to D conversion factor of differential LED voltage measurement in LSB/V

1.0V < VS-VOUTn < 5.0V, VOUTn > 2V

ALEDn 660 780 900

6 A to D conversion factor of voltage meas-urement at pins OUTn in LSB/V

AOUTn 135 146.25 156





7 A to D conversion factor of voltage meas-urement at pin DB in LSB/V

ADB 1130 1170 1210

8 Offset in ADC measurement Valid for chan-nels DB and OUTn, ADC value > 60 LSB

AOffset -20 20 LSB

*) Not tested in production1) This time is corresponds to the sampling time extension

3.4.3 Temperature sensor

Table 3.4.3-1: Temperature Sensor: Electrical Parameters


1 ADC value of temperature measurement inLSB

TJ=125°C VTEMP,125°,ADC 1205

2 Temperature dependency on temperature measurement in LSB/K*)

TCVTEMP,ADC -4.2

3 Over-temperature shut down threshold TJ,OT,high 150 155 °C

4 Over-temperature recovery threshold TJ,OT,low 120 130 °C*) Not tested in production

3.5 Wake-up Logic and Power Mode Control

Table 3.5-1: Wake-up locgic and Power Mode Control: Electrical Parameter


1 Wake-up timer period with ideal oscillator frequency of 1MHz

Twu_timer 8.2 ms

3.6 Microcontroller Unit

3.6.1 Supporting Blocks

3.6.1.1 System Clock RC Oscillator

Table 3.6.1.1-1: System Clock Oscillator: Electrical Parameters


1 Output frequency FOSC_SYS 46 48 50 MHz

3.6.1.2 General purpose IO & Debug interface; pin DB

Table 3.6.1.2-1: Debug Interface: Electrical Parameters


1 Input threshold of pin DB (rising) VDB,th,rise 2.0 3.0 V

2 Input threshold of pin DB (falling) VDB,th,fall 1.7 2.7 V

3 Hysteresis of pin DB*) VDB,hys 0.3 V

4 Output voltage at HIGH level IDB = -5mA VDB,out,HIGH 2.7 3.0 3.3 V

5 Output voltage at LOW level IDB = 5mA VDB,out,LOW 0 0.1 0.25 V





6 Difference voltage between high output voltage VDB,out,HIGH and high threshold VDB,th,rise

VDB,diff_out,th 0.3 V

7 Pull-up resistance of pin DB when enabled Pull-up enabled RPU,DB 1.1 kΩ

8 Pull-down resistance of pin DB when IC is in reset

at power-on reset

RPD,DB 5 kΩ

9 Current sink at pin DB VDB=3.3V IDB,pd 10 mA

10 Time after reset after which the output at pin DB may be usable

Measured after POR at µC is released

tGPIO3,avail 30 ms


3.6.2 Memory IPs

3.6.2.1 OTP

Table 3.6.2.1-1: OTP: Electrical Parameters


1 Data Retention Time*) maximum 5 years in active mode

DROTP 15 years

2 Programming time of a single OTP Bit (logic 1)*)

successful pro-gramming after first attempt, no soak pulses needed

tPROG,OTP_BIT 120 us


3.6.2.2 EEPROM

Table 3.6.2.2-1: Timings


1 Read access time*) fSYS = 4 MHz tREAD_4MHz 2 us

2 Read access time*) fSYS = 24 MHz tREAD_24MHz 1 us

3 2 x 16 bit page erase time tERASE 4.2 9.0 ms

4 16 bit word program time tPROG 4.2 9.0 ms

5 Data retention of the EEPROM cells*) DREE 15 100 years

6 Endurance of the EEPROM cells*) ENEE 100 kcycles

7 Cumulative programming events*) 1) write_disturb 12.6 106

*) Not tested in production1) When an address is programmed, the unselected addresses can be subject to a write disturb stress. While a single write disturb event is not a concern, the cumulative effect of write disturb events can potentially cause bit-flips on the unselected addresses.




3.6.3 Sub Parts

3.6.3.1 LIN SCI Module (LINSCI)

Table 3.6.3.1-1: LIN Parameters


1 Value of accuracy of the byte field detec-tion*)

tBFS 1/16 2/16 TBIT

2 Earliest bit sample timetEBS <= tLBS

*)tEBS 7/16 TBIT

3 Latest bit sample timetEBS <= tLBS

*)tLBS 10/16 -

tBFS

TBIT





4 Functional Description

4.1 LIN Transceiver with Slave Node Position Detection (SNPD)

4.1.1 LIN Transceiver; pins LIN_M, LIN_S, GND

4.1.1.1 CharacteristicsThe LIN bus physical interface is implemented as a LIN 2.2a standard high-voltage single wire interface according to ISO 9141 for baud rates from 2.4kBds to 20.4kBds. The LIN bus Interface can be operated in Master or Slave mode. The LIN bus has two logical values. The dominant state - bus voltage near GND - represents logical LOW level and the recessive state - bus voltage near VS - represents logical HIGH level. In the recessive state, the bus is pulled high by an internal pull-up resistor and a diode in series, thus no external pull-up components are requiredfor slave applications. Master applications require an additional external pull-up resistor and a series diode. The LIN protocol output data stream is converted into the LIN bus signal through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer Specification Revision 2.2a. The receiver converts thedata stream from the bus.

Figure 4.1.1.1-1: LIN 2.2 physical layer timing

The LIN transceiver can handle a bus voltage swing from +40V down to ground and survives -27V. The device alsoprevents current flow through the LIN pin to the supply pin in case of a ground shift / loss or supply voltage discon-nection.




In sleep mode the LIN block requires a very low quiescent current by using a special wake up comparator allowing the remote wake up via the LIN bus. The sleep mode can be activated during recessive or dominant level of the LIN bus line.

To transmit data via LIN bus, the LIN transmitter must be activated. Therefore, bit PHY_CONFIG.lin_on must be set to H.

4.1.1.2 LIN High Speed ModeThe device supports a LIN high speed mode. This mode allows an increasing of the transmit and receive baud rate up to 115 kBds. To enter this mode see PHY_CONFIG.lin_hs.

4.1.1.3 LIN Wake UpThe device can be woken up remotely via pin LIN. The wake-up capability is enabled in low power states only.A falling edge at the pin LIN followed by a dominant bus level VLIN,DOM maintained for a time period of at least tLIN,WU ended by a rising edge results in a remote wake-up request. The wake-up request is only generated if the IC is in low power state when the rising edge at pin LIN is applied.

Figure 4.1.1.3-1: LIN wake up at rising edge

4.1.1.4 LIN Failure detection and recoveryThe device provides a failure detection for TXD dominant clamping. If TXD is clamped for tLIN,TXD,DOM to dominant thetransmitter is disabled. If TXD is released the failure is cleared and the transmitter is enabled again.

Figure 4.1.1.4-1: LIN TXD dominant failure

4.1.2 LIN Auto-addressing; pins LIN_M, LIN_S

The device supports an auto-addressing feature using the bus shunt method (BSM). If this optional feature is not used, the pin LIN_S has to be kept open. In this case, the device behaves like a standard LIN transceiver.

The auto-addressing feature added to the normal LIN bus functionality allows slave devices to detect their relative position within a bus system. The internal hardware extensions needed for that purpose are a shunt resistor between nodes LIN_M and LIN_S, a pull-up current source and a circuitry that allows to measure the differential voltage across the shunt resistor. The slaves within such a bus system have to be connected as a daisy-chain. Fig-ure 4.1.2-1 shows such a bus architecture.




Figure 4.1.2-1: LIN Bus auto-addressing architecture

On the left side of the schematic, the ECU is terminating the LIN bus. Next to it, there is a group of addressable slaves, each of them having its own auto-addressing circuitry. Finally, shown on the right side of the schematic, there may be some standard LIN bus transceivers without auto-addressing capability. They may be mixed up with the addressable slaves in any possible position.

The start of the addressing sequence is initialized by the ECU with a command sent to the slaves telling them that the addressing sequence starts with the next break field. During the next break field, each slave starts its auto-ad-dressing sequence. The sequence is divided up in measuring the offset current on the bus line, measuring the bus load and, depending on the bus load, switching on the current source for the detection of the last not addressed slave in the line.

Figure 4.1.2-2: LIN BSM auto-addressing block schematic of a single LIN slave

Figure 4.1.2-2 shows the auto-addressing support circuits of a single slave:• Pull-up resistor• Pull-up current source• Differential to single-ended voltage amplifier with shunt resistor connected to ADC




The different parts can be controlled by software via the registers of the LIN_CTRL Module (e.g. PHY_CONFIG register). See chapter 4.4.6.8 for details. The ADC can be controlled by the ADC Control Module.

The software can either manage the auto-addressing sequence by accessing the LIN_CTRL registers and followingthe sequence shown in the flow chart diagram (Figure 4.1.2-3) or it can enable the implemented auto-addressing state machine (recommended).The state machine will step through the flow chart and will automatically set up the pull-up configurations and trig-ger the ADC measurements as well as calculating the measurement differences and compare the results to thresholds. Before enabling the state machine, the software has to configure the FSM control registers:• PHY_CONFIG• LIN_AA_CONFIG_MODES0 & LIN_AA_CONFIG_MODES1• LIN_AA_I_DIFF_THD_1 & LIN_AA_I_DIFF_THD_2

The following flowchart shows the command sequence executed during every synch break within the auto-address-ing process.




All slavesdetect break field

All slaves switch off allLIN pull-ups (offset phase)

Slave alreadyaddressed ?

Measure bus current ISHUNT1

switch on pull-up configuration1(pre-selection phase)


Calculate differenceIDIFF21 = ISHUNT2 - ISHUNT1

IDIFF21 > threshold ?

switch on pull-up configuration2(selection phase)


Calculate differenceIDIFF31 = ISHUNT3 - ISHUNT1

IDIFF31 > threshold ?

Slave saves NAD containedin auto-addressing command

All slaves switch offPull-up current source andswitch on 30kW LIN pullup

Master sends auto-addressingcommand

Masterchecks: all slaves

addressed ?

START

STOP

Switch off all LIN pull-up sources, wait for end of step 6

Y

N

N

N

N

Y

Y

Y

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Figure 4.1.2-3: Flowchart auto-addressing process

In order to assure that the different steps of the auto-addressing sequence are executed synchronously by all the slaves, a timing scheme for the break field is defined. The time reference is the bit time TBIT,SLAVE. The following tim-ing diagram shows the requested timing for the different steps executed during the break field.




Figure 4.1.2-4: Timing diagram auto-addressing process

The LIN auto-addressing measurement scheme is shown in Figure 4.1.2-5. The LIN auto-addressing amplifier has to be enabled at least tAA,en before it is used. First, the amplifiers auto-zeroing has to be enabled for a time t > tAA_AZ,act. When auto-zeroing has been finished, the amplifier is settling in tAA,set. After the settling time has elapsed, the measurements can be done for a time tAA,meas. A new auto-zero sequence has to initiated after this time.

Note: When using the auto-addressing state machine all timings are handled by the FSM. The timings are based on actual configured baud rate.

Figure 4.1.2-5: LIN auto-addressing measurement timing

4.2 Measurement System

4.2.1 12Bit SAR ADC

The ADC has a resolution of 12Bit. It uses a successive approximation algorithm to convert an input voltage to its digital representation. The algorithm uses two clock cycles for sampling phase and 12 cycles for conversion. The clock can be stopped during sampling phase to increase the settling time to ensure a full settling of the S&H stage.

The ADC has two sleep modes:• Power Down• No current consumption (except leakage)• Slow startup

• Standby• Reduced current consumption• Fast startup




4.2.2 Analog Multiplexer (AMUX)

Table 4.2.2-1: Analog mulitplexer for ADC measurements

Channel Source Ratio

0 VDIFF_AA 1:1

1 VS 1:8

2 VLED0 (VS-VOUT0) 2:3



5 VOUT0 1:8

6 VOUT1 1:8

7 VOUT2 1:8

8 VDB 1:1

9 VTEMP 1:1

Figure 4.2.2-1: Analog multiplexer structure and measurement architecture




The analog multiplexer is used to measure several voltages with the integrated ADC. Therefore, the selected chan-nel is buffered and then applied to the ADC input. The channels which can be selected are listed in Table 4.2.2-1 with their ratio from the output voltage to the input voltage.Note: To measure the forward voltage of the LEDs, the pull-up resistor at the corresponding pin has to be enabled.

4.2.3 Temperature sensor

The temperature sensor outputs a voltage which is linearly depended on temperature. The voltage can be meas-ured via ADC when the corresponding channel is selected.Additionally, an internal hardware temperature shut down is implemented ensuring the safety of the IC. At over-temperature events, the IC switches in an extra mode. This is described in 4.3.

4.3 Wake-up Logic and Power Mode Control

Figure 4.3-1: Power modes

The IC has an internal power mode and wake-up logic. This logic includes a state machine which can be controlled by the microcontroller. Furthermore, another timer is included in the logic. This timer can be used as wake-up timer.Additionally, the LIN receiver signal is evaluated to detect a wake-up request via LIN (see 4.1.1.3 for further inform-ation).

Figure 4.3-1 shows the states and the state transitions. After power up, the IC is in NORMAL mode. To go to SLEEP mode or STANDBY mode, the register POWER.sleep respectively POWER.standby has to be written with 1. If both registers are written at the same time the transition to SLEEP mode is prioritized.

Once in SLEEP or STANDBY mode, the IC can be woken up by LIN or by the wake-up timer. This leads to a trans-ition to NORMAL mode. All blocks necessary for normal function are enabled during this transition.

The microcontroller can now select the power mode by writing to register POWER in the system state module. Bothstates, SLEEP mode and STANDBY mode, behave in the same way except that in STANDBY mode the core regu-lator stays enabled to maintain the state of the microcontroller, thus the boot process is not needed. The system clock oscillator and the watchdog clock oscillator are disabled in STANDBY mode.

The wake-up timer is enabled if the timer configuration in register POWER is not 0x00 and the state is either SLEEP or STANDBY. See chapter 4.3.1 for additional notes on SLEEP and STANDBY mode. If the wake-up timer




is enabled, the wake-up logic will count upwards from zero to the defined value with a period of TWU_timer. When the configured value is reached, a transition to NORMAL mode is initiated.

To protect the IC, the integrated temperature sensor monitors the temperature in NORMAL mode to detect over-temperature events. In case of a junction temperature greater than TJ,OT,high, the IC goes into OVER-TEMPERAT-URE mode. This mode is equivalent to SLEEP mode. The transition to NORMAL mode is only initiated, if the junc-tion temperature falls below TJ,OT,low.

Table 4.3-1: Active blocks in the different power modes

Block SLEEP STANDBY NORMAL OVER-TEMPERATURE

Wake-up logic &power mode control

Active Active Active Active

Analog supply Active Active Active Active

LIN receiver (low-power mode)

Active Active Active Active

Temperature Sensor - - Active Active

1.8V core regulator - Active Active -

system clock &watchdog clock

- - Active -

LED driver - - Active -

All other blocks(depends onconfiguration)

- - Active -

4.3.1 Enter Sleep or Standby Mode

SLEEP Mode:Switching to SLEEP mode resets the digital part of the IC since the core regulator will be switched off. Waking up from SLEEP leads to system boot.

STANDBY Mode:When switching to STANDBY mode it is mandatory to additionally enter the CPU HALT mode for a clean CPU state during STANDBY. See chapter 4.4.5 for details. Be sure to enable interrupts, e.g. SYS_STATE wake-up event interrupts to be able to recover from CPU HALT after wake-up.Recommended procedure:a) configure and enable wake-up interruptsb) configure wake-up source, e.g. wake-up timer and set STANDBY bit in SYS_STATE.POWER registerc) set HALT bit in CPU status register

b+c is covered by the provided API function sys_state_go_to_standby.

Note:The API function is based on function code implemented in a ROM section of the memory located at address 0x0002:go_to_standby():

BIS #0x0018, R2 NOP NOP RET




4.4 Microcontroller UnitDigital Part Description

Figure 4.4-1: Digital Part Block Diagram (Note: Only 128Bytes of EEPROM memory are usable by customer)

4.4.1 Supporting Blocks

4.4.1.1 System Clock RC OscillatorThis oscillator clocks the digital system. The PWM and the OTP block are clocked directly with this clock whereas the other blocks are clocked with a frequency divided by 2.

4.4.1.2 General purpose IO & Debug interface; pin DBThe Debug interface is used to access the micro controller for debugging purposes. Additionally, it can be used as a general purpose IO (GPIO3) and analog input.The input can always be used, whereas the output has to be enabled by TEST_MODE.mode. The enabling is pro-tected by hardware for a time tGPIO3,avail after reset. This mechanism prevents enabling the general purpose output in this time after reset and delays it until tGPIO3,avail has elapsed.




Figure 4.4.1.2-1: GPIO3 output timing

4.4.2 Memory Map

Table 4.4.2-1: Address Table

base address size module name instance name description

0x8000 0x8000 OTP OTP OTP Memory (Customer Instruction Memory)

0x4000 0x4000 SYS_ROM SYS_ROM System ROM Memory

0x0B00 0x0500 SRAM SRAM SRAM Memory

0x0700 0x00A0 EEPROM EEPROM EEPROM Memory (Only 128Bytes are usable by cus-tomer)

0x0640 0x40 EEPROM_CTRL

EEPROM_CTRL

EEPROM Control Module

0x0600 0x40 OTP_CTRL OTP_CTRL OTP Control Module

0x0440 0x40 PWM PWM LED PWM Module

0x0400 0x40 ADC_CTRL ADC_CTRL ADC Control Module

0x0280 0x40 LIN_CTRL LIN_CTRL LIN PHY Control Module

0x0240 0x40 CRC16 CRC16 CCITT-CRC-16 Module

0x0200 0x40 GPIO GPIO GPIO Module

0x01C0 0x40 LINSCI LINSCI LIN SCI Module

0x0180 0x40 SYS_STATE SYS_STATE System State Module

0x0140 0x40 DIVIDER DIVIDER Divider Module

0x0100 0x40 H430_MUL H430_MUL H430 Multiplier Module

0x00C0 0x40 SWTIMER SWTIMER Timer Module

0x0080 0x40 WDOG WDOG Watchdog Module

0x0040 0x40 VIC VIC Vector Interrupt Controller Module

0x0000 0x40 ROM ROM Start-up ROM

4.4.3 Memory IPs

4.4.3.1 OTPThe micro controller system includes one instance of an OTP IP which is mapped into the address space as defined by the above Memory Map Table.The OTP instance is controlled by the OTP_CTRL module.




OTP ProgrammingAll memory cells in the macro are initially manufactured as "0"s and their state may be changed from a "0" to a "1" using the write (program) operation. Once programmed, it is not possible to reverse a "1" to a "0". Programming is done one cell at a time.

During program operation the "1"s in the data input word, are "burned" into the addressed memory location. "0"s inthe data input word mask programming in the corresponding bit locations.

Typically tPROG,OTP_BIT is needed to program a single logical "1".

Programming is completely controlled by a state machine which can be accessed via the OTP_CTRL module. See OTP_CTRL register description for details.

The state machine verifies the programmed bit location and, if necessary, repeats programming by inserting "soak pulses".The status of the latest word programming can be determined by accessing the OTP_CTRL.PROG_STATUS register.

4.4.3.2 System ROM (SYS_ROM)System ROM memory.• Size: 16Kbyte• Read only• Contains standard LIN routines which can be used by the executed user program or boot loader program.The System ROM content may vary depending on customer requirements and may contains for example:• Standard LIN routines (LIN stack)• Standard Elmos boot loader• Customer specific boot loader delivered by Elmos• Customer boot loader

4.4.3.3 EEPROMThe EEPROM instance is controlled by the EEPROM_CTRL module.

• lower 64 x 16 Bit for customer usage• Page erase (2 x 16 Bit) capability• Word write (1 x 16 Bit) capability

4.4.3.4 SRAM• Size: 1.25K byte• Byte write support• Per byte parity protection

4.4.3.5 Memory Access Protection• CPU and memory access via JTAG is protected by a logic which has to be set up via JTAG with the correct 64

bit signature value to allow full system access.• This signature value depends on a 64 bit customer specified signature value which is copied to SYS_STATE

module registers and locked during device INFO boot process before JTAG can halt device CPU for debug purpose.

• This 64 bit signature should also be used by software to allow memory access via LIN interface.

4.4.4 System Start-up

The digital system start up is done as follows:• The CPU executes the ROM start up code which checks the OTP memory for a valid boot vector located at

address 0x8004• If a valid OTP memory boot vector exists:




• The CPU executes the OTP memory start up code which is usually used to initialize the micro controller analog part calibration registers.

• The CPU returns to ROM start up code• The CPU fetches the user program reset vector which is located at address 0xFFFE in the OTP memory

which also enables the JTAG interface for CPU debugging• The CPU starts executing the user programAn OTP boot vector is valid if:• it's value is even (bit 0 == 0)• it points into first 0x80 bytes of OTP memory

4.4.5 CPU - H430

Features

• 16 bit CPU• MSP430 binary code compatible• Harvard architecture with AHBL data and instruction bus interfaces• RISC architecture with 27 instructions and 7 addressing modes• Orthogonal architecture: every instruction usable with every addressing mode• Full register access including program counter, status registers, and stack pointer• 16 x 16-bit register• 64 KByte linear address space• 16-bit native data bus width• Constant generator provides six most used immediate values and reduces code size• Direct memory-to-memory transfers without intermediate register holding• Word and byte addressing and instruction formats• IAR development IDE compatible JTAG debug interface• Several C compilers are available

Figure 4.4.5-1: H430 Environment Example




Interrupts

The embedded H430 IP core does not contain a primary interrupt controller. It has only a IRQ request signal and an address, pointing to a vector table in memory, which contains addresses of the interrupt handlers.Therefore the H430 IP does not support a fixed number of interrupts. Any number fitting reasonable in the 64k memory range is supported.All interrupts can be enabled or disabled with the GIE bit in the status register.

Handling an interrupt (other than RESET) consists of:• Push PC on stack.• Push SR on stack.• Choose the highest priority interrupt to service.• If there are multiple possible sources, leave them for software to poll.• Clear the SR, which disables interrupts and power-saving.• Fetch the interrupt vector into the PC• Start executing the interrupt handlerA reset is similar, but doesn't save any state.

You can nest interrupt handlers by disabling the current source and setting the GIE bit back to 1.

Byte and Word Issues

The H430 is byte-addressed, and Little-Endian. Word operands must be located at even addresses.Most instructions have a byte/word bit, which selects the operand size. Appending ".B" to an instruction makes it a byte operation. Appending ".W" to an instruction, to make it a word operation, is also legal. However, since it is alsothe default behavior, if you add nothing, it is generally omitted.A byte instruction with a register destination clears the high 8 bits of the register to 0. Thus, the following would clear the top byte of the register, leaving the lower byte unchanged:

MOV.B Rn,Rn

Mostly the on-chip peripherals support only one bus size, e.g. the data width of the processor. These peripherals must be accesses only with the supported access mode and with correct alignment. Any other access may producean undefined behavior.When performing a word access, address bit 0 is undefined and has to be ignored.

CPU States

The CPU supports the following states:

Table 4.4.5-1: CPU States

state description

RUN • normal operation of the CPU• the CPU accesses program storage and RAM• the CPU returns to RUN state on any interrupt

HALT • the CPU is halted• the HALT state is entered when setting HALT flag in status register• the CPU does not access program storage or RAM• the CPU returns to RUN state on any interrupt




CPU Halt Entry

After setting the halt bit in the CPU status register the following instruction will be executed, then halt mode will be entered. A good idea is to use the following sequence to ensure a later wake up.

BIS #0x18, SR ; sets halt flag and enables interrupts for wake upNOP ; needed for correct halt entry behavior

CPU Halt Exit

• An interrupt will force the CPU to exit the halt mode. The CPU will enter the interrupt service routine directly.• After the interrupt routine has been finished the CPU will NOT return to previous halt mode.• A system reset (e.g. by the watchdog) will restart the device and therefore exit the halt mode.

4.4.5.1 CPU RegistersThe processor has 16 16-bit registers, although only 12 of them are truly general purpose. The first four have ded-icated uses:

4.4.5.1.1 Program Counter (PC)The 16-bit Program Counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. The PC can be addressed with all instructions and addressing modes.

4.4.5.1.2 Stack Pointer (SP)The Stack Pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a pre-decrement, post-increment scheme. In addition, the SP can be used by software with all instructions and addressing modes. The SP is initialized into RAM by the user, and is aligned to even addresses.

4.4.5.1.3 Status Register (SR)The Status Register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the con-stant generator.

Table 4.4.5.1.3-1: Register Table

Register Name Address Description

Status Register SR/R2

Table 4.4.5.1.3-2: Register Status Register SR/R2

MSB LSB

Content - - - - - - - 8 - - - 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R R

Bit Description 8 : V4 : HALT3 : GIE2 : N1 : Z0 : C




V: Overflow bitThis bit is set when the result of an arithmetic operation overflows the signed-variable range.

HALT: Halt flagSee "CPU States" for details

GIE: Global Interrupt EnableGIE is the global interrupt enable. Turning off this bit masks interrupts. (NOTE: it may be delayed by 1 cycle, so an interrupt may be taken after the instruction after GIE is cleared. Add a NOP or clear GIE one instruction earlier thanyour "critical section".)

N: Negative bitThis bit is set when the result of a byte or word operation is negative and cleared when the result is not negative.Word operation: N is set to the value of bit 15 of the resultByte operation: N is set to the value of bit 7 of the result

Z: Zero bitThis bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0.

C: Carry bitThis bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred.

4.4.5.1.4 Constant Generation Registers (CG1 / CG2)Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. This is one of the important features of the H430 instruction set, allowing it to achieve a high level of code density, and a flexible instruction set.These constant registers can provide the numbers -1, 1, 2, 4 or 8. So, for example, the "CLR x" is actually emu-lated by the instruction "MOV #0,x". The constant "0" is taken from the constant register r3. The assembler under-stands both "CLR x" and "MOV #0,x", and produces the same code for either.The constants are selected with the source-register addressing modes (As):

Table 4.4.5.1.4-1: Register Table

Register As Value Remarks

R2 00 - Register mode (access R2)

R2 01 (0) Used for absolute address mode

R2 10 0x0004 Constant +4


R3 00 0x0000 Constant 0



R3 11 0xFFFF Constant -1

The constant generator advantages are:

• No special instructions required• No additional code word for the six constants• No code memory access required to retrieve the constantThe assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers.




4.4.5.1.5 General Purpose Registers (R4 - R15)The twelve registers, R4-R15, are general-purpose registers. All of these registers can be used as data registers oraddress pointers and can be used with byte or word instructions.

4.4.5.2 Addressing ModesThe available H430 instruction addressing modes have at most two operands, a source and a destination.All instructions are 16 bits long, followed by at most two optional offsets words, one for each of the source and the destination.

As Modes

The source operand is specified with 2 addressing mode bits (As):

Table 4.4.5.2-1: As Modes

As mnemonic remarks

00 Rn Register direct

01 X(Rn) Register indexed

10 @Rn Register indirect

11 @Rn+ Register indirect with post-increment

Ad Modes

The destination operand is specified with 1 addressing mode bit (Ad):

Table 4.4.5.2-2: Ad Modes

Ad mnemonic remarks

0 Rm Register direct

1 Y(Rm) Register indexed

The only addressing mode that uses an extension word is the indexed mode.The destination operand in a two-operand instruction has only one addressing mode bit, which selects either register direct or indexed. Register indirect can obviously be faked up with a zero index.When r0 (the program counter) is used as a base address, indexed mode provides PC-relative addressing. This is, in fact, the usual way that the H430 assembler accesses operands when a label is referred to.@r0 just specifies the following instruction word, but @r0+ specifies that word and skips over it. In other word, an immediate constant! You can just write #1234 and the assembler will specify the addressing mode properly.r1, the stack pointer, can be used with any addressing mode, but @r1+ always increments by 2 bytes, even on a byte access.

Table 4.4.5.2-3: Addressing Modes Table

As/Ad Addressing Mode Syntax Description

00/0 Register mode Rn Register contents are oper-and

01/1 Indexed mode X(Rn) (Rn + X) point to the oper-and. X is stored in the next word.

01/1 Symbolic mode ADDR (Rn + X) point to the oper-and. X is stored in the next word. Indexed mode X(PC) is used.




As/Ad Addressing Mode Syntax Description

01/1 Absolute mode &ADDR (Rn + X) point to the oper-and. X is stored in the next word. Indexed mode X(0) isused.

10/- Indirect Register mode @Rn Rn is used as a pointer to the

11/- Indirect auto increment @Rn+ Rn is used as a pointer to the operand. Rn is incre-mented afterwards by 1 for .B instructions and by 2 for .W instructions

11/- Immediate mode #N The word following the instruction contains the immediate constant N. Indirect auto-increment mode @PC+ is used.

Register Direct

Table 4.4.5.2-4: Register Direct

Assembler Code MOV R10,R11

Length One or two words

Operation Move the content of R10 to R11. R10 is not affected.

Comment Valid for source and destination

Note The data in the register can be accessed using word or byte instructions. If byte instruc-tions are used, the high byte is always 0 in the result. The status bits are handled accord-ing to the result of the byte instruction.

Register Indexed

Table 4.4.5.2-5: Register Indexed

Assembler Code MOV 2(R5),6(R6)

Length Two or three words

Operation Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execu-tion continues with the next instruction.

Comment Valid for source and destination

Register Indirect

Table 4.4.5.2-6: Register Indirect

Assembler Code MOV @R10,0(R11)


Operation Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified.

Comment Valid only for source operand. The substitute for destination operand is 0(Rd).




Register Indirect with post increment

Table 4.4.5.2-7: Register Indirect with post-increment

Assembler Code MOV @R10+,0(R11)


Operation Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing.

Comment Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd.

4.4.5.3 Instruction SetThe complete H430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instruc-tions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automat-ically by the assembler with an equivalent core instruction. There is no code or performance penalty for using emu-lated instruction.All instructions are 16 bits long, and there are only three instruction formats:

Figure 4.4.5.3-1: Instruction Coding

All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W extensions. Byte instructions are used to access byte data or byte peripherals. Word instructions are used to access word data or word peripherals. If no extension is used, the instruction is a word instruction.The source and destination of an instruction are defined by the following fields:

Table 4.4.5.3-1: Source and destination of an instruction

Abbr. Description

src The source operand defined by As and S-reg

dst The destination operand defined by Ad and D-reg

As The addressing bits responsible for the addressing modeused for the source (src)

S-reg The working register used for the source (src)

Ad The addressing bits responsible for the addressing modeused for the destination (dst)

D-reg The working register used for the destination (dst)

B/W Byte or word operation:0: word operation1: byte operation




Dual Operand Instructions

These basically perform dst = src op dst operations. However, MOV doesn't fetch the destination, and CMP and BIT do not write to the destination. All are valid in their 8 and 16 bit forms.

+ The status bit is affected- The status bit is not affected0 The status bit is cleared1 The status bit is set

Table 4.4.5.3-2: Dual Operand Instructions

Opcode Mnemonic S-Reg, D-Reg Operation V N Z C Remark

0100 MOV(.B) src, dst dst = src - - - - The status flags are NOT set.

0101 ADD(.B) src, dst dst += src + + + +

0110 ADDC(.B) src, dst dst += src + C + + + +

1000 SUB(.B) src, dst dst += ~src + 1 + + + +

0111 SUBC(.B) src, dst dst += ~src + C + + + +

1001 CMP(.B) src, dst dst - src + + + + Sets status only; the des-tination is not written.

1010 DADD(.B) src, dst dst += src + C, BCD

0 + + +

1011 BIT(.B) src, dst dst & src 0 + + + Sets status only; the des-tination is not written.

1100 BIC(.B) src, dst dst &= ~src - - - - The status flags are NOT set.

1101 BIS(.B) src, dst dst |= src - - - - The status flags are NOT set.

1110 XOR(.B) src, dst dst ^= src + + + +

1111 AND(.B) src, dst dst &= src 0 + + +

Single Operand Instructions

The status flags are set by RRA, RRC, SXT, and RETI.The status flags are NOT set by PUSH, SWPB, and CALL.

+ The status bit is affected- The status bit is not affected0 The status bit is cleared1 The status bit is set




Table 4.4.5.3-3: Single Operand Instructions


000 RRC(.B) dst C -> MSB -> ... -> LSB -> C

0 + + + 9-bit rotate right through carry. Clear the carry bit beforehand to do a logical right shift.

010 RRA(.B) dst MSB -> MSB ->... LSB -> C

0 + + + Badly named, this is an 8-bit arithmetic rightshift.

100 PUSH(.B) src SP-2 -> SPsrc -> @SP

- - - - Push operand on stack. Pushbyte decre-ments SP by 2.

001 SWPB dst swap bytes - - - - The destina-tion operand high and low bytes are exchanged. This has no byte form.

101 CALL src SP-2 -> SPPC+2 -> @SPsrc -> PC

- - - - Fetch operand,push PC, then assign oper-and value to PC.Note: the immediate form is the most com-monly used. There is no easy way to perform a PC-relative call; the PC-relativeaddressing mode fetches a word and uses it as an absolute address. This has no byte form.





110 RETI TOS -> SRSP+2 -> SPTOS -> PCSP+2 -> SP

+ + + + Pop SP, then pop PC.Note: The CPUOFF flag will not be stored to stackon interrupt entry, so the CPU will NOT return to low-power mode it was previouslyin.

011 SXT dst Bit 7 -> Bit 8........Bit 15

0 + + + Sign extend 8 bits to 16. No byte form.

Emulated Instructions

There are a number of zero- and one-operand pseudo-operations that can be built from these two-operand forms. These are usually referred to as "emulated" instructions:

Table 4.4.5.3-4: Emulated Instructions

Instruction Emulation Remark

NOP MOV r3,r3 Any register from r3 to r15 would do the same thing.Note: that other forms of a NOP instruction can be constructed as emu-lated instructions, which take different numbers of cycles to execute. These can sometimes be useful in constructing accurate timing patterns in software.

POP dst MOV @SP+,dst

BR dst MOV dst,PC Branch and return can be done by moving to PC (r0)

RET MOV @SP+,PC Branch and return can be done by moving to PC (r0)

CLRC BIC #1,SR The constants were chosen to make status register (r2) twiddling efficient

SETC BIS #1,SR The constants were chosen to make status register (r2) twiddling efficient

CLRZ BIC #2,SR The constants were chosen to make status register (r2) twiddling efficient

SETZ BIS #2,SR The constants were chosen to make status register (r2) twiddling efficient

CLRN BIC #4,SR The constants were chosen to make status register (r2) twiddling efficient

SETN BIS #4,SR The constants were chosen to make status register (r2) twiddling efficient

DINT BIC #8,SR The constants were chosen to make status register (r2) twiddling efficient

EINT BIC #8,SR The constants were chosen to make status register (r2) twiddling efficient

RLA(.B) dst ADD(.B) dst,dst Shift and rotate left is done with add

RLC(.B) dst ADDC(.B) dst,dst Shift and rotate left is done with add

INV(.B) dst XOR(.B) #-1,dst Some common one-operand instructions

CLR(.B) dst MOV(.B) #0,dst Some common one-operand instructions

TST(.B) dst CMP(.B) #0,dst Some common one-operand instructions

DEC(.B) dst SUB(.B) #1,dst Increment and decrement (by one or two)

DECD(.B) dst SUB(.B) #2,dst Increment and decrement (by one or two)




Instruction Emulation Remark

INC(.B) dst ADD(.B) #1,dst Increment and decrement (by one or two)

INCD(.B) dst ADD(.B) #2,dst Increment and decrement (by one or two)

ADC(.B) dst ADDC(.B) #0,dst Increment and decrement carry.

DADC(.B) dst DADD(.B) #0,dst Increment and decrement carry.

SBC(.B) dst SUBC(.B) #0,dst Increment and decrement carry.

Relative Jumps

Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jumprange is from -511 to +512 words relative to the PC value at the jump instruction. The 10-bit program-counter offsetis treated as a signed 10-bit value that is doubled and added to the program counter:

PCnew = PCold + 2 + PCoffset × 2

Table 4.4.5.3-5: Relative Jumps

Opcode Mnemonic Jump Condition

000 JNE/JNZ Z == 0

001 JEQ/JZ Z == 1

010 JNC/JLO C == 0

011 JC/JHS C == 1

100 JN N == 1

101 JGE N == V

110 JL N != V

111 JMP unconditionally




4.4.5.4 Instruction Cycle Counts

Figure 4.4.5.4-1: Cycle Count Table

4.4.5.5 JTAG Debug InterfaceTo access the debug structures a standard JTAG interface is used.

The debugging logic provides the following features:• CPU register read and write access• Data bus (memory) read and write access• Breakpoint logic• IAR can be used as debug IDE




The H430 embedded breakpoint logic provides the following features:• 3 breakpoint triggers• Each trigger can match a separate address or data bus value• A trigger value compare mask can be defined• Trigger can match a greater, smaller, equal or non-equal value• Trigger can be configured for read / write or instruction fetch / non instruction fetch bus cycles• Triggers can be combined (trigger dependency)• All breakpoints can be used for stepping and run-stop a program




4.4.6 Sub Parts

4.4.6.1 Vector Interrupt Control Module (VIC)Two Stage Vector Interrupt System

Description

The Vector Interrupt System is a two stage interrupt handling structure. The first stage is located inside the interruptcapable digital modules. The second stage collects all module interrupts and provides a single interrupt signal to the CPU. All module interrupts provided to the main interrupt controller are level interrupts.The Vector Interrupt Control (VIC) logic - included in every module and the main interrupt controller - is built as fol-lows:The incoming interrupt sources are latched by hold elements if the interrupt source is classified to be an "event". "level" interrupt sources are not latched to hold elements. "event" interrupt sources are usually conditions which areactive for a very short time and they need to be latched to be handled. Their latched status flag has to be cleared by the interrupt handling routine. "level" interrupt sources are usually slow signals and their status changes by the interrupt handling itself which removes the interrupt condition.The unmasked interrupt status can be read via the IRQ_STATUS register. Writing to the IRQ_STATUS register clears all "event" status bits which are written as one. The value of IRQ_MASK bit wise makes the interrupt status. The IRQ_MASK register can be written directly or modified using the IRQ_VENABLE and IRQ_VDISABLE registers. These two registers implement a fast vector based mask modification possibility.The masked interrupt status is converted to an integer value and compared with the value of the IRQ_VMAX register. It defines a maximum interrupt vector level for the outgoing interrupt.The IRQ_VNO register implements the possibility to read the current interrupt vector of the highest priority. Low vector numbers have high priority. This value can be used for a fast table based interrupt routine entry. A write access to the IRQ_VNO register clears the interrupt status bit of the written vector.

VIC Logic Structure:

Figure 4.4.6.1-1: VIC logic structure




Two Stage Interrupt System Structure:

Figure 4.4.6.1-2: Two stage interrupt system structure

Features

• IRQ number for fast IRQ processing• Main IRQ enable to enable or disable all IRQs• Main IRQ enable MIE for easy cli() and sei() implementation• IRQ base address for IRQ vector table in memory• Prioritized IRQ sources where irq 0 has highest priority• Fast vector based interrupt enable and disable• Nested IRQ support

Table 4.4.6.1-1: Registers


TABLE_BASE 0x00 Table base register

TABLE_TYPE 0x02 Table type register

MAIN_ENABLE 0x04 IRQ main enable register

IRQ_STATUS 0x30 IRQ status register 0

IRQ_MASK 0x34 IRQ mask register 0

IRQ_VENABLE 0x38 IRQ vector enable register

IRQ_VDISABLE 0x3A IRQ vector disable register

IRQ_VMAX 0x3C IRQ max vector register

IRQ_VNO 0x3E IRQ vector number register




Table 4.4.6.1-2: Register TABLE_BASE (0x00) Table base register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 15:0 : base - base address of vector table in memory

Table 4.4.6.1-3: Register TABLE_TYPE (0x02) Table type register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R R/W

Bit Description 0 : type - auto combine vector number and table base to create vectornumber related CPU interrupt pointer.0: base value is combined with vector number to be used asCPU interrupt pointer (an interrupt service routine per module)1: base value is directly used as CPU interrupt pointer (onecommon interrupt service routine)

Table 4.4.6.1-4: Register MAIN_ENABLE (0x04) IRQ main enable register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : enable - main interrupt enable / disable1: enabled0: disabled

Table 4.4.6.1-5: Register IRQ_STATUS (0x30) IRQ status register 0

MSB LSB

Content - - - - - - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 7 : lin_ctrl (level)6 : gpio (level)5 : swtimer (level)4 : sci (level)3 : pwm (level)2 : adc_ctrl (level)1 : divider (level)0 : sys_state (level)




Table 4.4.6.1-6: Register IRQ_MASK (0x34) IRQ mask register 0

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : mask - enable irq source1: enabled0: disabled

Table 4.4.6.1-7: Register IRQ_VENABLE (0x38) IRQ vector enable register

MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R W W W

Bit Description 2:0 : vno - vector number of interrupt to enable

Table 4.4.6.1-8: Register IRQ_VDISABLE (0x3A) IRQ vector disable register

MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 2:0 : vno - vector number of interrupt to disable

Table 4.4.6.1-9: Register IRQ_VMAX (0x3C) IRQ max vector register

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Access R R R R R R R R R R R R R/W R/W R/W R/W

Bit Description 3:0 : vmax - needed for nested interrupt supportsoftware writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest

Table 4.4.6.1-10: Register IRQ_VNO (0x3E) IRQ vector number register

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0


Bit Description 3:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused irq number is returned.write: vector number of interrupt event to clear




4.4.6.2 Watchdog Module (WDOG)Features• 8 bit pre-scaler• pre-scaler is driven by system clock

• 16 bit decrementing timer• this timer is driven by pre-scaled system clock

• the window-watchdog triggers a system reset when counter value = 0• when system clock is not running or stops the watchdog will assert a system reset• the watchdog clock is used to implement this feature

• when watchdog clock oscillator is not running or stops a system reset is asserted• the system clock is used to implement this feature

• window-watchdog timer is disabled after reset and has to be armed by software• window-watchdog generates a maskable reset when watchdog is restarted outside specified window• window-watchdog cannot be disabled or changed when armed• NOTE: watchdog will be halted during CPU debug halt• NOTE: watchdog will be halted during system standby mode

Figure 4.4.6.2-1: Structure




Figure 4.4.6.2-2: Timing



CONTROL 0x00 Control register

WINDOW 0x02 Window configuration register

PRESCALER 0x04 Pre-scaler configuration register

RELOAD 0x06 Counter reload value register

COUNTER 0x08 Current counter value register

Table 4.4.6.2-2: Register CONTROL (0x00) Control register

MSB LSB

Content 15:8 - - - - - - 1 0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R W R/W

Bit Description 15:8 : password -must be written as 0xA5will always be read as 0x961 : restart -0 : no influence1 : restart watchdogNote: Wait at least 3 watchdog clock periods between two successive restart commands becausethe restart command is also used to trigger the watchdog clock guard.0 : run_enable -0 - watchdog stopped1 - watchdog enabled




Table 4.4.6.2-3: Register WINDOW (0x02) Window configuration register

MSB LSB

Content - - - - - - - - - - - 4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Access R R R R R R R R R R R R/W R/W R/W R/W R/W

Bit Description 4 : enable -0 - window inactive : watchdog can be restarted all the time1 - window active3:0 : size -restart window is defined as: counter value < (2window size)

Table 4.4.6.2-4: Register PRESCALER (0x04) Pre-scaler configuration register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1


Bit Description 7:0 : val - watchdog counter pre-scaler (cycles = pre-scaler+1)

Table 4.4.6.2-5: Register RELOAD (0x06) Counter reload value register

MSB LSB

Content 15:0

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Bit Description 15:0 : val - counter restart value

Table 4.4.6.2-6: Register COUNTER (0x08) Current counter value register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - current counter value




4.4.6.3 Multiplier Module (H430_MUL)The hardware multiplier is a memory mapped peripheral (at a fixed address range from 0x130 to 0x13F). It can be accessed by CPU with full support of common compilers. Though the hardware architecture is different, the unit is fully compatible with the MPY16 multiplier unit in chips of the MSP430 family, providing the same interface, soft-ware support, and arithmetic results.The barrel shifter extension allows to shift either the 32/33 bit result of the multiply/MAC operation or any other 32 bit value by a variable number of bits. This unit can be accessed by a normal register interface.

Features• Unsigned/signed multiplication (MPY / MPYS)• Unsigned/signed MAC (multiply and accumulate) operation (MAC / MACS)• Using the old result and adding the new product• 16*16, 8*16, 16*8, and 8*8 bit input data width• 32/33 bit output data width• 1 system clock cycle calculation time• No CPU wait states (no NOP required)The type of operation to be performed is selected by writing the first operand to one of the following four registers. Writing the first operand does not start the operation. The first operand (and thus the type of operation) may remainconstant for more than one operation. Writing the second operand starts the operation.

SumLo stores the low word of the result, SumHi stores the high word of the result, and SumExt stores information about the result.For signed operations, results are provided in 2's complement format. The sum extension register SUMEXT allows calculations with results exceeding the 32-bit range. This read-only register holds the most significant part of the result (bits 32 and higher). The register simplifies multiple word operations, because straightforward additions can be performed without conditional jumps.

Figure 4.4.6.3-1: Multiplier Structure






LAST_MODE 0x00 Last mode of multiply/MAC unit

MPY 0x30 Multiply unsigned register

MPYS 0x32 Multiply signed register

MAC 0x34 Mac unsigned register

MACS 0x36 Mac signed register

OP2 0x38 Operand 2 register

RESLO 0x3A Result register (bits 15:0)

RESHI 0x3C Result register (bits 31:16)

SUMEXT 0x3E Sum extension register

Table 4.4.6.3-2: Register LAST_MODE (0x00) Last mode of multiply/MAC unit

MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 1:0 : last_mode - last mode of multiply/MAC unit:0x0 = MPY0x1 = MPYS0x2 = MAC0x3 = MACS

Table 4.4.6.3-3: Register MPY (0x30) Multiply unsigned register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - unsigned multiply

Table 4.4.6.3-4: Register MPYS (0x32) Multiply signed register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - signed multiply

Table 4.4.6.3-5: Register MAC (0x34) Mac unsigned register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - unsigned multiply accumulate




Table 4.4.6.3-6: Register MACS (0x36) Mac signed register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - signed multiply accumulate

Table 4.4.6.3-7: Register OP2 (0x38) Operand 2 register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts multiplication

Table 4.4.6.3-8: Register RESLO (0x3A) Result register (bits 15:0)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_lo - lower 16 bit of result

Table 4.4.6.3-9: Register RESHI (0x3C) Result register (bits 31:16)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_hi - In case of operation:MPY: upper 16 bit of resultMPYS: The MSB is the sign of the result. The remaining bits are the upper 15-bits of the result. Two's complement notation is used for the result.MAC: upper 16 bit of resultMACS: Upper 16-bits of the result. Two's complement notation is used for the result.




Table 4.4.6.3-10: Register SUMEXT (0x3E) Sum extension register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : sum_ext - In case of operation:MPY: always 0x0000MPYS: contains the extended sign of the result0x0000 if result was positive0xFFFF if result was negativeMAC: contains the carry of the result0x0000 no carry result0x0001 result with carryMPYS: contains the extended sign of the result0x0000 if result was positive0xFFFF if result was negative




4.4.6.4 Divider Module (DIVIDER)Features• unsigned and signed integer divide arithmetic• 32bit / 16bit• 32 bit result• 16 bit remainder

• 16 system clock cycles calculation time• If a result or remainder register is accessed before calculation has finished the read access is halted until the

calculation has finished and the value is valid



OP1LO 0x00 Operand 1 (low 16 bit)

OP1HI 0x02 Operand 1 (high 16 bit)

OP2 0x04 Unsigned operand 2 register

OP2S 0x06 Signed operand 2 register

RESULTLO 0x08 Result register (low 16 bit)

RESULTHI 0x0A Result register (high 16 bit)

REMAINDER 0x0C Remainder register

IRQ_STATUS 0x30 IRQ status register

IRQ_MASK 0x34 IRQ mask register





Table 4.4.6.4-2: Register OP1LO (0x00) Operand 1 (low 16 bit)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - operand 1 (lower 16 bit)

Table 4.4.6.4-3: Register OP1HI (0x02) Operand 1 (high 16 bit)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op1 - operand 1 (higher 16 bit)




Table 4.4.6.4-4: Register OP2 (0x04) Unsigned operand 2 register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts unsigned operation

Table 4.4.6.4-5: Register OP2S (0x06) Signed operand 2 register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : op2 - write access starts signed operation

Table 4.4.6.4-6: Register RESULTLO (0x08) Result register (low 16 bit)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : result - equals "op1 div op2" (lower part)

Table 4.4.6.4-7: Register RESULTHI (0x0A) Result register (high 16 bit)

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : result - equals "op1 div op2" (higher part)

Table 4.4.6.4-8: Register REMAINDER (0x0C) Remainder register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : remainder - equals "op1 mod op2"

Table 4.4.6.4-9: Register IRQ_STATUS (0x30) IRQ status register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : evt_div_by_zero (event) - divide by zero event




Table 4.4.6.4-10: Register IRQ_MASK (0x34) IRQ mask register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : mask - enable irq source1: enabled0: disabled


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R R W

Bit Description 0 : vno - vector number of interrupt to enable


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : vno - vector number of interrupt to disable


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vmax - needed for nested interrupt supportsoftware writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Bit Description 0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IRQ number is returned.write: vector number of interrupt event to clear




4.4.6.5 System State Module (SYS_STATE)Features• Device power management• Clock frequency selection• System clock frequency selection : influences CPU and module clock frequency• PWM module clock frequency selection• ADC_CTRL will always runs at 24MHz

• Reset source status• Reset enable• Reset source based sleep mode entry enable• Reset sources which are disabled will assert an interrupt if enabled• Reset sources which are disabled will enter sleep mode if enabled

• Parity protected calibration registersNote: Once set, RESET_ENABLE, SLEEP_ENABLE and CALIBRATION_LOCK bits cannot be cleared again.Note: CALIBRATIONx will be locked by CALIBRATION_LOCK. These registers will be initialized and locked by boot program after power up and are therefore not changeable by customer software.



POWER 0x00 Power control register

CONTROL 0x02 System control register

RESET_STATUS 0x04 Reset status register

RESET_STATUS_CLEAR

0x06 Reset status clear register

RESET_ENABLE 0x08 Reset enable register

SW_RESET 0x0A Software reset register

SLEEP_ENABLE 0x0C Sleep entry enable register

TEST_MODE 0x0E Test mode config register

SIGNATURE_0 0x10 Customer signature register




OSC_5V_CON-TROL

0x18 5V digital part oscillator control register

OSC_5V_STATUS 0x1A 5V digital part oscillator status register

TEST_MODE_COUNTER

0x1C Test mode counter register

ENABLE_JTAG 0x2C JTAG enable register










Table 4.4.6.5-2: Register POWER (0x00) Power control register

MSB LSB

Content - - - - - - - 8:2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R W W W W W W W W W

Bit Description 8:2 : wakeup_delay - selects a delay value after which the analogue part wake up timer will wake up the digital part0 : never1-127 : Twu_timer * wakeup_delay1 : standby - system standby mode activation (fast wakeup mode)Note: standby requests will be ignored until register TEST_MODE_COUNTER.val value has reached value 00 : sleep - system sleep mode activationNote: sleep requests will be ignored until register TEST_MODE_COUNTER.val value has reached value 0

Table 4.4.6.5-3: Register CONTROL (0x02) System control register

MSB LSB

Content - - - - - - - - - - - - - 2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Access R R R R R R R R R R R R R R/W R/W R/W

Bit Description 2 : pwm_clk_sel - PWM module clock selection0 : 24 MHz1 : 48 MHz1:0 : sys_clk_sel - system clock selection (CPU and all modules except PWM and ADC_CTRL)0: 24 MHz1: 12 MHz2: 8 MHz3: 4 MHz

Table 4.4.6.5-4: Register RESET_STATUS (0x04) Reset status register

MSB LSB

Content - - - - - - - 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 X X X X X X X X X


Bit Description 8 : cal_parity - calibration registers parity error reset flag7 : crc_mismatch - CRC16 calculation mismatch reset flag6 : watchdog_zero - watchdog counted to zero reset flag5 : watchdog - watchdog clock watch reset flag4 : watchdog_window - watchdog window reset flag3 : sram_parity - SRAM parity reset flag2 : software - software reset flag1 : sys_clk_fail - watchdog system clock watch reset flag0 : v1v8_ok - digital core voltage watch reset flag




Table 4.4.6.5-5: Register RESET_STATUS_CLEAR (0x06) Reset status clear register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : clear - writing clears RESET_STATUS register

Table 4.4.6.5-6: Register RESET_ENABLE (0x08) Reset enable register

MSB LSB

Content - - - - - - - - - 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W

Bit Description 6 : cal_parity - calibration registers parity error reset enable5 : crc_mismatch - CRC16 calculation mismatch reset enable4 : watchdog_zero - watchdog counted to zero reset enable3 : watchdog - watchdog clock watch reset enable2 : watchdog_window - watchdog window reset enable1 : sram_parity - SRAM parity reset enable0 : software - software reset enableNote: setting these registers to '1' will enable reset via the corresponding source

Table 4.4.6.5-7: Register SW_RESET (0x0A) Software reset register

MSB LSB

Content - - - - - - - - - - - - - - 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X

Access R R R R R R R R R R R R R R W R

Bit Description 1 : sw_reset - assert a system reset which also clears SW_RESET.por_flagNote: RESET_ENABLE.software has to be set to 1 before0 : por_flag - separate Power-On-Reset flag

Table 4.4.6.5-8: Register SLEEP_ENABLE (0x0C) Sleep entry enable register

MSB LSB

Content - - - - - - - - - 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 6 : cal_parity - calibration registers parity error sleep enable5 : crc_mismatch - CRC16 calculation mismatch sleep enable4 : watchdog_zero - watchdog counted to zero sleep enable3 : watchdog - watchdog clock watch sleep enable2 : watchdog_window - watchdog window sleep enable1 : sram_parity - SRAM parity sleep enable0 : software - software sleep enableNote: setting these registers to '1' will enable going to sleep via the corresponding source




Table 4.4.6.5-9: Register TEST_MODE (0x0E) Test mode config register

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x967:0 : mode - IC debug mode

default : debug mode ONswitched off by software which disconnects JTAG interface from pins when written with value dif-ferent than default value

Note: This configuration when changed by software will take affect not earlier than 30ms after digital core start up. This guarantees a JTAG availability of at least 30ms after digital core start up. If 2nd level JTAG access signature was written correctly during this time, this register config-uration will not take affect and device will stay in debug mode.

Table 4.4.6.5-10: Register SIGNATURE_0 (0x10) Customer signature register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - customer specific signature value (bits 15:0)may be used by software as valid key value to allow instruction memory read via LIN (e.g. an access key is received via LIN and compared by software with this 64 bit signature value to allow instruction memory content access)

used by hardware to allow JTAG access to CPU and instruction memory content

Note: Once written, this register cannot be set again.


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0









MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0






MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0





Table 4.4.6.5-14: Register OSC_5V_CONTROL (0x18) 5V digital part oscillator control register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : do_meas -1: do a 5V digital part oscillator frequency measurement (count system oscillator cycles fitting intotwo 5V digital part oscillator cycles)

Table 4.4.6.5-15: Register OSC_5V_STATUS (0x1A) 5V digital part oscillator status register

MSB LSB

Content - - - - - - - 8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 8 : busy - 1 : measurement in progress7:0 : meas_val - number of system oscillator cycles fitting into two 5V digital part oscillator cyclesNote: measurement is triggered by OSC_5V_CONTROL.do_measNote: meas_val is invalid when busy = 1




Table 4.4.6.5-16: Register TEST_MODE_COUNTER (0x1C) Test mode counter register

MSB LSB

Content - 14:0

Reset value 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0


Bit Description 14:0 : val - down counting value which represents the status of the 30ms interval use by TEST_MODE registerNote: value is decremented by 1 every 1usNote: sleep and standby requests will be ignored until register value has reached value 0

Table 4.4.6.5-17: Register ENABLE_JTAG (0x2C) JTAG enable register

MSB LSB

Content - - - - - - - - - - - - - - 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 1 : exit_boot_loader - exit boot loader request (digital TMR)0 : enable - enable CPU JTAG access


MSB LSB

Content - - - - 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 X X X X X

Access R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 11 : cal_parity (event) - calibration registers parity error event10 : crc_mismatch (event) - CRC calculation mismatch event9 : watchdog_zero (event) - watchdog counted to zero event8 : watchdog (event) - watchdog clock watch event7 : watchdog_window (event) - watchdog window event6 : sram_parity (event) - SRAM parity event5 : software (event) - software reset event triggered by SW_RESET register4 : jtag_wake_up (event) - standby and sleep state wake up event3 : temp_wake_up (event) - standby and sleep state wake up event2 : timer_wake_up (event) - standby and sleep state wake up event1 : lin_wake_up (event) - standby and sleep state wake up event0 : por5v_wake_up (event) - standby and sleep state wake up eventNote: Wake-up events can be set after reset, since they may be the wake-up source


MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R W W W W



MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0


Bit Description 3:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IEQ number is returned.write: vector number of interrupt event to clear




4.4.6.6 Timer Module (SWTIMER)This module implements the following features:

Features• 2 timers• Pre-divider with:• Reload value• Trigger reload possible by software• Event when zero

• Counter with:• Reload value• Trigger reload possible by software• Can be started / stopped• Automatic reload possible, otherwise counter stops when reaching zero (single shot mode)• Event when zero

Using the timers:

1. Set reload values for the counter and pre-scaler2. Enable the counter via the register CONFIG, choosing between free running and single shot mode3. Reload/restart the counter and or its pre-scaler by triggering a reload via the command register, e.g. to realign the phase of several counters



CONFIG 0x00 Config register

COMMAND 0x02 Command register

CNT0_RELOAD 0x04 Counter 0 reload value register

CNT1_RELOAD 0x06 Counter 1 reload value register

DIV0_RELOAD 0x08 Pre-divider 0 reload value register

DIV1_RELOAD 0x0A Pre-divider 1 reload value register

CNT0_VALUE 0x0C Counter 0 current value register

CNT1_VALUE 0x0E Counter 1 current value register










Table 4.4.6.6-2: Register CONFIG (0x00) Config register

MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : cnt_auto_reloads1: auto reload for counter n enabled, 0: disabled1:0 : enables1: counter n and pre-scaler n enabled, 0: disabledDisabling a running counter will stop the counter and pre-scalerimmediately.

Table 4.4.6.6-3: Register COMMAND (0x02) Command register

MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : div_reload_cmd1: trigger pre-divider n reload / restart1:0 : cnt_reload_cmd1: trigger counter n reload / restart

Table 4.4.6.6-4: Register CNT0_RELOAD (0x04) Counter 0 reload value register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_reload -counter reload value (cnt_reload_val = clock cycles -1)

Table 4.4.6.6-5: Register CNT1_RELOAD (0x06) Counter 1 reload value register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_reload -counter reload value (cnt_reload_val = clock cycles -1)

Table 4.4.6.6-6: Register DIV0_RELOAD (0x08) Pre-divider 0 reload value register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : div_reload -pre-divider reload value (div_reload_val = clock cycles -1)




Table 4.4.6.6-7: Register DIV1_RELOAD (0x0A) Pre-divider 1 reload value register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : div_reload -pre-divider reload value (div_reload_val = clock cycles -1)

Table 4.4.6.6-8: Register CNT0_VALUE (0x0C) Counter 0 current value register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_val -current counter value (clock cycles = cnt_val +1)

Table 4.4.6.6-9: Register CNT1_VALUE (0x0E) Counter 1 current value register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : cnt_val -current counter value (clock cycles = cnt_val +1)


MSB LSB

Content - - - - - - - - - - - - 3:2 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:2 : evt_div_zero (event) -pre-divider n has been zero1:0 : evt_cnt_zero (event) -counter n has been zero


MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R R W W



MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Bit Description 2:0 : vno -read: vector number of enabled pending interrupt with highest priority (smallest vector number). when no IRQ is pending the first unused IRQ number is returned.write: vector number of interrupt event to clear




4.4.6.7 LIN SCI Module (LINSCI)FeaturesUART Function• Full duplex operation• 8N1 data format, standard mark/space NRZ format• Parity bit (even, odd, zero, none)• Programmable stop bit length (1,2)• selectable module clock (sys clock or 4MHz clock based)LIN Support:• LIN Master task support• LIN Header generation (software driven)• Break generation(programmable break length up to 255 x TBit)• SYNC byte transmission• Break delimiter length: 2• PID byte transfer

• LIN Slave Task Support• LIN header processing• Programmable break detection threshold(9.5xTBit, 11xTBit)• Break measurement counter (baud clock based) to detect concurrent break events• Measurement counter to measure bit times (used for baud rate recovery -> module clock base): Baud

Measurement Results can directly be fed into the baud register to adjust the baud rate (Baud self-synchron-ization with SYNC byte)

• SYNC Byte plausibility check: check TBit every RXD edge (1us clock based) -> supported baud rates for plausibility check: 2400 to 115200 BAUD

• LIN response frame processing• Collision detection with auto transmit shut down• Auto checksum insertion (classic or enhanced) to transmit frame• Checksum calculation• DMA driven transmit/receive

• Timer-Compare Module• used for• LIN Bus Idle measurement• LIN Break measurement (used for auto addressing)• LIN Header/Frame Length measurement

• auto restart with falling RXD edge• break detection with auto compare register pre-loading




RECEIVER

LIN RX BREAKLIN RX SYNC

RESYNCHYST

data

eot_evt

data(8)

fe_evtprty_evtbrk10_evtbrk11_evt

brk_evtsync_err_evtsync_ov_evtsync_byte_evtrx_2bit_times

FRAC DIV

RX FIFO(1)

LIN RX CTRL

datdata(8)

data_stb

pid_evt

pid_prty_evt

pid(8)

conc_brk_evt

RX DMA

DATA BUS

data(8)fullrun

read

TRANSMITTER TX FIFO(1)

TX DMA

DATA BUS

data(8)emptyrun

write

data(8)

read

breakfull

LIN TX CTRL

LIN CHECKSUM

classic_chksum

data(8)

emptywrite

LIN_AAFSM

configadc_trigger

phy_controladc_data

LIN TIMER

configcompare_evtcompare_val

Tbit_brk_cnt

RXD

TXD

break

Figure 4.4.6.7-1: SCI block diagram

Functional DescriptionGeneral function can be derived from Register description.

Concurrent Break MeasurementConcurrent break measurement works independent from the receiver status and detects breaks of length of 10 nominal bit length (respectively 11 nominal bit length when break threshold is set) A valid break signal starts meas-urement of a SYNC byte. After the SYNC byte measurement the sync_evt interrupt is raised and optionally re-trig-gers the fractional baud rate counter. Afterwards the PID will be received and the parity will be checked. In case of a valid parity the pid_evt interrupt will be raised and the PID will be copied to the LIN_PID register.

The concurrent break error flag will only be handled during header processing. The software has to handle occur-ring concurrent breaks during data transmission (unexpected break event during transfer).

Note: Since concurrent break measurement is based on the actual baud_rate and concurrent break measurement is also enabled during sync byte measurement the actual baud_rate must not exceed 10 times (respectively 11 times when LIN mode is set) the expected baud rate of the external sci. Otherwise low bits of the sync byte are detected as breaks and sync break measurement will be canceled:Condition: Actual baud_rate < 11 times expected external baud_rateExample: When setting internal baud_rate = 115200 concurrent baud measurement works with external baud_rates down to 10472 baud. The external baud_rate = 9600 baud cannot be synchronized.

Concurrent break measurement supports the LIN requirement of interrupting ongoing frames by a new break/sync header.

DMAStart DMA transfer by writing a length to the LENGTH register. Set a valid base address to the DMA_ADDRESS register before. Write access to the Address register during DMA operation will be ignored.The LENGTH register will be decremented, the ADDRESS register will be incremented with each transferred data. If an error occurs the DMA finish flag will be raised and the DMA controller will stop operation and has to be restar-ted by accessing the LENGTH register.




Check DMA_LENGTH register and SCI error flags when DMA finished flag is set to check if the DMA transfer abor-ted abnormally. Possible error cases are:• For TXD: transmitter disabled, bus error• For RXD: receiver disabled, bus errorSCI flags are not suppressed during DMA operation. The FIFO_full flags will be handled by the DMA controller. Reading/writing of the DATA_IO register is prohibited during DMA operation.

Principle of Baud Rate SynchronizationIn principal the baud rate synchronization is based on counting system clock cycles / 4MHz cycles for 8 x TBit. The result of the bit time measurement can be fed into the fractional baud rate divider register. The error of the meas-urement is the ratio of the measurement clock to the Bit clock. See the following description for details.• Sync Byte Measurement:• Measurement of 8 Bit Times (4 falling edges)• measurement counter (18bit) running at system clock frequency/4MHz (configurable)• measurement error8Tbit[%] = Tsysclk x 100 / 8 x Tbit

• Measurement Averaging: divide counter value by 4 and rounding 2 Bit Times in 16bit• measurement error after averaging and rounding error2Tbit[%] (Tsysclk/2) x 100 / 2 x Tbit (considering

more accuracy because of rounding)• Example for 24MHz sys_clk and 20kbaud: 41,66ns/2 x 100 / 2 x 50us = 0,021% Error• Example for 4MHz sys_clk and 20kbaud: 250ns/2 x 100 / 2 x 50us = 0,125% Error

• The 16 bit bit time measurement result can be fed to the fractional baud rate divider (see LIN_CONFIG.autobaudfunction)• the fractional divider interprets the value as a decimal number with 11 digits left of the decimal point and 5

fractional digits This corresponds to a division by 32• the output of the fractional divider is a clock 16 times the baud rate (2 x Tbit/32 = Tbit/16). This clock is used

for the LIN transmitter and receiver.• no granularity error has to be added since the average output frequency corresponds to 16 times the

measured bit rate: generated baud_clk = master_baud_clock + measurement_error



BAUD_RATE 0x00 Baud config register

UART_CONFIG 0x02 Control register

LIN_CONFIG 0x04 Configuration of LIN function

LIN_CONTROL 0x06 LIN control

STATUS 0x08 Status register

ERROR 0x0A Error flag register

LIN_CONFIGURA-TION

0x0C LIN configuration

DATA 0x0E LIN SCI data register

TBIT2_LENGTH 0x10 Length of 2TBit

LIN_PID 0x12 LIN PID

LIN_CHECKSUM 0x14 LIN checksum logic

TIMER 0x16 Timer

TIMER_COUNTER 0x18 Timer Counter

TIMER_COMPARE 0x1A Timer Compare

DMA_TX_ADDRESS

0x1C Transmit DMA Address

DMA_TX_LENGTH 0x1E Transmit DMA Length





DMA_RX_ADDRESS

0x20 Receive DMA Address

DMA_RX_LENGTH 0x22 Receive DMA Length







Table 4.4.6.7-2: Register BAUD_RATE (0x00) Baud config register

MSB LSB

Content 15:5 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:5 : DIV - SCI baud divisor selectDivisor:0x000 --> 1 (bypass divider)0x001 --> 20x002 --> 3...0x007 --> 8...

4:0 : FRAC - SCI baud divisor fractional partThese bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average baud frequency shown in the following table.

FRAC[00000] = 0/32 = 0FRAC[00001] = 1/32 = 0.03125FRAC[00010] = 2/32 = 0.0625...FRAC[10000] = 16/32 = 0.5...FRAC[11111] = 31/32 = 0.96875

The divider can be used to achieve divisor values between 1 and 2047.96875. The baud divisor fractional part can be used to fine tune the baud rate in 1/32 steps of the divisor.Use the following formula to calculate the SCI baud rate:

Baud rate = clkbase/(16*(DIV+FRAC))

Note: clkbase is clk_src dependent, see UART_CONFIG register for details.

Note: The 16 bit baud divisor value represents the number of system clock cycles of two bit lengths. The result of a SYNC byte measurement(see below) can directly be written to the baud rate register.




Table 4.4.6.7-3: Register UART_CONFIG (0x02) Control register

MSB LSB

Content - 14:12

11 10 9 8 - 6 5 4 3:2 1 0

Reset value 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0

Access R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 14:12 : debounce - Debounce filter for RXD signal, based on 4MHz clock

filter time: t_debounce = x 0: bypass1: 500ns2: 1us3: 2us4: 4usNote: Also consider debounce filter in LIN PHY module11 : rxd_valRXD Receiver signal (direct input)10 : rxd_mask0: RXD path unmasked, signal will be routed to RX logic1: RXD path masked, RXD signal will be forced to '1'9 : txd_valTXD value register, used when UART_CONFIG.txd_mask=18 : txd_mask0: TXD path unmasked, UART generated TXD will be used1: TXD logic masked, UART_CONFIG.txd_val will be used as TXD signal (allows cpu generated txd)6 : clk_src - Clock source0: sys clock used as input for fractional BAUD_RATE divider1: 4Mhz clock used as input for fractional BAUD_RATE divider5 : mask_brk_err - Mask break errors0: frame error event and parity error event will be generated even when break is received1: frame error event and parity error event will be suppressed when break is received4 : STOP - number of stop bits0: 1 stop bit1: 2 stop bitsNote: break delimiter has always 2 stop bits3:2 : PARITY - parity selection00: no parity bit01: parity bit always zero10: odd parity11: even parity1 : TE - transmitter enableIf software clears TE while a transmission is in progress (tx_idle = 0) the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for tx_fifo_empty to go high after the last frame before clearing TE.Note: the transmitter immediately fills the transmit shift register with ones and clears the tx fifo when a collision event occurs and collision detection is enabled.0 : RE - receiver enableRE set to '0' suppresses start bit recognition,setting RE to '1' during an ongoing transfer can cause erroneous data reception and interrupt generationsetting RE to '0' during an ongoing transfer can cause erroneous data reception and interrupt generation, received data should be ignored




Table 4.4.6.7-4: Register LIN_CONFIG (0x04) Configuration of LIN function

MSB LSB

Content - - - - - 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 10 : dma_rx_skip_last - Skip last RX byte during DMA operationPrevents last byte to be written to memory:Example: dma_rx_length = 9, DMA will handle 9 incomingdata bytes but only the first 8 are written to memory. DMA finished irq will be generated after 9 data bytes.Note: Function can be used to prevent checksum to be writtento memory9 : sync_validation0: sync byte validation logic disabled1: sync validation enabledNote: Recommended for LIN communicationBaud Rates between 2400 und 115200 Hz are supported by SYNC validation hardware. Too slow Baud Rates lead to sync validation hardware overflow, too fast Baud Rates lead to plausibil-ity check errors (both resulting in a ERROR.sync_err)8 : suppress_tx_fb0: normal function1: Suppress TXD -> RXD feedback loop when in transmit_modeNote: received data will be forwarded to checksum logic but not to fifo buffer7 : chksum_insert - Auto checksum insertion0: no automatic checksum insertion1: automatically transmit checksum when DMA TX transfer is finished.Note: Auto checksum insertion only works in conjunction with DMA transfer and LIN_CON-TROL.tx_chksum enabled6 : chksum_type - checksum type selection0: classic checksum1: enhanced checksum (includes PID)Note: see chksum_enable for details5 : chksum_enable - enable automatic checksum calculation0: checksum auto feed hardware disabled1: Add rx/tx data to checksum module (LIN_CONTROL.tx_chksum dependent)Initialize checksum with each pid_evt (init with zero for classic checksum, init with PID for enhanced checksum), used checksum type:for PID 0..59 lin_chksum_type will be usedfor PID 60..63 always classic checksum will be usedNote: checksum hardware can also be accessed by software4 : filter_pid - filter(mask) PID byte0: pass through PID to receive FIFO1: do not forward PID byte to receive FIFO




MSB LSB

3 : header_processing - enable header processing0: function disabled1: enable receive header processing: BREAK/SYNC sequence will be detected, PID will be received and validated, SYNC byte will not be forwarded to receive FIFO, PID byte can be option-ally be forwarded. PID reception initializes the checksum calculation and generates a header event.Note: Recommended for LIN communicationNote: RX unit is disabled during sync byte reception to avoid data reception and framing errors.2 : break_thd - break detection threshold length0: break detection threshold 9.5 x TBit (UART mode)1: break detection threshold 11 x TBit (LIN mode)Note: use msk_brk_err in UART_CONFIG to avoid frame/parity error generation during break recognition.1 : collision - TXD collision detection0: collision detection disabled1: collision detection enabled while transmittingNote: if a collision is detected the transmit process will be aborted immediately, an ongoing DMA transfer will be stoppedNote: only applicable when operating in single line mode (LIN)Note: Recommended for LIN communication0 : autobaud - LIN auto setup new baud rate after reception of valid LIN BREAK/SYNC sequence0: disabled1: enabledNote: Recommended for LIN communication

Table 4.4.6.7-5: Register LIN_CONTROL (0x06) LIN control

MSB LSB

Content - - - - - - - - - - - - 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R/W R/W W W

Bit Description 3 : rx_sleep - temporarily disable receiver logic (sleep)0: receiver enabled (when UART_CONFIG.re=1)1: receiver disabled(sleeping), transfers will be finished when rx_sleep is set during ongoing transfers,receiver will leave sleep mode when a valid sync eventoccurs (valid break/sync sequence received)Note: rx_sleep can be used to prevent data reception,e.g. when slave is not addressed by master2 : tx_chksum0: add rx data to checksum calculation1: Slave Node transmit Mode:Add tx data to checksum calculation instead of rx data.Will be reset to 0 when valid LIN header is detectedNote: only applicable when chksum_enable=11 : abort_tx - transmitter abortstop transmitter, set txd=1, clear tx fifo, reset tx fsm to idle, stop tx DMA0 : abort_rx - receiver abortstop receiver, clear rx fifo, reset rx fsm to idle, stop rx DMA, abort SYNC measurements




Table 4.4.6.7-6: Register STATUS (0x08) Status register

MSB LSB

Content - - - - - - - - - 6 5:4 - 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1


Bit Description 6 : rx_chksum_valid -0: current calculated checksum invalid1: current calculated checksum is valid (0xFF)Note: bit can be evaluated after reception of complete frame5:4 : rx_header_state - LIN RX Header state00: idle/break receiving01: sync byte receiving10: PID receiving3 : tx_fifo_full - Status of tx fifo (fifo depth=1)2 : rx_fifo_full - Status of rx fifo (fifo depth=1)1 : TX_IDLE0: transmit in progress1: transmitter in idle mode0 : RX_IDLE0: receive in progress1: receiver in idle mode

Table 4.4.6.7-7: Register ERROR (0x0A) Error flag register

MSB LSB

Content - - - - - - - 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 8 : txd_timeout - TXD dominat timeoutWrite 1 to clear flagrelated to bus_err interruptflag will be raised when the hardware detects a permanent dominant txd line (see LIN transceiverchapter for details)7 : concurrent_brk - Concurrent BreakWrite 1 to clear flagrelated to bus_err interruptflag will be raised when a break occurs during an ongoing transferNote: only concurrent breaks during header processing will set the concurrent_brk flag6 : bus_collision - Bus CollisionWrite 1 to clear flagrelated to bus_err interruptflag will be raised when bus collision is detected during txNote: only applicable when collision is enabled in LIN_CONFIG register5 : pid_parity_err - PID Parity ErrorWrite 1 to clear flagrelated to header_err interruptflag will be raised when received PID has wrong parityNote: only applicable when header_processing is enabled in LIN_CONFIG register




MSB LSB

4 : sync_invalidWrite 1 to clear flagrelated to header_err interruptflag will be raised when receiver unit is in unexpected state after sync byte measurementNote: only applicable when header_processing is enabled in LIN_CONFIG register3 : sync_ov - Sync byte overflowWrite 1 to clear flagrelated to header_err interruptflag will be raised when sync byte counter overflows, e.g. when time between two edges is too longNote: LIN header processing will be stopped when overflow error occurs2 : sync_err - Sync byte errorWrite 1 to clear flagrelated to header_err interruptflag will be raised when sync byte plausibility check failedNote: only applicable when sync_validation is enabled in LIN_CONFIG registerNote: LIN header processing will be stopped when error occursNote: In error case the RX unit is potentially out of sync. All incoming data should be refused untilnext break/sync sequence1 : parity_err - UART parity errorWrite 1 to clear flagrelated to receiver_err interruptflag will be raised when a parity error is detectedError flag can be suppressed during break with UART_CONFIG.mask_brk_err0 : frame_err - UART frame errorWrite 1 to clear flagrelated to receiver_err interruptflag will be raised when no stop bit is present. Break signals will generate a frame error. Error flagcan be suppressed during break with UART_CONFIG.mask_brk_err

Table 4.4.6.7-8: Register LIN_CONFIGURATION (0x0C) LIN configuration

MSB LSB

Content - - - - - - - - 7:4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1


Bit Description 7:4 : version0x0 and 0x8 reserved for former products3 : dma - DMA module implemented2 : timer - SCI internal timer module implemented1 : txd_timeout_reg - TXD timeout enable register implemented0 : cbm - Concurrent break measurement implemented




Table 4.4.6.7-9: Register DATA (0x0E) LIN SCI data register

MSB LSB

Content - - - - - - - 8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 8 : send_break - send breakwrite: send break of length ('data'+ 1) x TBit

7:0 : data - sci data registerWrite: fill transmit fifo, only applicable when tx_fifo is empty, written byte will be transmittedRead: read received byte from rx_fifo, only applicable when fifo is fullNote: read access clears the fifo, data can only read once

Table 4.4.6.7-10: Register TBIT2_LENGTH (0x10) Length of 2TBit

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : data - result dataResult of latest Sync Byte measurement

Table 4.4.6.7-11: Register LIN_PID (0x12) LIN PID

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : data - PID data byteLatest received PID

Table 4.4.6.7-12: Register LIN_CHECKSUM (0x14) LIN checksum logic

MSB LSB

Content - - - - - - - 8 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 8 : initialize0: perform checksum calculation with chksum_val1: initialize accumulator with chksum_val value7:0 : chksum_valwrite access: add new value to checksum calculation (see initialize flag for details)read access: current checksum valueNote: Checksum logic will also be fed by receiver logic when chksum_enable bit is set or by transmitter logic when chksum_enable bit and transmit_mode bit is set. In transmit_mode the checksum can optionally transmitted at the end of a DMA driven transfer (chksum_insert).




Table 4.4.6.7-13: Register TIMER (0x16) Timer

MSB LSB

Content - - - - - - - - - - 5 4 3:2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R/W R/W R/W R/W R/W R/W

Bit Description 5 : txd_timeout_e - Enable TXD timeout countertLIN,TXD,DOM timeout counter: In case of a dominant TXD signal for a time greater than tLIN,TXD,DOM the TXD output will be forced to 1. See txd_timeout ERROR flag above.4 : break_restart - Break Restart0: no function1: restart timer when LIN break signal is detected-> preload timer with 11 x TBit x 16 = 176 (break time when LIN_CONFIG.break_thd==1)-> preload timer with 9.5 x TBit x 16 = 152 (break time when LIN_CONFIG.break_thd==0)-> preload compare register with maximum header length=> 48 x TBit x 16 = 768Note:a disabled timer will be started when a LIN break signal is detectedNote:only applicable when clk_base=baud_rate and expected baud rate nearly actual baud rate3:2 : prepare - Timer Prepare0: normal operation1: restart timer from 0 when a falling RXD edge is detected.timer_prepare bit will be reset immediately2: restart timer from 0 when a falling RXD edge is detectedtimer_prepare bit will be reset when a valid break is detected3: restart timer from 0 when a falling RXD edge is detectedtimer_prepare bit will not be reset automatically

Note: As long as timer_prepare is >0 no compare events will be generated, this allows preload-ing of the timer compare register.timer_prepare works only with timer_enable=11 : clk_src - timer_clk_baseTimer counts with0: 16 x baud rate1: 1µs clock0 : enable - Timer Enable0: timer not running(reset counter to 0)1: timer runningtimer counter is incremented by timer_clk_baseNote: a disabled timer can be auto enabled when a valid break signal is detected and the 'break_restart' bit is set

Table 4.4.6.7-14: Register TIMER_COUNTER (0x18) Timer Counter

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : timer_counter - Timer CounterTimer counter is running when timer is enabled with timer_enable. sci_timer_ov flag is set when timer overflows.




Table 4.4.6.7-15: Register TIMER_COMPARE (0x1A) Timer Compare

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : timer_comparetimer_cmp flag is set when timer reaches timer_compare valueNote: Timer compare flag will not be set when timer_compare=0Note: Timer compare flag will NOT be set as long as timer_prepare>1. Timer overflow events willbe generated

Table 4.4.6.7-16: Register DMA_TX_ADDRESS (0x1C) Transmit DMA Address

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : dma_tx_addrStart address of source of transmit data.Note: Address is incremented with each DMA transfer executed.

Table 4.4.6.7-17: Register DMA_TX_LENGTH (0x1E) Transmit DMA Length

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : dma_tx_lengthLength of data to be transmitted via DMA in BYTE.Value will be decremented with each transfer.Write access to register will stop current DMA operation and will restart DMA controller.

Table 4.4.6.7-18: Register DMA_RX_ADDRESS (0x20) Receive DMA Address

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : dma_rx_addrStart address of destination of receive data.Note: Address is incremented with each DMA transfer executed.




Table 4.4.6.7-19: Register DMA_RX_LENGTH (0x22) Receive DMA Length

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : dma_rx_lengthLength of data to be transmitted via DMA in BYTE.Value will be decremented with each transfer. Write access to register will stop current DMA operation and will restart DMA controller.


MSB LSB

Content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15 : tick_1ms (event) - generates an interrupt each 1ms14 : tx_finish_evt (event) - transmit transfer finished, transmitter returned to idle state13 : tx_dma_finished (event) - transmit dma transfer finished12 : tx_fifo_empty (level) - transmit fifo empty11 : rx_dma_finished (event) - receive dma transfer finished10 : rx_fifo_full (level) - receive fifo full9 : pid_evt (event) - valid PID received8 : sync_evt (event) - SYNC byte received7 : break_evt (event) - valid BREAK detected6 : header_err (level) - header error occurred, see ERROR register for details5 : receiver_err (level) - receiver error occurred, see ERROR register for details

4 : bus_err (level) - bus error occurred, see ERROR register for details3 : sci_timer_ov (event) - SCI timer overflow2 : sci_timer_cmp (event) - SCI timer compare1 : rxd_rising (event) - rising edge of RXD signal0 : rxd_falling (event) - falling edge of RXD signal


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0




MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0






4.4.6.8 LIN PHY Control Module (LIN_CTRL)Features• Configuration Registers of LIN PHY Module• Auto-addressing(AA) Support FSM• Keep track of AA break position and auto set configuration signals (pull-up/current source)• Trigger ADC measurement, auto process ADC results• Return AA result and generate interrupt

• Software driven ADC measurement when AA FSM is disabled

LINSCI

LIN PHYWITH

AUTO ADDRESSING

LIN_CTRLWITH AA FSM

config

adc_trigger

phy_control

adc_data

Tbit_brk_cnt

LIN_M

RXD

ADC

irq

LIN_S

linsci_rxd

TXD

result

pull-up config

Figure 4.4.6.8-1: LIN_CTRL block diagram

Auto-addressing Hardware Support

The auto-addressing sequence specified in chapter 4.1.2 is supported by a dedicated hardware block.Features of the hardware support are:• Automated pull-up configuration handling dependent on the position within the auto-addressing break.• Position within the break is monitored by a Tbit counter• Pull-up configuration registers LIN_AA_CONFIG_MODESx

• Hardware driven trigger of a the ADC measurement of the shunt current• Supports two times and four times ADC oversampling• Hardware driven auto zero signal management

• Calculation of current difference and comparison against threshold values(register LIN_AA_I_DIFF_THD)• Generation of aa_finished interrupt event when an auto-addressing sequence successfully finished• Set/reset of aa_store_nad flag which has to be handled by software

• Handling of short auto-addressing breaks (auto abort auto-addressing sequence)• Handling of errors during auto-addressing sequence• In case of measurement timeout errors the device behaves like not pre-selected

Enable the hardware support with the PHY_CONFIG.aa_fsm_enable bit.Set bit PHY_CONFIG.aa_addressed when the device is already addressed.Use bits PHY_CONFIG.aa_restore_eob and PHY_CONFIG.aa_st5_mid_wait to configure the sequence timing.

Note: When auto-addressing hardware is enabled each falling edge of the RXD signal leads to a start of the auto-addressing sequence, including the change of the pull-up configuration.Warning: Since the auto-addressing hardware triggers ADC measurements with high priority the ADC measure-ments of the currently running application can be delayed.

Note: Software has to consider that shunt measurement has to be finished within the given time in a measurement step.This time is limited by:• Amplifier parameter tAA,meas

• Measurement time window, e.g. 3 x Tbit (baud rate dependent), whereof tAA_AZ,act + tAA,set is used for autozero.




Since ongoing ADC conversion cannot be interrupted by the auto-addressing ADC trigger, a huge configured sampling extension can delay the start of the AA measurement and can therefore lead to an aa_adc_timout_evt error. In addition the sampling extension for the AA measurement must not exceed the given time window. Con-sider the oversampling config bit PHY_CONFIG.aa_oversampling.

The software has to handle the aa_addressed bit and has to evaluate the resulting aa_store_nad flag.

The hardware follows the auto-addressing sequence in chapter Figure 4.1.2-3 and the timing diagram in chapterFigure 4.1.2-4.The following diagram shows the states of the FSM which reflects the sequence:

STEP0

STEP1

STEP2

STEP4

STEP3

STEP5

STEP7

ALLOFF STEP6

Reset

If end of 1xTbitStart measurement of ishunt1

If AA enabled and falling RXDreset Tbit counter

If aa_addressed==1

If end of 4xTbitstore ishunt1

If end of 9xTbitStart measurementof ishunt3

If end of 5xTbitStart measurement of ishunt2

If end of 8xTbit and thd<ishunt2-ishunt1

If end of 8xTbit and aa_st5_mid_wait=0 andthd>=ishunt2-ishunt1

If end of 8.5xTbit

If end of 12xTbit and aa_restore_eob

If end of 11xTbit andaa_restore_eob = 0

If RXD=1 and valid_break and meas finished

If RXD=1 and meas not yet finished

If end of 11xTbit andnot aa_restore_eob

orIf end of 12xTbit and

aa_restore_eob

From all states except STEP6If (RXD=1)

always:aa_finished eventIf thd<ishunt3-ishunt1aa_store_nad=0elseaa_store_nad=1

Offset Mode Pre-sel Mode Selection Mode Default Mode

Figure 4.4.6.8-2: Auto-Addressing FSM

Dependent on the current state of the auto-addressing FSM different pull-up configurations are valid:1. Default Mode: The default configuration is valid in states STEP0 and STEP7. It is also valid when the auto-ad-

dressing hardware is disabled.2. Offset Mode: The offset mode configuration is valid in states STEP1, STEP2 and in ALL OFF state. It is used to

measure the offset current on the bus and to disable all pull-up sources when the device is already addressed.3. Pre-Selection Mode: The pre-selection configuration is valid states STEP3 and STEP4. It is used to selected

the last 3-4 not addressed devices on a bus.4. Selection Mode: The selection configuration is valid in states STEP5 and STEP6. It is used to select the last

not addressed device on the bus.




Note: When auto-addressing is implemented completely software driven use the default mode setting to set up the pull-up configuration for the different phases. In that case the ADC measurement can be triggered by writing to the LIN_AA_ADC_RESULT register. This is only allowed when the AA FSM is disabled (aa_fsm_enable=0) and when the amplifier is enabled by software (aa_amp_on=1). A finished ADC conversion will be signaled by aa_adc_valid_evt interrupt.

Note: Auto-addressing can be implemented partial software driven. Use the configuration bits PHY_CONFIG.aa_st4_sw_wait and CONTROL.aa_st4_sw_proceed to stop the FSM at STEP4 and wait for soft-ware intervention. The software has the possibility to decide if the the FSM should proceed with STEP5 or with state ALLOFF. If no software interaction occurs the FSM will step to state ALLOFF.



PHY_CONFIG 0x00 LIN Phy configuration

LIN_AA_STATUS 0x02 Auto Addressing status

LIN_AA_CONFIG_MODES0

0x04 Auto Addressing config modes

LIN_AA_CONFIG_MODES1

0x06 Auto Addressing config modes

LIN_AA_ADC_RESULT

0x08 Auto Addressing averaged ADC input

LIN_AA_I_DIFF_THD_1

0x10 Auto Addressing thresholds

LIN_AA_I_DIFF_THD_2

0x12 Auto Addressing thresholds

LIN_AA_I_SHUNT_1

0x14 Auto Addressing I shunt measurement result

LIN_AA_CON-TROL

0x16 Auto Addressing control










Table 4.4.6.8-2: Register PHY_CONFIG (0x00) LIN Phy configuration

MSB LSB

Content - - - - - 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 10 : aa_disable_adc_trig - Disable FSM generated ADC trigger.When selected: software has to trigger ADC conversionNote: aa_adc_timeout checks are disabled in that case9 : aa_st4_sw_wait - Wait at STEP4 for software intervention.0: normal operation1: software triggered decision, use aa_st4_sw_proceed to select next state, if no software trigger occurs the FSM will goto ALLOFF stateNote: in STEP4, the ADC measurement has to be finshed, otherwise State ALLOFF will be entered8 : aa_st5_mid_wait - Step5 middle wait0: switch to pull-up configuration 2 at begin of step 51: wait until middle of step 5 before switching to pull-up configuration 2 (LIN BSM Spec conform)7 : aa_restore_eob - Restore pull-up settings to defaults in case of FSM driven auto-addressing0: restore settings after 12 x Tbit1: restore settings after 13 x Tbit at the end of break (LIN BSM Spec conform)Note: in both cases pull-up settings will be restored when LIN bus changes to recessive state6 : aa_oversampling - Auto Addressing oversampling in case of FSM driven auto-addressing0: two times oversampling1: four times oversampling5 : aa_addressed - Auto Addressing Addressed Flag0: slave not yet addressed1: slave addressedBit has to be managed by SW. The addressed status influences the auto addressing state machine4 : aa_fsm_enable - Auto Addressing State Machine0: FSM disabled1: in case of a falling RXD signal the auto addressing FSM starts the sequence. ADC trigger sig-nals will be generated according the aa_oversampling settings.3 : aa_autozero - Auto Addressing Auto Zero Amplifier0: Auto Addressing auto zero signal controlled by AA ADC control FSM (recommended)1: enables LIN Auto Addressing amplifier autozero (use for test only)2 : aa_amp_on - Auto Addressing Amplifier On0: Auto Addressing amplifier ON signal controlled by AA FSM1: enables LIN Auto Addressing amplifier1 : lin_hs - High speed signal to LIN PHY0: LIN SCI normal speed (up to 20kBaud)1: LIN SCI high speed (up to 115,2kBaud) for non-volatile memory programming0 : lin_on - LIN Phy power mode0 : reduced power mode (transmitter disabled, wakeups can be detected)1 : Phy enabled




Table 4.4.6.8-3: Register LIN_AA_STATUS (0x02) Auto Addressing status

MSB LSB

Content - - - - - 10 9 8 7:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 10 : aa_adc_valid - Auto Addressing LIN_AA_ADC_RESULT register status0: register not valid1: register valid9 : aa_adc_idle - Auto Addressing ADC Measurement status0: ADC measurement in progress1: ADC measurement in IDLE state8 : aa_result - Auto Addressing Result0: not last device on bus1: store NAD in MemoryNote:flag will be updated at the end of a valid AA cycle (aa_finished event)7:4 : fsm_state - AA state machine status0: STEP01: STEP12: STEP23: STEP34: STEP45: STEP56: STEP67: STEP78: ALL_OFF3:0 : tbit_cnt - Tbit counter valueTBit counter during AA break detection. Counting from 1(step 1) to 14(step 7)

Table 4.4.6.8-4: Register LIN_AA_CONFIG_MODES0 (0x04) Auto Addressing config modes

MSB LSB

Content 15:0 - - - - - - - - - - - - - - -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 15:0 : Note: Make sure the value of this register is always 0x0001

Table 4.4.6.8-5: Register LIN_AA_CONFIG_MODES1 (0x06) Auto Addressing config modes

MSB LSB

Content 15:0 - - - - - - - - - - - - - - -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Bit Description 15:0 : Note: Make sure the value of this register is always 0x0143




Table 4.4.6.8-6: Register LIN_AA_ADC_RESULT (0x08) Auto Addressing averaged ADC input

MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:0 : value - ADC result of I_shunt measurementread: Averaged result of ADC measurement (two or four times oversampling depending on aa_oversampling), Value is valid when aa_adc_valid=1. A valid result is signaled by aa_adc_valid_evt event.Note: Consider inconsistency of value when measurement is in progress e.g. triggered by the AA FSMwrite: write access triggers i_shunt ADC measurement, use for software driven AA, e.g. when PHY_CONFIG.aa_disable_adc_trig is set.Note: To start the measurement the aa_amp_on must be set and the measurement status must be IDLE

Table 4.4.6.8-7: Register LIN_AA_I_DIFF_THD_1 (0x10) Auto Addressing thresholds

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 9:0 : i_diff_thd_1 - Threshold for step 5if (Idiff_thd_1 < Ishunt_2 - Ishunt_1) not pre-selectedelse pre-selected nodeNote:Threshold restricted to 10 bit, threshold will be compared to upper 10 bit of difference of I_shunt_2 - I_shunt_1.

Table 4.4.6.8-8: Register LIN_AA_I_DIFF_THD_2 (0x12) Auto Addressing thresholds

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9:0 : i_diff_thd_2 - Threshold for step 7if (Idiff_thd_2 < Ishunt_3 - Ishunt_1) not selected nodeelse selected node-> store NADNote:Threshold restricted to 10 bit, threshold will be compared to upper 10 bit of difference of I_shunt_3 - I_shunt_1.

Table 4.4.6.8-9: Register LIN_AA_I_SHUNT_1 (0x14) Auto Addressing I shunt measurement result

MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:0 : i_shunt_1 - Result of latest I_SHUNT_1 measurementNote: i_shunt value will be updated within STEP2 of the LIN Auto-Addressing FSM.




Table 4.4.6.8-10: Register LIN_AA_CONTROL (0x16) Auto Addressing control

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : aa_st4_sw_proceed - Proceed FSM when in State STEP40: goto State ALLOFF1: goto State STEP5Note: only applicable when aa_st4_sw_wait is setNote: next state will be entered aa_st5_mid_wait dependentNote: internal flag will store the proceed selection, flag will be reset when auto addressing sequence has finished


MSB LSB

Content - - - - - - - - - - - 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 4 : aa_t_bit_evt (event) - Interrupt event each time the LIN_AA_STATUS.tbit_cnt counter incre-ments, starting with the falling edge of RXD3 : aa_adc_valid_evt (event) - auto addressing ADC measurement result valid2 : aa_adc_timout_evt (event) - auto addressing adc busy timeout, will be asserted when leaving a measurement STEP but ADC measurement is not yet finished1 : aa_amp_timout_evt (event) - auto addressing amplifier timeout, will be asserted when adc measurement exceeds tAA,meas

0 : aa_finished (event) - auto addressing cycle successfully finished


MSB LSB

Content - - - - - - - - - - - 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1






4.4.6.9 GPIO Module (GPIO)This module gives access to general purpose digital IOs.

Features• 4 IOs ( ports )• Interrupt capable• Positive IO signal edge interrupt• Negative IO signal edge interrupt

• IO [0] is connected to LED0 pin• IO [1] is connected to LED1 pin• IO [2] is connected to LED2 pin• IO [3] is connected to PWM3 / debug pin

Figure 4.4.6.9-1: Device IOMUX structure

Note: When going to standby or sleep, the LED drivers have to be disabled.






SELECT 0x00 Data out register

DATA_OE 0x02 Output enable register

DATA_IN 0x04 Data in register

DATA_IE 0x06 Input enable register

DATA_OUT 0x08 Data out register







Table 4.4.6.9-2: Register SELECT (0x00) Data out register

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:0 : select - GPIO select0 : IO used by PWM module1 : IO used by GPIO module

Note: If IO is used as output(GPIO or PWM), the corresponding output driver has to be enabled in the PWM.CONTROL register.

Table 4.4.6.9-3: Register DATA_OE (0x02) Output enable register

MSB LSB

Content - - - - - - - - - - - - 3 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3 : enable3 - GPIO output enableRelated to the structure of the device pin its state will be determined by the input/output setting:0: input - pin state is undriven (high z)1: output - pin state defined by GPIO_OUT register

Note: DATA_OE only applies when GPIO is selected by GPIO.SELECT register.2:0 : enable - GPIO output enableRelated to the structure of the device pin its state will be determined by the input/output setting:0: input - pin state is undriven (high z)1: output - pin state is pull down

Note: DATA_OE only applies when GPIO is selected by GPIO.SELECT register.Note: Pull up resistor required when configured as output.




Table 4.4.6.9-4: Register DATA_IN (0x04) Data in register

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:0 : data - input data

Note: IO state can also be read throught this register when PWM module is selected by SELECT register and related GPIO.DATA_IE bits are set.

Table 4.4.6.9-5: Register DATA_IE (0x06) Input enable register

MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 3:0 : enable - GPIO input enable0 : input path disabled1 : input path enabled

Note: When configured as 0, related DATA_IN bits will be masked to 0.Note: enable[3] has no effect on masking the input signal from pin DB. The value can always be read in register DATA_IN

Table 4.4.6.9-6: Register DATA_OUT (0x08) Data out register

MSB LSB

Content - - - - - - - - - - - - 3 - - -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R R R/W R R R

Bit Description 3 : data - output data


MSB LSB

Content - - - - -- - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7 : evt_neg_3 (event) - negative edge event at IO port bit 36 : evt_pos_3 (event) - positive edge event at IO port bit 35 : evt_neg_2 (event) - negative edge event at IO port bit 24 : evt_pos_2 (event) - positive edge event at IO port bit 23 : evt_neg_1 (event) - negative edge event at IO port bit 12 : evt_pos_1 (event) - positive edge event at IO port bit 11 : evt_neg_0 (event) - negative edge event at IO port bit 00 : evt_pos_0 (event) - positive edge event at IO port bit 0





MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : mask - enable IRQ source1: enabled0: disabled


MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0






4.4.6.10 CCITT-CRC-16 Module (CRC16)This module can be used to calculate a CCITT-CRC-16 check sum of a configurable memory area.

Features:• DMA based memory read access• Concurrent CRC calculation• CPU starts CRC calculation by writing start address value• Application can run in parallel with little performance loss. See CONFIG register description. The duration of

the CRC calculation depends on the CONFIG and LENGTH register values.• CCITT-CRC-16 compatible• Algorithm parameters:• Generator polynomial = 0x1021• Check sum initial value = 0xFFFF

Equivalent C code:

uint16_t calc_ccitt_crc_16(uint16_t *buffer, uint16_t words) {

uint16_t poly = 0x8408; // reverse 0x1021uint16_t crc = 0xFFFF;

int n, b;

uint8_t *byte_buffer = (uint8_t *)buffer;int bytes = words * 2;

for (n = 0; n < bytes; n++) {crc ^= (uint16_t)byte_buffer[n];for (b = 0; b < 8; b++) {

if (crc & 1) {crc = (crc >> 1) ^ poly;

} else {crc = (crc >> 1);

}}

}return crc;

}



START 0x00 Start address register

LENGTH 0x02 Length register

EXPECTED_CRC 0x04 Expected CRC register

CONFIG 0x06 Configuration register


CRC_SUM 0x0A CRC sum register




Table 4.4.6.10-2: Register START (0x00) Start address register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : addr - CRC calculation start addressNote: Address value has to be even !

Writing this register starts CRC calculation and CRC_STATUS.state changes to 0. When CRC calculation has been finished, CRC_STATUS.state changes to 1 or 2.

Table 4.4.6.10-3: Register LENGTH (0x02) Length register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : bytes - number of bytes to be included in calculationNote: Number of bytes has to be even !Note: Before starting CRC calculation, this value has to be set by Software to a value !=0, other-wise a maskable reset will be asserted.

Table 4.4.6.10-4: Register EXPECTED_CRC (0x04) Expected CRC register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : crc - expected CRC sum

Note: This value has to be set by Software before starting CRC calculation.If calculated CRC sum does not match this value, a maskable reset will be asserted.




Table 4.4.6.10-5: Register CONFIG (0x06) Configuration register

MSB LSB

Content - - - - - - - - - - - - 3 2:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1


Bit Description 3 : keep_sum - CRC sum behavior

0 : clear CRC sum to 0xFFFF at start of CRC calculation1 : use previous sum or set sum as CRC calculation start value2:0 : timing - CRC unit read access timing

With every CRC module DMA read access the CRC check sum will be "extended" by the read 16bit data word.

To less influence the CPU performance, CRC calculation read accesses can be done with spa-cing.

Space between 2 successive CRC reads = (2timing) - 1


MSB LSB

Content - - - - - - - - - - - - - - 1:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0


Bit Description 1:0 : state - CRC unit state

0 : CRC unit is running / CRC calculation is ongoing1 : last CRC calculation was PASS, CRC unit is ready to be started by software2 : last CRC calculation was FAIL, CRC unit is ready to be started by software3 : unused state code

Table 4.4.6.10-7: Register CRC_SUM (0x0A) CRC sum register

MSB LSB

Content 15:0

Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


Bit Description 15:0 : crc - calculated CRC sum / CRC sum set register

Note: Calculated CRC sum is only valid when STATUS.state != 0.




4.4.6.11 ADC Control Module (ADC_CTRL)This module implements ADC control functionality.

Features• PWM based trigger to start ADC conversion• Variable PWM trigger to ADC channels assignment• Register based conversion trigger• ADC result data DMA to a 10 word memory area• 10 result data update interrupts• Configurable DMA base address• ADC data valid status• Valid, when related PWM channel was ON during ADC sampling

• ADC channel 0 has highest priority• ADC channel 9 has lowest priority• ADC conversions will be done in order of their priority• All trigger events will be halted until the corresponding conversion is executed

The cyclic trigger is automatically generated inside the ADC_CTRL module if the cyclic measurement mode is used.





Figure 4.4.6.11-2: Memory Map Example

Note: When bits in the ORed PWMx_CONFIG are change from '1' to '0' the related pending conversion flags are cleared immediately.

Trigger Flags Behavior Description• Trigger events from PWM channels, register trigger or in cyclic mode by the state of the PWMx_CONFIG

registers will be halted by internal trigger flags until they are processed• The internal trigger flag behavior depends on the cyclic configuration bit• Non-cyclic mode:• PWM triggers will set internal trigger flags of all channels configured by the PWM channel related

PWMx_CONFIG registers• When software writes to REG_TRIGGER register, bits are written as 1 will immediately set related internal

trigger flags• Internal trigger flags will be processed in order of their priority (from bit 0 to bit 9)• An internal trigger flag will be cleared when its processing has been started• When the processing has been finished, the ADC result value will be written to the related ADC channel result

data address• Cyclic mode:• PWM triggers will not set internal trigger flags• When software writes to REG_TRIGGER register, bits are written as 1 will immediately set related internal

trigger flags• When all internal trigger flags are cleared (are in a cleared state), the internal trigger flags will be set to the

ORed PWMx_CONFIG which means that all bits set in the PWMx_CONFIG registers will lead to set internal trigger flags

• Internal trigger flags will be processed in order of their priority (from bit 0 to bit 9)• An internal trigger flag will be cleared when its processing has been started• When the processing has been finished, the ADC result value will be written to the related ADC channel result

data addressSample Extension Note• When using ADC power-mode cycling (ADC_POWER register)• Please make sure, that the sample extension values are greater than t-WARM-UP (see ADC electrical para-

meter table).• The ADC is switched to run mode at the beginning of ADC measurement and switched to standby mode after

conversion has been finished.




Figure 4.4.6.11-3: ADC timing, here a PWM triggered conversion is shown when no ADC conversion is in progress



REG_TRIGGER 0x00 Register trigger register

PWM0_CONFIG 0x02 PWM 0 trigger configuration register




CONTROL 0x0A Control register

STATUS 0x0C Conversion status register

ADC_POWER 0x0E ADC power control register

SAMPLE_EXT 0x10 ADC sample time extension

SAMPLE_EXT_VT 0x12 ADC VT sample time extension

DMA_BASE_ADDR

0x14 DMA base address

SAMPLE_EXT_AA 0x1A ADC AA sample time extension

MUX_OFFSET 0x1C ADC MUX offset register

TRIGGER_DELAY0

0x20 PWM 0 trigger delay register

TRIGGER_DELAY1


TRIGGER_DELAY2


TRIGGER_DELAY3











Table 4.4.6.11-2: Register REG_TRIGGER (0x00) Register trigger register

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R W W W W W W W W W W

Bit Description 9:0 : trigger - register based triggerWhen software sets bits in this register the related ADC channel conversions will be triggered. Bits can only be added but not cleared by software. Bits will be cleared when related conversion is started. When bits need to be cleared in this register it is possible to do this by a '1', '0' sequence of these bits in the ORed PWMx_CONFIG (e.g. by a write sequence to PWM0_CON-FIG).bit 0 : ADC channel 0...

Table 4.4.6.11-3: Register PWM0_CONFIG (0x02) PWM 0 trigger configuration register

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9:0 : config - configures which ADC channel conversions will be triggered by PWM channel 0Note: When bits in the ORed PWMx_CONFIG are change from '1' to '0' the related pending con-version flags are cleared immediately.


MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.11-7: Register CONTROL (0x0A) Control register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : cyclic - configures ADC conversion behavior0 : non-cyclic measurement which uses PWM or register triggers to start an ADC channel conver-sion1 : cyclic measurement which converts all configured PWM related channels continually

Table 4.4.6.11-8: Register STATUS (0x0C) Conversion status register

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 9:0 : valid - Related PWM channel was active during ADC conversion.

0 : related PWM channel was inactive (OFF) during ADC conversion1 : related PWM channel was active (ON) during ADC conversion

At the moment the ADC samples an ADC channel the status bit related to this ADC channel is setto 1 when ALL configured (enabled by PWMx_CONFIG) PWM channels are active (ON) other-wise the status bit is cleared to 0.When an ADC channel is only configured (enabled) in one PWMx_CONFIG register, the status bit is set to 1 when the related PWM channel is active at the moment the ADC samples and cleared to 0 otherwise.

Delayed PWM triggers will be scheduled and "executed" in order of their priority. It may be hap-pen that a conversion is done some system clock cycles later than determined by the trigger delay. The valid flag is set after a conversion when the related PWM output was active during the ADC conversion else it is cleared.

bit 0 : ADC channel 0 conversion status...bit 9 : ADC channel 9 conversion status




Table 4.4.6.11-9: Register ADC_POWER (0x0E) ADC power control register

MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : always_on - force ADC to always ON mode0 : normal mode : ADC ON will be cycled automatically depending on active ADC triggers (saves power)1 : force ADC to stay always ON (needs more power and may only be a fall back solution if auto-matic power cycling does not work properly)

Table 4.4.6.11-10: Register SAMPLE_EXT (0x10) ADC sample time extension

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0


Bit Description 9:0 : cycles - sample extension for all channels except VT measurement

extend ADC sample time by given number of ADC half clock cycles

Table 4.4.6.11-11: Register SAMPLE_EXT_VT (0x12) ADC VT sample time extension

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0


Bit Description 9:0 : cycles - sample extension for VT measurement channel


Table 4.4.6.11-12: Register DMA_BASE_ADDR (0x14) DMA base address

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : base_addr - ADC DMA result base address

Table 4.4.6.11-13: Register SAMPLE_EXT_AA (0x1A) ADC AA sample time extension

MSB LSB

Content - - - - - - 9:0

Reset value 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0


Bit Description 9:0 : cycles - sample extension for LIN AA measurement channel





Table 4.4.6.11-14: Register MUX_OFFSET (0x1C) ADC MUX offset register

MSB LSB

Content - - - - - - - - - - 5 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R R R R R R R R/W R/W R/W R/W R/W R/W

Bit Description 5 : static_sel - ADC MUX channel behavior0 : use hardware generated ADC MUX channel1 : use offset value to set MUX channel (static)4:0 : offset - ADC multiplexer channel offset added to trigger based ADC MUX channel to select different / higher ADC MUX channel.Note: may only be used during IC test. Leave unchanged in application software.Note: set to high value (11111) to have mux output disabled/undriven

Table 4.4.6.11-15: Register TRIGGER_DELAY0 (0x20) PWM 0 trigger delay register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : delay - PWM channel 0 trigger delay (pre-scaled PWM clock cycles between PWM period start event and ADC conversion triggering)


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - 10 9:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 10 : ready (level) - ADC control ready (no ADC conversion pending or running)9:0 : evt_update (event) - ADC channel result data update events

bit 0 : ADC channel 0...bit 9 : ADC channel 9


MSB LSB

Content - - - - - 10:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1







MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1






4.4.6.12 LED PWM Module (PWM)This module implements the PWM functionality.

Features• 3x Low-side LED driver configuration and 1x digital output configuration (GPIO3)• 4 x 8 bit pre-scaler• 4 x 16 bit PWM channel with independent period length, pulse start and pulse stop timestamps• External PWM signal polarity configuration• Period, pulse start and pulse stop interrupts per channel• PWM channel related trigger delay (timestamp) configuration (see ADC_CTRL module)• Pre-scaler, period, pulse start, pulse stop, polarity and ADC_CTRL.trigger_delay configurations will be loaded

into active (current) registers with channel related period event• START-STOP cases• start < stop : PWM pulse length > 0• ON at start• OFF at stop

• start == stop : PWM pulse length = 0• 0% ON

• start == 0, stop == period• 100% ON

• start > stop : PWM pulse length > 0 (inverted pulse form behaviour)• OFF at stop• ON at start


PWM ON cycles in relation to (stop-start):

Please note: The picture shows the none continuous transition at 0 where (stop-start) changes its sign.




Figure 4.4.6.12-2: Relationship of output duty cycle to stop-start

POLARITY.pwm_term:

Figure 4.4.6.12-3: PWM termination

Start Stop PWM Timing Examples:




Figure 4.4.6.12-4: PWM output behavior in relation to the setting of start and stop(1)

Figure 4.4.6.12-5: PWM output behavior in relation to the setting of start and stop(2)

Note: When going to sleep, the LED drivers have to be disabled.






CONTROL 0x00 Control register

DRIVER 0x02 Driver config register

STATUS 0x04 Status registers

POLARITY 0x06 Polarity config register

PRESCALER0 0x08 Pre-scaler 0 config register

PRESCALER1 0x0A Pre-scaler 1 config register

PRESCALER2 0x0C Pre-scaler 2 config register

PRESCALER3 0x0E Pre-scaler 3 config register

PERIOD0 0x10 Channel 0 period config register

START0 0x12 Channel 0 pulse start config

STOP0 0x14 Channel 0 pulse stop config

COUNTER0 0x16 Channel 0 current counter value


START1 0x1A Channel 1 pulse start config

STOP1 0x1C Channel 1 pulse stop config

COUNTER1 0x1E Channel 1 current counter value


START2 0x22 Channel 2 pulse start config

STOP2 0x24 Channel 2 pulse stop config

COUNTER2 0x26 Channel 2 current counter value


START3 0x2A Channel 3 pulse start config

STOP3 0x2C Channel 3 pulse stop config

COUNTER3 0x2E Channel 3 current counter value










Table 4.4.6.12-2: Register CONTROL (0x00) Control register

MSB LSB

Content - - - - - - - - 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7 : driver_3_enable - enable channel 3 output driverNote: This bit enables channel 3 output driver stage regardless of GPIO.SELECT configuration.6 : driver_2_enable - enable channel 2 output driverNote: This bit enables channel 2 output driver stage regardless of GPIO.SELECT configuration.5 : driver_1_enable - enable channel 1 output driverNote: This bit enables channel 1 output driver stage regardless of GPIO.SELECT configuration.4 : driver_0_enable - enable channel 0 output driverNote: This bit enables channel 0 output driver stage regardless of GPIO.SELECT configuration.3 : pwm_3_enable - enable channel 3 PWM generator2 : pwm_2_enable - enable channel 2 PWM generator1 : pwm_1_enable - enable channel 1 PWM generator0 : pwm_0_enable - enable channel 0 PWM generator

Table 4.4.6.12-3: Register DRIVER (0x02) Driver config register

MSB LSB

Content - - - 12:10

9:7 6:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description 12:10 : led2_current - LED2 driver current selectionIOUT2 = 5mA * (led2_current + 1)9:7 : led1_current - LED1 driver current selectionIOUT1 = 5mA * (led1_current + 1)6:4 : led0_current - LED0 driver current selectionIOUT0 = 5mA * (led0_current + 1)3:0 : pull -0 : no pull active1 : internal pull active (prevents related LED from emitting light when the driver is switched off)Note: Pull-up has to be enabled for measuring the LED forward voltage.

bit 0 : LED0 driverbit 1 : LED1 driverbit 2 : LED2 driverbit 3 : DB pin




Table 4.4.6.12-4: Register STATUS (0x04) Status registers

MSB LSB

Content - - - - - - - - - - - 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 4 : running - "running" is set if at least one PWM channel is enabled. After disabling all PWM channels, the PWM may run some clock cycles until it is stopped. This time is caused by the PWM pre-scaler logic. When PWM enters stopped state, the "running" flag will be cleared.3 : pwm3 - PWM channel 3 state2 : pwm2 - PWM channel 2 state1 : pwm1 - PWM channel 1 state0 : pwm0 - PWM channel 0 state

Table 4.4.6.12-5: Register POLARITY (0x06) Polarity config register

MSB LSB

Content - - - - 11:8 7:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11:8 : pwm_zero - PWM signal behavior selection0 : no end of period PWM signal clear1 : clear PWM signal at end of period to zero levelNote: pwm_zero has higher priority than pwm_term7:4 : pwm_term - PWM signal behavior selection0 : no end of period PWM signal terminate1 : terminate PWM signal at end of period to next period default level (0 at normal mode, 1 at inverse mode)Note: inverse mode means : stop < start3:0 : pwm_polarity - PWM signal polarity configuration0 : off level = 01 : off level = 1

Table 4.4.6.12-6: Register PRESCALER0 (0x08) Pre-scaler 0 config register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 7:0 : val - PWM pre-scaler reload config registerperiod = val+1 [PWM module frequency cycles]

Table 4.4.6.12-7: Register PRESCALER1 (0x0A) Pre-scaler 1 config register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0






Table 4.4.6.12-8: Register PRESCALER2 (0x0C) Pre-scaler 2 config register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-9: Register PRESCALER3 (0x0E) Pre-scaler 3 config register

MSB LSB

Content - - - - - - - - 7:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-10: Register PERIOD0 (0x10) Channel 0 period config register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 period reload value configPWM period = val [pre-scaled cycles]

Note: minimum val = 4

Table 4.4.6.12-11: Register START0 (0x12) Channel 0 pulse start config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 start timestamp configtimestamp = val [pre-scaled cycles]

Table 4.4.6.12-12: Register STOP0 (0x14) Channel 0 pulse stop config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - channel 0 stop timestamp configtimestamp = val [pre-scaled cycles]




Table 4.4.6.12-13: Register COUNTER0 (0x16) Channel 0 current counter value

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : val - current PWM period counter value


MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




Table 4.4.6.12-15: Register START1 (0x1A) Channel 1 pulse start config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-16: Register STOP1 (0x1C) Channel 1 pulse stop config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-17: Register COUNTER1 (0x1E) Channel 1 current counter value

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




Table 4.4.6.12-19: Register START2 (0x22) Channel 2 pulse start config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-20: Register STOP2 (0x24) Channel 2 pulse stop config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-21: Register COUNTER2 (0x26) Channel 2 current counter value

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







Table 4.4.6.12-23: Register START3 (0x2A) Channel 3 pulse start config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-24: Register STOP3 (0x2C) Channel 3 pulse stop config

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Table 4.4.6.12-25: Register COUNTER3 (0x2E) Channel 3 current counter value

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - 11 10 9 8 7 6 5 4 3 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 11 : evt_stop3 (event) - channel 3 pulse stop event10 : evt_start3 (event) - channel 3 pulse start event9 : evt_period3 (event) - channel 3 period reload event8 : evt_stop2 (event) - channel 2 pulse stop event7 : evt_start2 (event) - channel 2 pulse start event6 : evt_period2 (event) - channel 2 period reload event5 : evt_stop1 (event) - channel 1 pulse stop event4 : evt_start1 (event) - channel 1 pulse start event3 : evt_period1 (event) - channel 1 period reload event2 : evt_stop0 (event) - channel 0 pulse stop event1 : evt_start0 (event) - channel 0 pulse start event0 : evt_period0 (event) - channel 0 period reload event





MSB LSB

Content - - - - 11:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0




MSB LSB

Content - - - - - - - - - - - - 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0






4.4.6.13 OTP Control Module (OTP_CTRL)This module can be used to configure OTP read access. OTP programming can also be done using these module registers.

Features:• Read mode and read speed configuration• OTP programming configuration• OTP programming state machine controlNote: The READ_CONFIG and PROG_CONFIG registers can only be written once. A write access protects their contents. Usually they will be set during boot procedure.

OTP program sequence:• set PROG_CONTROL.otp_prog = 1• for all data• set WDATA0 and/or WDATA1 registers with data to be programmed• set WADDR which starts word programming• poll PROG_STATUS.busy until ready• evaluate PROG_STATUS error flags

• set PROG_CONTROL.otp_prog = 0• check programmed content (for instance by CRC check sum calculation)OTP bit soak status• bit soak status may be evaluated during word programming by polling BIT_SOAK_STATUS register and evalu-

ation of soak counts



READ_CONFIG 0x00 Read config register

PROG_CONFIG 0x02 Program config register

PROG_CONTROL 0x06 Program flow control register

WDATA0 0x08 OTP write data [15:0] register

WDATA1 0x0A OTP write data [31:16] register

WADDR 0x10 OTP write address register

PROG_STATUS 0x14 OTP program status register

BIT_SOAK_STATUS

0x16 OTP bit soak status register

PROTECT 0x18 Protection config register

BOOT_PROTECT 0x1A boot protection register




Table 4.4.6.13-2: Register READ_CONFIG (0x00) Read config register

MSB LSB

Content - - - - - - - - - - - - 3:2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Bit Description 3:2 : trp_config - tRP timing configurationconfigures number of 48MHz clock cycles to fulfill tRP

tRP cycles = 2 * trp_config + 30 : tRP = 3 cycles = 3 * 20.8ns = 62.5ns (differential read mode / redundant read mode)1 : tRP = 5 cycles = 5 * 20.8ns = 104.2ns (single ended read mode)2 : tRP = 145.6ns3 : tRP = 187.2ns1 : redundant - redundant read mode selected0 : differential - differential read mode selected

Table 4.4.6.13-3: Register PROG_CONFIG (0x02) Program config register

MSB LSB

Content - - - - - - - - - 6:4 3:0

Reset value 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0


Bit Description 6:4 : trp_config - 48MHz tRP cycles (= trp_config + 1) during verify read

4 : tRP cycles = 4 + 1 = 5 cycles = 5 * 20.8ns = 104.2ns3:0 : max_soak - maximum number of soak pulses to doFor details please see OTP IP programming document.

Table 4.4.6.13-4: Register PROG_CONTROL (0x06) Program flow control register

MSB LSB

Content 15:8 - - - - - - - 0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W

Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x960 : otp_prog -0 : OTP in read mode1 : set OTP to programming modeNote: Consider stable supply voltage conditions during OTP-programming




Table 4.4.6.13-5: Register WDATA0 (0x08) OTP write data [15:0] register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : data - OTP write data bits [15:0]

Note: If WDATA0 register is not written since last WADDR write, it's content will be cleared to 0 at WADDR write and it will not be used in the programming process. This makes possible to writea 16 bit word in case of an already written 16 bit word at the other address of the corresponding 32 bit word.

Table 4.4.6.13-6: Register WDATA1 (0x0A) OTP write data [31:16] register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : data - OTP write data bits [31:16]

Note: If WDATA1 register is not written since last WADDR write, it's content will be cleared to 0 at WADDR write and it will not be used in the programming process. This makes possible to writea 16 bit word in case of an already written 16 bit word at the other address of the corresponding 32 bit word.

Table 4.4.6.13-7: Register WADDR (0x10) OTP write address register

MSB LSB

Content 15:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 15:0 : addr - write address

Note: addr bits 1 and 0 will be ignored.Note: addr write starts 32 bit word program process !

Table 4.4.6.13-8: Register PROG_STATUS (0x14) OTP program status register

MSB LSB

Content - - - - - - - - - 6 5 4 3:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 6 : fail1 - 1 : programming failed (expected a bit as 1, but read a bit as 0)=> at least one 1-bit could not be set to 15 : fail0 - 1 : programing failed (expected a bit as 0, but read a bit as 1)=> at least one 0-bit was set to 14 : busy - 1 : programming is ongoing3:0 : last_soak - number of soak pulses during last word programming




Table 4.4.6.13-9: Register BIT_SOAK_STATUS (0x16) OTP bit soak status register

MSB LSB

Content - - - - - - - - - - 5 4:0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 5 : take - 1 : increment soak count of bit "soak_bit" by 1 (program software has to evaluate this forgetting soak count information)

Note: "take" will be cleared to 0 at register read4:0 : soak_bit - actual soaked bit number

Table 4.4.6.13-10: Register PROTECT (0x18) Protection config register

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x967:0 : protect - OTP protection1 : area protected0 : area writable

OTP single ended read mode:bit 0 : IP address offset 0x8000 .. 0x8FFFbit 1 : IP address offset 0x9000 .. 0x9FFFbit 2 : IP address offset 0xA000 .. 0xAFFFbit 3 : IP address offset 0xB000 .. 0xBFFFbit 4 : IP address offset 0xC000 .. 0xCFFFbit 5 : IP address offset 0xD000 .. 0xDFFFbit 6 : IP address offset 0xE000 .. 0xEFFFbit 7 : IP address offset 0xF000 .. 0xFFFF

OTP redundant or differential read mode:bit 0 : IP address offset 0xC000 .. 0xC7FFbit 1 : IP address offset 0xC800 .. 0xCFFFbit 2 : IP address offset 0xD000 .. 0xD7FFbit 3 : IP address offset 0xD800 .. 0xDFFFbit 4 : IP address offset 0xE000 .. 0xE7FFbit 5 : IP address offset 0xE800 .. 0xEFFFbit 6 : IP address offset 0xF000 .. 0xF7FFbit 7 : IP address offset 0xF800 .. 0xFFFF

Note: protect bits can only be set. Once set they cannot be cleared again.




Table 4.4.6.13-11: Register BOOT_PROTECT (0x1A) boot protection register

MSB LSB

Content 15:8 - - - - - 2:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W

Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x962:0 : protect - fine granular OTP boot area protection, starting at lowest OTP address

0 : no protection1 : 128 byte (0x0080)2 : 256 byte (0x0100)3 : 384 byte (0x0180)4 : 512 byte (0x0200)5 : 1024 byte (0x0400)6 : 1536 byte (0x0600)7 : 2048 byte (0x0800)

Note: Once written, this register cannot be changed anymore. This register will usually be initial-ized during boot process (device calibration).




4.4.6.14 EEPROM Control Module (EEPROM_CTRL)This module can be used to erase and program the EEPROM memory.

Features:• EEPROM memory erase and write access is protected by a special handling sequence• To erase or write access the EEPROM this sequence has to be used by software• This sequence is necessary to lower the risk of accidental EEPROM erase or write• 1. Increment lock counter 9 times => lock_counter == 9• 2. Configure LOCK_L/LOCK_U register(s) if needed• LOCK_L/LOCK_U bits can only be configured when lock_counter == 9

• 3. Increment lock counter 2 times => lock_counter == 11• 4. Configure LOCK_U_FREEZE register if needed• LOCK_L_FREEZE/LOCK_U_FREEZE bits can only be configured when lock_counter == 11

• 5. Increment lock counter => lock_counter == 12• 6. Set needed MODE bits• MODE bits can only be configured when lock_counter == 12

• 7. Increment lock counter => lock_counter == 13• 8. Write data to memory area OR do erase mode dummy write to memory area• 9. Read STATUS until STATUS.busy == 0

• When writing LOCK_CNT with 0 value, MODE, LOCK_CNT (lock_counter) and LOCK_L/LOCK_U will be reset to their default or frozen state

Note: Erased data words should be programmed before they are erased again. Violating this constraint will result inunnecessary bit-cell stress.



MODE 0x00 Mode register


LOCK_L 0x04 Lock (lower) config register

LOCK_U 0x06 Lock (upper) config register

LOCK_CNT 0x0A Lock counter register

LOCK_L_FREEZE 0x0C Lock (lower) freeze register

LOCK_U_FREEZE 0x0E Lock (upper) freeze register

IP_ENABLE 0x10 IP enable register










Table 4.4.6.14-2: Register MODE (0x00) Mode register

MSB LSB

Content 15:8 - - - - - - 1 0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W

Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x961 : program - program mode selectNote: single 16 bit word program0 : erase - erase mode selectNote: double 16 bit word erase


MSB LSB

Content - - - - - - - - - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 0 : busy -0 : Ready for erase, program or read operation.1 : IP is busy. No erase, program or read operation is allowed.

The status is self timed and depends on the IP and may vary between devices and over voltage, temperature and time.

To be sure that a started erase or program operation has been finished poll STATUS.busy until it's 0.




Table 4.4.6.14-4: Register LOCK_L (0x04) Lock (lower) config register

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x967:0 : lock - memory protection (lower half of IP memory range)1 : area protected0 : area writeable / erasable

bit 0 : IP address offset 0x00 .. 0x0Ebit 1 : IP address offset 0x10 .. 0x1Ebit 2 : IP address offset 0x20 .. 0x2Ebit 3 : IP address offset 0x30 .. 0x3Ebit 4 : IP address offset 0x40 .. 0x4Ebit 5 : IP address offset 0x50 .. 0x5Ebit 6 : IP address offset 0x60 .. 0x6Ebit 7 : IP address offset 0x70 .. 0x7E

Note: Lock bits can only be changed (set or cleared) when related LOCK_FREEZE bit is 0.

Table 4.4.6.14-5: Register LOCK_U (0x06) Lock (upper) config register

MSB LSB

Content 15:8 - - - - - - 1:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x961:0 : lock - memory protection (upper half of IP memory range)1 : area protected0 : area writeable / erasable

bit 0 : IP address offset 0x80 .. 0x8Ebit 1 : IP address offset 0x90 .. 0x9E

Note: Lock bits can only be changed (set or cleared) when related LOCK_FREEZE bit is 0.




Table 4.4.6.14-6: Register LOCK_CNT (0x0A) Lock counter register

MSB LSB

Content 15:8 - - - - 3:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W

Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x963:0 : lock_counter -write : writing 0xA increments lock_counterread : returns current lock counter value

Table 4.4.6.14-7: Register LOCK_L_FREEZE (0x0C) Lock (lower) freeze register

MSB LSB

Content 15:8 7:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x967:0 : freeze - memory protection freeze (lower half of IP memory range)1 : area protection frozen0 : area protection changeable

bit 0 : IP address offset 0x00 .. 0x0Ebit 1 : IP address offset 0x10 .. 0x1Ebit 2 : IP address offset 0x20 .. 0x2Ebit 3 : IP address offset 0x30 .. 0x3Ebit 4 : IP address offset 0x40 .. 0x4Ebit 5 : IP address offset 0x50 .. 0x5Ebit 6 : IP address offset 0x60 .. 0x6Ebit 7 : IP address offset 0x70 .. 0x7E

Note: Freeze bits can only be set. Once set they cannot be cleared again.




Table 4.4.6.14-8: Register LOCK_U_FREEZE (0x0E) Lock (upper) freeze register

MSB LSB

Content 15:8 - - - - - - 1:0

Reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0


Bit Description 15:8 : pass - passwordmust be written as 0xA5will always be read as 0x961:0 : freeze - memory protection freeze (upper half of IP memory range)1 : area protection frozen0 : area protection changeable

bit 0 : IP address offset 0x80 .. 0x8Ebit 1 : IP address offset 0x90 .. 0x9E

Note: Freeze bits can only be set. Once set they cannot be cleared again.

Table 4.4.6.14-9: Register IP_ENABLE (0x10) IP enable register

MSB LSB

Content 15:8 - - - - - - - 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W

Bit Description 15:8 : password - must be written as 0xA5, will always be read as 0x960 : enable - EEPROM enable

0 : OFF1 : ON


MSB LSB

Content - - - - - - - - - - - - - 2 1 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Bit Description 2 : ip_off_access (event) - EEPROM memory access during IP_ENABLE.enable OFF state1 : invalid_addr (event) - invalid address event (access outside of valid EEPROM memory range)0 : timeout (event) - EEPROM IP ran into time out


MSB LSB

Content - - - - - - - - - - - - - 2:0 - -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0







MSB LSB

Content - - - - - - - - - - - - - - 1:0 -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - - 1:0 -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




MSB LSB

Content - - - - - - - - - - - - - - 1:0 -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Access R R R R R R R R R R R R R R R/W R/W

Bit Description 1:0 : vmax - needed for nested interrupt support software writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest


MSB LSB

Content - - - - - - - - - - - - - - 1:0 -

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Access R R R R R R R R R R R R R R R/W R/W





5 ESD, Latch Up and EMC

5.1 Electro Static Discharge (ESD)

Table 5.1-1: ESD on IC Level, Human Body Model (HBM)

Standard AEC-Q100-002

Model Human Body Model (HBM)

Capacitance 100pF

Resistance 1,5kΩ

Minimum withstand Voltage 8kV for LIN to system ground

Minimum withstand Voltage 4kV for VS to system ground

Minimum withstand Voltage 2kV for all other pins

Pulse rise time (10%-90%) < 10ns

Test point pin to supply

Number of pulses 1 of each polarity

Table 5.1-2: ESD Test on IC Level, Machine model (MM)


Model Machine Model (MM)

Test point Pin to system ground

Capacitance 200pF

Resistance 0kΩ

Minimum withstand Voltage 200V for all pins to system ground

Table 5.1-3: ESD on IC Level, Charged Device Model (CDM)


Model Charged Device Model (CDM)

Resistance 1Ω

Minimum withstand Voltage 750V for edge pins

500V for all other pins

Pulse rise time (10%-90%) < 400ps

Table 5.1-4: Optional ESD Test on IC Level for Special Pins

Optional ESD Test Test equipment similar IEC 61000-4-2

Capacitance 150pF

Resistance 330Ω

Minimum withstand Voltage 8kV(According to document "OEM hardware requirements for LIN, CAN and FlexRay Interfaces", version 1.3)

5.2 Latch-upLatch-up performance is validated according JEDEC standard JESD 78D.




5.3 EMC The device fulfils the OEM EMC requirements specified in the "Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications", V1.3, dated 04.05.2012

5.4 Pulses according ISO-7637The E521.36 passes tests according to ISO7637-2 Pulse 2a 75V with an external 2.2µF X7R capacitor at pin VS. (Conditions: VS=13.5V, T=25°C)The device passed tests with the following capacitor: Kemet C1206C225K5RACTU




6 Package ReferenceThe E521.36 is available in a Pb free, RoHs compliant, SO8ep plastic package according to JEDEC MS-012-F, variant BA. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020C witha soldering peak temperature of 260°C.Note: Thermal resistance junction to ambient Rth,ja is typ. 45 K/W, based on JEDEC standard JESD-51-2, JESD-51-5 and JESD-51-7.

Figure 6-1: Package Outline

Note: Contact factory for specific location and type of pin 1 identification.




Table 6-1: Package Characteristics

Description Symbol mm inch

min typ max min typ max

Package height A -- -- 1.70 -- -- 0.067

Stand off A1 0.00 -- 0.15 0.000 -- 0.006

Package body thickness A2 1.25 -- -- 0.049 -- --

Width of terminal leads, inclusive lead finish

b 0.31 -- 0.51 0.012 -- 0.020

Thickness of terminal leads, includ-ing lead finish

c 0.10 -- 0.25 0.004 -- 0.010

Package length D 4.900 BSC 0.193 BSC

Package width E 6.000 BSC 0.236 BSC

Package body width E1 3.900 BSC 0.154 BSC

Length of exposed pad D1 3.300 BSC 0.130 BSC

Width of exposed pad E2 2.540 BSC 0.100 BSC

Lead pitch e 1.270 BSC 0.050 BSC

Length of terminal for soldering to substrate

L 0.4 -- 1.27 0.016 -- 0.050

Body chamfer (45°) h 0.25 -- 0.50 0.010 -- 0.020

Angle of lead mounting area phi [°] 0 -- 8 0 -- 8

Mold release angle phi1 [°] 5 -- 15 5 -- 15

Number of terminal positions N 8 8Values in mm are valid, values in inch contain rounding errors

6.1 Device Marking

6.1.1 Top Side

E52136B

XXXXC

YWWR@

Table 6.1.1-1: Top Side

where

Signature Explanation

E52136B Elmos project number

XXXX Production lot number

C Assembler code

YWW Year and week of assembly

R Mask revision code

@ Elmos internal code

Table 6.1.1-2: Marking of the Devices

6.1.2 Bottom Side

No marking.




7 General

7.1 WARNING - Life Support Applications PolicyElmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product could cause loss of human life, body injury or damage to property. In development your designs, please ensure thatElmos Semiconductor AG products are used within specified operating ranges as set forth in the most recent product specifications.

7.2 General DisclaimerInformation furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsib-ility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Elmos Semiconductor AG. Elmos Semiconductor AG reserves the right to make changes to this documentor the products contained therein without prior notice, to improve performance, reliability, or manufacturability .

7.3 Application DisclaimerCircuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes isnot necessarily given. The information in the application examples has been carefully checked and is believed to beentirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos Semiconductor AG or others.




8 Contact InfoTable 8-1: Contact Information

HeadquartersELMOS Semiconductor AGHeinrich-Hertz-Str. 1,D-44227 Dortmund (Germany)www.elmos.com

Phone: +49 (0) 231 / 75 49-100Fax: +49 (0) 231 / 75 [email protected]

Sales and Application Support Office North AmericaELMOS NA. Inc.32255 Northwestern Highway, Suite 220Farmington Hills, MI 48334 (USA)

Phone: +1 (0) 248 / 8 65 32 00Fax: +1 (0) 248 / 8 65 32 [email protected]

Sales and Application Support Office Korea and JapanELMOS KoreaB-1007, U-Space 2, #670 Daewangpangyo-ro, Sampyoung-dong,Bunddang-gu, Sungnam-si Kyounggi-do463-400 Republic of Korea

Phone: +82 (0) 31 / 7 14 11 [email protected]

Sales and Application Support Office ChinaElmos Semiconductor Technology (Shanghai) Co., Ltd.Unit London, 1BF GC Tower, No. 1088 Yuan Shen Road,Pudong New District, Shanghai, 200122, P.R. China

Phone: +86 (0) 21 / 51 78 51 88Fax: +86 (0) 21 / 51 78 52 [email protected]

Sales and Application Support Office SingaporeELMOS Semiconductor Singapore Pte Ltd.3A International Business Park,#09-13 ICON@IBP, Singapore 609935

Phone: +65 (0) 690 / 8 12 61Fax: +65 (0) 6570 / [email protected]



Documents

521.36 - RGB LIN Controller with Current Source - … · RGB LIN Controller with Current Source E521.36 PRODUCTION DATA – May 23, 2017 Pin Configuration Figure 1: Pin Configuration