UART SPI I2C

2

UART/ Universal asynchronous receiver/transmitter

FFUART 230.4 kbps

(DMA)I/O (TXDRXD) 3

BTUART UART 921.6 kbps

STUART 230.4 kbps4

1

UART (I) RXD UARTTXD 1 Low FFUA RT BTUA RT STU ART

UART (II) FFUA RT BTUA RT STU ART V V V

nDCD Low nRI Low

V

TXD

V

V

V

V

nCTS

V

V

nDTR Low UART nRTS Low UART

V

nDSR Low UART

V

V

V

5

6

UART712 58 11.52 LSB MSB7

UART

8

2

(0x6A)

SPI(SPISerial Peripheral Interface) - (10 Mhz) (ADC and DAC) (EEPROM and FLASH) (RTC) () (LCDUART/CAN USB)

TXD

S 0 1 0 1 0 1 1 0 P

TXD

S 0 1 0 1 0 1 1 0 E P

9

TXD

S 0 1 0 1 0 1 1 0 O P

TXD

S 0 1 0 1 0 1 1 0 O P P

10

Inside the BoxSPIMotorola Popular IC MPC8260 (communication processors) M68HC11 (microcontrollers)

Theory of OperationFour signals clock (SCLK) master output/slave input (MOSI) master input/slave output (MISO) slave select (SS)

Synchronous serial data link that operates in full duplex Master Initiates data frame Generates clock Selects slave device Data transferred in both directions simultaneously11

No pre-defined protocol Data transferred at high speed (tens of megahertz) No acknowledgment, no flow control Master may not even be aware of the slave's presence12

3

Single Master, Single Slave

Single Master, Multiple SlaveMasterSCLK MOSI MISO SS1 SS2 SS3

Slave 1SCLK MOSI MISO SS

Slave 2SCLK MOSI MISO SS

clock (SCLK) master output/slave input (MOSI) master input/slave output (MISO) slave select (SS)13

Slave 3SCLK MOSI MISO SS

14

Independent slavesIf a SPI device is not selected, its data output goes into a high-impedance state (hi-Z), so that it does not interfere with the currently activated devices. The SCLK and the MOSI data lines are brought to each slave. Also the MISO data lines are tied together and led back to the master. Only the chip selects are separately brought to each SPI device

Cascading several SPI devices

15

16

4

Cascaded devicesWhen cascading several SPI devices, they are treated as one larger slave and therefore connected to the same chip select. The data output of the preceding device is tied to the data input of the next, thus forming a wider shift register.

SPI Modes

17

18

SPI Modes TableSCLK MOSI

MODE 01

SPI-mode 0 1 2 3

CPOL 0 0 1 1

CPHA 0 1 0 119

0SCLK MOSI

1

1

0

1

0

1

0

0

1

1

0

1

0

1

0

20

5

MODE 23SCLK MOSI

AT93C46 3-wire Serial EEPROMs1024 bits = 64 words of 16 bits 2 MHz Clock Rate (5V)

0SCLK MOSI

1

1

0

1

0

1

0

0

1

1

0

1

0

1

021 22

Read & Write TimingRead

EWEN & EWDS TimingERASE/WRITE Enable (EWEN)

Write ERASE/WRITE Disable (EWDS):

23

24

6

WRAL & ERAL TimingWRITE ALL (WRAL):

ERASE Timing

ERASE ALL (ERAL)

25

26

I2C(IICInter Integrated Circuit Bus) ICeye-squared-see IC,

I2C

1980 (protocol)

EEPROMIO A/DD/A(CODEC)27

(master DSP) (priority)

IC28

7

() (PCB)

100 kbps 400 kbps 3.4 Mbps

IC 29

I2C 30

400 pF ( 20-3010 m) (open drain)2K ~ 10 K 3 mA 0.4 mA

SPI vs. I2CBoth support for communication with slow peripheral devices that are accessed intermittently Benefits Higher data rates (tens of megahertz) Full duplex capability (simultaneously in and out) Lack of device addressing Simpler and more efficient than I2C in point-to-point

Drawbacks31

Requires more effort and more hardware resources Increased board complexity

32

8

IC(Transmitter) (Receiver) (Master) (Start) (SCL) (Stop) (Slave) 33

(Multi-master) bit-banged IC DSPASIC(Application Specific Integrated Circuit)

(Arbitration) (Synchronization) SDA (Serial DAta) SCL (Serial CLock)34

I2CSDASCL ()(open-drainopen-collector) AND

Data validityThe data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW

35

36

9

START and STOP conditionsSTART condition A HIGH to LOW transition on the SDA line while SCL is HIGH

Byte formatByte on the SDA line 8-bits long The most significant bit (MSB) first Each byte has to be followed by an acknowledge bit The number of bytes per transfer is unrestricted A slave cant receive or transmit another complete byte of data Hold the clock line SCL LOW to force the master into a wait state Data transfer continues when the slave is ready for another byte of data and releases clock line SCL

STOP condition A LOW to HIGH transition on the SDA line while SCL is HIGH

START and STOP conditions are always generated by the master. Bus busy after the START condition, a repeated START (Sr) is generated instead of a STOP condition Bus free after the STOP condition

37

38

Acknowledge on the I2C busThe acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the HIGH period of acknowledge clock pulse When a slave doesnt acknowledge the slave address slave leaves (release) the data line HIGH master generates a STOP or a repeated START condition

A complete data transferSTART slave address (7 bits) (R/W) ACK STOP 0 : WRITE 1 : READ

direction bit

A master can generate a (Sr) and address another slave without first generating a STOP condition.

39

40

10

Master send dataMaster-transmitter transmits to slave-receiver. The transfer direction is not changed.

Master read dataMaster reads slave immediately after first byte. At the moment of the first acknowledge, master-transmitter master-receiver slave-receiver slave-transmitter

The STOP condition is generated by the master, which has previously sent a not-acknowledge (A).

41

42

Write/ Read data format

Combined formatDuring a change of direction within a transfer START condition & slave address are both repeated the R/W bit reversed

If a master-receiver sends a Sr condition, it has previously sent a not-acknowledge (A). Serial memory control Internal memory location to be written S condition & slave address repeated, data can be transferred.

43

44

11

7-Bit AddressingWhen an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit. The first byte after the START procedure

Definition in the first byte

45

1. No device is allowed to acknowledge the reception of the START byte. 2. The CBUS address has been reserved to enable the inter-mixing of CBUS compatible and I2C-bus compatible devices in the same system. 3. The address reserved for a different bus format is included to enable 46 I2C and other protocols to be mixed.

Address formatEach device has a unique 7-bit IC address Four most significant bits are fixed and assigned to specific categories of devices e.g. 1010 is assigned to serial EEPROMs Three less significant bits (A2, A1 and A0) are programmable eight different type of device to operate on the same IC-bus. 7-bit addressing allows up to 128 devices on the same bus but some of these addresses are reserved for special commands so the practical limit is around 120

Program examplebit UI2cSCLHigh(void) { unsigned char cnt ; D11_SCL = 1; for (cnt=8;cnt>0;cnt--) { if (D11_SCL) return(1); }; return(0); } bit UI2cStart(void) { D11_SDA = 0 ; _nop_(); _nop_(); D11_SCL = 0 ; return(1) ; } bit UI2cStop(void) { D11_SCL = 1; _nop_(); _nop_(); D11_SDA = 1 ; return(1); }

47

48

12

Send databit UI2cSend(unsigned char SendData) { unsigned char mask; //Strobe first 8 bit of data with //MSB first to I2C bus mask = 0x80 ; do { D11_SDA = ((SendData & mask) != 0); mask = mask >>1 ; if(UI2cSCLHigh() == 0) return(0) ; D11_SCL = 0 ; }while (mask); } //Check for number 9 acknowledgement //bit from I2C Device D11_SDA =1 ; _nop_(); _nop_(); if(UI2cSCLHigh() == 0) return(0); if ( D11_SDA == 0 ) { //Device has acknowledged _nop_(); D11_SCL=0; return(1); }; return(0);

Receive databit UI2cReceive(unsigned char *pReceiveData, bit Ack) { unsigned char i,mask; D11_SDA = 1; mask = 0x80; i=0; _nop_(); do { if(UI2cSCLHigh() == 0) return(0); _nop_(); if (D11_SDA) i = i | mask ; D11_SCL = 0 ; _nop_(); mask=mask>>1; }while(mask);49

if (Ack) D11_SDA =1; else D11_SDA =0; if(UI2cSCLHigh() == 0) return(0); _nop_(); *pReceiveData=i; D11_SCL = 0; return(1); }

50

Read / write N datavoid Rd_Ndata(unsigned char *POINTER, unsigned char N) { unsigned char count; bit ReceiveAck ; UI2cStart(); if (UI2cSend(I2C_DATA_R)) { for (count = 0; count < N; count++) { ReceiveAck= (count == (N-1));UI2cReceive(POINTER+count, ReceiveAck);

HT24LC08 CMOS 8K 2-Wire Serial EEPROM81024 bits =1024 bytes = 256 bytes 4 (pages) A2 hard wire, A1 & A0 have no connection Total of two 8K devices may be addressed on a single bus system.

void Wr_Ndata(unsigned char *POINTER, unsigned char N) { unsigned char count; UI2cStart(); if (UI2cSend(I2C_DATA_W)) { for (count = 0; count < N; count++) { UI2cSend(*(POINTER+count)); } UI2cStop(); } else { D11_SCL = 1; D11_SDA = 1; } }

} } UI2cStop(); }

51

52

13

Write Timing

Read Timing

53

54

(I)

(II)

0 (Page)

01 (H)

13 (H)

1 (Page)

32 (H)

3B (H)

55

56

14

(III)

(V)

2 (Page)

1A (H)

19 (H)

3 (Page)

29 (H)

82 (H)

57

58

UARTSPII2C

SPII2C

(PCB)

59

15