6 - 1 Texas Instruments Incorporated Module 6 : Analogue Digital Converter C28x 32-Bit-Digital Signal Controller TMS320F2812

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Texas Instruments IncorporatedTexas Instruments Incorporated

Module 6 : Analogue Digital Converter C28xModule 6 : Analogue Digital Converter C28x

32-Bit-Digital Signal Controller32-Bit-Digital Signal ControllerTMS320F2812TMS320F2812

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ADC ModuleADC Module 12-bit resolution ADC core12-bit resolution ADC core Sixteen analog inputs (range of 0 to 3V)Sixteen analog inputs (range of 0 to 3V) Two analog input multiplexersTwo analog input multiplexers

Up to 8 analog input channels eachUp to 8 analog input channels each Two sample/hold units (for each input mux)Two sample/hold units (for each input mux) Sequential and simultaneous sampling modesSequential and simultaneous sampling modes Auto sequencing capability - up to 16 auto Auto sequencing capability - up to 16 auto

conversionsconversions Two independent 8-state sequencersTwo independent 8-state sequencers

““Dual-sequencer mode”Dual-sequencer mode” ““Cascaded mode”Cascaded mode”

Sixteen individually addressable result registersSixteen individually addressable result registers Multiple trigger sources for start-of-conversionMultiple trigger sources for start-of-conversion

External trigger, S/W, and Event Manager eventsExternal trigger, S/W, and Event Manager events

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ADC Module Block Diagram ADC Module Block Diagram (Cascaded Mode)(Cascaded Mode)

12-bit A/D12-bit A/DConverterConverter

ResultResultSelectSelect

Result MUXResult MUXRESULT0RESULT0

. . .

. . .

RESULT1RESULT1

RESULT2RESULT2

RESULT15RESULT15

CHSEL00 CHSEL00 (state 0)(state 0)





......

MAX_CONV1MAX_CONV1

Auto sequencerAuto sequencer

Start SequenceStart SequenceTriggerTrigger

SOCSOC EOCEOC

SoftwareSoftwareEVAEVAEVBEVB

Ext Pin (ADCSOC)Ext Pin (ADCSOC)

Analog MUXAnalog MUX

MUXMUXAA

ADCINA0ADCINA0ADCINA1ADCINA1

ADCINA7ADCINA7

......

MUXMUXBB

ADCINB0ADCINB0ADCINB1ADCINB1

ADCINB7ADCINB7

......

S/HS/H

AA

S/HS/HMUXMUX

S/HS/H

BB

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ADC Module Block Diagram ADC Module Block Diagram (Dual-Sequencer mode)(Dual-Sequencer mode)

12-bit A/D12-bit A/DConverterConverter

SoftwareSoftwareEVAEVA

Ext PinExt Pin (ADCSOC)(ADCSOC)


Result MUXResult MUX

RESULT0RESULT0

. . .

. . .

RESULT1RESULT1

RESULT7RESULT7


RESULT8RESULT8

. . .

. . .

RESULT9RESULT9

RESULT15RESULT15





......

MAX_CONV1MAX_CONV1



SOC1/SOC1/EOC1EOC1

SEQ1SEQ1





......

MAX_CONV2MAX_CONV2



SEQ2SEQ2

SequencerSequencerArbiterArbiter

SOC2/SOC2/EOC2EOC2

SoftwareSoftwareEVBEVB

Analog MUXAnalog MUX

MUXMUXAA

ADCINA0ADCINA0ADCINA1ADCINA1

ADCINA7ADCINA7

......

MUXMUXBB

ADCINB0ADCINB0ADCINB1ADCINB1

ADCINB7ADCINB7

......

S/HS/H

AA

S/HS/HMUXMUX

S/HS/H

BB

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F2812 ADC Clocking ExampleF2812 ADC Clocking ExampleCLKINCLKIN

(30 MHz)(30 MHz)HSPCLKHSPCLK

(150 (150 MHz)MHz)

ADCCLKPS

bits

ADCTRL3ADCTRL3

0011b0011b

FCLKFCLK

(25 MHz)(25 MHz)

FCLK = HSPCLK/(2*ADCCLKPS)FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK =ADCCLK =

FCLK/(CPS+1)FCLK/(CPS+1)

ADCCLKADCCLK

(25 MHz)(25 MHz)CPS bit

ADCTRL1ADCTRL1

0b

To ADC To ADC pipelinepipeline

sampling sampling windowwindowACQ_PS

bits

ADCTRL1ADCTRL1

0111b

Important: ADCCLK can be a maximum of 25 MHz!Important: ADCCLK can be a maximum of 25 MHz!

SYSCLKOUTSYSCLKOUT(150 MHz)(150 MHz)

PLLCRPLLCR

DIV

bits

1010bTo CPUTo CPU

sampling window = (ACQ_PS + 1)*(1/ADCCLK)sampling window = (ACQ_PS + 1)*(1/ADCCLK)

PCLKCR.ADCENCLK = 1PCLKCR.ADCENCLK = 1

HISPCPHISPCP

HSPCLK

bits

000b

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Analog-to-Digital Converter RegistersAnalog-to-Digital Converter Registers

ADCTRL1ADCTRL1 0x007100 ADC Control Register 1 0x007100 ADC Control Register 1


ADCMAXCONV 0x007102 ADC Maximum Conversion Channels RegisterADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register

ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1




ADCASEQSR 0x007107 ADC Auto sequence Status RegisterADCASEQSR 0x007107 ADC Auto sequence Status Register

ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0


ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2 :: :: :: :: :: :: :: :: ::




ADCSTADCST 0x007119 ADC Status and Flag Register 0x007119 ADC Status and Flag Register

RegisterRegister Address Description Address Description

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ADC Control Register 1 - ADC Control Register 1 - Upper ByteUpper ByteADCTRL1 @ 0x007100ADCTRL1 @ 0x007100

1515 1414 1313 1212 1010 8899

reserved SUSMOD0SUSMOD0

Emulation Suspend ModeEmulation Suspend Mode00 = [Mode 0] free run (do not stop)00 = [Mode 0] free run (do not stop)01 = [Mode 1] stop after current sequence01 = [Mode 1] stop after current sequence10 = [Mode 2] stop after current conversion10 = [Mode 2] stop after current conversion11 = [Mode 3] stop immediately11 = [Mode 3] stop immediately

1111

ADC Module ResetADC Module Reset 0 = no effect0 = no effect 1 = reset (set back to 01 = reset (set back to 0 by ADC logic)by ADC logic)

SUSMOD1SUSMOD1RESETRESET ACQ_PS3ACQ_PS3 ACQ_PS2ACQ_PS2 ACQ_PS1ACQ_PS1 ACQ_PS0ACQ_PS0

Acquisition Time Prescale (S/H)Acquisition Time Prescale (S/H)Value = (binary+1)Value = (binary+1)** Time dependent on the “Conversion Time dependent on the “Conversion Clock Prescale” bit (Bit 7 “CPS”)Clock Prescale” bit (Bit 7 “CPS”)

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ADC Control Register 1 - ADC Control Register 1 - Lower ByteLower ByteADCTRL1 @ 0x007100ADCTRL1 @ 0x007100

77 66 55 44 22 0011

CPSCPS CONT_RUNCONT_RUN reserved

Sequencer ModeSequencer Mode0 = dual mode0 = dual mode1 = cascaded mode1 = cascaded mode

33

Continuous RunContinuous Run0 = stops after reaching 0 = stops after reaching end of sequence end of sequence 1 = continuous (starts all over1 = continuous (starts all over again from “initial state”)again from “initial state”)

Conversion PrescaleConversion Prescale0 = CLK / 10 = CLK / 11 = CLK / 21 = CLK / 2

SEQ_CASCSEQ_CASC reserved reserved reservedSEQ1_OVRDSEQ1_OVRD

Sequencer OverrideSequencer Override(continuous run mode)(continuous run mode)0 = sequencer pointer resets to “initial state”0 = sequencer pointer resets to “initial state” at end of MAX_CONVnat end of MAX_CONVn1 = sequencer pointer resets to “initial state”1 = sequencer pointer resets to “initial state” after “end state”after “end state”

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ADC Control Register 2 - ADC Control Register 2 - Upper ByteUpper ByteADCTRL2 @ 0x007101ADCTRL2 @ 0x007101

1515 1414 1313 1212 1010 8899

EVB_SOCEVB_SOC_SEQ_SEQ

RST_SEQ1RST_SEQ1

Interrupt Enable (SEQ1)Interrupt Enable (SEQ1)0 = interrupt disable0 = interrupt disable1 = interrupt enable1 = interrupt enable

EVB SOCEVB SOC(cascaded mode only)(cascaded mode only)0 = no action0 = no action1 = start by EVB 1 = start by EVB signalsignal

1111

Reset SEQ1Reset SEQ1 0 = no action0 = no action 1 = immediate reset1 = immediate reset SEQ1 to “initial state”SEQ1 to “initial state”

Start Conversion (SEQ1)Start Conversion (SEQ1)0 = clear pending SOC trigger0 = clear pending SOC trigger1 = software trigger-start SEQ11 = software trigger-start SEQ1

EVA SOCEVA SOCSEQ1 Mask BitSEQ1 Mask Bit0 = cannot be started0 = cannot be started by EVA triggerby EVA trigger1 = can be started 1 = can be started by EVA triggerby EVA trigger

INT_ENA_INT_ENA_SEQ1SEQ1

INT_MODINT_MOD_SEQ1_SEQ1

reservedEVA_SOC_EVA_SOC_

SEQ1SEQ1SOC_SEQ1SOC_SEQ1 reserved

Interrupt Mode (SEQ1)Interrupt Mode (SEQ1)0 = interrupt every EOS0 = interrupt every EOS1 = interrupt every other EOS1 = interrupt every other EOS

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ADC Control Register 2 - ADC Control Register 2 - Lower ByteLower ByteADCTRL2 @ 0x007101ADCTRL2 @ 0x007101

77 66 55 44 22 0011

EXT_SOCEXT_SOC_SEQ1_SEQ1

RST_SEQ2RST_SEQ2

External SOC (SEQ1)External SOC (SEQ1)0 = no action0 = no action1 = start by signal1 = start by signal from ADCSOC pinfrom ADCSOC pin

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Reset SEQ2Reset SEQ2 0 = no action0 = no action 1 = immediate reset1 = immediate reset SEQ2 to “initial state”SEQ2 to “initial state”

Start Conversion (SEQ2)Start Conversion (SEQ2)(dual-sequencer mode only)(dual-sequencer mode only)0 = clear pending SOC trigger0 = clear pending SOC trigger1 = software trigger-start SEQ21 = software trigger-start SEQ2

EVB SOCEVB SOCSEQ2 Mask bitSEQ2 Mask bit0 = cannot be started0 = cannot be started by EVB triggerby EVB trigger1 = can be started 1 = can be started by EVB triggerby EVB trigger

INT_ENA_INT_ENA_SEQ2SEQ2

INT_MODINT_MOD_SEQ2_SEQ2

reservedEVB_SOC_EVB_SOC_

SEQ2SEQ2SOC_SEQ2SOC_SEQ2 reserved

Interrupt Enable (SEQ2)Interrupt Enable (SEQ2)0 = interrupt disable0 = interrupt disable1 = interrupt enable1 = interrupt enable Interrupt Mode (SEQ2)Interrupt Mode (SEQ2)

0 = interrupt every EOS0 = interrupt every EOS1 = interrupt every other EOS1 = interrupt every other EOS

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ADC Control Register 3ADC Control Register 3ADCTRL3 @ 0x007118ADCTRL3 @ 0x007118

Sampling Mode SelectSampling Mode Select0 = sequential sampling mode0 = sequential sampling mode1 = simultaneous sampling mode1 = simultaneous sampling mode

ADC Clock PrescaleADC Clock Prescale

ADCCLKPS3ADCCLKPS3 ADCCLKPS2ADCCLKPS2 ADCCLKPS1ADCCLKPS1 ADCCLKPS0ADCCLKPS0 SMODE_SELSMODE_SEL

44 22 001133

ADCRFDNADCRFDN ADCBGNDADCBGND ADCPWDNADCPWDN

77 556615 - 815 - 8

reserved

ADC ReferenceADC ReferencePower DownPower Down0 = powered down0 = powered down1 = powered up1 = powered up

ADC BandgapADC BandgapPower DownPower Down0 = powered down0 = powered down1 = powered up1 = powered up

ADC Power DownADC Power Down(except Bandgap & Ref.)(except Bandgap & Ref.)0 = powered down0 = powered down1 = powered up1 = powered up

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Maximum Conversion Channels RegisterMaximum Conversion Channels RegisterADCMAXCONV @ 0x007102ADCMAXCONV @ 0x007102

MAX_MAX_CONV 2_2CONV 2_2







reserved

Cascaded ModeCascaded Mode

Dual ModeDual ModeSEQ2SEQ2 SEQ1SEQ1

Bit fields define the maximum number of auto conversions (binary+1)Bit fields define the maximum number of auto conversions (binary+1)

Auto conversion session always starts with the “initial state”Auto conversion session always starts with the “initial state” and continues sequentially until the “end state”, if allowedand continues sequentially until the “end state”, if allowed

SEQ1 SEQ2 CascadedSEQ1 SEQ2 CascadedInitial state CONV00 CONV08 CONV00Initial state CONV00 CONV08 CONV00End state CONV07 CONV15 CONV15End state CONV07 CONV15 CONV15

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ADC Input Channel Select Sequencing ADC Input Channel Select Sequencing Control RegisterControl Register

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

0x0071030x007103 CONV03 CONV02 CONV01 CONV00CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1ADCCHSELSEQ1




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Example - Sequencer “Start/Stop” OperationExample - Sequencer “Start/Stop” Operation

II11, I, I22, I, I33 VV11, V, V22, V, V33 II11, I, I22, I, I33 VV11, V, V22, V, V33

EVAEVATimer 1Timer 1

EVAEVAPWMPWM

System Requirements:System Requirements:•Three auto conversions (IThree auto conversions (I11, I, I22, I, I33) off trigger 1 (Timer underflow)) off trigger 1 (Timer underflow)•Three auto conversions (VThree auto conversions (V11, V, V22, V, V33) off trigger 2 (Timer period)) off trigger 2 (Timer period)

Event Manager A (EVA) and SEQ1 are used for this exampleEvent Manager A (EVA) and SEQ1 are used for this examplewith sequential sampling modewith sequential sampling mode

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Example - Sequencer “Start/Stop” Operation Example - Sequencer “Start/Stop” Operation (Continued)(Continued)

Bits Bits 15-12 11-8 7-4 3-0 15-12 11-8 7-4 3-0

0x007103 V0x007103 V11 I I33 I I22 I I11 ADCCHSELSEQ1 ADCCHSELSEQ1

0x007104 x x V0x007104 x x V33 V V22 ADCCHSELSEQ2 ADCCHSELSEQ2

• MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:

• Once reset and initialized, SEQ1 waits for a triggerOnce reset and initialized, SEQ1 waits for a trigger

• First trigger three conversions performed: CONV00 (IFirst trigger three conversions performed: CONV00 (I11), CONV01 (I), CONV01 (I22), CONV02 (I), CONV02 (I33))

• MAX_CONV1 value is reset to 2 (unless changed by software)MAX_CONV1 value is reset to 2 (unless changed by software)• SEQ1 waits for second triggerSEQ1 waits for second trigger

• Second trigger three conversions performed: CONV03 (VSecond trigger three conversions performed: CONV03 (V11), CONV04 (V), CONV04 (V22), CONV05 (V), CONV05 (V33))

• End of second auto conversion session, ADC Results registers have the following values:End of second auto conversion session, ADC Results registers have the following values:

RESULT0 IRESULT0 I11 RESULT3 V RESULT3 V11



User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 sessionUser can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session• SEQ1 keeps “waiting” at current state for another triggerSEQ1 keeps “waiting” at current state for another trigger

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ADC Conversion Result Buffer RegisterADC Conversion Result Buffer RegisterADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117

(Total of 16 Registers)(Total of 16 Registers)

With analog input 0V to 3V, we have:With analog input 0V to 3V, we have:

analog voltsanalog volts converted valueconverted value RESULTxRESULTx

3.03.0 FFFhFFFh 1111|1111|1111|00001111|1111|1111|0000

1.51.5 7FFh7FFh 0111|1111|1111|00000111|1111|1111|0000

0.000730.00073 1h1h 0000|0000|0001|00000000|0000|0001|0000

00 0h0h 0000|0000|0000|00000000|0000|0000|0000

MSBMSB

00112233445566778899101011111212131314141515

LSBLSB

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How do we Read the Result?How do we Read the Result?Integer formatInteger format

RESULTxRESULTx

ACCACC

Data MemData Mem

bit shift rightbit shift right

xx xx xx xx xx xx xx xx xx xx00000000

1515 00

xx xx xx xx xx xx xx xx xx xx 000000 00

xx xx xx xx xx xx xx xx xx xx00000000000000000000000000000000

xx xx

xx xx

xx xx

Example: read RESULT0 registerExample: read RESULT0 register

#include "DSP281x_Device.h"#include "DSP281x_Device.h"

void main(void)void main(void){{ Uint16 value;Uint16 value; // unsigned// unsigned

value = AdcRegs.ADCRESULT0 >> 4;value = AdcRegs.ADCRESULT0 >> 4;}}

#include "DSP281x_Device.h"#include "DSP281x_Device.h"

void main(void)void main(void){{ Uint16 value;Uint16 value; // unsigned// unsigned

value = AdcRegs.ADCRESULT0 >> 4;value = AdcRegs.ADCRESULT0 >> 4;}}

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Lab 6: Two Channel Analogue Conversion Lab 6: Two Channel Analogue Conversion initiated by GP Timer 1initiated by GP Timer 1

AIM :AIM : AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by

GPT1-period of 0.1 sec. GPT1-period of 0.1 sec. ADCIN_A0 and ADCIN_B0 are connected to two ADCIN_A0 and ADCIN_B0 are connected to two

potentiometers to control analogue input voltages between 0 potentiometers to control analogue input voltages between 0 and 3,0V. and 3,0V.

no GPT1-interrupt-service no GPT1-interrupt-service Auto-start of ADC with Auto-start of ADC with T1TOADC-bit !!T1TOADC-bit !!

Use ADC-Interrupt Service Routine to read out the ADC Use ADC-Interrupt Service Routine to read out the ADC resultsresults

Use main loop to show alternately the two results as light-Use main loop to show alternately the two results as light-beam on LED’s (GPIO port B7..B0)beam on LED’s (GPIO port B7..B0)

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Additional Registers to initialize Lab 6:Additional Registers to initialize Lab 6:

General Purpose Timer Control : : GPTCONA Timer 1 Control : T1CON Timer 1 Period : T1PR Timer 1 Compare : T1CMPR Timer 1 Counter : T1CNT Interrupt Flag : IFR Interrupt Enable ask : IER ADC – Control 3 : ADCTRL3 ADC – Control 2 : ADCTRL2 ADC – Control 1 : ADCTRL1 Channel Select Sequencer 1 : CHSELSEQ1 Max. number of conversions : MAXCONV ADC - Result 0 : ADCRESULT0 ADC - Result 1 : ADCRESULT1

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Optional Lab6AOptional Lab6A

Modify Lab-Exercise 4 ( ‘Knight-Rider’) :Modify Lab-Exercise 4 ( ‘Knight-Rider’) :

• use the Analogue Input ADCIN0 to changeuse the Analogue Input ADCIN0 to change the frequency for the LED’sthe frequency for the LED’s• to add the ADC-setup use Lab6 as a startto add the ADC-setup use Lab6 as a start• use a LED-frequency range between 50Hz and 1 Hzuse a LED-frequency range between 50Hz and 1 Hz• use (1) a linear or (2) a logarithm scale use (1) a linear or (2) a logarithm scale between Fbetween Fminmin and F and Fmaxmax..

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6 - 1 Texas Instruments Incorporated Module 6 : Analogue Digital Converter C28x 32-Bit-Digital Signal Controller TMS320F2812