6-Bit Serial MultiplierThu NguyenKenny Yip

Chao-Ton YangMing Li

Advisor: Prof. David ParentDec 6, 2004

Introduction

• We design a 6-bit serial.

• The advantage of this design over the parallel circuit is the reducing of required hardware and input, output routing when the high clock rate is not important factor in application.

Specifications

• Clock f = 100 MHz, duty cycle = 50%

• Output Cload = 10 pF

• Power < 500 mW

• Tpavg < 5ns

• Area < 600 mil2

Block Diagram

A5 A4 A3 A2 A1 A0

B5 B4 B3 B2 B1 B0

Full Adder5

Full Adder4

Full Adder3

Full Adder2

Full Adder4

Full Adder1

Full Adder0

S5 S4 S3 S2 S1 S0

input

output

s c s s s sc cs c c c

delay

1-bit schematic

Schematic

Longest Path Calculations

Logic Level Gate

Cg to Drive NSN NSP N M WN WP

Cg of Gate Tpavg

1 DFF-NAND2 Slave 10 2 1 1 2 4 3.5 12.8 0.312

2 DFF-Driver mux Slave 12.8 2 2 1 3 4.1 7 18.9 0.4

3 DFF-NAND2 Master 18.9 2 1 1 2 3.8 3.3 12.2 0.312

4 DFF-Driver mux Master 12.2 2 2 2 2 3.2 5.4 14.7 0.4

5 MUX-INV 14.7 1 1 1 1 1.5 2.6 5.1 0.312

6 MUX-NAND2 5.1 1 1 3 2 1.5 2.6 5 0.312

7 FA-INV 5 1 1 1 1 1.5 2.6 5 0.312

8 FA-AOI1 5 2 2 10 10 3.5 6.1 16.3 0.312

9 FA-AOI2 16.3 2 2 7 7 3.5 5.8 15.8 0.312

10 AND2-INV 15.8 1 1 1 1 1.5 2.6 5.4 0.312

11 AND2-NAND2 5.4 2 1 1 2 2 1.76 4.8 0.312

12 DFF-NAND2 Slave 4.8 2 1 1 2 1.7 1.5 5.4 0.312

13 DFF-Driver mux Slave 5.4 2 2 1 3 3.9 6.8 18.3 0.355

14 DFF-NAND2 Master 18.3 2 1 1 2 3.7 3.2 11.8 0.312

15 DFF-Driver mux Master 11.8 2 2 2 2 3.1 5.3 14.4 0.4

                Total Tpavg = 4.987

* Note: All widths are in microns, capacitances in fF and time in nS

D Flip-Flop schematic

D Flip-Flop transient response

Full Adder schematic

Full adder verilog waveform

Full Adder transient response

Verilog Waveform

6bit serial multiplier simulation

Tpavg = 4.2 ns

Power Consumption

• Pavg=1/2 x CL x f x VDD2 • P avg = 1/2 x 10 x 10-12 F

x 100 x 106 Hz x 52 = 12.5mW for 1 component.

• Power transient response of entire circuitry read from the simulation P = 148mW.

DRC & Extraction

LVS

Complete Design Layout

Test results

• Tpavg = 4.2ns (< 5ns)

• Total area A = 345 x 310m (1070 mil2 > 600 mil2)

• Power P = 148mW (< 500 mW)

Summary

• Product test results meet most of specifications except the layout area are larger than 600 mil2 target specifications but we could easily reduced it if we have more time to rearrange all the compoments and routing. So Layout area is not actually a problem.

• This a very challenge project, although we were not having much time left for project after the other heavy class works, this is the best we can accomplish.

Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab

• Thanks to Professor D. Parent

• Thanks to our EE166 classmates