6 Registers and Counters6 Registers and Counters

2011-05-17 ASIC LAB 1

6-1 REGISTERS6 1 REGISTERS

Register- a group of binary cells suitable for holding binary information.

Clock=1 ;input information transferredtransferred

Clock=0 ;unchanged

Clear=0 ;clearing the register to

2011-05-17 ASIC LAB 2

Clear 0 ;clearing the register to all 0’s prior to its clocked operation.

Register with Parallel LoadRegister with Parallel Load

Clock=1 ;input information

->loading

Clock=0 ;the content of the register ->unchanged

Load input 1 ; the I inputsLoad input=1 ; the I inputs are transferred into the register

Load input=0 ; maintain the

2011-05-17 ASIC LAB 3

content of the register

6-2 SHIFT REGISTERS6-2 SHIFT REGISTERS

Shift register-capable of shifting its binary information in one or both directions

The simplest shift register

2011-05-17 ASIC LAB 4

Serial TransferSerial Transfer

To prevent the loss of information storedof information stored in the source register

2011-05-17 ASIC LAB 5

Serial-Transfer ExampleSerial Transfer Example

Serial output of BShift register BShift register ATiming pulse

00 0 1 01 0 1 1Initial value

Serial output of BShift register BShift register ATiming pulse

1

0

1 0 0 1

1 1 0 0

1 1 0 1

1 1 1 0

After T1

After T2

0

1

0 1 1 0

1 0 1 1

0 1 1 1

1 0 1 1

After T3

After T4

01 1 0 01 1 1 0After T2

2011-05-17 ASIC LAB 6

Serial AdditionSerial Addition

OperationFor storing sum

the A register ->augend ,the B register ->addend ,carry ->0, y

The SO of A and B provide a pair of significant bits for the FAthe FA Output Q gives the input carry at zTh hift i ht t lThe shift-right control enables both registers and the carry flip-flop.The sum bit from S enters the leftmost flip-flop of A

2011-05-17 ASIC LAB 7

State Table for Serial AdderState Table for Serial Adder

Present value of carryO t tOutput carry

' ' ( ) 'QQ

J x yK x y x yS x y Q

By k-map

2011-05-17 ASIC LAB 8

S x y Q

Second form of Serial AdderSecond form of Serial Adder

2011-05-17 ASIC LAB 9

Universal Shift RegisterUniversal Shift Register

S1, S0 -> 0, 0 ;No change, , ; g

S1, S0 -> 0, 1 ;Shift right

S1, S0 -> 1, 0 ;Shift left

S1, S0 -> 1, 1 ;Parallel load

2011-05-17 ASIC LAB 10

6-3 RIPPLE COUNTERS6-3 RIPPLE COUNTERS

LSB

2011-05-17 ASIC LAB 11

Count sequence for a binary CounterCount sequence for a binary Counter

Count sequence Conditions forCount sequenceA3 A2 A1 A0

Conditions for Complementing

0 0 0 0 Complement A0

0 0 0 10 0 1 00 0 1 1

Complement A0

Complement A0

Complement A0

A0 will go from 1 to 0 and complement A1

A0 will go from 1 to 0 0 0 1 1

0 1 0 0

Complement A0

Complement A0

gand complement A1 ;A1will go from 1 to 0 and complement A2

0 1 0 10 1 1 00 1 1 1

Complement A0

Complement A0

Complement A0

and complement A2

A0 will go from 1 to 0 and complement A1

………………1 0 0 0

p

and so on…

2011-05-17 ASIC LAB 12

BCD Ripple CounterBCD Ripple Counter

2011-05-17 ASIC LAB 13

BCD Ripple CounterBCD Ripple Counter

11 QQ is complemented on the negative edge of everyis complemented on the negative edge of every

operation

1. 1. QQ1 1 is complemented on the negative edge of every is complemented on the negative edge of every count pulse.count pulse.

2. Q2. Q22 is complemented if Qis complemented if Q88=0 and Q=0 and Q11 goes from 1 to 0. goes from 1 to 0. QQ22 is cleared if Qis cleared if Q88=1 and Q=1 and Q11 goes from 1 to 0.goes from 1 to 0.

3. Q3. Q4 4 is complemented when Qis complemented when Q2 2 goes from 1 to 0.goes from 1 to 0.

l d hl d h dd ff4 .Q4 .Q88 is complemented when Qis complemented when Q44QQ22=11 and Q=11 and Q1 1 goes from goes from 1 to 0. Q1 to 0. Q88 is cleared if either Qis cleared if either Q44 or Qor Q22 is 0 and Qis 0 and Q11 goes goes from 1 to 0from 1 to 0

2011-05-17 ASIC LAB 14

Three-Decade Decimal BCD CounterThree-Decade Decimal BCD Counter

To count from 0 to 999, We need a three-decade counter.

2011-05-17 ASIC LAB 15

6-4 SYNCHRONOUS COUNTERS6-4 SYNCHRONOUS COUNTERS

The first stage A0 has its J The first stage A0 has its Jand K equal to 1 if the counter is enabled .

The other J and K inputs areThe other J and K inputs are equal to 1 if all previous low-order bits are equal to 1 and the count is enabled

2011-05-17 ASIC LAB 16

count is enabled.

Up-Down Binary CounterUp-Down Binary Counter

Up input control=1 ;count up (the T inputs receive their signals from the values of the previous normal outputs of the flip-flops.)

Down input control=1, up input control=0 ; count downcontrol 0 ; count down

Up=down=0 ;unchanged state

Up=down=1 ;count up

2011-05-17 ASIC LAB 17

p o ; p

BCD CounterBCD Counter

1 1'

QTT Q Q

2 8 1

4 2 1

8 8 1 4 2 1

'Q

Q

Q

T Q QT Q QT Q Q Q Q Q

8 1

Q Q Q Q Q Qy Q Q

2011-05-17 ASIC LAB 18

Binary Counter with Parallel LoadBinary Counter with Parallel Load

Input load control=1 ; disables the count sequence ,data transfer

Load 0 and co nt 1 co ntLoad =0 and count=1 ;count

Load=0 and count=0 ;unchangedg

Carry out=1(all flip-flop=1)

2011-05-17 ASIC LAB 19

BCD COUNTER using Binary Counter with Parallel LoadBCD COUNTER using Binary Counter with Parallel Load

The AND gate detects the occurrence of state 1001(9) in the output. In this state, the load input is

bl d d ll ’enabled and all-0’s input is loaded into register.

The NAND gate detects e gate detectsthe count of 1010(10) , as soon as this count occurs the register is gcleared.

A momentary spikeoccurs in output A2 as theoccurs in output A2 as the count goes from 1001 to 1010 and immediately to 0000

2011-05-17 ASIC LAB 20

0000

6-5 OTHER COUNTERS6-5 OTHER COUNTERS

AJ B AK B

'

A

B

C

J BJ CJ B

11

A

B

C

K BKK

Except 011 ,111

2011-05-17 ASIC LAB 21

Ring CounterRing Counter

A circular sift register with only one flip flop being set at anyonly one flip-flop being set at any particular time. ; all others are cleared.

The single bit is shifted from one flip-flop to the other.

2011-05-17 ASIC LAB 22

Johnson CounterJohnson Counter

A circular shift register with thecomplement output of the lastcomplement output of the last flip-flop connected to the input of the first flip-flop.

2011-05-17 ASIC LAB 23