8051Micro-Controller

8051Micro-Controller

* To Understand the Architecture of the 8051

* On-Chip Peripherals of the 8051

* Memory Architecture

* Brief Introduction about I/O Ports

* Timers/Counters * Modes of Operation * Control Registers

OBJECTIVES

ControlUnit

ALU

CPU

Memory Unit

Input Unit

Output Unit

GENERIC MICROCOMPUTER ARCHITECTUREGENERIC MICROCOMPUTER ARCHITECTURE

Microcontroller

= Single Chip Microcomputer

=CPU+I/O+Memory

Unique Features of micro-controllers are:

* Internal RAM and ROM * I/O Ports with programmable pins

* Timers and counters * Serial data communication

COMPARISON BETWEEN MICRO COMPUTER AND 8051

Sl.No Generic 80511. Input unit P0 – P4, RxD, INT0,

INT1, RD,WR

2. Output unit P0 – P4, TxD, RD,WR

3. Memory unit ROM / EPROM,RAM

4. CPU ALU, SFRs, Timingand control blocks

4K ROM128 BYTES RAM

32 INPUT / OUTPUT PORT2 TIMER / COUNTER T0, T1

1 FULL DUPLEX SERIAL PORT

On –Chip Peripherals

* 8 bit registers A and B. * 16 bit program counter(PC) and data pointer.

* 8 bit program status word (PSW).

* 8 bit stack pointer(SP).

* Internal ROM or EPROM (4K).

* Internal RAM of 128 bytes:

- 4 register banks, each with 8 registers.- 16 bytes, addressed at bit level.- 80 bytes of general purpose data memory.

Specific features of 8051

* 32 input/output pins arranged as four 8 bit ports(P0-P3).

* Two 16 bit timers/counters (T0, T1).

* Full duplex serial data receiver/transmitter(SBUF)

* Control registers:TCON, TMOD, SCON, PCON, IP and IE.

* Two external and three internal interrupt sources.

* Oscillator and clock circuits.

ALU PSW

A B

PC DPTRDPHDPL

SFRRAM

ROM

Latch

Latch

Latch

Latch

Port 0

Port 1

Port 2

Port 3

I/OA0-A7

I/O

I/OA8-A15

I/OInterruptCounter

SerialData

8051 Block Diagram

RB 0

RB 1

RB 2

RB 3

Byte/Bitaddresses

TH1TL1TH0TL0

TMODTCONSCONSBUFPCON

IPIE

SFRs

Internal RAM Structure

8 bit address bus

16 bit address bus

Port 1 Bit 0 1 P1.0 Vcc 40 + 5v

Port 1 Bit 1 2 P1.1 (ADD)P0.0 39 Port 0 Bit 0 (Address/Data 0)

Port 1 Bit 2 3 P1.2 (ADI)P0.1 38 Port 0 Bit 1 (Address/Data 1)

Port 1 Bit 3 4 P1.3 (AD2)P0.2 37 Port 0 Bit 2 (Address/Data 2)

Port 1 Bit 4 5 P1.4 (AD3)P0.3 36 Port 0 Bit 3 (Address/Data 3)

Port 1 Bit 5 6 P1.5 (AD4)P0.4 35 Port 0 Bit 4 (Address/Data 4)

Port 1 Bit 6 7 P1.6 (AD5)P0.5 34 Port 0 Bit 5 (Address/Data 5)

Port 1 Bit 7 8 P1.7 (AD6)P0.6 33 Port 0 Bit 6 (Address/Data 6)

Reset Input 9 RST (AD7)P0.7 32 Port 0 Bit 7 (Address/Data 7)

Port 3 Bit 0 (Receive Data) 10 P3.0(RXD) (Vpp)/EA 31 External Enable

Port 3 Bit 1(XMIT Data) 11.P3.1 (TXD) (PROG)ALE 30 Address Latch Enable(EPROM Program Pulse)

Port 3 Bit 2(Interrupt 0) 12 P3.2(INTO) PSEN 29 Program Store Enable

Port 3 Bit 3(Interrupt 1) 13 P3.3(INT1) (A15)P2.7 28 Port 2 Bit 7 (Address 15)

Port 3 Bit 4(Timer 0 Input) 14 P3.4(TO) (A14)P2.6 27 Port 2 Bit 6 (Address 14)

Port 3 Bit 5(Timer 1 Input) 15 P3.5(T1) (A13)P2.5 26 Port 2 Bit 5 (Address 13)

Port 3 Bit 6(Write Strobe) 16 P3.6(WR) (A12)P2.4 25 Port 2 Bit 4 (Address 12)

Port 3 Bit 7 (Read Strobe) 17 P3.7(RD) (A11)P2.3 24 Port 2 Bit 3 (Address 11)

Crystal Input 2 16 XTAL2 (A10)P2.2 23 Port 2 Bit 2 (Address 10)

Crystal Input 1 19 XTAL1 (A9)P2.1 22 Port 2 Bit 1 (Address 9)

Ground 20 Vss (A8)P2.0 21 Port 2 Bit 0 (Address 8)

MEMORY: * Harvard architecture Internal RAM: * 128 bytes * 3 distinct areas: 1) 32 bytes,organized as 4 Register banks 2) 16 bytes of bit-addressable areas 3) 80 bytes of general-purpose RAM Internal ROM: * Code bytes occupies address space from 0000h to 0FFFh * (or)Code bytes fetched exclusively from 0000h to FFFFh * PC used to address from 0000h to FFFFh

60K BYTES EXTERNAL60K BYTES EXTERNAL

4K BYTES INTERNAL4K BYTES INTERNAL

64K BYTES EXTERNAL64K BYTES EXTERNAL=

PROGRAM MEMORY ORGANISATION

SFRs DIRECT ADDRESSING

ONLY

SFRs DIRECT ADDRESSING

ONLY

64K BYTES EXTERNAL64K BYTES EXTERNALAND

DIRECT AND INDIRECT

ADDDRESSING

DIRECT AND INDIRECT

ADDDRESSING

0000

7F7F

8080

FFFF

DATA MEMORY ORGANISATION

CY AC FO RS1 RS0 OV - P

7 6 5 4 3 2 1 0

RS1 RS0 0 0 Select register bank 0 0 1 Select register bank 1 1 0 Select register bank 2 1 1 Select register bank 3

Program Status Word (PSW)

Program counter: * 16-bit Register * Program instruction bytes are fetched from locations in memory addressed by the PC * No internal address

Data pointer: * Two 8 bit registers:DPH and DPL * Used for internal and external code access and data access * DPH and DPL are assigned an address

A and B registers: * 8-bit registers. * used for addition,subtraction,division

and multiplication. * used for data transfer. * B is used with A for multiplication

and division.

I/O PORTS: * 32 I/O Programmable Pins with alternate

functions * 4 ports P0,P1,P2,P3 1) Port-0: * Input/Output port * Supply low-order address and data bus for external memory 2) Port-1: * No dual functions 3) Port-2: * supply high-order byte for external memory 4) Port-3: * Alternate Functions are:

OSCfreq

F/12

TL15

BITS

TH18

BITS

TF1

T1 PIN

GATE

INT1PIN

C/T=1

C/T=0

TR1

CONTROL

INTERRUPT

TIMER MODE 0 BLOCK DIAGRAM

Timer Control Register(TCON):

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT07 6 5 4 3 2 1 0

Timer Mode Control Register:

Gate C/T M1 M0 Gate C/T M1 M0

[ Timer 1 ][ Timer 0 ]

* Not bit addressable* Select mode of operation M1 M0 Mode 0 0 0 0 1 1 1 0 2 1 1 3

7 6 5 4 3 2 1 0

OBJECTIVES

* SFRs available* Brief Introduction about SFRs* Counters and Timers * Timer Mode Of Operation * Control Register Available * Serial Data Input/Output * Modes of Transfer * Control Registers

SERIAL DATA I/O: * SBUF is used to hold data.Physically 2 registers: * write only * Read only * SCON controls data communication * RXD and TXD connect to serial data network * SM0,SM1 in SCON decides mode of operation

4-Types of transmission modes are: * Serial data Mode 0: Shift register mode * Serial data Mode 1: Standard UART * Serial data Mode 2: Multiprocessor mode * Serial data Mode 3

SCON Register:

SM0 SM1 SM2 REN TB8 RB8 TI RI

01234567

SM0 SM1 MODE 0 0 0 Shift register mode ; baud=f/12 0 1 1 8-bit UART mode ; baud=variable 1 0 2 9-bit UART mode ; baud=f/32 or f/64 1 1 3 9-bit UART mode ; baud=variable

OBJECTIVES

* Interrupt system

* Control registers available

* Addressing Modes

INTERRUPTS:

* Hardware signals to determine conditions that exist in internal and external circuits. * 5 interrupts - T0,T1,Serial interrupt(internal) Two external interrupts. * All interrupt functions are under control of program. * Programmer can alter control bits in IP,IE, TCON register.

Interrupt Enable Register(IE):

EA - ET2 ES ET1 EX1 ET0 EX0

7 6 5 4 3 2 1 0

Interrupt Priority Register(IP):

- - PT2 PS PT1 PX1 PT0 PX0

7 6 5 4 3 2 1 0

ADDRESSING MODES:

* Four addressing modes are: 1) Immediate addressing mode: * Value is stored in memory immediately following

op-code. * Ex: MOV A , #20h * Not flexible

2) Direct addressing mode: * Value to be stored in memory is retrieved from

another memory location. * Ex: MOV A , 30h. * Flexible

3) Indirect addressing mode: * Ex: MOV A,@R0 * Value from internal RAM which is found at address

indicated by R0 is loaded into accumulator.

4) External direct: * Used to access external memory * Only two commands are used : 1) MOVX A,@DPTR 2) MOVX @DPTR,A5) External indirect: * Used to access external memory * Ex: MOVX @R0,A

* Instruction Set Classification * Small Examples

OBJECTIVES

INSTRUCTION SET CLASSIFICATION:

1) Data Transfer Instructions 2) Logical Instructions

3) Arithmetic Instructions

4) Control Transfer Instructions