8086 Signal Description

7/31/2019 8086 Signal Description

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8086 Signal Description

Plastic Package

40 PinsSingle and Multi Processor Modes



Pin Diagram



• AD15-AD0:• Time Multiplexed Addr/Data Line

• T1- Address Cycle

•

T2, T3, TW, T4- Data Cycle• T are clock states of machine cycle

• A19/S6- A16/S3:• Time Muxed Address/Status Lines• During T1- Address line

• During I/O these lines are low.

• S5 -- status of IE Flag at beginning of

each cycle.• S4 , S3 indicate segment register used

for memory

• Latches separate addr and status bits

•

S6 is always low

S4

S3

Indication

0 0 Alternate Data

0 1 Stack

1 0 Code or None

1 1 Data



• /S7: BUS HIGH ENABLE• Indicates a transfer over D8-D15

• S7

is not currently used.

• : Read•

0 – Processor is performing Read• READY:

• Acknowledgement from slowdevices that they completed

transfer

BHE

A0 Indication

0 0 Whole Word

0 1 Upper byte

from/to odd addr

1 0 Lower bytefrom/to even add

1 1 None

BHE

RD



• INTR: Interrupt Request

• Level triggered input

•

Sampled during last clock cycle of each instruction to determine

availability of request.

• Internally Synchronized

• :• 0 – Execution continues

• 1 – Idle State

• Examined by WAIT instruction

• NMI:

• Non-maskable interrupt

• Causes type 2 interrupt

• Cannot be masked internally

TEST



• RESET:• Stops execution and starts from

FFFF0H

• Restarts when returns to low

• CLK: Clock Input• Provides timing for processor.

•

Square wave of 33% duty Cycle.• Range: 5Mhz- 10 Mhz

• VCC: +5V

• GND: Ground

• MN/MX:• 1-- Min Mode

• 0-- Max Mode



• M/IO:• Memory/I/O Operation

• 0 – I/O Operation

• 1 – Memory Operation

• Active from T4 to present T4

• INTA:•

Interrupt Acknowledge• 0 – Processor accepted interrupt.

• Low during T2,T2,TW of interruptacknowledge cycle.

•ALE: Address Latch Enable

• Indicates availability of validaddress on address/data line

• Connected to latch enable input

of Latches



• DT/R:

• Data Transmit or receive

•

1- Transmit• 0- Receive

• Same timing as M/IO

• DEN: Data Enable

• Availability of valid data over

address/data lines

•

Used to enable transreceivers toseparate data from multiplexed

address/data signal.

• Active from middle of T2 to

middle of T4.



• HOLD/HLDA

• Hold Acknowledge.

•

1 – Another master is requestingbus access

• After hold processer gives hold

acknowledge signal in middle of

next clock cycle after currentinstruction cycle.

• 0 – HDLA is also low



• S2,S1,S0:

• Status lines

•

Active from T4 to current T1,T2.

S2 S1 S0 Indication

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive



• LOCK:

• 0 – Other system bus masters will

be prevented from gaining

system bus.

• Activated by LOCK prefix

Instruction.

•QS1, QS0 – Queue Status

• Status of code-prefetch queue.

QS1 QS0 Indication

0 0 No Operation

0 1 First byte of opcode from the queue

1 0 Empty Queue

1 1 Subsequent byte from the queue



• RQ/GT0, RQ/GT1:

• Request/Grant

•

Used by other local bus mastersto force the processor to release

the local bus at end of

processor’s current bus cycle.

• RQ/GT0

have high priority than

RQ/GT1.

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8086 Signal Description