80x86 Processor Instruction Set (Intel 8086 – AMD Athlon)

Integer Instruction Opcode, Mnemonic, Operand, and Abbreviation Legend: n – This is a Number variable, which represents a range of the possible values for a particular instruction opcode or operand. i – The operand is an Immediate constant, which is provided as part of the instruction itself. Also, it can be an address label. c – A Code label, pointing to part of the program either jumped to or called. A “byte” is -128 to 127 bytes of the instruction,

a “word” is within the same code segment, and a “doubleword” (segment:offset) is within the 32-bit (4GB) address space. e – This prefix is used to specify word/doubleword register, that depends on the presence of the operand override prefix byte. cc – This represents a Conditional abbreviated mnemonic suffix defining which action is taken upon a true comparison result. r, reg – The operand is a general-purpose Register, which may be a high/low byte, a word, or doubleword operand data type. m , mem – A Memory variable or an indexed memory quantity; anything which is an Effective Address (except for a register). rm, reg/mem – An Effective Address operand (general-purpose register, a memory variable, or an indexed memory quantity). moffsb , moffsv – The operands are simple Memory variables (Offset) byte or word/doubleword relative to the segment base. dword , qword, dqword – These abbreviations specify operand size meaning Doubleword, Quadword, or Double-quadword. xb, xw, xd, xv, xq, xdq, xp – Define size Byte, Word, Dword, word/dword, Qword, packed DQword, or segment-offset Pair. sreg – This is one of the segment registers (CS, DS, SS, ES, FS, GS), which is used as an operand data type in an instruction. v&v – This is used in Bound instruction to specify a pair of signed word/dword integers, which are lower and upper bounds. SIMD – The abbreviation means Simultaneous Instruction Multiple Data, used by the MMX, XMM, and SSE(2) instructions. mm , m n – An MMX(0-7) 64-bit SIMD packed byte, word, doubleword, or quadword integer register. Also, used by SSE(2). xm , x n – One of XMM(0-7) 128-bit SIMD packed/scalar single-/double-precision floating-point, or packed integer registers. B – This abbreviation means Byte(s), that is used in the instruction description column to specify the size of the data operand. S – This means Signed, which is an operand format that uses the most significant binary digit to indicate positive or negative. P – This abbreviation means Packed, which describes the data operand storage format used in MMX and XMM instructions. O – The abbreviation stands for Overflow, in which the operation’s destination operand does not have enough bits of storage. OS – The abbreviation is for Operand-Size, which is a prefix override of the operand-size 16-/32-bits for the next instruction. TOS – This means the Top Of Stack, that is the lowest word/doubleword on the stack frame, pointed to by the (E)SP register. Quo , Rem – These abbreviations mean Quotient and Remainder; used in division and multiplication instruction descriptions. SP , DP; FP – The first two stand for Single-Precision and Double-Precision, which are descriptions used with Floating-Point. CR , DR, TR – The abbreviations mean Control Register, Debug Register, and Test Register; used with system instructions. GDTR , IDTR, LDTR – These mean Global/Interrupt/Local Descriptor Table Register, which is used in system instructions. CPL, RPL – These mean Current/Register Privilege Level, used by system instructions for segment protection mechanisms. TLB – Used by INVLPG, is Translation Lookaside Buffer, an internal cache storing most recently used page-directory/table. SMM – This abbreviation means System Management Mode, in which the context of current program is saved until resumed.

The Integer Instruction Set:In the CPU column, the instruction’s level of processor support is given. The numbers 1, 2, 3, 4, and 5 are for the 186, 286, 386, 486, and Pentium. “M” is for MMX instructions, “P2” for Pentium Pro/ Pentium II, “P3” for Pentium III, “P4” for Pentium IV, “3D” is for AMD 3DNow!, and “3E” for the DSP Extensions. The Athlon supports all Pentium III instructions except ones using SIMD registers.The instructions are listed by categories in alphabetical order in the divisions of: mnemonic, destination operand, and source operand.

Opcode Instruction CPU Description FLAGS/FP Exceptions

Lock and Repeat Prefixes:F0 LOCK Assert LOCK# signal for the following instruction noneF3 REP Repeat INSx, LODSx, MOVSx, OUTSx, STOSx CX times noneF3 REPE/REPZ Repeat CMPSx or SCASx CX times or until ZF = 0 noneF2 REPNE/REPNZ Repeat CMPSx or SCASx CX times or until ZF = 1 none

Segment Override Prefixes:2E CS Use Code Seg next mem reference or Jcc hint (branch untaken) none3E DS Use Data Seg next mem reference or Jcc hint (branch is taken) none26 ES Use ES data segment for following memory reference none64 FS 3 Use FS data segment for following memory reference none65 GS 3 Use GS data segment for following memory reference none36 SS Use Stack Segment for following memory reference none

Operand-Size Override Prefix:66 or null O2/O4 3 Use 16-/32-bit (2 or 4 byte) data Operand in next instruction none

Address-Size Override Prefix:67 or null A2/A4 3 Use 16-/32-bit (2 or 4 byte) Addressing in next instruction none

Data Transfer Instructions:0F C8+rd BSWAP rd 4 Byte Swap 1, 4 & 2, 3 of dword register to reverse byte order none98 CBW Convert Byte AL to Word AX (AH[15-0] ¬ bit 7) none99 CDQ 3 Convert Dword EAX, Qword EDX:EAX (EDX[31-0] ¬ bit 7) none0F 4n /r CMOVcc rv, rmv P2 Conditional Move (see Jcc, all conditions valid except xECXZ) none0F B0 /r CMPXCHG rmb, rb 4 If AL = rb, then AL ¬ rb, else AL ¬ rmb CF, PF, AF, ZF, SF, OF0F B1 /r CMPXCHG rmv, rv 4 If eAX = rv, then eAX ¬ rv, else eAX ¬ rmv CF, PF, AF, ZF, SF, OF0F C7 /1 mq CMPXCHG8B mq 5 If EDX:EAX = mq, mq ¬ ECX:EBX, else EDX:EAX ¬ mq CF, PF, AF, ZF, SF, OF99 CWD Convert Word AX to Dword DX:AX (DX[15-0] ¬ bit 7) none98 CWDE 3 Convert Word AX to Dword EAX with sign-Extension noneE4 ib IN AL, ib Input byte from immediate port ib (0-255) into AL noneEC IN AL, DX Input byte from port in DX (0-65,535) into AL noneE5 ib IN eAX, ib Input vword from immediate port ib (0-255) into eAX noneED IN eAX, DX Input vword from port in DX (0-65,535) into eAX noneA0 iv MOV AL, moffsb Move byte at moffsb (segment:offset) into AL noneA1 iv MOV eAX, moffsv Move vword at moffsv (segment:offset) into eAX noneA2 iv MOV moffsb, AL Move AL into byte at moffsb (segment:offset) noneA3 iv MOV moffsv, eAX Move eAX into vword at moffsv (segment:offset) noneB0+rb ib MOV rb, ib Move immediate byte into byte register none8A /r MOV rb, rmb Move reg/mem byte into byte register noneC6 /0 ib MOV rmb, ib Move immediate byte into reg/mem byte none88 /r MOV rmb, rb Move byte register into reg/mem byte noneC7 /0 iv MOV rmv, iv Move immediate vword into reg/mem vword none89 /r MOV rmv, rv Move vword register into reg/mem vword none8C /r MOV rmw, sreg Move segment reg into reg/mem word (OS prefix) noneB8+rv iv MOV rv, iv Move immediate vword into vword register none8B /r MOV rv, rmv Move reg/mem vword into vword register none8E /r MOV sreg, rmw Move reg/mem word to sreg, except CS (OS prefix) none0F BF /r MOVSX rd, rmw 3 Move reg/mem word to dword register and Sign-Extend none0F BE /r MOVSX rv, rmb 3 Move reg/mem byte to vword register and Sign-Extend none0F B7 /r MOVZX rd, rmw 3 Move word to dword with Zero-Extension none0F B6 /r MOVZX rv, rmb 3 Move byte to vword with Zero-Extension noneE6 ib OUT ib, AL Output byte AL to immediate port number ib (0-255) noneE7 ib OUT ib, eAX Output word eAX to immediate port number ib (0-255) noneEE OUT DX, AL Output byte AL to port in DX (0-65,535) noneEF OUT DX, eAX Output word eAX to port in DX (0-65,535) none1F POP DS Pop TOS to DS register, eSP ¬ (eSP + 2) none07 POP ES Pop TOS to ES register, eSP ¬ (eSP + 2) none0F A1 POP FS 3 Pop TOS to FS register, eSP ¬ (eSP + 2) none0F A9 POP GS 3 Pop TOS to GS register, eSP ¬ (eSP + 2) none8F /0 POP mv Pop TOS to mem vword, eSP ¬ (eSP + (2 or 4 (word/dword)) none58+rv POP rv Pop TOS to vword reg, eSP ¬ (eSP + (2 or 4 (word/dword)) none17 POP SS Pop TOS to SS register, eSP ¬ (eSP + 2) none61 POPA 1 Pop DI, SI, BP, BX, DX, CX, & AX (SP ignored) none61 POPAD 3 Pop EDI, ESI, EBP, EBX, EDX, ECX, & EAX (ESP ignored) none0E PUSH CS eSP ¬ (eSP - 2); Push CS register to TOS none1E PUSH DS eSP ¬ (eSP - 2); Push DS register to TOS none06 PUSH ES eSP ¬ (eSP - 2); Push ES register to TOS none0F A0 PUSH FS 3 eSP ¬ (eSP - 2); Push FS register to TOS none0F A8 PUSH GS 3 eSP ¬ (eSP - 2); Push GS register to TOS none6A ib PUSH ib 1 Push sign-extended immediate byte to TOS none68 iv PUSH iv 1 eSP ¬ (eSP + (2 or 4 (word/dword)); Push iv to TOS noneFF /6 PUSH mv eSP ¬ (eSP + (2 or 4 (word/dword)); Push mem vword to TOS none50+rv PUSH rv eSP ¬ (eSP + (2 or 4 (word/dword)); Push vword reg to TOS none16 PUSH SS eSP ¬ (eSP - 2); Push SS register to TOS none60 PUSHA 1 Push AX, CX, DX, BX, original SP, BP, SI, & DI none60 PUSHAD 3 Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, & EDI none0F C0 /r XADD rmb, rb 4 Exchange rmb & rb; load sum to rmb (LOCK prefix) CF, PF, AF, ZF, SF, OF0F C1 /r XADD rmv, rv 4 Exchange rmv & rv; load sum to rmv (LOCK prefix) CF, PF, AF, ZF, SF, OF90+rv XCHG eAX, rv Exchange vword register with eAX none86 /r XCHG rb, rmb Exchange reg/mem byte with byte register none86 /r XCHG rmb, rb Exchange byte register with reg/mem byte none

87 /r XCHG rmv, rv Exchange vword register with reg/mem vword none90+rv XCHG rv, eAX Exchange eAX with vword register none87 /r XCHG rv, rmv Exchange reg/mem vword with register vword none

Binary Arithmetic Instructions:14 ib ADC AL, ib Add with Carry immediate byte into AL CF, PF, AF, ZF, SF, OF15 iv ADC eAX, iv Add with Carry immediate vword into eAX CF, PF, AF, ZF, SF, OF12 /r ADC rb, rmb Add with Carry reg/mem byte into byte register CF, PF, AF, ZF, SF, OF80 /2 ib ADC rmb, ib Add with Carry immediate byte into reg/mem byte CF, PF, AF, ZF, SF, OF10 /r ADC rmb, rb Add with Carry byte register into reg/mem byte CF, PF, AF, ZF, SF, OF83 /2 ib ADC rmv, ib Add with CF sign-extend immediate byte into reg/mem vword CF, PF, AF, ZF, SF, OF81 /2 iv ADC rmv, iv Add with Carry immediate vword into reg/mem vword CF, PF, AF, ZF, SF, OF11 /r ADC rmv, rv Add with Carry vword register into reg/mem vword CF, PF, AF, ZF, SF, OF13 /r ADC rv, rmv Add with Carry reg/mem vword into vword register CF, PF, AF, ZF, SF, OF04 ib ADD AL, ib Add immediate byte into AL CF, PF, AF, ZF, SF, OF05 iv ADD eAX, iv Add immediate vword into eAX CF, PF, AF, ZF, SF, OF02 /r ADD rb, rmb Add reg/mem byte into byte register CF, PF, AF, ZF, SF, OF80 /0 ib ADD rmb, ib Add immediate byte into reg/mem byte CF, PF, AF, ZF, SF, OF00 /r ADD rmb, rb Add byte register into reg/mem byte CF, PF, AF, ZF, SF, OF83 /0 ib ADD rmv, ib Add immediate byte into reg/mem vword CF, PF, AF, ZF, SF, OF81 /0 iv ADD rmv, iv Add immediate vword into reg/mem vword CF, PF, AF, ZF, SF, OF01 /r ADD rmv, rv Add vword register into reg/mem vword CF, PF, AF, ZF, SF, OF03 /r ADD rv, rmv Add reg/mem vword into vword register CF, PF, AF, ZF, SF, OF3C ib CMP AL, ib Compare subtracting ib from AL, setting EFLAGS only CF, PF, AF, ZF, SF, OF3D iv CMP eAX, iv Compare subtracting iv from eAX, setting EFLAGS only CF, PF, AF, ZF, SF, OF3A /r CMP rb, rmb Compare subtracting rmb from rb, setting EFLAGS only CF, PF, AF, ZF, SF, OF80 /7 ib CMP rmb, ib Compare subtracting ib from rmb, setting EFLAGS only CF, PF, AF, ZF, SF, OF38 /r CMP rmb, rb Compare subtracting rb from rmb, setting EFLAGS only CF, PF, AF, ZF, SF, OF83 /7 ib CMP rmv, ib Compare subtracting ib from rmv, setting EFLAGS only CF, PF, AF, ZF, SF, OF81 /7 iv CMP rmv, iv Compare subtracting iv from rmv, setting EFLAGS only CF, PF, AF, ZF, SF, OF39 /r CMP rmv, rv Compare subtracting rv from rmv, setting EFLAGS only CF, PF, AF, ZF, SF, OF3B /r CMP rv, rmv Compare subtracting rmv from rv, setting EFLAGS only CF, PF, AF, ZF, SF, OFFE /1 DEC rmb Decrement reg/mem byte 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OFFF /1 DEC rmv Decrement reg/mem vword 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OF48+rv DEC rv Decrement vword register by 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OFF6 /6 DIV rmb Unsigned Divide AX by reg/mem byte (AL = Quo, AH = Rem) undefinedF7 /6 DIV rmv Unsigned Divide eDX:eAX, rmv (eAX = Quo, eDX = Rem) undefinedF6 /7 IDIV rmb Signed Divide AX by reg/mem byte (AL = Quo, AH = Rem) undefinedF7 /7 IDIV rmv Signed Divide eDX:eAX by rmv (eAX = Quo, eDX = Rem) undefinedF6 /5 IMUL rmb Signed Multiply (AX ¬ AL * reg/mem byte) CF, OFF7 /5 IMUL rmv Signed Multiply (eDX:eAX ¬ eAX * reg/mem vword) CF, OF6B /r ib IMUL rv, ib 1 Signed Multiply sign-extend immediate byte into vword reg CF, OF69 /r iv IMUL rv, iv 1 Signed Multiply immediate vword into vword register CF, OF0F AF /r IMUL rv, rmv 3 Signed Multiply reg/mem vword into vword register CF, OF6B /r ib IMUL rv, rmv, ib 1 Signed Multiply (rv ¬ reg/mem vword * sign-extended ib) CF, OF69 /r iv IMUL rv, rmv, iv 1 Signed Multiply (rv ¬ reg/mem vword * immediate vword) CF, OFFE /0 INC rmb Increment reg/mem byte 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OFFF /0 INC rmv Increment reg/mem vword 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OF40+rv INC rv Increment vword register 1 (CF unaffected, LOCK prefix) PF, AF, ZF, SF, OFF6 /4 MUL rmb Unsigned Multiply (AX ¬ AL * reg/mem byte) CF, OFF7 /4 MUL rmv Unsigned Multiply (eDX:eAX ¬ eAX * reg/mem vword) CF, OFF6 /3 NEG rmb Two’s complement Negate reg/mem byte (LOCK prefix) CF, PF, AF, ZF, SF, OFF7 /3 NEG rmv Two’s complement Negate reg/mem vword (LOCK prefix) CF, PF, AF, ZF, SF, OF1C ib SBB AL, ib Subtract with Borrow ib from/to AL (LOCK prefix) CF, PF, ZF, SF, OF1D iv SBB eAX, iv Subtract with Borrow iv from/to eAX (LOCK prefix) CF, PF, ZF, SF, OF1A /r SBB rb, rmb Subtract with Borrow rmb from/to rb (LOCK prefix) CF, PF, ZF, SF, OF80 /3 ib SBB rmb, ib Subtract with Borrow ib from/to rmb (LOCK prefix) CF, PF, ZF, SF, OF18 /r SBB rmb, rb Subtract with Borrow rb from/to rmb (LOCK prefix) CF, PF, ZF, SF, OF83 /3 ib SBB rmv, ib Subtract with Borrow ib from/to rmv (LOCK prefix) CF, PF, ZF, SF, OF81 /3 iv SBB rmv, iv Subtract with Borrow iv from/to rmv (LOCK prefix) CF, PF, ZF, SF, OF19 /r SBB rmv, rv Subtract with Borrow rv from/to rmv (LOCK prefix) CF, PF, ZF, SF, OF1B /r SBB rv, rmv Subtract with Borrow rmv from/to rv (LOCK prefix) CF, PF, ZF, SF, OF

2C ib SUB AL, ib Subtract immediate byte from/to AL (LOCK prefix) CF, PF, AF, ZF, SF, OF2D iv SUB eAX, iv Subtract immediate vword from/to eAX (LOCK prefix) CF, PF, AF, ZF, SF, OF2A /r SUB rb, rmb Subtract reg/mem byte from/to rb (LOCK prefix) CF, PF, AF, ZF, SF, OF80 /5 ib SUB rmb, ib Subtract immediate byte from/to rmb (LOCK prefix) CF, PF, AF, ZF, SF, OF28 /r SUB rmb, rb Subtract byte register from/to rmb (LOCK prefix) CF, PF, AF, ZF, SF, OF83 /5 ib SUB rmv, ib Subtract immediate byte from/to rmv (LOCK prefix) CF, PF, AF, ZF, SF, OF81 /5 iv SUB rmv, iv Subtract immediate vword from/to rmv (LOCK prefix) CF, PF, AF, ZF, SF, OF29 /r SUB rmv, rv Subtract vword register from/to rmv (LOCK prefix) CF, PF, AF, ZF, SF, OF2B /r SUB rv, rmv Subtract reg/mem vword from/to rv (LOCK prefix) CF, PF, AF, ZF, SF, OF

Decimal (base 10) Arithmetic Instructions:37 AAA ASCII Adjust sum of AL (carry into AH) after Addition CF, AFD5 0A AAD ASCII Adjust AX before Divide (AL¬AH * 10 + AL; AH¬0) PF, ZF, SFD4 0A AAM ASCII Adjust AX after Multiply (AH = Quo, AL = Rem) PF, ZF, SF3F AAS ASCII Adjust AL (borrows of AH, AH ¬ 0) after Subtraction CF, AF27 DAA Decimal Adjust AL after Addition CF, PF, AF, ZF, SF2F DAS Decimal Adjust AL after Subtraction CF, PF, AF, ZF, SF

Logic Instructions:24 ib AND AL, ib Bitwise logical AND immediate byte into AL (LOCK prefix) CF, PF, ZF, SF, OF25 iv AND eAX, iv Bitwise logical AND iv into eAX (LOCK prefix) CF, PF, ZF, SF, OF22 /r AND rb, rmb Bitwise logical AND rmb into byte register (LOCK prefix) CF, PF, ZF, SF, OF80 /4 ib AND rmb, ib Bitwise logical AND ib into reg/mem byte (LOCK prefix) CF, PF, ZF, SF, OF20 /r AND rmb, rb Bitwise logical AND byte register into rmb (LOCK prefix) CF, PF, ZF, SF, OF83 /4 ib AND rmv, ib Bitwise logical AND ib into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF81 /4 iv AND rmv, iv Bitwise logical AND iv into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF21 /r AND rmv, rv Bitwise logical AND vword register into rmv (LOCK prefix) CF, PF, ZF, SF, OF23 /r AND rv, rmv Bitwise logical AND rmv into vword register (LOCK prefix) CF, PF, ZF, SF, OFF6 /2 NOT rmb Bitwise logical NOT on reg/mem byte (LOCK prefix) noneF7 /2 NOT rmv Bitwise logical NOT on reg/mem vword (LOCK prefix) none0C ib OR AL, ib Bitwise logical OR immediate byte into AL (LOCK prefix) CF, PF, ZF, SF, OF0D iv OR eAX, iv Bitwise logical OR immediate vword into eAX (LOCK prefix) CF, PF, ZF, SF, OF0A /r OR rb, rmb Bitwise logical OR reg/mem byte into rb (LOCK prefix) CF, PF, ZF, SF, OF80 /1 ib OR rmb, ib Bitwise logical OR ib into reg/mem byte (LOCK prefix) CF, PF, ZF, SF, OF08 /r OR rmb, rb Bitwise logical OR rb into reg/mem byte (LOCK prefix) CF, PF, ZF, SF, OF83 /1 ib OR rmv, ib Bitwise logical OR ib into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF81 /1 iv OR rmv, iv Bitwise logical OR iv into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF09 /r OR rmv, rv Bitwise logical OR rv into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF0B /r OR rv, rmv Bitwise logical OR reg/mem vword into rv (LOCK prefix) CF, PF, ZF, SF, OF34 ib XOR AL, ib Bitwise logical XOR immediate byte into AL (LOCK prefix) CF, PF, ZF, SF, OF35 iv XOR eAX, iv Bitwise logical XOR iv into eAX (LOCK prefix) CF, PF, ZF, SF, OF32 /r XOR rb, rmb Bitwise logical XOR reg/mem byte into rb (LOCK prefix) CF, PF, ZF, SF, OF80 /6 ib XOR rmb, ib Bitwise logical XOR ib into reg/mem byte (LOCK prefix) CF, PF, ZF, SF, OF30 /r XOR rmb, rb Bitwise logical XOR rb into reg/mem byte (LOCK prefix) CF, PF, ZF, SF, OF83 /6 ib XOR rmv, ib Bitwise logical XOR ib into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF81 /6 iv XOR rmv, iv Bitwise logical XOR iv into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF31 /r XOR rmv, rv Bitwise logical XOR rv into reg/mem vword (LOCK prefix) CF, PF, ZF, SF, OF33 /r XOR rv, rmv Bitwise logical XOR reg/mem vword into rv (LOCK prefix) CF, PF, ZF, SF, OF

Shift and Rotate Instructions:D0 /2 RCL rmb, 1 Rotate 9 bits (CF, reg/mem byte) Left once CF, OFC0 /2 ib RCL rmb, ib 1 Rotate 9 bits (CF, reg/mem byte) Left ib times CF, OFD2 /2 RCL rmb, CL Rotate 9 bits (CF, reg/mem byte) Left CL times CF, OFD1 /2 RCL rmv, 1 Rotate 17/33 (word/dword) bits (CF, rmv) Left once CF, OFC1 /2 ib RCL rmv, ib 1 Rotate 17/33 (word/dword) bits (CF, rmv) Left ib times CF, OFD3 /2 RCL rmv, CL Rotate 17/33 (word/dword) bits (CF, rmv) Left CL times CF, OFD0 /3 RCR rmb, 1 Rotate 9 bits (CF, reg/mem byte) Right once CF, OFC0 /3 ib RCR rmb, ib 1 Rotate 9 bits (CF, reg/mem byte) Right ib times CF, OFD2 /3 RCR rmb, CL Rotate 9 bits (CF, reg/mem byte) Right CL times CF, OFD1 /3 RCR rmv, 1 Rotate 17/33 (word/dword) bits (CF, rmv) Right once CF, OFC1 /3 ib RCR rmv, ib 1 Rotate 17/33 (word/dword) bits (CF, rmv) Right ib times CF, OFD3 /3 RCR rmv, CL Rotate 17/33 (word/dword) bits (CF, rmv) Right CL times CF, OF

D0 /0 ROL rmb, 1 Rotate 8 bits reg/mem byte Left once CF, OFC0 /0 ib ROL rmb, ib 1 Rotate 8 bits reg/mem byte Left ib times CF, OFD2 /0 ROL rmb, CL Rotate 8 bits reg/mem byte Left CL times CF, OFD1 /0 ROL rmv, 1 Rotate 16/32 bits (word/dword) reg/mem vword Left once CF, OFC1 /0 ib ROL rmv, ib 1 Rotate 16/32 bits (word/dword) reg/mem vword Left ib times CF, OFD3 /0 ROL rmv, CL Rotate 16/32 bits (word/dword) reg/mem vword Left CL times CF, OFD0 /1 ROR rmb, 1 Rotate 8 bits reg/mem byte Right once CF, OFC0 /1 ib ROR rmb, ib 1 Rotate 8 bits reg/mem byte Right ib times CF, OFD2 /1 ROR rmb, CL Rotate 8 bits reg/mem byte Right CL times CF, OFD1 /1 ROR rmv, 1 Rotate 16/32 (word/dword) bits reg/mem vword Right once CF, OFC1 /1 ib ROR rmv, ib 1 Rotate 16/32 (word/dword) bits reg/mem vword Right ib times CF, OFD3 /1 ROR rmv, CL Rotate 16/32 (word/dword) bits reg/mem vword Right CL times CF, OFD0 /4 SAL rmb, 1 Multiply reg/mem byte by 2 once CF, PF, ZF, SF, OFC0 /4 ib SAL rmb, ib 1 Multiply reg/mem byte by 2 ib times CF, PF, ZF, SF, OFD2 /4 SAL rmb, CL Multiply reg/mem byte by 2 CL times CF, PF, ZF, SF, OFD1 /4 SAL rmv, 1 Multiply reg/mem vword by 2 once CF, PF, ZF, SF, OFC1 /4 ib SAL rmv, ib 1 Multiply reg/mem vword by 2 ib times CF, PF, ZF, SF, OFD3 /4 SAL rmv, CL Multiply reg/mem vword by 2 CL times CF, PF, ZF, SF, OFD0 /7 SAR rmb, 1 Signed divide reg/mem byte by 2 once (rounding to -¥) CF, PF, ZF, SF, OFC0 /7 ib SAR rmb, ib 1 Signed divide reg/mem byte by 2 ib times (rounding to -¥) CF, PF, ZF, SF, OFD2 /7 SAR rmb, CL Signed divide reg/mem byte by 2 CL times (rounding to -¥) CF, PF, ZF, SF, OFD1 /7 SAR rmv, 1 Signed divide reg/mem vword by 2 once (rounding to -¥) CF, PF, ZF, SF, OFC1 /7 ib SAR rmv, ib 1 Signed divide reg/mem vword by 2 ib times (rounding to -¥) CF, PF, ZF, SF, OFD3 /7 SAR rmv, CL Signed divide reg/mem vword by 2 CL times (rounding to -¥) CF, PF, ZF, SF, OFD0 /4 SHL rmb, 1 Multiply reg/mem byte by 2 once CF, PF, ZF, SF, OFC0 /4 ib SHL rmb, ib 1 Multiply reg/mem byte by 2 ib times CF, PF, ZF, SF, OFD2 /4 SHL rmb, CL Multiply reg/mem byte by 2 CL times CF, PF, ZF, SF, OFD1 /4 SHL rmv, 1 Multiply reg/mem vword by 2 once CF, PF, ZF, SF, OFC1 /4 ib SHL rmv, ib 1 Multiply reg/mem vword by 2 ib times CF, PF, ZF, SF, OFD3 /4 SHL rmv, CL Multiply reg/mem vword by 2 CL times CF, PF, ZF, SF, OF0F A4 /r ib SHLD rmv, rv, ib 3 Shift rmv to Left ib places while shifting rv bits in from right CF, PF, ZF, SF, OF0F A5 /r SHLD rmv, rv, CL 3 Shift rmv to Left CL places while shifting rv bits in from right CF, PF, ZF, SF, OFD0 /5 SHR rmb, 1 Unsigned divide reg/mem byte by 2 once CF, PF, ZF, SF, OFC0 /5 ib SHR rmb, ib 1 Unsigned divide reg/mem byte by 2 ib times CF, PF, ZF, SF, OFD2 /5 SHR rmb, CL Unsigned divide reg/mem byte by 2 CL times CF, PF, ZF, SF, OFD1 /5 SHR rmv, 1 Unsigned divide reg/mem vword by 2 once CF, PF, ZF, SF, OFC1 /5 ib SHR rmv, ib 1 Unsigned divide reg/mem vword by 2 ib times CF, PF, ZF, SF, OFD3 /5 SHR rmv, CL Unsigned divide reg/mem vword by 2 CL times CF, PF, ZF, SF, OF0F AC /r ib SHRD rmv, rv, ib 3 Shift rmv to Right ib places while shifting rv bits in from left CF, PF, ZF, SF, OF0F AD /r SHRD rmv, rv, CL 3 Shift rmv to Right CL places while shifting rv bits in from left CF, PF, ZF, SF, OF

Bit and Byte Instructions:0F BC /r BSF rv, rmv 3 Set rv to lowest set Bit (1 bit) in rmv (if rmv = 0, rv undefined) ZF0F BD /r BSR rv, rmv 3 Set rv to highest set Bit (1 bit) in rmv (if rmv = 0, rv undefined) ZF0F BA /4 ib BT rmv, ib 3 Set CF to Bit in rmv at immediate byte CF0F A3 /r BT rmv, rv 3 Set CF to Bit in rmv at vword register CF0F BA /7 ib BTC rmv, ib 3 Set CF to, then Complement Bit in rmv at ib (LOCK prefix) CF0F BB /r BTC rmv, rv 3 Set CF to, then Complement Bit in rmv at rv (LOCK prefix) CF0F BA /6 ib BTR rmv, ib 3 Set CF to, then Reset (set to 0) Bit in rmv at ib (LOCK prefix) CF0F B3 /r BTR rmv, rv 3 Set CF to, then Reset (set to 0) Bit in rmv at rv (LOCK prefix) CF0F BA /5 ib BTS rmv, ib 3 Set CF to, then Set (set to 1) Bit in rmv at ib (LOCK prefix) CF0F AB /r BTS rmv, rv 3 Set CF to, then Set (set to 1) Bit in rmv at rv (LOCK prefix) CF0F 97 SETA rmb 3 Set byte if Above unsigned integer (CF = 0 & ZF = 0) none0F 93 SETAE rmb 3 Set byte if Above or Equal to unsigned integer (CF = 0) none0F 92 SETB rmb 3 Set byte if Below unsigned integer (CF = 1) none0F 96 SETBE rmb 3 Set byte if Below or Equal to unS integer (CF = 1/ZF = 1) none0F 92 SETC rmb 3 Set byte if Carry (CF = 1) none0F 94 SETE rmb 3 Set byte if Equal (ZF = 1) none0F 9F SETG rmb 3 Set byte if Greater than signed integer (ZF = 0 & SF = OF) none0F 9D SETGE rmb 3 Set byte if Greater or Equal to signed integer (SF = OF) none0F 9C SETL rmb 3 Set byte if Less than signed integer (SF <> OF) none0F 9E SETLE rmb 3 Set byte if Less or Equal to signed integer (ZF = 1/SF <> OF) none

0F 96 SETNA rmb 3 Set byte if Not Above unsigned integer (CF = 1/ZF = 1) none0F 92 SETNAE rmb 3 Set byte if Not Above or Equal to unsigned integer (CF = 1) none0F 93 SETNB rmb 3 Set byte if Not Below unsigned integer (CF = 0) none0F 97 SETNBE rmb 3 Set byte if Not Below or Equal to unS int. (CF = 0 & ZF = 0) none0F 93 SETNC rmb 3 Set byte if Not Carry (CF = 0) none0F 95 SETNE rmb 3 Set byte if Not Equal (ZF = 0) none0F 9E SETNG rmb 3 Set byte if Not Greater than signed integer (ZF = 1/SF <> OF) none0F 9C SETNGE rmb 3 Set byte if Not Greater or Equal to signed integer (SF <> OF) none0F 9D SETNL rmb 3 Set byte if Not Less than signed integer (SF = OF) none0F 9F SETNLE rmb 3 Set byte if Not Less or Equal to S integer (ZF = 0 & SF = OF) none0F 91 SETNO rmb 3 Set byte if Not Overflow (OF = 0) none0F 9B SETNP rmb 3 Set byte if Not Parity (lowest byte 1 bits not even #, PF = 0) none0F 99 SETNS rmb 3 Set byte if Not Signed (positive integer, SF = 0) none0F 95 SETNZ rmb 3 Set byte if Not Zero (ZF = 0) none0F 90 SETO rmb 3 Set byte if Overflow (OF = 1) none0F 9A SETP rmb 3 Set byte if Parity (lowest byte 1 bits not even #, PF = 1) none0F 9A SETPE rmb 3 Set byte if Parity Even (lowest byte 1 bits not even #, PF = 1) none0F 9B SETPO rmb 3 Set byte if Parity Odd (lowest byte 1 bits not even #, PF = 0) none0F 98 SETS rmb 3 Set byte if Signed (negative integer, SF = 1) none0F 94 SETZ rmb 3 Set byte if Zero (ZF = 1) noneA8 ib TEST AL, ib Bitwise logical AND ib with AL, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OFA9 iv TEST eAX, iv Bitwise logical AND iv with eAX, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OFF6 /0 ib TEST rmb, ib Bitwise logical AND ib with rmb, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OF84 /r TEST rmb, rb Bitwise logical AND rb with rmb, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OFF7 /0 iv TEST rmv, iv Bitwise logical AND iv with rmv, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OF85 /r TEST rmv, rv Bitwise logical AND rv with rmv, set EFLAGS (CF, OF ← 0) CF, PF, ZF, SF, OF

Control Transfer Instructions:62 /r BOUND rv, mv&v 2 Check if rv is within Bounds of mv&v (if not, exception #BR) none9A cp CALL cp Push CS & EIP; Call far, absolute, 4-/6-byte address cp all or noneE8 cv CALL cv Push EIP; Call near offset cv (relative to next instruction) all or noneFF /3 CALL mp Push CS & EIP; Call far, absolute indirect, 4-/6-B address mp all or noneFF /2 CALL rmv Push CS & EIP; Call far, absolute indirect, address rmv all or noneC8 iw 00 ENTER iw, 0 1 Make procedural stack frame, iw bytes local storage, 0 levels noneC8 iw 01 ENTER iw, 1 1 Make procedural stack frame, iw bytes local storage, 1 level noneC8 iw ib ENTER iw, ib 1 Make procedural stack frame, iw bytes local storage, ib levels noneCC INT 3 Interrupt 3–trap to debugger (push EFLAGS, CS, EIP; far call) TF, IF, NT, RF, VM, ACCD ib INT ib Interrupt vector number ib (push EFLAGS, CS, EIP; far call) TF, IF, NT, RF, VM, ACCE INTO Interrupt 4–if OF is 1 (push EFLAGS, CS, & EIP; far call) TF, IF, NT, RF, VM, ACCF IRET Interrupt Return (pops EIP, CS, EFLAGS; may SS, data sregs) allCF IRETD 3 Interrupt Return (pops EIP, CS, EFLAGS; may SS, data sregs) all77 cb JA cb Jump short if Above unsigned integer (CF = 0 & ZF = 0) none0F 87 cv JA cv 3 Jump near if Above unsigned integer (CF = 0 & ZF = 0) none73 cb JAE cb Jump short if Above or Equal to unsigned integer (CF = 0) none0F 83 cv JAE cv 3 Jump near if Above or Equal to unsigned integer (CF = 0) none72 cb JB cb Jump short if Below unsigned integer (CF = 1) none0F 82 cv JB cv 3 Jump near if Below unsigned integer (CF = 1) none76 cb JBE cb Jump short if Below or Equal to unS integer (CF = 1/ZF = 1) none0F 86 cv JBE cv 3 Jump near if Below or Equal to unS integer (CF = 1/ZF = 1) none72 cb JC cb Jump short if Carry (CF = 1) none0F 82 cv JC cv 3 Jump near if Carry (CF = 1) noneE3 cb JCXZ cb Jump short if CX register is Zero none74 cb JE cb Jump short if Equal (ZF = 1) none0F 84 cv JE cv 3 Jump near if Equal (ZF = 1) noneE3 cb JECXZ cb 3 Jump short if ECX register is Zero none7F cb JG cb Jump short if Greater than signed integer (ZF = 0 & SF = OF) none0F 8F cv JG cv 3 Jump near if Greater than signed integer (ZF = 0 & SF = OF) none7D cb JGE cb Jump short if Greater than or Equal to signed integer (SF = OF) none0F 8D cv JGE cv 3 Jump near if Greater than or Equal to signed integer (SF = OF) none7C cb JL cb Jump short if Less than signed integer (SF <> OF) none0F 8C cv JL cv 3 Jump near if Less than signed integer (SF <> OF) none7E cb JLE cb Jump short if Less or Equal to S integer (ZF = 1/SF <> OF) none

0F 8E cv JLE cv 3 Jump near if Less or Equal to S integer (ZF = 1/SF <> OF) noneEB cb JMP cb Jump short signed byte (relative to next instruction) all or noneEA cp JMP cp Jump far, absolute, 4-/6-byte address cp all or noneE9 cv JMP cv Jump near, offset cv (relative to next instruction) all or noneFF /4 JMP rmv Jump near, absolute indirect, address reg/mem vword all or noneFF /5 JMP mp Jump far, absolute indirect, 4-/6-byte address mp all or none76 cb JNA cb Jump short if Not Above unsigned integer (CF = 1 & ZF = 1) none0F 86 cv JNA cv 3 Jump near if Not Above unsigned integer (CF = 1 & ZF = 1) none72 cb JNAE cb Jump short if Not Above or Equal to unsigned integer (CF = 1) none0F 82 cv JNAE cv 3 Jump near if Not Above or Equal to unsigned integer (CF = 1) none73 cb JNB cb Jump short if Not Below unsigned integer (CF = 0) none0F 83 cv JNB cv 3 Jump near if Not Below unsigned integer (CF = 0) none77 cb JNBE cb Jump short if Not Below or Equal to unS (CF = 0 or ZF = 0) none0F 87 cv JNBE cv 3 Jump near if Not Below or Equal to unS (CF = 0 or ZF = 0) none73 cb JNC cb Jump short if Not Carry (CF = 0) none0F 83 cv JNC cv 3 Jump near if Not Carry (CF = 0) none75 cb JNE cb Jump short if Not Equal (ZF = 0) none0F 85 cv JNE cv 3 Jump near if Not Equal (ZF = 0) none7E cb JNG cb Jump short if Not Greater than unsigned (ZF = 1 or SF <> OF) none0F 8E cv JNG cv 3 Jump near if Not Greater than unsigned (ZF = 1 or SF <> OF) none7C cb JNGE cb Jump short if Not Greater or Equal to unsigned (SF <> OF) none0F 8C cv JNGE cv 3 Jump near if Not Greater or Equal to unsigned (SF <> OF) none7D cb JNL cb Jump short if Not Less than unsigned integer (SF = OF) none0F 8D cv JNL cv 3 Jump near if Not Less than unsigned integer (SF = OF) none7F cb JNLE cb Jump short if Not Less or Equal to unS (ZF = 0 & SF = OF) none0F 8F cv JNLE cv 3 Jump near if Not Less or Equal to unS (ZF = 0 & SF = OF) none71 cb JNO cb Jump short if Not Overflow (OF = 0) none0F 81 cv JNO cv 3 Jump near if Not Overflow (OF = 0) none7B cb JNP cb Jump short if Not Parity (lowest byte 1 bits not even #, PF = 0) none0F 8B cv JNP cv 3 Jump near if Not Parity (lowest byte 1 bits not even #, PF = 0) none79 cb JNS cb Jump short if Not Signed (positive integer, SF = 0) none0F 89 cv JNS cv 3 Jump short if Not Signed (positive integer, SF = 0) none75 cb JNZ cb Jump short if Not Zero (ZF = 0) none0F 85 cv JNZ cv 3 Jump near if Not Zero (ZF = 0) none70 cb JO cb Jump short if Overflow (OF = 1) none0F 80 cv JO cv 3 Jump near if Overflow (OF = 1) none7A cb JP cb Jump short if Parity (lowest byte 1 bits are even #, PF = 1) none0F 8A cv JP cv 3 Jump near if Parity (lowest byte 1 bits are even #, PF = 1) none7A cb JPE cb Jump short if Parity Even (lowest byte 1 bits are even #, PF = 1) none0F 8A cv JPE cv 3 Jump near if Parity Even (lowest byte 1 bits are even #, PF = 1) none7B cb JPO cb Jump short if Parity Odd (lowest byte 1 bits not even #, PF = 0) none0F 8B cv JPO cv 3 Jump near if Parity Odd (lowest byte 1 bits not even #, PF = 0) none78 cb JS cb Jump short if Signed (negative integer, SF = 1) none0F 88 cv JS cv 3 Jump near if Signed (negative integer, SF = 1) none74 cb JZ cb Jump short if Zero (ZF = 1) none0F 84 cv JZ cv 3 Jump near if Zero (ZF = 1) noneC9 LEAVE 1 Set SP to BP, then pop BP (releases stack frame of ENTER) noneE2 cb LOOP cb DEC eCX; jump short if eCX ¹ 0 noneE1 cb LOOPE cb DEC eCX; jump short if eCX ¹ 0 & equal (ZF = 1) noneE0 cb LOOPNE cb DEC eCX; jump short if eCX ¹ 0 & ¹ (ZF = 0) noneE0 cb LOOPNZ cb DEC eCX; jump short if eCX ¹ 0 & not 0 (ZF = 0) noneE1 cb LOOPZ cb DEC eCX; jump short if eCX ¹ 0 & zero (ZF = 1) noneC3 RET Near Return to calling procedure (return address on TOS) noneCB RET Far Return to calling procedure (return address on TOS) noneC2 iw RET iw Near Return to calling procedure (TOS); pop iw B from stack noneCA iw RET iw Far Return to calling procedure (TOS); pop iw B from stack noneCB RETF Return Far to calling procedure (return address on TOS) noneCA iw RETF iw Return Far to calling procedure (TOS); pop iw B from stack noneC3 RETN Return Near to calling procedure (return address on TOS) noneC2 iw RETN iw Return Near to calling procedure (TOS); pop iw B from stack noneString Instructions (may use REPx prefix for block operations):A6 CMPS mb, mb Compare bytes DS:[eSI] to ES:[eDI]; advance eSI & eDI CF, PF, AF, ZF, SF, OF

A7 CMPS mv, mv Compare vwords DS:[eSI] to ES:[eDI]; advance eSI & eDI CF, PF, AF, ZF, SF, OFA6 CMPSB Compare Bytes DS:[eSI] to ES:[eDI]; advance eSI & eDI CF, PF, AF, ZF, SF, OFA7 CMPSD 3 Compare Dwords DS:[eSI] to ES:[eDI]; advance eSI & eDI CF, PF, AF, ZF, SF, OFA7 CMPSW Compare Words DS:[eSI] to ES:[eDI]; advance eSI & eDI CF, PF, AF, ZF, SF, OF6C INS rmb, DX 1 Input byte from port DX (0-65,535) to ES:[eDI]; advance eDI none6D INS rmv, DX 1 Input vword of port DX (0-65,535) to ES:[eDI]; advance eDI none6C INSB 1 Input Byte from port DX (0-65,535) to ES:[eDI]; advance eDI none6D INSD 3 Input Dword of port DX (0-65,535) to ES:[eDI]; advance eDI none6D INSW 1 Input Word of port DX (0-65,535) to ES:[eDI]; advance eDI noneAC LODS mb Load byte DS:[eSI] into AL; advance eSI noneAD LODS mv Load vword DS:[eSI] into eAX; advance eSI noneAC LODSB Load Byte DS:[eSI] into AL; advance eSI noneAD LODSD 3 Load Dword DS:[eSI] into EAX; advance eSI noneAD LODSW Load Word DS:[eSI] into AX; advance eSI noneA4 MOVS mb, mb Move byte DS:[eSI] to ES:[eDI]; advance eSI & eDI noneA5 MOVS mv, mv Move vword DS:[eSI] to ES:[eDI]; advance eSI & eDI noneA4 MOVSB Move Byte DS:[eSI] to ES:[eDI]; advance eSI & eDI noneA5 MOVSD 3 Move Dword DS:[eSI] to ES:[eDI]; advance eSI & eDI noneA5 MOVSW Move Word DS:[eSI] to ES:[eDI]; advance eSI & eDI none6E OUTS DX, rmb 1 Output byte DS:[eSI] to port in DX (0-65,535); advance eSI none6F OUTS DX, rmv 1 Output vword DS:[eSI] to port in DX (0-65,535); advance eSI none6E OUTSB 1 Output Byte DS:[eSI] to port in DX (0-65,535); advance eSI none6F OUTSD 3 Output Dword DS:[eSI] to port in DX (0-65,535); advance eSI none6F OUTSW 1 Output Word DS:[eSI] to port in DX (0-65,535); advance eSI noneAE SCAS mb Compare byte AL to ES:[eDI]; advance eDI; set EFLAGS CF, PF, AF, ZF, SF, OFAF SCAS mv Compare vword eAX to ES:[eDI]; advance eDI; set EFLAGS CF, PF, AF, ZF, SF, OFAE SCASB Compare Byte AL to ES:[eDI]; advance eDI; set EFLAGS CF, PF, AF, ZF, SF, OFAF SCASD 3 Compare Dword EAX to ES:[eDI]; advance eDI; set EFLAGS CF, PF, AF, ZF, SF, OFAF SCASW Compare Word AX to ES:[eDI]; advance eDI, set EFLAGS CF, PF, AF, ZF, SF, OFAA STOS mb Store byte AL to ES:[eDI]; advance eDI noneAB STOS mv Store vword eAX to ES:[eDI]; advance eDI noneAA STOSB Store Byte AL to ES:[eDI]; advance eDI noneAB STOSD 3 Store Dword EAX to ES:[eDI]; advance eDI noneAB STOSW Store Word AX to ES:[eDI]; advance eDI none

Flag Control Instructions:F8 CLC Clear Carry flag (CF ¬ 0) CFFC CLD Clear Direction flag (DF ¬ 0) so eSI and eDI auto-increment DFFA CLI Clear Interrupt enable flag (IF ¬ 0) (interrupts disabled) IFF5 CMC Complement Carry flag (CF) (set CF to opposite value) CF9F LAHF Load: AH ¬ EFLAGS (SF, ZF, 0, AF, 0, PF, 1, CF) none9D POPF Pop TOS into lower 16 bits of EFLAGS; increment eSP by 2 all but reserve & VM bits9D POPFD 3 Pop TOS into EFLAGS; increment eSP by 2 all but reserve & VM bits9C PUSHF Decrement eSP by 2; Push lower 16 bits of EFLAGS to TOS none9C PUSHFD 3 Decrement eSP by 4; Push EFLAGS to TOS none9E SAHF Store: SF, ZF, xx, AF, xx, PF, xx, & CF of AH ® EFLAGS CF, PF, AF, ZF, SFF9 STC Set Carry flag (CF ¬ 1) CFFD STD Set Direction flag (DF ¬ 1) so SI and DI auto-decrement DFFB STI Set Interrupt enable flag (IF ¬ 1) (interrupts enabled) IF

Segment Register Instructions:C5 /r LDS rv, mp Load far 32-/48-bit pointer from reg/mem to DS & vword reg noneC4 /r LES rv, mp Load far 32-/48-bit pointer from reg/mem to ES & vword reg none0F B4 /r LFS rv, mp 3 Load far 32-/48-bit pointer from reg/mem to FS & vword reg none0F B5 /r LGS rv, mp 3 Load far 32-/48-bit pointer from reg/mem to GS & vword reg none0F B2 /r LSS rv, mp 3 Load far 32-/48-bit pointer from reg/mem to SS & vword reg none

Miscellaneous Instructions:0F A2 CPUID 5 EAX value ® CPU Id & features to EAX, EBX, ECX, & EDX none

8D /r LEA rv, m Calculate & Load Effective Address for m into vword register none90 NOP No Operation (takes up space in execution, only affects EIP) none0F 0B UD2 Raise invalid opcode exception (#UD) noneD7 XLAT mb Set AL to memory byte DS:[eBX + unsigned AL] noneD7 XLATB Set AL to memory byte DS:[eBX + unsigned AL] none

MMX Data Transfer (Integer) Instructions:0F 6E /r MOVD mm, rmd M Move reg/mem Dword to mm; zero-extend (mm[63-32] ¬ 0) none0F 7E /r MOVD rmd, mm M Move low Dword of mm to reg/mem dword none0F 6F /r MOVQ mm, mm/mq M Move Qword from mm/mq to mm; if mq, mm[127-64] ¬ 0 none0F 7F /r MOVQ mm/mq, mm M Move Qword from mm to mm/mq none

MMX Conversion (Integer) Instructions:0F 6B /r PACKSSDW m1, m2/mq M Pack m1, 2 Dwords m2/mq to 4 Words m1 (Signed Saturation) none0F 63 /r PACKSSWB x1, x2/mdq M Pack 8 Words x1, x2/mdq to 16 Bytes x1 (Signed Saturation) none0F 67 /r PACKUSWB mm, mm/mq M Pack 4 Words mm, mm/m64 to 8 unsigned B mm (unS sat.) none0F 68 /r PUNPCKHBW mm, mm/mq M Unpack, interleave High Bytes mm, mm/mq into Words mm none0F 6A /r PUNPCKHDQ mm, mm/mq M Unpack, interleave High Dwords mm, mm/mq into Qwords mm none0F 69 /r PUNPCKHWD mm, mm/mq M Unpack, interleave High Words mm, mm/mq into Dwords mm none0F 60 /r PUNPCKLBW mm, mm/md M Unpack, interleave Low Bytes mm, mm/md into Words mm none0F 62 /r PUNPCKLDQ mm, mm/md M Unpack, interleave Low Dwords mm, mm/md into Qwords mm none0F 61 /r PUNPCKLWD mm, mm/md M Unpack, interleave Low Words mm, mm/md into Dwords mm none

MMX Packed Arithmetic (Integer) Instructions:0F FC /r PADDB mm, mm/mq M Packed Add Bytes mm/mq into mm; wrap-around overflow none0F FE /r PADDD mm, mm/mq M Packed Add Dwords mm/mq into mm; wrap-around overflow none0F EC /r PADDSB mm, mm/mq M Packed Add Bytes mm/mq into mm; wrap-around O (S sat.) none0F ED /r PADDSW mm, mm/mq M Packed Add Words mm/mq into mm; wrap-around O (S sat.) none0F DC /r PADDUSB mm, mm/mq M Packed Add Bytes mm/mq into mm; wrap-around O (UnS sat.) none0F DD /r PADDUSW mm, mm/mq M Packed Add Words mm/mq into mm; wrap-around O (UnS sat.) none0F FD /r PADDW mm, mm/mq M Packed Add Words mm/mq into mm; wrap-around overflow none0F F5 /r PMADDWD mm, mm/mq M Packed Multiply Words mm, mm/mq; Add adjacents into mm none0F E5 /r PMULHW m1, m2/mq M Packed Multiply S Words m1, m2/mq; High 16 bits into m1 none0F D5 /r PMULLW m1, m2/mq M Packed Multiply S Words m1, m2/mq; Low 16 bits into m1 none0F F8 /r PSUBB mm, mm/mq M Packed Subtract B mm/mq from/to mm, wrap-around overflow none0F FA /r PSUBD mm, mm/mq M Packed Subtract Dwords mm/mq from/to mm, wrap-around O none0F E8 /r PSUBSB mm, mm/mq M Packed Subtract Bytes mm/mq from/to mm (S saturate) none0F E9 /r PSUBSW mm, mm/mq M Packed Subtract Words mm/mq from/to mm (S saturate) none0F D8 /r PSUBUSB mm, mm/mq M Packed Subtract Bytes mm/mq from/to mm (UnS saturate) none0F D9 /r PSUBUSW mm, mm/mq M Packed Subtract Words mm/mq from/to mm (UnS saturate) none0F F9 /r PSUBW mm, mm/mq M Packed Subtract Words mm/mq from/to mm, wrap-around O none

MMX Comparison (Integer) Instructions:0F 74 /r PCMPEQB mm, mm/mq M Packed Compare Bytes mm/mq to mm; 1s mm if =, else 0s none0F 76 /r PCMPEQD mm, mm/mq M Packed Compare Dwords mm/mq to mm; 1s mm if =, else 0s none0F 75 /r PCMPEQW mm, mm/mq M Packed Compare Words mm/mq to mm; 1s mm if =, else 0s none0F 64 /r PCMPGTB mm, mm/mq M Packed Compare S B mm/mq to mm; 1s mm if >, else 0s none0F 66 /r PCMPGTD mm, mm/mq M Packed Compare S Dwords mm/mq to mm; 1s mm if >, else 0s none0F 65 /r PCMPGTW mm, mm/mq M Packed Compare S Words mm/mq to mm; 1s mm if >, else 0s none

MMX Logic (Integer) Instructions:0F DB /r PAND mm, mm/mq M Packed bitwise AND mm/mq into mm none0F DF /r PANDN mm, mm/mq M Packed bitwise AND NOT mm/mq into mm none0F EB /r POR mm, mm/mq M Packed bitwise OR mm/mq into mm none0F EF /r PXOR mm, mm/mq M Packed bitwise XOR mm/mq into mm none

MMX Shift and Rotate (Integer) Instructions:0F 72 /6 ib PSLLD mm, ib M Packed Shift Dwords mm Left by ib, shifting 0s in right none

0F F2 /r PSLLD mm, mm/mq M Packed Shift Dwords mm Left by mm/mq, shifting 0s in right none0F 73 /6 ib PSLLQ mm, ib M Packed Shift Qword mm Left by ib, shifting 0s in right none0F F3 /r PSLLQ mm, mm/mq M Packed Shift Qword mm Left by mm/mq, shifting 0s in right none0F 71 /6 ib PSLLW mm, ib M Packed Shift Words mm Left by ib, shifting 0s in right none0F F1 /r PSLLW mm, mm/mq M Packed Shift Words mm Left by mm/mq, shifting 0s in right none0F 72 /4 ib PSRAD mm, ib M Packed Shift Dwords mm Right by ib, shifting in sign bits none0F E2 /r PSRAD mm, mm/mq M Packed Shift Dwords mm Right by mm/mq, shifting in sign bits none0F 71 /4 ib PSRAW mm, ib M Packed Shift Words mm Right by ib, shifting in sign bits none0F E1 /r PSRAW mm, mm/mq M Packed Shift Words mm Right by mm/mq, shifting in sign bits none0F 72 /2 ib PSRLD mm, ib M Packed Shift Dwords mm Right by ib, shifting 0s in left none0F D2 /r PSRLD mm, mm/mq M Packed Shift Dwords mm Right by mm/mq, shifting 0s in left none0F 73 /2 ib PSRLQ mm, ib M Packed Shift Qword mm Right by ib, shifting 0s in left none0F D3 /r PSRLQ mm, mm/mq M Packed Shift Qword mm Right by mm/mq, shifting 0s in left none0F 71 /2 ib PSRLW mm, ib M Packed Shift Words mm Right by ib, shifting 0s in left none0F D1 /r PSRLW mm, mm/mq M Packed Shift Words mm Right by mm/mq, shifting 0s in left none

MMX State Management Instruction:0F 77 EMMS M Set x87 FPU tag word to Empty (clear the MMX State) none

SSE Data Transfer (SP Floating-Point) Instructions:0F 28 /r MOVAPS x1, x2/mdq P3 Move 4 P SP FPs from x2/mdq to x1 (16-B Aligned or #GP) none0F 29 /r MOVAPS x2/mdq, x1 P3 Move 4 P SP FPs from x1 to x2/mdq (16-B Aligned or #GP) none0F 12 /r MOVHLPS x1, x2 P3 Move 2 P SP FPs from High qword of x2 to Low qword of x1 none0F 17 /r MOVHPS mq, xm P3 Move 2 P SP FP from High qword of xm to mqword none0F 16 /r MOVHPS xm, mq P3 Move 2 P SP FP from mqword to High qword of xm none0F 16 /r MOVLHPS x1, x2 P3 Move 2 P SP FPs from Low qword of x2 to High qword of x1 none0F 13 /r MOVLPS mq, xm P3 Move 2 P SP FPs from Low qword of xm to mqword none0F 12 /r MOVLPS xm, mq P3 Move 2 P SP FPs from mqword to Low qword of xm none0F 50 /r MOVMSKPS rd, xm P3 Extract 4-bit sign Mask from xm and store in dword register noneF3 0F 10 /r MOVSS x1, x2/md P3 Move Scalar SP FP dword x2/md to x1; if md, x1[127-32] ¬ 0 noneF3 0F 11 /r MOVSS x2/md, x1 P3 Move Scalar SP FP dword value from x1 register to x2/md none0F 10 /r MOVUPS x1, x2/mdq P3 Move 4 P SP FPs from x2/mdq to x1 (may be Unaligned) none0F 11 /r MOVUPS x2/mdq, x1 P3 Move 4 P SP FPs from x1 to x2/mdq (may be Unaligned) none

SSE Packed Arithmetic (SP Floating-Point) Instructions:0F 58 /r ADDPS x1, x2/mdq P3 Add 4 Packed SP FPs from x2/mdq into x1 #I, #D, #O, #U, #PF3 0F 58 /r ADDSS x1, x2/md P3 Add low SP FPs from x2/md into x1; x1[127-32] not changed #I, #D, #O, #U, #P0F 5E /r DIVPS x1, x2/mdq P3 Divide 2 P SP FPs in x2/mdq into x1 (x1 = quotient) #I, #D, #Z, #O, #U, #PF3 0F 5E /r DIVSS x1, x2/md P3 Divide low SP FP in x2/md into x1 (x1 = quotient) #I, #Z, #D, #O, #U, #P0F 5F /r MAXPS x1, x2/mdq P3 Return Maximum SP FPs between x2/mdq and/to x1 #I (with QNaN source), #DF3 0F 5F /r MAXSS x1, x2/md P3 Return Maximum Scalar SP FP between x2/md and/to x1 #I (with QNaN source), #D0F 5D /r MINPS x1, x2/mdq P3 Return Minimum SP FPs between x2/mdq and/to x1 #I (with QNaN source), #DF3 0F 5D /r MINSS x1, x2/md P3 Return Minimum Scalar SP FP between x2/md and/to x1 #I (with QNaN source), #D0F 59 /r MULPS x1, x2/mdq P3 Multiply Packed SP FPs in x2/mdq into x1 #I, #D, #O, #U, #PF3 0F 59 /r MULSS x1, x2/md P3 Multiply low SP FP in x2/md into x1 #I, #D, #O, #U, #P0F 53 /r RCPPS x1, x2/mdq P3 Set 4 approximate Reciprocals of P SP FPs x2/mdq to x1 noneF3 0F 53 /r RCPSS x1, x2/md P3 Set approximate Reciprocal low Scalar SP FP x2/md to x1 none0F 52 /r RSQRTPS x1, x2/mdq P3 Set 4 approx. Reciprocal Square Roots P SP FP x2/mdq to x1 noneF3 0F 52 /r RSQRTSS x1, x2/md P3 Set approx. Reciprocal Square Root low SP FP x2/md to x1 none0F 51 /r SQRTPS x1, x2/mdq P3 Set 4 Square Roots of P SP FPs x2/mdq to x1 #I, #D, #PF3 0F 51 /r SQRTSS x1, x2/md P3 Set Square Root of low SP FP x2/md to x1 #I, #D, #P0F 5C /r SUBPS x1, x2/mdq P3 Subtract 4 P SP FPs in x2/mdq from/to x1 #I, #D, #O, #U, #PF3 0F 5C /r SUBSS x1, x2/md P3 Subtract low SP FP in x2/md from/to x1 #I, #D, #O, #U, #P

SSE Comparison (SP Floating-Point) Instructions:0F C2 /r 00 CMPEQPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if =, else 0s #I (if SNaN), #DF3 0F C2 /r 00 CMPEQSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if =, else 0s #I (if SNaN/QNaN), #D0F C2 /r 02 CMPLEPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if £, else 0s #I (if SNaN), #DF3 0F C2 /r 02 CMPLESS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if £, else 0s #I (if SNaN/QNaN), #D0F C2 /r 01 CMPLTPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if <, else 0s #I (if SNaN), #DF3 0F C2 /r 01 CMPLTSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if <, else 0s #I (if SNaN/QNaN), #D0F C2 /r 04 CMPNEQPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if ¹, else 0s #I (if SNaN), #D

F3 0F C2 /r 04 CMPNEQSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if ¹, else 0s #I (if SNaN/QNaN), #D0F C2 /r 06 CMPNLEPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if not £, else 0s #I (if SNaN), #DF3 0F C2 /r 06 CMPNLESS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if not £, else 0s #I (if SNaN/QNaN), #D0F C2 /r 05 CMPNLTPS x1, x2/mdq P3 Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 if not <, else 0s #I (if SNaN), #DF3 0F C2 /r 05 CMPNLTSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if not <, else 0s #I (if SNaN/QNaN), #D0F C2 /r 07 CMPORDPS x1, x2/mdq P3 Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 Ordered, else 0s #I (if SNaN), #DF3 0F C2 /r 07 CMPORDSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 if Ordered, else 0s #I (if SNaN/QNaN), #D0F C2 /r 03 CMPUNORDPS x1, x2/mdq P3 Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 Unorder, else 0s #I (if SNaN), #DF3 0F C2 /r 03 CMPUNORDSS x1, x2/md P3 Compare low SP FP x2/md, x1; dword 1s x1 Unordered, else 0s #I (if SNaN/QNaN), #D0F 2F /r COMISS x1, x2/md P3 Ordered Compare low SP FP x2/md & x1; set EFLAGS #I (if SNaN/QNaN), #D0F 2E /r UCOMISS x1, x2/md P3 Unordered Compare low SP FP x2/md & x1; set EFLAGS #I (if SNaN), #D

SSE Logical (SP Floating-Point) Instructions:0F 55 /r ANDNPS x1, x2/mdq P3 Bitwise logical AND NOT 4 P SP FPs in x2/mdq into x1 none0F 54 /r ANDPS x1, x2/mdq P3 Bitwise logical AND 4 P SP FPs in x2/mdq into x1 none0F 56 /r ORPS x1, x2/mdq P3 Bitwise logical OR 4 P SP FPs in x2/mdq into x1 none0F 57 /r XORPS x1, x2/mdq P3 Bitwise logical XOR 4 P SP FPs x2/mdq into x1 none

SSE Shuffle and Unpack (SP Floating-Point) Instructions:0F C6 /r ib SHUFPS x1, x2/mdq, ib P3 Shuffle P SP FP x2/mdq to low or high of x1, selected by ib none0F 15 /r UNPCKHPS x1, x2/mdq P3 Unpack & interleave SP FPs of High qwords x2/mdq and/to x1 none0F 14 /r UNPCKLPS x1, x2/mdq P3 Unpack & interleave SP FPs of Low qwords x2/mdq and/to x1 none

SSE Conversion (SP Floating-Point) Instructions:0F 2A /r CVTPI2PS xm, mm/mq P3 Convert 2 P signed dwords from mm/mq to 2 P SP FPs in xm #P0F 2D /r CVTPS2PI mm, xm/mq P3 Convert 2 P SP FPs from xm/mq to 2 P signed dwords in mm #I, #PF3 0F 2A /r CVTSI2SS xm, rmd P3 Convert signed dword from rmw to SP FP in xm #PF3 0F 2D /r CVTSS2SI rd, xm/md P3 Convert SP FP xm/md to rounded signed dword in rd #I, #P0F 2C /r CVTTPS2PI mm, xm/mq P3 Convert 2 P SP FPs xm/mq to 2 P S Truncated dwords in mm #I, #PF3 0F 2C /r CVTTSS2SI rd, xm/md P3 Convert SP FP from xm/md to S Truncated dword in rd #I, #P

MXCSR (SSE(2) SIMD FP Control/Status Register) State Management Instructions:0F AE /2 LDMXCSR md P3 Load md into SIMD Control/Status Register (MXCSR) none0F AE /3 STMXCSR md P3 Store SIMD Control/Status Register (MXCSR) to md none

SSE 64-Bit SIMD Integer Instructions:0F E0 /r PAVGB m1, m2/mq P3 Packed Average unS B m2/mq and/to m1 with rounding none0F E3 /r PAVGW m1, m2/mq P3 Packed Average unS Words m2/mq and/to m1 with rounding none0F C5 /r ib PEXTRW rd, mm, ib P3 Packed Extract Word number ib from mm and move to rd none0F C4 /r ib PINSRW mm, rd/mw, ib P3 Packed Insert low Word of rd/mw into word number ib of mm none0F EE /r PMAXSW m1, m2/mq P3 Return Packed Maximum of Signed Words in m2/mq and/to m1 none0F DE /r PMAXUB m1, m2/mq P3 Return Packed Maximum of Unsigned B in m2/mq and/to m1 none0F EA /r PMINSW m1, m2/mq P3 Return Packed Minimum of Signed Words in m2/mq and/to m1 none0F DA /r PMINUB m1, m2/mq P3 Return Packed Minimum Unsigned B in m2/mq and/to m1 none0F D7 /r PMOVMSKB rd, mm P3 Set dword register to most significant bits of bytes in mm none0F E4 /r PMULHUW m1, m2/mq P3 Packed unS Multiply words m2/mq, m1;High 16-bit result®m1 none0F F6 /r PSADBW m1, m2/mq P3 Word sum of P unS B absolute differences of x2/mq and/to m1 none0F 70 /r ib PSHUFW m1, m2/mq, ib P3 Packed Shuffle Words m2/mq to m1, using 2-bit encoding ib none

SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions:0F F7 /r MASKMOVQ m1, m2 P3 Non-temporal Move m2 Masked B of m1 to [eDI]; MMX state none0F 2B /r MOVNTPS mdq, xm P3 Non-temporal SP FP Move from xm to 16-B aligned mdqword none0F E7 /r MOVNTQ mq, mx P3 Non-temporal Qword Move from mx to 16-B aligned mqword none0F 18 /1 PREFETCH0 mb P3 Prefetch memory mb into all cache levels none0F 18 /2 PREFETCH1 mb P3 Prefetch memory mb into all cache levels, except level 0 none0F 18 /3 PREFETCH2 mb P3 Prefetch memory mb into all cache levels, except levels 0 & 1 none0F 18 /0 PREFETCHNTA mb P3 Non-temporal prefetch memory mb into all cache levels none0F AE FF SFENCE P3 Serializes so that previous stores are visible before next stores none

SSE2 Data Movement (DP Floating-Point) Instructions:66 0F 28 /r MOVAPD x1, x2/mdq P4 Move 2 P DP FPs from x2/mdq to x1 (16-B Aligned or #GP) none

66 0F 29 /r MOVAPD x2/mdq, x1 P4 Move 2 P DP FPs from x1 to x2/mdq (16-B Aligned or #GP) none66 0F 17 /r MOVHPD mq, xm P4 Move DP FP from High qword of xm to mqword none66 0F 16 /r MOVHPD xm, mq P4 Move DP FP from mqword to High qword of xm none66 0F 13 /r MOVLPD mq, xm P4 Move DP FP from Low qword of xm to mqword none66 0F 12 /r MOVLPD xm, mq P4 Move DP FP from mqword to Low qword of xm none66 0F 50 /r MOVMSKPD rd, xm P4 Extract 2-bit sign Mask from xm and store in dword register noneF2 0F 10 /r MOVSD x1, x2/mq P4 Move Scalar DP FP dword x2/md to x1; if md, x1[127-32] ¬ 0 noneF2 0F 11 /r MOVSD x2/mq, x1 P4 Move Scalar DP FP dword value from x1 register to x2/md none66 0F 10 /r MOVUPD x1, x2/mdq P4 Move 2 P DP FPs from x2/mdq to x1 (may be Unaligned) none66 0F 11 /r MOVUPD x2/mdq, x1 P4 Move 2 P DP FPs from x1 to x2/mdq (may be Unaligned) none

SSE2 Packed Arithmetic (DP Floating-Point) Instructions:66 0F 58 /r ADDPD x1, x2/mdq P4 Add 2 Packed DP FPs from x2/mdq into x1 #I, #D, #O, #U, #PF2 0F 58 /r ADDSD x1, x2/mq P4 Add low DP FPs from x2/mq into x1; x1[127-32] not changed #I, #D, #O, #U, #P66 0F 5E /r DIVPD x1, x2/mdq P4 Divide 2 P DP FPs in x2/mdq into x1 (x1 = quotient) #I, #Z, #D, #O, #U, #PF2 0F 5E /r DIVSD x1, x2/mq P4 Divide low DP FP in x2/mq into x1 (x1 = quotient) #I, #Z, #D, #O, #U, #P66 0F 5F /r MAXPD x1, x2/mdq P4 Return Maximum DP FPs between x2/mdq and/to x1 #I (with QNaN source), #DF2 0F 5F /r MAXSD x1, x2/mq P4 Return Maximum Scalar DP FP between x2/mq and/to x1 #I (with QNaN source), #D66 0F 5D /r MINPD x1, x2/mdq P4 Return Minimum DP FPs between x2/mdq and/to x1 #I (with QNaN source), #DF2 0F 5D /r MINSD x1, x2/mq P4 Return Minimum Scalar DP FP between x2/mq and/to x1 #I (with QNaN source), #D66 0F 59 /r MULPD x1, x2/mdq P4 Multiply Packed DP FPs in x2/mdq into x1 #I, #D, #O, #U, #PF2 0F 59 /r MULSD x1, x2/mq P4 Multiply low DP FP in x2/mq into x1 #I, #D, #O, #U, #P66 0F 51 /r SQRTPD x1, x2/mdq P4 Set Square Roots of 2 P DP FPs in x2/mdq to x1 #I, #D, #O, #U, #PF2 0F 51 /r SQRTSD x1, x2/mq P4 Set Square Root of low DP FP in x2/mdq to x1 #I, #D, #P66 0F 5C /r SUBPD x1, x2/mdq P4 Subtract 2 P DP FPs in x2/mdq from/to x1 #I, #D, #O, #U, #PF2 0F 5C /r SUBSD x1, x2/mq P4 Subtract low DP FP in x2/mq from/to x1 #I, #D, #O, #U, #P

SSE2 Logical (DP Floating-Point) Instructions:66 0F 55 /r ANDNPD x1, x2/mdq P4 Bitwise logical AND NOT 2 P DP FPs in x2/mdq into x1 none66 0F 54 /r ANDPD x1, x2/mdq P4 Bitwise logical AND 2 P DP FPs in x2/mdq into x1 none66 0F 56 /r ORPD x1, x2/mdq P4 Bitwise logical OR 2 P DP FPs in x2/mdq into x1 none66 0F 57 /r XORPD x1, x2/mdq P4 Bitwise logical XOR 2 P DP FPs x2/mdq into x1 none

SSE2 Compare (DP Floating-Point) Instructions:66 0F C2 /r 00 CMPEQPD x1, x2/mdq P4 Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if =, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 02 CMPLEPD x1, x2/mdq P4 Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if £, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 01 CMPLTPD x1, x2/mdq P4 Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if <, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 04 CMPNEQPD x1, x2/mdq P4 Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if ¹, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 06 CMPNLEPD x1, x2/mdq P4 Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 if not £, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 05 CMPNLTPD x1, x2/mdq P4 Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 if not <, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 07 CMPORDPD x1, x2/mdq P4 Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 Ordered, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 03 CMPUNORDPD x1, x2/mdq P4 Compare low DP FP x2/mdq, x1; dword 1s x1 Unord., else 0s #I (if SNaN/QNaN), #DF2 0F C2 /r 00 CMPEQSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if =, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 02 CMPLESD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if £, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 01 CMPLTSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if <, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 04 CMPNEQSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if ¹, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 06 CMPNLESD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if not £, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 05 CMPNLTSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if not <, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 07 CMPORDSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 if Ordered, else 0s #I (if SNaN/QNaN), #D66 0F C2 /r 03 CMPUNORDSD x1, x2/mq P4 Compare low DP FP x2/mq, x1; dword 1s x1 Unordered, else 0s #I (if SNaN/QNaN), #D66 0F 2F /r COMISD x1, x2/mq P4 Ordered compare low DP FP x2/mq & x1; set EFLAGS #I (if SNaN/QNaN), #D66 0F 2E /r UCOMISD x1, x2/mq P4 Unordered compare low DP FP x2/mq & x1; set EFLAGS #I (if SNaN), #D

SSE2 Shuffle and Unpack (DP Floating-Point) Instructions:66 0F C6 /r ib SHUFPD x1, x2/mdq, ib P4 Shuffle P DP FP x2/mdq to low or high of x1, selected by ib none66 0F 15 /r UNPCKHPD x1, x2/mdq P4 Unpack & interleave DP FPs of High qwords x2/mdq and/to x1 none66 0F 14 /r UNPCKLPD x1, x2/mdq P4 Unpack & interleave DP FPs of Low qwords x2/mdq and/to x1 none

SSE2 Conversion (DP Floating-Point) Instructions:F3 0F E6 CVTDQ2PD x1, x2/mq P4 Convert 2 P signed Dwords from x2/mq to 2 P DP FPs in x1 none

F2 0F E6 CVTPD2DQ x1, x2/mdq P4 Convert 2 P DP FPs from x2/mdq to 2 P signed Dwords in x1 #I, #P66 0F 2D /r CVTPD2PI mm, xm/mdq P4 Convert 2 P DP FPs from xm/mdq to 2 P S Dwords in mm #I, #P66 0F 5A /r CVTPD2PS x1, x2/mdq P4 Convert 2 P DP FPs form x2/mdq to 2 Packed SP FPs in x1 #I, #D, #O, #U, #P66 0F 2A /r CVTPI2PD xm, mm/mq P4 Convert 2 P S dwords from mm/mq to 2 P DP FPs in xm none0F 5A /r CVTPS2PD x1, x2/mq P4 Convert 2 P SP FPs from x2/mq to 2 P DP FPs in x1 #I, #DF2 0F 2D /r CVTSD2SI rd, xm/mq P4 Convert DP FP from xm/mq to S dword in rd #I, #PF2 0F 5A /r CVTSD2SS x1, x2/mq P4 Convert DP FP from x2/mq to SP FP in x1 #I, #D, #O, #U, #PF2 0F 2A /r CVTSI2SD xm, rmd P4 Convert Signed dword from reg/mem dword to DP FP in xm noneF3 0F 5A /r CVTSS2SD x1, x2/md P4 Convert SP FP from x2/md to DP FP in x1 #I, #D66 0F E6 CVTTPD2DQ x1, x2/mdq P4 Convert 2 P DP FPs x2/mdq to 2 P S Truncated dwords in x1 #I, #P66 0F 2C /r CVTTPD2PI mm, xm/mdq P4 Convert 2 P DP FPs xm/mdq to 2 P S Truncated dwords in mm #I, #PF2 0F 2C /r CVTTSD2SI rd, xm/mq P4 Convert DP FP form xm/mq to Signed Truncated dword in rd #I, #P

SSE2 Packed Single-Precision Floating-Point Instructions:0F 5B /r CVTDQ2PS x1, x2/mdq P4 Convert 4 P S dwords from x2/mdq to 4 SP FPs in x1 #P66 0F 5B /r CVTPS2DQ x1, x2/mdq P4 Convert 4 P SP FPs from x2/mdq to 4 P S dwords in x1 #I, #PF3 0F 5B /r CVTTPS2DQ x1, x2/mdq P4 Convert 4 SP FPs from x2/mdq to 4 S Truncated dwords in x1 #I, #P

SSE2 128-Bit SIMD Integer Instructions:66 0F 6F /r MOVDQA x1, x2/mdq P4 Move Aligned Dqword x2/mdq to x1 (16-B aligned or #GP) none66 0F 7F /r MOVDQA x2/mdq, x1 P4 Move Aligned Dqword x1 to x2/mdq (16-B aligned or #GP) noneF3 0F 6F /r MOVDQU x1, x2/mdq P4 Move Unaligned Dqword x2/mdq to x1 noneF3 0F 7F /r MOVDQU x2/mdq, x1 P4 Move Unaligned Dqword x1 to x2/mdq noneF2 0F D6 MOVDQ2Q mm, xm P4 Move low Qword from xm to mm register noneF3 0F D6 MOVQ2DQ xm, mm P4 Move Qword from mm register to low qword of xm register none0F D4 /r PADDQ m1, m2/mq P4 Add Qword m2/mq into m1 (EFLAGS unaffected) none66 0F D4 /r PADDQ x1, x2/mdq P4 Packed Add Qwords m2/mdq into x1 (EFLAGS unaffected) none0F F4 /r PMULUDQ m1, m2/mq P4 Multiply Unsigned Dwords m1 and/to m2/mq none66 0F F4 /r PMULUDQ x1, x2/mdq P4 Packed Multiply Unsigned Dwords x1 and/to x2/mdq none66 0F 70 /r ib PSHUFD x1, x2/mdq P4 Shuffle Dwords in x2/mdq to x1 in order selected by ib noneF3 0F 70 /r ib PSHUFHW x1, x2/mdq, ib P4 Shuffle High Words in x2/mdq to x1 in order selected by ib noneF2 0F 70 /r ib PSHUFLW x1, x2/mdq, ib P4 Shuffle Low Words in x2/mdq to x1 in order selected by ib none66 0F 73 /7 ib PSLLDQ x1, ib P4 Shift x1 Left by ib bytes while shifting 0s in right none66 0F 73 /3 ib PSRLDQ x1, ib P4 Shift x1 Right by ib bytes while shifting 0s in left none0F FB /r PSUBQ m1, m2/mq P4 Subtract Qword m2/mq from/to m1 none66 0F FB /r PSUBQ x1, x2/mdq P4 Packed Subtract Qwords x2/mdq from/to x1 none66 0F 6A /r PUNPCKHQDQ x1, x2/mdq P4 Unpack & Interleave High Qwords from x2/mdq and/to x1 none66 0F 6C /r PUNPCKLQDQ x1, x2/mdq P4 Unpack & Interleave Low Qwords from x2/mdq and/to x1 none

SSE2 Cacheability Control and Instruction Ordering Instructions:0F AE /7 CLFLUSH mb P4 Flushes Cache Line containing mb none0F AE /5 LFENCE P4 Serializes load-from-memory instruction operations none0F F7 /r MASKMOVDQU m1, m2 P4 Selectively write B from m1 to memory using m2 B Mask none0F AE /6 MFENCE P4 Serialize load-from-memory & store-from-memory operations none66 0F E7 /r MOVNTDQ mdq, xm P4 Non-temporal Move Dqword from xm to mdq none0F C3 /r MOVNTI md, rd P4 Non-temporal Move dword from rd to md none66 0F 2B /r MOVNTPD mdq, xm P4 Non-temporal Move P DP FPs from xm to mdq noneF3 90 PAUSE P4 Processor hint & delay to improve spin-wait loop performance none

System Instructions (* - Protected Mode; @ - CPL 3 Application, else need CPL 0):63 /rw *@ ARPL rmw, rw 2 Adjust RPL of reg/mem word to not less than RPL of rw ZF0F 06 CLTS 2 Clear Task Switched flag (TS) in CR0 TSF4 HLT Halt (start: interrupts, debug except., BINIT#, INIT#, RESET#) none0F 08 INVD 4 Flush internal caches; initiate flushing external caches none0F 01 /7 INVLPG m 4 Invalidate TLB Entry for Page that contains m none0F 02 /r *@ LAR rv, rmv 2 Load: rv ¬ rmv mask by FF00/00FxFF00 hex (16/32); set ZF ZF0F 01 /2 LGDT m 2 Load lower 16-bit limit, upper 24-/32-bit base m into GDTR none0F 01 /3 LIDT m 2 Load lower 16-bit limit, upper 24-/32-bit base m into IDTR none0F 00 /2 * LLDT rmw 2 Load selector rmw into Local Descriptor Table reg (LDTR) none0F 01 /6 LMSW rmw 2 Load reg/mem word into Machine Status Word of CR0[15-0] none0F 03 /r *@ LSL rv, rmv 2 Load: rv ¬ Segment Limit (20-bits) of selector rmv; set ZF ZF0F 00 /3 * LTR rmw 2 Load reg/mem word into Task Register none

0F 22 /4 MOV CR4, rd 5 Move register dword into Control Register 4 undefined0F 22 /n MOV CRn, rd 3 Move dword register into Control Register n (= 0, 2, or 3) undefined0F 23 /n MOV DRn, rd 3 Move dword register into Debug register n (= 0-3, 6, or 7) undefined0F 20 /4 MOV rd, CR4 5 Move Control Register 4 into dword register undefined0F 20 /n MOV rd, CRn 3 Move Control Register n (= 0, 2, or 3) into dword register undefined0F 21 /n MOV rd, DRn 3 Move Debug register n (= 0-3, 6, or 7) into dword register undefined0F 24 /n MOV rd, TRn 3 Move Test Register n (= 6, 7) into register dword undefined0F 26 /n MOV TRn, rd 3 Move register dword into Test Register n (= 6, 7) undefined0F 32 RDMSR 5 Read 64-bit Model Specific Register by ECX to EDX:EAX none0F 33 RDPMC P2 Read Performance Monitoring Counter by ECX to EDX:EAX none0F 31 RDTSC 5 Read Time Stamp Counter into EDX:EAX (not serializing) none0F AA RSM 5 Resume (return control) to interrupted program from SMM all0F 01 /0 @ SGDT m 2 Store lower 16-bit limit, upper 24-/32-bit base GDTR to m none0F 01 /1 @ SIDT m 2 Store lower 16-bit limit, upper 24-/32-bit base IDTR to m none0F 00 /0 *@ SLDT rmw 2 Store lower 16-bit limit, upper 24-/32-bit base LDTR to rmw none0F 01 /4 @ SMSW rmw 2 Store Machine Status Word to reg/mem word of CR0[15-0] none0F 00 /1 *@ STR rmw 2 Store segment selector from Task Register to reg/mem word none0F 34 *@ SYSENTER P2 Fast call from level 3 code to level 0 operating system code IF, RF, VM0F 35 * SYSEXIT P2 Fast call from level 0 code to level 3 user application code none0F 00 /4 *@ VERR rmw 2 Set ZF = 1 if segment of selector at rmw address can be read ZF0F 00 /5 *@ VERW rmw 2 Set ZF = 1 if segment of selector at rmw can be written ZF0F 09 WBINVD 4 Write Back & flush internal caches; initiate in external caches none0F 30 WRMSR 5 Write EDX:EAX to 64-bit Model Specific Register by ECX none

3DNow! Floating-Point Instructions:0F 0F /r BF PAVGUSB m1, m2/mq 3D Packed rounded Average Unsigned Bytes m2/mq and/to m1 none0F 0F /r 1D PF2ID m1, m2/mq 3D Packed truncated convert SP FP m2/mq into 32-bit Integer m1 none0F 0F /r 1C PF2IW mm, m2/mq 3E Packed truncated convert SP FP m2/mq into 16-bit Integer mm none0F 0F /r AE PFACC m1, m2/mq 3D Packed SP FP Accumulate 2 words m2/mq and/to low, high m1 none0F 0F /r 9E PFADD m1, m2/mq 3D Packed SP FP Addition of m2/mq and/to m1 none0F 0F /r B0 PFCMPEQ m1, m2/mq 3D Packed FP Compare dwords m2/mq to m1; 1s m1 if =, else 0s none0F 0F /r 90 PFCMPGE m1, m2/mq 3D Packed FP Compare dwords m2/mq to m1; 1s m1 if ³, else 0s none0F 0F /r A0 PFCMPGT m1, m2/mq 3D Packed FP Compare dwords m2/mq to m1; 1s m1 if >, else 0s none0F 0F /r A4 PFMAX m1, m2/mq 3D Return Packed Maximum of SP FPs m2/mq and/to m1 none0F 0F /r 94 PFMIN m1, m2/mq 3D Return Packed Minimum of SP FPs m2/mq and/to m1 none0F 0F /r B4 PFMUL m1, m2/mq 3D Packed SP FP Multiply m2/mq into m1 none0F 0F /r 8A PFNACC mm, m2/mq 3E Packed SP FP Negative Accumulate 2 dwords to low, high mm none0F 0F /r 8E PFPNACC mm, m2/mq 3E Packed SP FP mixed Positive-Negative Accumulate 2 dwords none0F 0F /r 96 PFRCP m1, m2/mq 3D Packed scalar FP Reciprocal approx.; result high & low B m1 none0F 0F /r A6 PFRCPIT1 m1, m2/mq 3D Packed FP Reciprocal first Iteration step none0F 0F /r B6 PFRCPIT2 m1, m2/mq 3D Packed FP Reciprocal second Iteration step none0F 0F /r A7 PFRSQIT1 m1, m2/mq 3D Packed FP Reciprocal Square Root of first Iteration step none0F 0F /r 97 PFRSQRT m1, m2/mq 3D Packed FP Reciprocal Square Root approximation none0F 0F /r 9A PFSUB m1, m2/mq 3D Packed SP FP Subtract m2/mq from/to m1 none0F 0F /r AA PFSUBR m1, m2/mq 3D Packed SP FP Subtract m1 from m2/mq; store result to m1 none0F 0F /r 0D PI2FD m1, m2/mq 3D Packed convert signed 32-bit Integer m2/mq to SP FP m1 none0F 0F /r 0C PI2FW mm, m2/mq 3E Packed convert signed 16-bit Integer m2/mq to SP FP mm none0F 0F /r B7 PMULHRW m1, m2/mq 3D Packed 16-bit integer Multiply m2/mq into m1 with Rounding none0F 0D /0 PREFETCH mb 3D Prefetch 32 bytes or more into L1 data cache, exclusive MESI none0F 0D /1 PREFETCHW mb 3D Prefetch 32 B or > into L1 data cache & set MESI to modified none0F 0F /r BB PSWAPD mm, m2/mq 3E Packed Swap high and low Doublewords of m2/mq to mm none

3DNow! Performance-Enhancement Instructions:0F 0E FEMMS 3D Faster Entry/Exit of MMX or floating-point State none

Floating-Point Instruction Abbreviation and Operand Legend: BCD – The abbreviation stands for Binary Coded Decimal, which is the format that is used to perform arithmetic operations.

m32fp – This 4-byte operand contains a single-precision floating-point number, which is less accurate than double precision. m64fp – An 8-byte double precision FP number operand, which takes the same length of calculation time as single precision. m80fp – A 10-byte operand which contains the binary coded decimal format recognized by the FBLD & FBSTP instructions. m16int , m32int – These are 2-byte or 4-byte memory operands, which contains a signed integer in 2's-complement notation. mem10r – This 10-byte full precision FP number operand is for maximum accuracy of double precision number calculations. mem14 , mem94 – These are 14-/94-byte buffers, which are used for saving and restoring the FPU machine state information. ST(0) , ST(i) – These 2 operands are for the top element and element number i (range 0 through 7) of the floating-point stack.

The Floating-Point Instruction Set:In the opcode column, w is for the WAIT/FWAIT instruction, and +i (with a range of 0-7) is a number used when an operand is ST(i).

x87 Data Transfer Instructions:w DF /4 FBLD m80fp Convert BCD to double-extended; push: ST(0) ¬ m80fp C1; #ISw DF /6 FBSTP m80fp Convert ST(0) to 18-digit P BCD; Pop: m80fp ¬ ST(0) C1; #IS, #IA, #P

DA C0+i FCMOVB ST(0), ST(i) P2 If Below (CF = 1): ST(0) ¬ ST(i) C1; #ISDA D0+i FCMOVBE ST(0), ST(i) P2 If Below or Equal (CF = 1, ZF = 1): ST(0) ¬ ST(i) C1; #ISDA C8+i FCMOVE ST(0), ST(i) P2 If Equal (ZF = 1): ST(0) ¬ ST(i) C1; #ISDB C0+i FCMOVNB ST(0), ST(i) P2 If Not Below (CF = 0): ST(0) ¬ ST(i) C1; #ISDB D0+i FCMOVNBE ST(0), ST(i) P2 If Not Below or Equal (CF = 0 & ZF = 0): ST(0) ¬ ST(i) C1; #ISDB C8+i FCMOVNE ST(0), ST(i) P2 If Not Equal (ZF = 0): ST(0) ¬ ST(i) C1; #ISDB D8+i FCMOVNU ST(0), ST(i) P2 If Not Unordered (PF = 0): ST(0) ¬ ST(i) C1; #ISDA D8+i FCMOVU ST(0), ST(i) P2 If Unordered (PF = 1): ST(0) ¬ ST(i) C1; #IS

w DF /0 FILD m16int Convert S m16int to double-extended; push: ST(0) ¬ m16int C1; #ISw DB /0 FILD m32int Convert S m32int to double-extended; push: ST(0) ¬ m32int C1; #ISw DF /5 FILD m64int Convert S m64int to double-extended; push: ST(0) ¬ m64int C1; #ISw DF /2 FIST m16int Convert ST(0) to S integer; m16int ¬ ST(0) C1; #IS, #IA, #Pw DB /2 FIST m32int Convert ST(0) to S integer; m32int ¬ ST(0) C1; #IS, #IA, #Pw DF /3 FISTP m16int Convert ST(0) to S integer; m16int ¬ ST(0); Pop reg stack C1; #IS, #IA, #Pw DB /3 FISTP m32int Convert ST(0) to S integer; m32int ¬ ST(0); Pop reg stack C1; #IS, #IA, #Pw DF /7 FISTP m64int Convert ST(0) to S integer; m64int ¬ ST(0); Pop reg stack C1; #IS, #IA, #Pw D9 /0 FLD m32fp Push register stack: ST(0) ¬ m32fp C1; #IS, #IA, #Dw DD /0 FLD m64fp Push register stack: ST(0) ¬ m64fp C1; #IS, #IA, #Dw DB /5 FLD mem10r Push register stack: ST(0) ¬ mem10r C1; #IS, #IA, #Dw D9 C0+i FLD ST(i) Push register stack: ST(0) ¬ ST(i) C1; #IS, #IA, #Dw D9 /2 FST m32fp Copy: m32fp ¬ ST(0) C1; #IS, #IA, #O, #U, #Pw DD /2 FST m64fp Copy: m64fp ¬ ST(0) C1; #IS, #IA, #O, #U, #Pw DD D0+i FST ST(i) Copy: ST(i) ¬ ST(0) C1; #IS, #IA, #O, #U, #Pw D9 /3 FSTP m32fp Copy: m32fp ¬ ST(0); pop register stack C1; #IS, #IA, #O, #U, #Pw DD /3 FSTP m64fp Copy: m64fp ¬ ST(0); pop register stack C1; #IS, #IA, #O, #U, #Pw DB /7 FSTP mem10r Copy: mem10r ¬ ST(0); pop register stack C1; #IS, #IA, #O, #U, #Pw DD D8+i FSTP ST(i) Copy: ST(i) ¬ ST(0); pop register stack C1; #IS, #IA, #O, #U, #Pw D9 C9 FXCH Exchange contents of ST(0) and ST(1) C1; #ISw D9 C8+i FXCH ST(i) Exchange contents of ST(0) and ST(i) C1; #IS

x87 Basic Arithmetic Instructions:w D9 E1 FABS ST(0) ¬ |ST(0)| C1; #ISw D8 /0 FADD m32fp ST(0) ¬ ST(0) + m32fp C1; #IS, #IA, #D, #O, #U, #Pw DC /0 FADD m64fp ST(0) ¬ ST(0) + m64fp C1; #IS, #IA, #D, #O, #U, #Pw D8 C0+i FADD ST(0), ST(i) ST(0) ¬ ST(0) + ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DC C0+i FADD ST(i), ST(0) ST(i) ¬ ST(0) + ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DE C1 FADDP ST(1) ¬ ST(0) + ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw DE C0+i FADDP ST(i), ST(0) ST(i) ¬ ST(0) + ST(i); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw D9 E0 FCHS ST(0) ¬ -ST(0) C1; #ISw D8 /6 FDIV m32fp ST(0) ¬ ST(0) / m32fp C1; #IS, #IA, #Z, #D, #O, #U, #Pw DC /6 FDIV m64fp ST(0) ¬ ST(0) / m64fp C1; #IS, #IA, #Z, #D, #O, #U, #Pw D8 F0+i FDIV ST(0), ST(i) ST(0) ¬ ST(0) / ST(i) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DC F8+i FDIV ST(i), ST(0) ST(i) ¬ ST(i) / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE F9 FDIVP ST(1) ¬ ST(1) / ST(0); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE F8+i FDIVP ST(i), ST(0) ST(i) ¬ ST(i) / ST(0); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #Pw D8 /7 FDIVR m32fp ST(0) ¬ m32fp / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DC /7 FDIVR m64fp ST(0) ¬ m64fp / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #Pw D8 F8+i FDIVR ST(0), ST(i) ST(0) ¬ ST(i) / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P

w DC F0+i FDIVR ST(i), ST(0) ST(i) ¬ ST(0) / ST(i) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE F1 FDIVRP ST(1) ¬ ST(0) / ST(1); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE F0+i FDIVRP ST(i), ST(0) ST(i) ¬ ST(0) / ST(i); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE /0 FIADD m16int ST(0) ¬ ST(0) + m16int C1; #IS, #IA, #D, #O, #U, #Pw DA /0 FIADD m32int ST(0) ¬ ST(0) + m32int C1; #IS, #IA, #D, #O, #U, #Pw DE /6 FIDIV m16int ST(0) ¬ ST(0) / m16int C1; #IS, #IA, #Z, #D, #O, #U, #Pw DA /6 FIDIV m32int ST(0) ¬ ST(0) / m32int C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE /7 FIDIVR m16int ST(0) ¬ m16int / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DA /7 FIDIVR m32int ST(0) ¬ m32int / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #Pw DE /1 FIMUL m16int ST(0) ¬ ST(0) * m16int C1; #IS, #IA, #D, #O, #U, #Pw DA /1 FIMUL m32int ST(0) ¬ ST(0) * m32int C1; #IS, #IA, #D, #O, #U, #Pw DE /4 FISUB m16int ST(0) ¬ ST(0) - m16int C1; #IS, #IA, #D, #O, #U, #Pw DA /4 FISUB m32int ST(0) ¬ ST(0) - m32int C1; #IS, #IA, #D, #O, #U, #Pw DE /5 FISUBR m16int ST(0) ¬ m16int - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw DA /5 FISUBR m32int ST(0) ¬ m32int - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw D8 /1 FMUL m32fp ST(0) ¬ ST(0) * m32fp C1; #IS, #IA, #D, #O, #U, #Pw DC /1 FMUL m64fp ST(0) ¬ ST(0) * m64fp C1; #IS, #IA, #D, #O, #U, #Pw D8 C8+i FMUL ST(0), ST(i) ST(0) ¬ ST(0) * ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DC C8+i FMUL ST(i), ST(0) ST(i) ¬ ST(0) * ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DE C9 FMULP ST(1) ¬ ST(0) * ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw DE C8+i FMULP ST(i), ST(0) ST(i) ¬ ST(i) * ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw D9 F8 FPREM ST(0) ¬ Partial Remainder of ST(0) / ST(1) (not IEEE) C0-C3; #IS, #IA, #D, #U

D9 F5 FPREM1 387 ST(0) ¬ Partial Remainder of ST(0) / ST(1) (IEEE Std 754) C0-C3; #IS, #IA, #D, #Uw D9 FC FRNDINT ST(0) ¬ round ST(0) to an integer C1; #IS, #IA, #D, #Pw D9 FD FSCALE ST(0) ¬ ST(0) * 2ST(1) C1; #IS, #IA, #D, #O, #U, #Pw D9 FA FSQRT ST(0) ¬ Square Root of ST(0) C1; #IS, #IA, #D, #Pw D8 /4 FSUB m32fp ST(0) ¬ ST(0) - m32fp C1; #IS, #IA, #D, #O, #U, #Pw DC /4 FSUB m64fp ST(0) ¬ ST(0) - m64fp C1; #IS, #IA, #D, #O, #U, #Pw D8 E0+i FSUB ST(0), ST(i) ST(0) ¬ ST(0) - ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DC E8+i FSUB ST(i), ST(0) ST(i) ¬ ST(i) - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw DE E9 FSUBP ST(1) ¬ ST(1) - ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw DE E8+i FSUBP ST(i), ST(0) ST(i) ¬ ST(i) - ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw D8 /5 FSUBR m32fp ST(0) ¬ m32fp - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw DC /5 FSUBR m64fp ST(0) ¬ m64fp - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw D8 E8+i FSUBR ST(0), ST(i) ST(0) ¬ ST(i) - ST(0) C1; #IS, #IA, #D, #O, #U, #Pw DC E0+i FSUBR ST(i), ST(0) ST(i) ¬ ST(0) - ST(i) C1; #IS, #IA, #D, #O, #U, #Pw DE E1 FSUBRP ST(1) ¬ ST(0) - ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw DE E0+i FSUBRP ST(i), ST(0) ST(i) ¬ ST(0) - ST(i); Pop register stack C1; #IS, #IA, #D, #O, #U, #Pw D9 F4 FXTRACT ST(1) ¬ exponent; ST(0) ¬ significand, push to reg stack C1; #IS, #IA, #Z, #D

x87 Comparison Instructions:w D8 /2 FCOM m32fp Compare: ST(0) - m32fp C0-C3; #IS, #IA, #Dw DC /2 FCOM m64fp Compare: ST(0) - m64fp C0-C3; #IS, #IA, #Dw D8 D1 FCOM Compare: ST(0) - ST(1) C0-C3; #IS, #IA, #Dw D8 D0+i FCOM ST(i) Compare: ST(0) - ST(i) C0-C3; #IS, #IA, #D

DB F0+i FCOMI ST(0), ST(i) P2 Compare: ST(0) - ST(i); set EFLAGS C1; #IS, #IADF F0+i FCOMIP P2 Compare: ST(0) - ST(1); set EFLAGS; Pop register stack C1; #IS, #IA

w D8 D9 FCOMP Compare: ST(0) - ST(1); Pop register stack C0-C3; #IS, #IA, #Dw D8 /3 FCOMP m32fp Compare: ST(0) - m32fp; Pop register stack C0-C3; #IS, #IA, #Dw DC /3 FCOMP m64fp Compare: ST(0) - m64fp, Pop register stack C0-C3; #IS, #IA, #Dw D8 D8+i FCOMP ST(i) Compare: ST(0) - ST(i); Pop register stack C0-C3; #IS, #IA, #Dw DE D9 FCOMPP Compare: ST(0) - ST(1); Pop register stack twice C0-C3; #IS, #IA, #Dw DE /2 FICOM m16int Compare: ST(0) - m16int C0-C3; #IS, #IA, #Dw DA /2 FICOM m32int Compare: ST(0) - m32int C0-C3; #IS, #IA, #Dw DE /3 FICOMP m16int Compare: ST(0) - m16int; Pop register stack C0-C3; #IS, #IA, #Dw DA /3 FICOMP m32int Compare: ST(0) - m32int; Pop register stack C0-C3; #IS, #IA, #Dw D9 E4 FTST Compare: ST(0) - 0.0 C0-C3; #IS, #IA, #D

DD E1 FUCOM 387 Unordered Compare: ST(0) - ST(1) C0-C3; #IS, #IA, #DDD E0+i FUCOM ST(i) 387 Unordered Compare: ST(0) - ST(i) C0-C3; #IS, #IA, #DDB E8+i FUCOMI ST(i) P2 Unordered Compare: ST(0) - ST(i); set EFLAGS C1; #IS, #IADF E8+i FUCOMIP ST(i) P2 Unordered Compare: ST(0) - ST(i); set EFLAGS, pop C1; #IS, #IADD E9 FUCOMP 387 Unordered Compare: ST(0) - ST(1); Pop register stack C0-C3; #IS, #IA, #D

DD E8+i FUCOMP ST(i) 387 Unordered Compare: ST(0) - ST(i); Pop register stack C0-C3; #IS, #IA, #DDA E9 FUCOMPP 387 Unordered Compare: ST(0) - ST(1); Pop register stack twice C0-C3; #IS, #IA, #D

w D9 E5 FXAM C0–C3 ¬ type of value in ST(0) (Classify value) C0, C1, C2, C3

x87 Transcendental Instructions:w D9 F0 F2XM1 ST(0) ¬ (2.0 ST(0) - 1) (where -1.0 £ ST(0) £ +1.0) C1; #IS, #IA, #D, #U, #Pw D9 FF FCOS 387 ST(0) ¬ Cosine(ST(0)) C1, C2; #IS, #IA, #D, #U, #Pw D9 F3 FPATAN ST(0) ¬ Arctan(ST(1) / ST(0)); pop register stack C1; #IS, #IA, #D, #U, #Pw D9 F2 FPTAN Push register to stack: ST(0) ¬ Tan(ST(0)) C1, C2; #IS, #IA, #D, #U, #P

D9 FE FSIN 387 ST(0) ¬ Sine(ST(0)) C1, C2; #IS, #IA, #D, #PD9 FB FSINCOS 387 ST(1) ¬ Sine; ST(0) ¬ Cos(ST(0)), push to register stack C1, C2; #IS, #IA, #D, #P

w D9 F1 FYL2X ST(0) ¬ ST(1) * Log2ST(0); pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #Pw D9 F9 FYL2XP1 ST(0) ¬ ST(1) * Log2(ST(0) + 1.0); pop reg stack C1; #IS, #IA, #D, #O, #U, #P

x87 Load Constants:w D9 E8 FLD1 Push register stack: ST(0) ¬ +1.0 C1; #ISw D9 EA FLDL2E Push register stack: ST(0) ¬ Log2℮ (» 1.442695040888963520) C1; #ISw D9 E9 FLDL2T Push register stack: ST(0) ¬ Log210 (» 3.321928094887362560) C1; #ISw D9 EC FLDLG2 Push register stack: ST(0) ¬ Log102 (» 0.301029995663981184) C1; #ISw D9 ED FLDLN2 Push register stack: ST(0) ¬ Log℮2 (» 0.693147180559945344) C1; #ISw D9 EB FLDPI Push register stack: ST(0) ¬ p (» 3.141592653589793280) C1; #ISw D9 EE FLDZ Push register stack: ST(0) ¬ +0.0 C1; #IS

x87 FPU Control Instructions:9B DB E2 FCLEX Clear (check unmasked) FP Exception flags IE, DE, ZE, OE, UE, PE, SF, Bw D9 F6 FDECSTP Decrement Stack Pointer (top field of FPU status register) C1w DD C0+i FFREE ST(i) Set tag for ST(i) to empty undefinedw D9 F7 FINCSTP Increment Stack Pointer (top field of FPU status register) C19B DB E3 FINIT Initialize (check unmasked exceptions) FPU C0, C1, C2, C3w D9 /4 FLDENV mem14 FPU Environment ¬ mem14 (check unmasked exceptions) C0, C1, C2, C3w D9 /5 FLDCW m16int FPU Control Word ¬ m16int undefined

DB E2 FNCLEX Clear Exceptions (nowait unmask exceptions) IE, DE, ZE, OE, UE, PE, SF, ES, BDB E3 FNINIT Initialize FPU (nowait unmask exceptions) C0, C1, C2, C3

w D9 D0 FNOP No Operation (takes up space in execution, only affects EIP) undefinedDD /6 FNSAVE mem94 mem94 ¬ 87 state (check unmasked exceptions) C0, C1, C2, C3D9 /7 FNSTCW m16int m16int ¬ FPU Control Word (nowait unmask exceptions) undefinedD9 /6 FNSTENV mem14 mem14 ¬ FPU Environment (nowait unmask exceptions) undefinedDF E0 FNSTSW AX AX ¬ FPU Status Word (nowait unmask exceptions) undefinedDD /7 FNSTSW m16int m16int ¬ FPU Status Word (nowait unmask exceptions) undefined

w DD /4 FRSTOR mem94 FPU state ¬ mem94 C0, C1, C2, C3w DD /6 FSAVE mem94 mem94 ¬ FPU state (check unmasked exceptions) C0, C1, C2, C3w D9 /7 FSTCW m16int m16int ¬ FPU Control Word (check unmasked exceptions) undefinedw D9 /6 FSTENV mem14 mem14 ¬ FPU Environment (check unmasked exceptions) undefinedw DF E0 FSTSW AX AX ¬ FPU Status Word (check unmasked exceptions) undefinedw DD /7 FSTSW m16int m16int ¬ FPU Status Word (check unmasked exceptions) undefined9B FWAIT Wait until pending unmasked FP exceptions are completed undefined9B WAIT Wait until pending unmasked FP exceptions are completed undefined

x87 FPU and SIMD State Management Instructions:0F AE /1 FXRSTOR m P3 Restore: x87, MMX, XMM, & MXCSR regs ¬ m (512 B) none0F AE /0 FXSAVE m P3 Save: m (512 B) ¬ x87, MMX, XMM, & MXCSR registers none

IA-32 Instruction Format: Instruction Prefixes

Opcode ModR/M SIB Displacement Immediate

Up to 4 prefixes of 1 byte each

1 or 2 byte opcode 1 byte (if required) 1 byte (if required) Address displacement 1, 2, or 4 bytes/none

Immediate data of1, 2, or 4 bytes/none

ModR/M: SIB: 7 6 5 3 2 0 7 6 5 3 2 0

Mod Reg/ R/M Scale Index Base

Opcode

16-Bit & 32-Bit Addressing Forms with the ModR/M Byte:rb(/r)rw(/r)rd(/r)mm(/r)xm(/r)/digit (Opcode)REG =

AL CL DL BL AH CH DH BHAX CX DX BX SP BP¹ SI DIEAX ECX EDX EDX ESP EBP ESI EDIMM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM70 1 2 3 4 5 6 7000 001 010 011 100 101 110 111

16-Bit Effective Address

32-Bit Effective Address Mod R/M Value of ModR/M Byte (in Hexadecimal)

[BX+SI][BX+DI][BP+SI][BP+DI][SI][DI]disp16²[BX]

[EAX] 00 000 00 08 10 18 20 28 30 38[ECX] 001 01 09 11 19 21 29 31 39[EDX] 010 02 0A 12 1A 22 2A 32 3A[EBX] 011 03 0B 13 1B 23 2B 33 3B[–][–]4 100 04 0C 14 1C 24 2C 34 3Cdisp325 101 05 0D 15 1D 25 2D 35 3D[ESI] 110 06 0E 16 1E 26 2E 36 3E[EDI] 111 07 0F 17 1F 27 2F 37 3F

[BX+SI]+disp8³[BX+DI]+disp8[BP+SI]+disp8[BP+DI]+disp8[SI]+disp8[DI]+disp8[BP]+disp8[BX]+disp8

[EAX]+disp86 01 000 40 48 50 58 60 68 70 78[ECX]+disp8 001 41 49 51 59 61 69 71 79[EDX]+disp8 010 42 4A 52 5A 62 6A 72 7A[EBX]+disp8 011 43 4B 53 5B 63 6B 73 7B[–][–]+disp8 100 44 4C 54 5C 64 6C 74 7C[EBP]+disp8 101 45 4D 55 5D 65 6D 75 7D[ESI]+disp8 110 46 4E 56 5E 66 6E 76 7E[EDI]+disp8 111 47 4F 57 5F 67 6F 77 7F

[BX+SI]+disp16[BX+DI]+disp16[BP+SI]+disp16[BP+DI]+disp16[SI]+disp16[DI]+disp16[BP]+disp16[BX]+disp16

[EAX]+disp32 10 000 80 88 90 98 A0 A8 B0 B8[ECX]+disp32 001 81 89 91 99 A1 A9 B1 B9[EDX]+disp32 010 82 8A 92 9A A2 AA B2 BA[EBX]+disp32 011 83 8B 93 9B A3 AB B3 BB[–][–]+disp32 100 84 8C 94 9C A4 AC B4 BC[EBP]+disp32 101 85 8D 95 9D A5 AD B5 BD[ESI]+disp32 110 86 8E 96 9E A6 AE B6 BE[EDI]+disp32 111 87 8F 97 9F A7 AF B7 BF

EAXECXEDXEBXESPEBPESIEDI

AXCXDXBXSPBPSIDI

ALCLDLBLAHCHDHBH

MM0MM1MM2MM3MM4MM5MM6MM7

XMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7

11

000001010011100101110111

C0 C1 C2 C3 C4 C5 C6 C7

C8 C9 CA CB CC CD CE CF

D0 D1 D2 D3 D4 D5 D6 D7

D8 D9 DA DB DC DD DE DF

E0 E1 E2 E3 E4 E5 E6 E7

E8 E9 EA EB EC ED EE EF

F0 F1 F2 F3 F4 F5 F6 F7

F8 F9 FA FB FC FD FE FF

Notes:1. The default segment register is SS for the effective addresses containing a BP index; DS register is for other effective addresses.2. The disp16 nomenclature denotes a 16-bit displacement that follows behind ModR/M byte and that is added to the index’s value.3. The disp8 nomenclature denotes an 8-bit displacement following ModR/M byte and that is sign-extended and added to the index.

4. The [–][–] nomenclature means a SIB (Scale, Index, & Base fields) byte follows ModR/M (Mod, reg/opcode, & R/M fields) byte. 5. The disp32 nomenclature denotes a 32-bit displacement that follows ModR/M byte (or SIB byte if present) that is added to index. 6. The disp8 denotes an 8-bit displacement that follows ModR/M byte (SIB byte if present) that is sign-extended and added to index. 32-Bit Addressing Forms with the SIB Byte:

rd(/r)Base =Base =

EAX ECX EDX EBX ESP [*] ESI EDI0 1 2 3 4 5 6 7000 001 010 011 100 101 110 111

Scaled Index SS Index Value of SIB Byte (in Hexadecimal)

[EAX][ECX][EDX][EBX]none[EBP][ESI][EDI]

00 000 001 010 011 100 101 110 111

00 08 10 18 20 28 30 38

01 09 11 19 21 29 31 39

02 0A 12 1A 22 2A 32 3A

03 0B 13 1B 23 2B 33 3B

04 0C 14 1C 24 2C 34 3C

05 0D 15 1D 25 2D 35 3D

06 0E 16 1E 26 2E 36 3E

07 0F 17 1F 27 2F 37 3F

[EAX*2][ECX*2][EDX*2][EBX*2]none[EBP*2][ESI*2][EDI*2]

01 000 001 010 011 100 101 110 111

40 48 50 58 60 68 70 78

41 49 51 59 61 69 71 79

42 4A 52 5A 62 6A 72 7A

43 4B 53 5B 63 6B 73 7B

44 4C 54 5C 64 6C 74 7C

45 4D 55 5D 65 6D 75 7D

46 4E 56 5E 66 6E 76 7E

47 4F 57 5F 67 6F 77 7F

[EAX*4][ECX*4][EDX*4][EBX*4]none[EBP*4][ESI*4][EDI*4]

10 000 001 010 011 100 101 110 111

80 88 90 98 A0 A8 B0 B8

81 89 91 99 A1 A9 B1 B9

82 8A 92 9A A2 AA B2 BA

83 8B 93 9B A3 AB B3 BB

84 8C 94 9C A4 AC B4 BC

85 8D 95 9D A5 AD B5 BD

86 8E 96 9E A6 AE B6 BE

87 8F 97 9F A7 AF B7 BF

[EAX*8][ECX*8][EDX*8][EBX*8]none[EBP*8][ESI*8][EDI*8]

11 000 001 010 011 100 101 110 111

C0 C8 D0 D8 E0 E8 F0 F8

C1 C9 D1 D9 E1 E9 F1 F9

C2 CA D2 DA E2 EA F2 FA

C3 CB D3 DB E3 EB F3 FB

C4 CC D4 DC E4 EC F4 FC

C5 CD D5 DD E5 ED F5 FD

C6 CE D6 DE E6 EE F6 FE

C7 CF D7 DF E7 EF F7 FF

Notes:1. The [*] nomenclature means a disp32 with no base if MOD is 00, [EBP] otherwise. This provides the following address modes: disp32[index] (MOD = 00). disp8[EBP][index] (MOD = 01). disp32[EBP][index] (MOD = 10).

ASCII Character Chart (rows 4-5 map to rows 0-1 using Ctrl + [letter/symbol]); read row then column: 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US2 SPC ! “ # $ % & ‘ ( ) * , + – . /3 0 1 2 3 4 5 6 7 8 9 : ; < = > ?4 @ A B C D E F G H I J K L M N O5 P Q R S T U V W X Y Z [ \ ] ^ _6 ` A b c d e f g h i j k l m n o7 P Q r s t u v w x y z { | } ~ DEL

Physical Communications Controls: NUL: Null; CAN: Cancel line; EM: End of Medium; SUB: Substitute; DEL: DeleteLogical Communications Controls: SOH: Start of Header; STX: Start Text; ETX: End Text; EOT: End of Transmission; ENQ: Enquiry

ACK: Acknowledgement; DLE: Data Link Escape; NAK: Negative Acknowledgement; SYN: Synchronous Idle; ETB: End Transmission BlockPhysical Device Controls: BEL: Bell; DC1, DC2, DC3, DC4: No ASCII meaning, used for XON/XOFF handshake schemes.Physical Device Format Affecters: BS: Backspace; HT: Horizontal Tab; LF: Line Feed; VT: Vertical Tab; FF: Form Feed; CR: CarriageControls for Code Extensions: SI: Shift In; SO: Shift Out; ESC: EscapeInformation Separators: FS: File Separator; GS: Group Separator; RS: Record Separator; US: Unit Separator

IA-32 General Exceptions and Interrupts (Vector Numbers are in hexadecimal):Vector No. Name Source Protected Mode Real Address Mode Virtual 8086 Mode 00 #DE–Divide Error DIV and IDIV instructions. Yes Yes Yes 01 #DB–Debug Any code or data reference. Yes Yes Yes

02 NMI Interrupt Un-mask external interrupt. Yes Yes Yes 03 #BP–Breakpoint INT 3 instruction. Yes Yes Yes 04 #OF–Overflow INTO instruction. Yes Yes Yes 05 #BR–BOUND Range Exceeded. BOUND instruction. Yes Yes Yes

06#UD–Invalid Opcode(undefined Opcode)

UD2 instruction (P2) orreserved opcode.

Yes Yes Yes

07#NM–Device Not Available (No Math Coprocessor)

Floating-point or WAIT/FWAIT instruction

Yes Yes Yes

08 #DF–Double FaultInstruction that can makeexception, NMI, or INTR.

Yes Yes Yes

09 #MF–Coprocessor Seg Overrun. Floating-Point instruction. Yes Yes Yes 0A #TS–Invalid TSS Task switch or TSS access. Yes Reserved Yes

0B #NP–Segment Not PresentLoading segment registersor accessing system segs.

Yes Reserved Yes

0C #SS–Stack Segment Fault Stack ops & SS reg loads. Yes Yes Yes

0D #GP–General Protection*Any memery reference &other protection checks.

Yes Yes Yes

0E #PF–Page Fault Any memory reference. Yes Reserved Yes 0F (Intel Reserved. Don’t use.) — — — — 10 #MF–Floating-Point Error FP or (F)WAIT instruction. Yes Yes Yes 11 #AC–Alignment Check Any data reference in mem. Yes Reserved Yes

12 #MC–Machine CheckModel dependent machinecheck errors.

Yes Yes Yes

13 #XF–SIMD FP Numeric Error SSE(2) FP instructions. Yes Yes Yes 14-1F (Intel Reserved. Don’t use.) — — — — 20-FF Maskable Interrupts External, INTR or INT n. — — —

Note:* In real-address mode, vector 0D is the segment-overrun exception.

SIMD & x87 FPU Floating-Point Exceptions (#IS & #IA are invalids for x87): Mnemonic Name Source

Encoding Sreg2 Field: #I Floating-point invalid operation: Invalid arithmetic operation or source operand #IS – Stack overflow or underflow – x87 FPU stack overflow or underflow Sreg2

Field*Segment register Selected #IA – Invalid arithmetic operation – Invalid FPU arithmetic operation

#Z Floating-point divide-by-zero Divide-by-zero 00 ES #D Floating-point denormal operand Source operand that is a denormal number 01 CS #O Floating-point numeric overflow Overflow in result 10 SS #U Floating-point numeric underflow Underflow in result 11 DS #P Floating-point inexact result Inexact result (precision) Note:

* Used only with Push/Pop.Note:* Do not use reserved encodings.

Segment Register (sreg3) & Special-Purpose Register (eee) Encodings: Register Encoding Chart:Sreg3 Field/eee Segment Register Selected Control Register Debug Register Reg No.* +rb +rw +rd 000 ES CR0 DR0 0 AL AX EAX 001 CS Reserved* DR1 1 CL CX ECX 010 SS CR2 DR2 2 DL DX EDX 011 DS CR3 DR3 3 BL BX EBX 100 FS CR4 Reserved* 4 AH SP ESP 101 GS Reserved* Reserved* 5 CH BP EBP 110 Reserved* Reserved* DR6 6 DH SI ESI 111 Reserved* Reserved* DR7 7 BH DI EDI

Note:* Do not use reserved encodings.

Note:* Add to the instruction’s opcode.

EFLAGS (Program Status & Control) Register:31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 0 0 0 0 0 0 I

DVIP

VIF

AC

VM

RF

0 NT

I O P

OF

DF

IF

TF

SF

ZF

0 AF

0 PF

1 CF

LS CF: Cary Flag; S PF: Parity Flag; S AF: Auxiliary Carry Flag; S ZF: Zero Flag; S SF: Sign Flag; X TF: Trap Flag; X IF: InterruptEnable Flag; X DF: Direction Flag; X OF: Overflow Flag; X IOPL: I/O Privilege Level; X NT: Nested Task; X RF: Resume Flag;X VM: Virtual-8086 Mode; X AC: Alignment Check; X VIF: Virtual Interrupt Flag; X VIP: Virtual Interrupt Pending; X ID: ID Flag

Reserved bit positions. DO NOT USE. Note: S Indicates a Status Flag; C Indicates a Control Flag; X Indicates a System Flag

x87 FPU Status Word Register: x87 FPU Control Word Register:15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BC3

TOPC2

C1

C0

ES

SF

PE

UE

OE

ZE

DE

IE

X RC PCPM

UM

OM

ZM

DM

IM

IE: Invalid Operation; DE: Denormalized Operand; ZE: ZeroDivide; OE: Overflow; UE: Underflow; PE: Exception FlagsPrecision; SF: Stack Fault; ES: Error Summary Status; C0-C3:Condition Code; TOP: Top of Stack Pointer; B: FPU Busy

IM: Invalid Operand; DM: Denormal Operand; ZM: ZeroDivide; OM: Overflow; UM: Underflow; PM: Precision; PC:Precision Control; RC: Rounding Control; X: Infinity Control

Reserved bit positions. DO NOT USE.

General-Purpose Registers:31 16 15 0 16-bit 32-bit Segment Registers Fundamental Data Types:

AH AL AX EAX (Segmented Model): Data Bits – 127 64 63 32 31 16 15 8 7 0 BH BL BX EBX 15 0 Byte – CH CL CX ECX CS (Code Segment) Word – H L DH DL DX EDX DS (Data Segment) Double Word – High Low BP EBP SS (Stack Segment) Quad Word – High Low SI ESI ES (Data Segment) DQword – High Qword Low Qword DI EDI FS (Data Segment) Note: The highest bit is sign-bit for signed data types, SP ESP GS (Data Segment) indicating if the number is negative (1) or positive (0).

Instruction Pointer: Effective Address (Offset) Computation:31 16 15 0 16-bit 32-bit Base Index Scale Displacement

IP EIP EAXEBXECXEDXESPEBPESIEDI

EAXEBXECXEDXEBPESIEDI

1

2

4

8

None

8-bit

16-bit

32-bit

+ * +Effective Operand- and Address-Size Attributes:D Flag in Code SegmentDescriptor (1 for 32-bit)

0 0 0 0 1 1 1 1

Operand-Size Prefix 66H N N Y Y N N Y YAddress-Size Prefix 67H N Y N Y N Y N YEffective Operand Size 16 16 32 32 32 32 16 16Effective Address Size 16 32 16 32 32 16 32 16 Note: Offset = Base + (Index * Scale) + Displacement

Boolean Logic Truth Tables (AND NOT: row 1st operand, column 2nd operand): Data Structure: Byte OffsetAND 0 1 OR 0 1 XOR 0 1 NOT 0 1 AND NOT 0 1 31 24 23 16 15 8 7 0 ↑ 0 0 0 0 0 1 0 0 1

1 0 0 0 1 Highest 4

1 0 1 1 1 1 1 1 0 1 0 0 Byte 3 Byte 2 Byte 1 Byte 0 0

Encoding of Operation Direction (d) Bit: Encoding of Operand Size (w) Bit:d Destination Source w Operand Size with 16-bit Attribute Operand Size with 32-bit Attribute0 ModR/M or SIB Byte reg Field 0 8 Bits 8 Bits1 reg Field ModR/M or SIB Byte 1 16 Bits 32 Bits

Encoding of Sign-Extend (s) Bit: Encoding of Granularity (gg):s Effect on 8-Bit Immediate Data Effect on 16- or 32-Bit Immediate Data gg Data Size gg Data Size0 None None 00 P Bytes 10 P Dwords1 Sign-extend to fill 16-bit or 32-bit destination None 01 P Words 11 Quadword

Encoding of Conditional Test (tttn) Field: Stack Structure: Stack on Near & Far Calls/Returns: tttn Mnemonic Condition Stack Segment Stack During

Near Call Stack During Far Call

0000 O Overflow Bottom of Stack (Initial ESP Value)

Parameter 1 0001 NO No Overflow Parameter 1 Parameter 2

(ESP Before) 0010 B, NAE Below, Not Above or Equal Frame Boundary Parameter 2 (ESP Before) 0011 NB, AE Not Below, Above or Equal Local Variables for

Calling Procedure ↑ Frame Before

0100 E, Z Equal, Zero ↑ Frame Before ↓ Frame After 0101 NE, NZ Not Equal, Not Zero Parameters Passed

to Called Procedure ↓ Frame After Calling CS

0110 BE, NA Below or Equal, Not Above Calling EIP (ESP After)

Calling EIP (ESP After) 0111 NBE, A Not Below or Equal, Above Frame Boundary

1000 S Sign Return Instruction Pointer(EBP points to this)

1001 NS Not Sign Stack During

Near ReturnStack During Far Ret

1010 P, PE Parity, Parity Even (ESP After) 1011 NP, PO Not Parity, Parity Odd ESP points to TOS

(SS Offset of Base) (ESP After) Parameter 1

1100 L, NGE Less than, Not Greater than or Equal to Parameter 1 Parameter 2 1101 NL, GE Not Less than, Greater than or Equal to Top of Stack Parameter 2 Calling CS 1110 LE, NG Less than or Equal to, Not Greater than ↓ Push TOS Lower Calling EIP

(ESP Before) Calling EIP (ESP Before) 1111 NLE, G Not Less than or Equal to, Greater than ↑ Pop TOS Higher

AAA 0011 0111AAD 1101 0101 : 0000 1010AAM 1101 0100 : 0000 1010AAS 0011 1111ADC reg1 to reg2 0001 000w : 11 reg1 reg2

reg2 to reg1 0001 001w : 11 reg1 reg2mem to reg 0001 001w : mod reg r/mreg to mem 0001 000w : mod reg r/mi to reg 1000 00sw : 11 010 reg : ii to AL/AX/EAX 0001 010w : ii to mem 1000 00sw : mod 010 r/m : i

ADD reg1 to reg2 0000 000w : 11 reg1 reg2reg2 to reg1 0000 001w : 11 reg1 reg2mem to reg 0000 001w : mod reg r/mreg to mem 0000 000w : mod reg r/mi to reg 1000 00sw : 11 000 reg : ii to AL/AX/EAX 0000 010w : ii to mem 1000 00sw : mod 000 r/m : i

AND reg1 to reg2 0010 000w : 11 reg1 reg2reg2 to reg1 0010 001w : 11 reg1 reg2mem to reg 0010 001w : mod reg r/mreg to mem 0010 000w : mod reg r/mi to reg 1000 00sw : 11 000 reg : ii to AL/AX/EAX 0010 010w : ii to mem 1000 00sw : mod 100 r/m : i

ARPL from reg 0110 0011 : 11 reg1 reg2from mem 0110 0011 : mod reg r/m

BOUND 0110 0010 : mod reg r/mBSF reg1, reg2 0000 1111 : 1011 1100 : 11 reg2 reg1

mem, reg 0000 1111 : 1011 1100 : mod reg r/mBSR reg1, reg2 0000 1111 : 1011 1101 : 11 reg2 reg1

mem, reg 0000 1111 : 1011 1101 : mod reg r/mBSWAP 0000 1111 : 1100 1 regBT reg, i 0000 1111 : 1011 1010 : 11 100 reg : ib

mem, i 0000 1111 : 1011 1010 : mod 100 r/m : ibreg1, reg2 0000 1111 : 1010 0011 : 11 reg2 reg1mem, reg 0000 1111 : 1010 0011 : mod reg r/m

BTC reg, i 0000 1111 : 1011 1010 : 11 111 reg : ibmem, i 0000 1111 : 1011 1010 : mod 111 r/m : ibreg1, reg2 0000 1111 : 1011 1011 : 11 reg2 reg1mem, reg 0000 1111 : 1011 1011 : mod reg r/m

BTR reg, i 0000 1111 : 1011 1010 : 11 110 reg : ibIDIV AL/AX/EAX by reg 1111 011w : 11 111 reg

AL/AX/EAX by mem 1111 011w : mod 111 r/mIMUL AL/AX/EAX with reg 1111 011w : 11 101 reg

AL/AX/EAX with mem 1111 011w : mod 101 reg

mem, i 0000 1111 : 1011 1010 : mod 110 r/m : ibreg1, reg2 0000 1111 : 1011 0011 : 11 reg2 reg1mem, reg 0000 1111 : 1011 0011 : mod reg r/m

BTS reg, i 0000 1111 : 1011 1010 : 11 101 reg : ibmem, i 0000 1111 : 1011 1010 : mod 101 r/m : ibreg1, reg2 0000 1111 : 1010 1011 : 11 reg2 reg1mem, reg 0000 1111 : 1010 1011 : mod reg r/m

CALL direct 1110 1000 : full displacementreg indirect 1111 1111 : 11 010 regmem indirect 1111 1111 : mod 010 r/m

CBW 1001 1000CDQ 1001 1001CLC 1111 1000CLD 1111 1100CLI 1111 1010CLTS 0000 1111 : 0000 0110CMC 1111 0101CMOVcc reg2 to reg1 0000 1111 : 0100 tttn : 11 reg1 reg2

mem to reg 0000 1111 : 0100 tttn : mod mem r/mCMP reg1 with reg2 0011 100w : 11 reg1 reg2

reg2 with reg1 0011 101w : 11 reg1 reg2mem with reg 0011 100w : mod reg r/mreg with mem 0011 101w : mod reg r/mi with reg 1000 00sw : 11 111 reg : ii with AL/AX/EAX 0011 110w : ii with mem 1000 00sw : mod 111 r/m

CMPS/CMPSB/CMPSW/CMPSD 1010 011wCMPXCHG reg1, reg2 0000 1111 : 1011 000w : 11 reg2 reg1

mem, reg 0000 1111 : 1011 000w : mod reg r/mCMPXCHG8B mem, reg 0000 1111 : 1100 0111 : mod reg r/mCPUID 0000 1111 : 1010 0010CWD 1001 1001CWDE 1001 1000DAA 0010 0111DAS 0010 1111DEC reg 1111 111w : 11 001 reg

reg (alt. encoding) 0100 1 regmem 1111 111w : mod 001 r/m

DIV AL/AX/EAX by reg 1111 011w : 11 110 regAL/AX/EAX by mem 1111 011w : mod 110 r/m

ENTER 1100 1000 : 16-bit disp : 8-bit levelHLT 1111 0100

AL/AX/EAX to mem 1010 001w : full dispMOV reg to CR0 0000 1111 : 0010 0010 : 11 000 reg

reg to CR2 0000 1111 : 0010 0010 : 11 010 regreg to CR3 0000 1111 : 0010 0010 : 11 011 reg

reg1 with reg2 0000 1111 : 1010 1111 : 11 : reg1 reg2reg with mem 0000 1111 : 1010 1111 : mod reg r/mreg1 with i to reg2 0110 10s1 : 11 reg1 reg2 : imem with i to reg 0110 10s1 : mod reg r/m : i

IN fixed port 1110 010w : port numbervariable port 1110 110w

INC reg 1111 111w : 11 000 regreg (alt. encoding) 0100 0 regmem 1111 111w : mod 000 r/m

INS 0110 110wINT ib 1100 1101 : ibINT 3 1100 1100INTO 1100 1110INVD 0000 1111 : 0000 1000INVLPG 0000 1111 : 0000 0001 : mod 111 r/mIRET/IRETD 1100 1111Jcc 8-bit displacement 0111 tttn : 8 bit disp

full displacement 0000 1111 : 1000 tttn : full dispJCXZ/JECXZ 1110 0011 : 8-bit dispJMP short 1110 1011 : 8-bit disp

direct 1110 1001 : full dispreg indirect 1111 1111 : 11 100 regmem indirect 1111 1111 : mod 100 r/m

JMP direct intersegment 1110 1010 : unS full offset, selectorindirect intersegment 1111 1111 : mod 101 r/m

LAHF 1001 1111LAR from reg 0000 1111 : 0000 0010 : 11 reg1 reg2

from mem 0000 1111 : 0000 0010 : mod reg r/mLDS 1100 0101 : mod reg r/mLEA 1000 1101 : mod reg r/mLEAVE 1100 1001LES 1100 0100 : mod reg r/mLFS 0000 1111 : 1011 0100 : mod reg r/mLGDT 0000 1111 : 0000 0001 : mod 010 r/mLGS 0000 1111 : 1011 0101 : mod reg r/mLIDT 0000 1111 : 0000 0001 : mod 011 r/mLLDT LDTR from reg 0000 1111 : 0000 0000 : 11 010 reg

LDTR from mem 0000 1111 : 0000 0000 : mod 010 r/mLMSW from reg 0000 1111 : 0000 0001 : 11 110 reg

from mem 0000 1111 : 0000 0001 : mod 110 r/mLOCK 1111 0000LODS/LODSB/LODSW/LODSD 1010 110wLOOP 1110 0010 : 8-bit dispLOOPZ/LOOPE 1110 0001 : 8-bit dispLOOPNZ/LOOPNE 1110 0000 : 8-bit dispLSL from reg 0000 1111 : 0000 0011 : 11 reg1 reg2

from mem 0000 1111 : 0000 0011 : mod reg r/mLSS 0000 1111 : 1011 0010 : mod reg r/mLTR from reg 0000 1111 : 0000 0000 : 11 011 reg

from mem 0000 1111 : 0000 0000 : mod 011 r/mMOV reg1 to reg2 1000 100w : 11 reg1 reg2

reg2 to reg1 1000 101w : 11 reg1 reg2mem to reg 1000 101w : mod reg r/mreg to mem 1000 100w : mod reg r/mi to reg 1100 011w : 11 000 reg : i i to reg (alt. encoding) 1011 w reg : ii to mem 1100 011w : mod 000 r/m : imem to AL/AX/EAX 1010 000w : full disp

RCR reg by 1 1101 000w : 11 011 regmem by 1 1101 000w : mod 011 r/mreg by CL 1101 001w : 11 011 regmem by CL 1101 001w : mod 011 r/m

reg to CR4 0000 1111 : 0010 0010 : 11 100 regCR0-CR4 to reg 0000 1111 : 0010 0000 : 11 eee reg

MOV reg to DR0-DR3 0000 1111 : 0010 0011 : 11 eee regreg to DR4-DR5 0000 1111 : 0010 0011 : 11 eee regreg to DR6-DR7 0000 1111 : 0010 0011 : 11 eee regDR6-DR7 to reg 0000 1111 : 0010 0001 : 11 eee regDR4-DR5 to reg 0000 1111 : 0010 0001 : 11 eee regDR0-DR3 to reg 0000 1111 : 0010 0001 : 11 eee reg

MOV reg to sreg 1000 1110 : 11 sreg3 regreg to SS 1000 1110 : 11 sreg3 regmem to sreg 1000 1110 : mod sreg3 r/mmem to SS 1000 1110 : mod sreg3 r/msreg to reg 1000 1100 : 11 sreg3 regsreg to mem 1000 1100 : mod sreg3 r/m

MOVS/MOVSB/MOVSW/MOVSD 1010 010wMOVSX reg2 to reg1 0000 1111 : 1011 111w : 11 reg1 reg2

mem to reg 0000 1111 : 1011 111w : mod reg r/mMOVZX reg2 to reg1 0000 1111 : 1011 011w : 11 reg1 reg2

mem to reg 0000 1111 : 1011 011w : mod reg r/mMUL AL/AX/EAX with reg 1111 011w : 11 100 reg

AL/AX/EAX with mem 1111 011w : mod 100 regNEG reg 1111 011w : 11 011 reg

mem 1111 011w : mod 011 r/mNOP 1001 0000NOT reg 1111 011w : 11 010 reg

mem 1111 011w : mod 010 r/mOR reg1 to reg2 0000 100w : 11 reg1 reg2

reg2 to reg1 0000 101w : 11 reg1 reg2mem to reg 0000 101w : mod reg r/mreg to mem 0000 100w : mod reg r/mi to reg 1000 00sw : 11 001 reg : ii to AL/AX/EAX 0000 110w : ii to mem 1000 00sw : mod 001 r/m : i

OUT fixed port 1110 011w : port numbervariable port 1110 111w

OUTS 0110 111wPOP reg 1000 1111 : 11 000 reg

reg (alt. encoding) 0101 1 regmem 1000 1111 : mod 000 r/m

POP sreg CS, DS, or ES 000 sreg2 111sreg SS 000 sreg2 111sreg FS or GS 0000 1111 : 10 sreg3 001

POPA/POPAD 0110 0001POPF/POPFD 1001 1101PUSH reg 1111 1111 : 11 110 reg

reg (alt. encoding) 0101 0 regmem 1111 1111 : mod 110 r/mi 0110 10s0 : i

PUSH sreg CS/DS/ES/SS 000 sreg2 110sreg FS or GS 0000 1111 : 10 sreg3 000

PUSHA/PUSHAD 0110 0000PUSHF/PUSHFD 1001 1100RCL reg by 1 1101 000w : 11 010 reg

mem by 1 1101 000w : mod 010 r/mreg by CL 1101 001w : 11 010 regmem by CL 1101 001w : mod 010 r/mreg by i 1100 000w : 11 010 reg : ibmem by i 1100 000w : mod 010 r/m :ibreg by CL 0000 1111 : 1010 0101 : 11 reg2 reg1mem by CL 0000 1111 : 1010 0101 : mod reg r/m

SHR reg by 1 1101 000w : 11 101 regmem by 1 1101 000w : mod 101 r/m

reg by i 1100 000w : 11 011 reg : ibmem by i 1100 000w : mod 011 r/m : ib

RDMSR 000 1111 : 0011 0010RDPMC 0000 1111 : 0011 0011RDTSC 0000 1111 : 0011 0001REP INS 1111 0011 : 0110 110wREP LODS 1111 0011 : 1010 110wREP MOVS 1111 0011 : 1010 010wREP OUTS 1111 0011 : 0110 111wREP STOS 1111 0011 : 1010 101wREP CMPS 1111 0011 : 1010 011wREPE SCAS 1111 0011 : 1010 111wREPNE CMPS 1111 0010 : 1010 011wREPNE SCAS 1111 0010 : 1010 111wRET (same) no argument 1100 0011

adding i to SP 1100 0010 : 16-bit dispRET (other) intersegment 1100 1011

adding i to SP 1100 1010 : 16-bit dispROL reg by 1 1101 000w : 11 000 reg

mem by 1 1101 000w : mod 000 r/mreg by CL 1101 001w : 11 000 regmem by CL 1101 001w : mod 000 r/mreg by i 1100 000w : 11 000 reg : ibmem by i 1100 000w : mod 000 r/m : ib

ROR reg by 1 1101 000w : 11 001 regmem by 1 1101 000w : mod 001 r/mreg by CL 1101 001w : 11 001 regmem by CL 1101 001w : mod 001 r/mreg by i 1100 000w : 11 001 reg : ibmem by i 1100 000w : mod 001 r/m : ib

RSM 0000 1111 : 1010 1010SAHF 1001 1110SAL same instruction as SHLSAR reg by 1 1101 000w : 11 111 reg

mem by 1 1101 000w : mod 111 r/mreg by CL 1101 001w : 11 111 regmem by CL 1101 001w : mod 111 r/mreg by i 1100 000w : 11 111 reg : ibmem by i 1100 000w : mod 111 r/m : ib

SBB reg1 to reg2 0001 100w : 11 reg1 reg2reg2 to reg1 0001 101w : 11 reg1 reg2mem to reg 0001 101w : mod reg r/mreg to mem 0001 100w : mod reg r/mi to reg 1000 00sw : 11 011 reg : ii to AL/AX/EAX 0001 110w : ii to mem 1000 00sw : mod 011 r/m : i

SCAS/SCASB/SCASW/SCASD 1101 111wSETcc reg 0000 1111 : 1001 tttn : 11 000 reg

mem 0000 1111 : 1001 tttn : mod 000 r/mSGDT 0000 1111 : 0000 0001 : mod 000 r/mSHL reg by 1 1101 000w : 11 100 reg

mem by 1 1101 000w : mod 100 r/mreg by CL 1101 001w : 11 100 regmem by CL 1101 001w : mod 100 r/mreg by i 1100 000w : 11 100 reg : ibmem by i 1100 000w : mod 100 r/m : ib

SHLD reg by i 0000 1111 : 1010 0100 : 11 reg2 reg1 : ibmem by i 0000 1111 : 1010 0100 : mod reg r/m : ib

FS segment override 0110 0100GS segment override 0110 0101SS segment override 0011 0110

EMMS 0000 1111 : 0111 0111

reg by CL 1101 001w : 11 101 regmem by CL 1101 001w : mod 101 r/mreg by i 1100 000w : 11 101 reg :i8mem by i 1100 000w : mod 101 r/m :i8

SHRD reg by i 0000 1111 : 1010 1100 : 11 reg2 reg1 : ibmem by i 0000 1111 : 1010 1100 : mod reg r/m : ibreg by CL 0000 1111 : 1010 1101 : 11 reg2 reg1mem by CL 0000 1111 : 1010 1101 : mod reg r/m

SIDT 0000 1111 : 0000 0001 : mod 001 r/mSLDT to reg 0000 1111 : 0000 0000 : 11 000 reg

to mem 0000 1111 : 0000 0000 : mod 000 r/mSMSW to reg 0000 1111 : 0000 0001 : 11 100 reg

to mem 0000 1111 : 0000 0001 : mod 100 r/mSTC 1111 1001STD 1111 1101STI 1111 1011STOS/STOSB/STOSW/STOSD 1010 101wSTR to reg 0000 1111 : 0000 0000 : 11 001 reg

to mem 0000 1111 : 0000 0000 : mod 001 r/mSUB reg1 to reg2 0010 100w : 11 reg1 reg2

reg2 to reg1 0010 101w : 11 reg1 reg2mem to reg 0010 101w : mod reg r/mreg to mem 0010 100w : mod reg r/mi to reg 1000 00sw : 11 101 reg : ii to AL/AX/EAX 0010 110w : ii to mem 1000 00sw : mod 101 r/m : i

TEST reg1 and reg2 1000 010w : 11 reg1 reg2mem and reg 1000 010w : mod reg r/mi and reg 1111 011w : 11 000 reg : ii and AL/AX/EAX 1010 100w : ii and mem 1111 011w : mod 000 r/m : i

UD2 0000 1111 : 0000 1011VERR reg 0000 1111 : 0000 0000 : 11 100 reg

mem 0000 1111 : 0000 0000 : mod 100 r/mVERW reg 0000 1111 : 0000 0000 : 11 101 reg

mem 0000 1111 : 0000 0000 : mod 101 r/mWAIT 1001 1011WBINVD 0000 1111 : 0000 1001WRMSR 0000 1111 : 0011 0000XADD reg1, reg2 0000 1111 : 1100 000w : 11 reg2 reg1

mem, reg 0000 1111 : 1100 000w : mod reg r/mXCHG reg1 with reg2 1000 011w : 11 reg1 reg2

AL/AX/EAX with reg 1001 0 regmem with reg 1000 011w : mod reg r/m

XLAT/XLATB 1101 0111XOR reg1 to reg2 0011 000w : 11 reg1 reg2

reg2 to reg1 0011 001w : 11 reg1 reg2mem to reg 0011 001w : mod reg r/mreg to mem 0011 000w : mod reg r/mi to reg 1000 00sw : 11 110 reg : ii to AL/AX/EAX 0011 010w : ii to mem 1000 00sw : mod 110 r/m : i

Prefix Bytes address size 0110 0111LOCK 1111 0000operand size 0110 0110CS segment override 0010 1110DS segment override 0011 1110ES segment override 0010 0110

FXSAVE 0000 1111 : 1010 1110 : 00 m512SYSENTER 0000 1111 : 0101 1111 : 11SYSEXIT 0000 1111 : 0101 1111 : 11ADDPS xm to xm 0000 1111 : 0101 1000 : 11 xm1 xm2

MOVD reg to mm 0000 1111 : 0110 1110 : 11 mm regmm to reg 0000 1111 : 0111 1110 : 11 mm regmem to mm 0000 1111 : 0110 1110 : mod mm r/mmm to mem 0000 1111 : 0111 1110 : mod mm r/m

MOVQ mm2 to mm1 0000 1111 : 0110 1111 : 11 mm1 mm2mm1 to mm2 0000 1111 : 0111 1111 : 11 mm1 mm2mem to mm 0000 1111 : 0110 1111 : mod mm r/mmm to mem 0000 1111 : 0111 1111 : mod mm r/m

PACKSSDW mm2 to mm1 0000 1111 : 0110 1011 : 11 mm1 mm2mem to mm 0000 1111 : 0110 1011 : mod mm r/m

PACKSSWB mm2 to mm1 0000 1111 : 0110 0011 : 11 mm1 mm2mem to mm 0000 1111 : 0110 0011 : mod mm r/m

PACKUSWB mm2 to mm1 0000 1111 : 0110 0111 : 11 mm1 mm2mem to mm 0000 1111 : 0110 0111 : mod mm r/m

PADD mm2 to mm1 0000 1111 : 1111 11gg : 11 mm1 mm2mem to mm 0000 1111 : 1111 11gg : mod mm r/m

PADDS mm2 to mm1 0000 1111 : 1110 11gg : 11 mm1 mm2mem to mm 0000 1111 : 1110 11gg : mod mm r/m

PADDUS mm2 to mm1 0000 1111 : 1101 11gg : 11 mm1 mm2mem to mm 0000 1111 : 1101 11gg : mod mm r/m

PAND mm2 to mm1 0000 1111 : 1101 1011 : 11 mm1 mm2mem to mm 0000 1111 : 1101 1011 : mod mm r/m

PANDN mm2 to mm1 0000 1111 : 1101 1111 : 11 mm1 mm2mem to mm 0000 1111 : 1101 1111 : mod mm r/m

PCMPEQ mm1 with mm2 0000 1111 : 0111 01gg : 11 mm1 mm2mm with mem 0000 1111 : 0111 01gg : mod mm r/m

PCMPGT mm1 with mm2 0000 1111 : 0110 01gg : 11 mm1 mm2mm with mem 0000 1111 : 0110 01gg : mod mm r/m

PMADD mm2 to mm1 0000 1111 : 1111 0101 : 11 mm1 mm2mem to mm 0000 1111 : 1111 0101 : mod mm r/m

PMULH mm2 to mm1 0000 1111 : 1110 0101 : 11 mm1 mm2mem to mm 0000 1111 : 1110 0101 : mod mm r/m

PMULL mm2 to mm1 0000 1111 : 1101 0101 : 11 mm1 mm2mem to mm 0000 1111 : 1101 0101 : mod mm r/m

POR mm2 to mm1 0000 1111 : 1110 1011 : 11 mm1 mm2mem to mm 0000 1111 : 1110 1011 : mod mm r/m

PSLL mm1 by mm2 0000 1111 : 1111 00gg : 11 mm1 mm2mm by mem 0000 1111 : 1111 00gg : mod mm r/mmm by i 0000 1111 : 0111 00gg : 11 110 mm : i8

PSRA mm1 by mm2 0000 1111 : 1110 00gg : 11 mm1 mm2mm by mem 0000 1111 : 1110 00gg : mod mm r/mmm by i 0000 1111 : 0111 00gg : 11 100 mm : i8

PSRL mm1 by mm2 0000 1111 : 1101 00gg : 11 mm1 mm2mm by mem 0000 1111 : 1101 00gg : mod mm r/mmm by i 0000 1111 : 0111 00gg : 11 010 mm : i8

PSUB mm1 to mm2 0000 1111 : 1111 10gg : 11 mm1 mm2mm to mem 0000 1111 : 1111 10gg : mod mm r/m

PSUBS mm1 to mm2 0000 1111 : 1110 10gg : 11 mm1 mm2mm to mem 0000 1111 : 1110 10gg : mod mm r/m

PSUBUS mm1 to mm2 0000 1111 : 1101 10gg : 11 mm1 mm2mm to mem 0000 1111 : 1101 10gg : mod mm r/m

PUNPCKH mm2 to mm1 0000 1111 : 0110 10gg : 11 mm1 mm2mem to mm 0000 1111 : 0110 10gg : mod mm r/m

PUNPCKL mm2 to mm1 0000 1111 : 0110 00gg : 11 mm1 mm2mem to mm 0000 1111 : 0110 00gg : mod mm r/m

PXOR mm2 to mm1 0000 1111 : 1110 1111 : 11 mm1 mm2mem to mm 0000 1111 : 1110 1111 : mod mm r/m

FXRSTOR 0000 1111 : 1010 1110 : 01 m512MULSS xm to xm 1111 0011 : 0000 1111 : 0101 1001 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1001 : mod xm r/m

ORPS xm to xm 0000 1111 : 0101 0110 : 11 xm1 xm2mem to xm 0000 1111 : 0101 0110 : mod xm r/m

mem to xm 0000 1111 : 0101 1000 : mod xm r/mADDSS xm to xm 1111 0011 : 0000 1111 : 0101 1000 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1000 : mod xm r/mANDNPS xm to xm 0000 1111 : 0101 0101 : 11 xm1 xm2

mem to xm 0000 1111 : 0101 0101 : mod xm r/mANDPS xm to xm 0000 1111 : 0101 0100 : 11 xm1 xm2

mem to xm 0000 1111 : 0101 0100 : mod xm r/mCMPPS xm to xm, i8 0000 1111 : 1100 0010 : 11 xm1 xm2 : i8

mem to xm, i8 0000 1111 : 1100 0010 : mod xm r/m : i8CMPSS xm to xm, i8 1111 0011 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : i8

mem to xm, i8 1111 0011 : 0000 1111 : 1100 0010 : mod xm r/m : i8COMISS xm to xm 0000 1111 : 0010 1111 : 11 xm1 xm2

mem to xm 0000 1111 : 0010 1111 : mod xm r/mCVTPI2PS mm to xm 0000 1111 : 0010 1010 : 11 xm1 mm1

mem to xm 0000 1111 : 0010 1010 : mod xm r/mCVTPS2PI xm to mm 0000 1111 : 0010 1101 : 11 mm1 xm1

mem to mm 0000 1111 : 0010 1101 : mod mm r/mCVTSI2SS rd to xm1 1111 0011 : 0000 1111 : 0010 1010 : 11 xm rd

mem to xm 1111 0011 : 0000 1111 : 0010 1010 : mod xm r/m

CVTSS2SI xm to rd 1111 0011 : 0000 1111 : 0010 1101 : 11 rd xm

mem to rd 1111 0011 : 0000 1111 : 0010 1101 : mod rd r/m

CVTTPS2PI xm to mm 0000 1111 : 0010 1100 : 11 mm1 xm1mem mm 0000 1111 : 0010 1100 : mod mm r/m

CVTTSS2SI xm to rd 1111 0011 : 0000 1111 : 0010 1100 : 11 rd xm1mem to rd 1111 0011 : 0000 1111 : 0010 1100 : mod rd r/m

DIVPS xm to xm 0000 1111 : 0101 1110 : 11 xm1 xm2mem to xm 0000 1111 : 0101 1110 : mod xm r/m

DIVSS xm to xm 1111 0011 : 0000 1111 : 0101 1110 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1110 : mod xm r/m

LDMXCSR md to MXCSR 0000 1111 : 1010 1110 : 10 mdMAXPS xm to xm 0000 1111 : 0101 1111 : 11 xm1 xm2

mem to xm 0000 1111 : 0101 1111 : mod xm r/mMAXSS xm to xm 1111 0011 : 0000 1111 : 0101 1111 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1111 : mod xm r/m

MINPS xm to xm 0000 1111 : 0101 1101 : 11 xm1 xm2mem to xm 0000 1111 : 0101 1101 : mod xm r/m

MINSS xm to xm 1111 0011 : 0000 1111 : 0101 1101 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1101 : mod xm r/m

MOVAPS xm2 to xm1 0000 1111 : 0010 1000 : 11 xm2 xm1mem to xm1 0000 1111 : 0010 1000 : mod xm r/mxm1 to xm2 0000 1111 : 0010 1001 : 11 xm1 xm2xm1 to mem 0000 1111 : 0010 1001 : mod xm r/m

MOVHLPS xm to xm 0000 1111 : 0001 0010 : 11 xm1 xm2MOVHPS mem to xm 0000 1111 : 0001 0110 : mod xm r/m

xm to mem 0000 1111 : 0001 0111 : mod xm r/mMOVLHPS xm to xm 0000 1111 : 0001 0110 : 11 xm1 xm2MOVLPS mem to xm 0000 1111 : 0001 0010 : mod xm r/m

xm to mem 0000 1111 : 0001 0011 : mod xm r/mMOVMSKPS xm to rd 0000 1111 : 0101 0000 : 11 rd xmMOVSS xm2 to xm1 1111 0011 : 0000 1111 : 0001 0000 : 11 xm2 xm1

mem to xm1 1111 0011 : 0000 1111 : 0001 0000 : mod xm r/m

xm1 to xm2 1111 0011 : 0000 1111 : 0001 0000 : 11 xm1 xm2

xm1 to mem 1111 0011 : 0000 1111 : 0001 0000 : mod xm r/m

MOVUPS xm2 to xm1 0000 1111 : 0001 0000 : 11 xm2 xm1mem to xm1 0000 1111 : 0001 0000 : mod xm r/mxm1 to xm2 0000 1111 : 0001 0001 : xm1 xm2xm1 to mem 0000 1111 : 0001 0001 : mod xm r/m

MULPS xm to xm 0000 1111 : 0101 1001 : 11 xm1 xm2mem to xm 0000 1111 : 0101 1001 : mod xm r/m

mem to xm 0110 0110 : 0000 1111 : 0101 1000 : mod xm r/m

ADDSD xm to xm 1111 0010 : 0000 1111 : 0101 1000 : 11 xm1 xm2

mem to xm 1111 0010 : 0000 1111 : 0101 1000 : mod xm r/m

RCPPS xm to xm 0000 1111 : 0101 0011 : 11 xm1 xm2mem to xm 0000 1111 : 0101 0011 : mod xm r/m

RCPSS xm to xm 1111 0011 : 0000 1111 : 0101 0011 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 0011 : mod xm r/m

RSQRTPS xm to xm 0000 1111 : 0101 0010 : 11 xm1 xm2mem to xm 0000 1111 : 0101 0010 : mod xm r/m

RSQRTSS xm to xm 1111 0011 : 0000 1111 : 0101 0010 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 0010 : mod xm r/m

SHUFPS xm to xm, i8 0000 1111 : 1100 0110 : 11 xm1 xm2 : i8mem to xm, i8 0000 1111 : 1100 0110 : mod xm r/m : i8

SQRTPS xm to xm 0000 1111 : 0101 0001 : 11 xm1 xm2mem to xm 0000 1111 : 0101 0001 : mod xm r/m

SQRTSS xm to xm 0101 0011 : 0000 1111 : 0101 0001 : 11 xm1 xm2

mem to xm 0101 0011 : 0000 1111 : 0101 0001 : mod xm r/m

STMXCSR MXCSR to mem 0000 1111 : 1010 1110 : 11 mdSUBPS xm to xm 0000 1111 : 0101 1100 : 11 xm1 xm2

mem to xm 0000 1111 : 0101 1100 : mod xm r/mSUBSS xm to xm 1111 0011 : 0000 1111 : 0101 1100 : 11 xm1 xm2

mem to xm 1111 0011 : 0000 1111 : 0101 1100 : mod xm r/m

UCOMISS xm to xm 0000 1111 : 0010 1110 : 11 xm1 xm2mem to xm 0000 1111 : 0010 1110 : mod xm r/m

UNPCKHPS xm to xm 0000 1111 : 0001 0101 : 11 xm1 xm2mem to xm 0000 1111 : 0001 0101 mod xm r/m

UNPCKLPS xm to xm 0000 1111 : 0001 0100 : 11 xm1 xm2mem to xm 0000 1111 : 0001 0100 : mod xm r/m

XORPS xm to xm 0000 1111 : 0101 0111 : 11 xm1 xm2mem to xm 0000 1111 : 0101 0111 : mod xm r/m

PAVGB mm to mm 0000 1111 : 1110 0000 : 11 mm1 mm2mem to mm 0000 1111 : 1110 0000 : mod mm r/m

PAVGW mm to mm 0000 1111 : 1110 0011 : 11 mm1 mm2mem to mm 0000 1111 : 1110 0011 : mod mm r/m

PEXTRW mm to rd, ib 0000 1111 : 1100 0101 : 11 rd mm : ibPINSRW rd to mm, ib 0000 1111 : 1100 0100 : 11 mm rd : ib

mw to mm, ib 0000 1111 : 1100 0100 : mod mm r/m : ibPMAXSW mm to mm 0000 1111 : 1110 1110 : 11 mm1 mm2

mem to mm 0000 1111 : 1110 1110 : mod mm r/mPMAXUB mm to mm 0000 1111 : 1101 1110 : 11 mm1 mm2

mem to mm 0000 1111 : 1101 1110 : mod mm r/mPMINSW mm to mm 0000 1111 : 1110 1010 : 11 mm1 mm2

mem to mm 0000 1111 : 1110 1010 : mod mm r/mPMINUB mm to mm 0000 1111 : 1101 1010 : 11 mm1 mm2

mem to mm 0000 1111 : 1101 1010 : mod mm r/mPMOVMSKB mm to rd 0000 1111 : 1101 0111 : 11 mm rdPMULHUW mm to mm 0000 1111 : 1110 0100 : 11 mm1 mm2

mem to mm 0000 1111 : 1110 0100 : mod mm r/mPSADBW mm to mm 0000 1111 : 1111 0110 : 11 mm1 mm2

mem to mm 0000 1111 : 1111 0110 : mod mm r/mPSHUFW mm to mm, ib 0000 1111 : 0111 0000 : 11 mm1 mm2 : ib

mem to mm, ib 0000 1111 : 0111 0000 : mod mm r/m : ibMASKMOVQ mm to mm 0000 1111 : 1111 0111 : 11 mm1 mm2MOVNTPS xm to mem 0000 1111 : 0010 1011 : mod xm r/mMOVNTQ mm to mem 0000 1111 : 1110 0111 : mod mm r/mPREFETCH0 0000 1111 : 0001 1000 : 01 memPREFETCH1 0000 1111 : 0001 1000 : 10 memPREFETCH2 0000 1111 : 0001 1000 : 11 memPREFETCHNTA 0000 1111 : 0001 1000 : 00 memSFENCE 0000 1111 : 1010 1110 : 1111 1000ADDPD xm to xm 0110 0110 : 0000 1111 : 0101 1000 : 11 xm1 xm2

xm to mem 0110 0110 : 0000 1111 : 0001 0010 : mod xm r/m

MOVMSKPD xm to rd 0110 0110 : 0000 1111 : 0101 0000 : 11 rd xm

MOVSD xm2 xm1 1111 0010 : 0000 1111 : 0001 0001 : 11 xm2 xm1

mem to xm1 1111 0010 : 0000 1111 : 0001 0001 : mod xm r/m

ANDNPD xm to xm 0110 0110 : 0000 1111 : 0101 0101 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 0101 : mod xm r/m

ANDPD xm to xm 0110 0110 : 0000 1111 : 0101 0100 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 0100 : mod xm r/m

CMPPD xm to xm, ib 0110 0110 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : ibmem to xm, ib 0110 0110 : 0000 1111 : 1100 0010 : mod xm r/m : ib

CMPSDxm to xm, ib 1111 0010 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : ibmem to xm, ib 1111 0010 : 0000 1111 : 1100 0010 : mod xm r/m : ib

COMISD xm to xm 0110 0110 : 0000 1111 : 0010 1111 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0010 1111 : mod xm r/m

CVTPI2PD mm to xm 0110 0110 : 0000 1111 : 0010 1010 : 11 xm1 mm1mem to mm 0110 0110 : 0000 1111 : 0010 1010 : mod xm r/m

CVTPD2PI xm to mm 0110 0110 : 0000 1111 : 0010 1101 : 11 mm1 xm1mem to mm 0110 0110 : 0000 1111 : 0010 1101 : mod mm r/m

CVTSI2SD rd to xm1 1111 0010 : 0000 1111 : 0010 1010 : 11 xm rdmem to xm 1111 0010 : 0000 1111 : 0010 1010 : mod xm r/m

CVTSD2SI xm to rd 1111 0010 : 0000 1111 : 0010 1101 : 11 rd xmmem to rd 1111 0010 : 0000 1111 : 0010 1101 : mod rd r/m

CVTTPD2PI xm to mm 0110 0110 : 0000 1111 : 0010 1100 : 11 mm xmmem to mm 0110 0110 : 0000 1111 : 0010 1100 : mod mm r/m

CVTTSD2SI xm to rd 1111 0010 : 0000 1111 : 0010 1100 : 11 rd xm

mem to rd 1111 0010 : 0000 1111 : 0010 1100 : mod rd r/m

CVTPD2PS xm to xm 0110 0110 : 0000 1111 : 0101 1010 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 1010 : mod xm r/m

CVTPS2PD xm to xm 0000 1111 : 0101 1010 : 11 xm1 xm2mem to xm 0000 1111 : 0101 1010 : mod xm r/m

CVTSD2SS xm to xm 1111 0010 : 0000 1111 : 0101 1010 : 11 xm1 xm2

mem to xm 1111 0010 : 0000 1111 : 0101 1010 : mod xm r/m

CVTSS2SD xm to xm 1111 0011 : 0000 1111 : 0101 1010 : 11 xm1 xm2mem to xm 1111 0011 : 0000 1111 : 0101 1010 : mod xm r/m

CVTPD2DQ xm to xm 1111 0010 : 0000 1111 : 1110 0110 : 11 xm1 xm2mem to xm 1111 0010 : 0000 1111 : 1110 0110 : mod xm r/m

CVTTPD2DQ xm to xm 0110 0110 : 0000 1111 : 1110 0110 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 0110 : mod xm r/m

CVTDQ2PD xm to xm 1111 0011 : 0000 1111 : 1110 0110 : 11 xm1 xm2mem to xm 1111 0011 : 0000 1111 : 1110 0110 : mod xm r/m

CVTPS2DQ xm to xm 0110 0110 : 0000 1111 : 0101 1011 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0101 1011 : mod xm r/m

CVTTPS2DQ xm to xm 1111 0011 : 0000 1111 : 0101 1011 : 11 xm1 xm2mem to xm 1111 0011 : 0000 1111 : 0101 1011 : mod xm r/m

CVTDQ2PS xm to xm 0000 1111 : 0101 1011 : 11 xm1 xm2mem to xm 0000 1111 : 0101 1011 : mod xm r/m

DIVPD xm to xm 0110 0110 : 0000 1111 : 0101 1110 : 11 xm1 xm2

mem to xm 0110 0010 : 0000 1111 : 0101 1110 : mod xm r/m

DIVSD xm to xm 1111 0010 : 0000 1111 : 0101 1110 : 11 xm1 xm2

mem to xm 1111 0010 : 0000 1111 : 0101 1110 : mod xm r/m

MAXPD xm to xm 0110 0110 : 0000 1111 : 0101 1111 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 1111 : mod xm r/m

MAXSD xm to xm 1111 0010 : 0000 1111 : 0101 1111 : 11 xm1 xm2

mem to xm 1111 0010 : 0000 1111 : 0101 1111 : mod xm r/m

MINPD xm to xm 0110 0110 : 0000 1111 : 0101 1101 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 1101 : mod xm r/m

MINSD xm to xm 1111 0010 : 0000 1111 : 0101 1101 : 11 xm1 xm2

mem to xm 1111 0010 : 0000 1111 : 0101 1101 : mod xm r/m

MOVAPD xm2 to xm1 0110 0110 : 0000 1111 : 0010 1001 : 11 xm2 xm1

mem to xm1 0110 0110 : 0000 1111 : 0010 1001 : mod xm r/m

xm1 to xm2 0110 0110 : 0000 1111 : 0010 1000 : 11 xm1 xm2xm1 to mem 0110 0110 : 0000 1111 : 0010 1000 : mod xm r/m

MOVHPD mem to xm 0110 0110 : 0000 1111 : 0001 0111 : mod xm r/m

xm to mem 0110 0110 : 0000 1111 : 0001 0110 : mod xm r/m

MOVLPD mem to xm 0110 0110 : 0000 1111 : 0001 0011 : mod xm r/m

mem to xm 0110 0110 : 0000 1111 : 1110 11gg : mod xm r/m

PADDUS xm2 to xm1 0110 0110 : 0000 1111 : 1101 11gg : 11 xm1 xm2

xm1 to xm2 1111 0010 : 0000 1111 : 0001 0000 : 11 xm1 xm2xm1 to mem 1111 0010 : 0000 1111 : 0001 0000 : mod xm r/m

MOVUPD xm2 to xm1 0110 0110 : 0000 1111 : 0001 0001 : 11 xm2 xm1mem to xm1 0110 0110 : 0000 1111 : 0001 0001 : mod xm r/m

xm1 to xm2 0110 0110 : 0000 1111 : 0001 0000 : 11 xm1 xm2xm1 to mem 0110 0110 : 0000 1111 : 0001 0000 : mod xm r/m

MULPD xm to xm 0110 0110 : 0000 1111 : 0101 1001 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0101 1001 : mod xm r/m

MULSD xm to xm 1111 0010 : 0000 1111 : 0101 1001 : 11 xm1 xm2mem to xm 1111 0010 : 0000 1111 : 0101 1001 : mod xm r/m

ORPD xm to xm 0110 0110 : 0000 1111 : 0101 0110 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0101 0110 : mod xm r/m

SHUFPD xm to xm, ib 0110 0110 : 0000 1111 : 1100 0110 : 11 xm1 xm2 : ibmem to xm, ib 0110 0110 : 0000 1111 : 1100 0110 : mod xm r/m : ib

SQRTPD xm to xm 0110 0110 : 0000 1111 : 0101 0001 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0101 0001 : mod xm r/m

SQRTSD xm to xm 1111 0010 : 0000 1111 : 0101 0001 : 11 xm1 xm2mem to xm 1111 0010 : 0000 1111 : 0101 0001 : mod xm r/m

SUBPD xm to xm 0110 0110 : 0000 1111 : 0101 1100 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0101 1100 : mod xm r/m

SUBSD xm to xm 1111 0010 : 0000 1111 : 0101 1100 : 11 xm1 xm2mem to xm 1111 0010 : 0000 1111 : 0101 1100 : mod xm r/m

UCOMISD xm to xm 0110 0110 : 0000 1111 : 0010 1110 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0010 1110 : mod xm r/m

UNPCKHPD xm to xm 0110 0110 : 0000 1111 : 0001 0101 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0001 0101 : mod xm r/m

UNPCKLPD xm to xm 0110 0110 : 0000 1111 : 0001 0100 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0001 0100 : mod xm r/m

XORPD xm to xm 0110 0110 : 0000 1111 : 0101 0111 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0101 0111 : mod xm r/m

MOVD reg to xm 0110 0110 : 0000 1111 : 0110 1110 : 11 xm reg

xm to reg 0110 0110 : 0000 1111 : 0111 1110 : 11 xm regmem to xm 0110 0110 : 0000 1111 : 0110 1110 : mod xm r/mxm to mem 0110 0110 : 0000 1111 : 0111 1110 : mod xm r/m

MOVDQA xm2 to xm1 0110 0110 : 0000 1111 : 0110 1111 : 11 xm1 xm2xm1 to xm2 0110 0110 : 0000 1111 : 0111 1111 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0110 1111 : mod xm r/mxm to mem 0110 0110 : 0000 1111 : 0111 1111 : mod xm r/m

MOVDQU xm2 to xm1 1111 0011 : 0000 1111 : 0110 1111 : 11 xm1 xm2xm1 to xm2 1111 0011 : 0000 1111 : 0111 1111 : 11 xm1 xm2mem to xm 1111 0011 : 0000 1111 : 0110 1111 : mod xm r/mxm to mem 1111 0011 : 0000 1111 : 0111 1111 : mod xm r/m

MOVQ2DQ mm to xm 1111 0011 : 0000 1111 : 1101 0110 : 11 mm1 mm2

MOVDQ2Q xm to mm 1111 0010 : 0000 1111 : 1101 0110 : 11 mm1 mm2

MOVQ mm2 to mm1 0110 0110 : 0000 1111 : 0111 1110 : 11 xm1 xm2

mm1 to mm2 0110 0110 : 0000 1111 : 1101 0110 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0111 1110 : mod xm r/m

xm to mem 0110 0110 : 0000 1111 : 1101 0110 : mod xm r/mPACKSSDW xm2 to xm1 0110 0110 : 0000 1111 : 0110 1011 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0110 1011 : mod xm r/mPACKSSWB xm2 to xm1 0110 0110 : 0000 1111 : 0110 0011 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0110 0011 : mod xm r/mPACKUSWB xm2 to xm1 0110 0110 : 0000 1111 : 0110 0111 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 0110 0111 : mod xm r/m

PADDQ mm to mm 0000 1111 : 1101 0100 : 11 mm1 mm2mem to mm 0000 1111 : 1101 0100 : mod mm r/mxm to xm 0110 0110 : 0000 1111 : 1101 0100 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1101 0100 : mod xm r/m

PADD xm2 to xm1 0110 0110 : 0000 1111 : 1111 11gg : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 1111 11gg : mod xm r/m

PADDS xm2 to xm1 0110 0110 : 0000 1111 : 1110 11gg : 11 xm1 xm2

xm to mem 0110 0110 : 0000 1111 : 1110 10gg : mod xm r/m

PSUBUS xm1 to xm2 0000 1111 : 1101 10gg : 11 xm1 xm2xm to mem 0000 1111 : 1101 10gg : mod xm r/m

PUNPCKH xm to xm 0110 0110 : 0000 1111 : 0110 10gg : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 1101 11gg : mod xm r/m

PAND xm2 to xm1 0110 0110 : 0000 1111 : 1101 1011 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 1101 1011 : mod xm r/m

PANDN xm2 to xm1 0110 0110 : 0000 1111 : 1101 1111 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 1101 1111 : mod xm r/m

PAVGB xm to xm 0110 0110 : 0000 1111 : 1110 0000 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 0000 : mod xm r/m

PAVGW xm to xm 0110 0110 : 0000 1111 : 1110 0011 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 0011 : mod xm r/m

PCMPEQ xm1 with xm2 0110 0110 : 0000 1111 : 0111 01gg : 11 xm1 xm2xm with mem 0110 0110 : 0000 1111 : 0111 01gg : mod xm r/m

PCMPGT xm1 with xm2 0110 0110 : 0000 1111 : 0110 01gg : 11 xm1 xm2xm with mem 0110 0110 : 0000 1111 : 0110 01gg : mod xm r/m

PEXTRW xm to rd, ib 0110 0110 : 0000 1111 : 1100 0101 : 11 rd xm : ib

PINSRW rd to xm, ib 0110 0110 : 0000 1111 : 1100 0100 : 11 xm rd : ib

mw to xm, ib 0110 0110 : 0000 1111 : 1100 0100 : mod xm r/m : ib

PMADD xm2 to xm1 0110 0110 : 0000 1111 : 1111 0101 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1111 0101 : mod xm r/m

PMAXSW xm to xm 0110 0110 : 0000 1111 : 1110 1110 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 1110 : mod xm r/m

PMAXUB xm to xm 0110 0110 : 0000 1111 : 1101 1110 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1101 1110 : mod xm r/m

PMINSW xm to xm 0110 0110 : 0000 1111 : 1110 1010 : 11 xm1 xm2

mem to xm 0110 0110 : 0000 1111 : 1110 1010 : mod xm r/m

PMINUB xm to xm 0110 0110 : 0000 1111 : 1101 1010 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1101 1010 : mod xm r/m

PMOVMSKB xm to rd 0110 0110 : 0000 1111 : 1101 0111 : 11 xm rd

PMULH xm2 to xm1 0110 0110 : 0000 1111 : 1110 0101 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 0101 : mod xm r/m

PMULL xm2 to xm1 0110 0110 : 0000 1111 : 1101 0101 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1101 0101 : mod xm r/m

PMULUDQ mm to mm 0000 1111 : 1111 0100 : 11 mm1 mm2mem to mm 0000 1111 : 1111 0100 : mod mm r/mxm to xm 0110 0110 : 0000 1111 : 1111 0100 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1111 0100 : mod xm r/m

POR xm2 to xm1 0110 0110 : 0000 1111 : 1110 1011 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 1011 : mod xm r/m

PSADBW xm to xm 0110 0110 : 0000 1111 : 1111 0110 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1111 0110 : mod xm r/m

PSHUFLW xm to xm, ib 1111 0010 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ibmem to xm, ib 1111 0010 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib

PSHUFHW xm to xm, ib 1111 0011 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ibmem to xm, ib 1111 0011 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib

PSHUFD xm to xm, ib 0110 0110 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ibmem to xm, ib 0110 0110 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib

PSLLDQ xm, ib 0110 0110 : 0000 1111 : 0111 0011 : 11 111 xm : ib

PSLL xm1 by xm2 0110 0110 : 0000 1111 : 1111 00gg : 11 xm1 xm2

xm by mem 0110 0110 : 0000 1111 : 1111 00gg : mod xm r/m

xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 110 xm : ib

PSRA xm1 by xm2 0110 0110 : 0000 1111 : 1110 00gg : 11 xm1 xm2

xm by mem 0110 0110 : 0000 1111 : 1110 00gg : mod xm r/m

xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 100 xm : ib

PSRLDQ xm, ib 0110 0110 : 0000 1111 : 0111 0011 : 11 011 xm : ib

PSRL xm1 by xm2 0110 0110 : 0000 1111 : 1101 00gg : 11 xm1 xm2

xm by mem 0110 0110 : 0000 1111 : 1101 00gg : mod xm r/m

xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 010 xm : ib

PSUBQ mm to mm 0000 1111 : 1111 1011 : 11 mm1 mm2mem to mm 0000 1111 : 1111 1011 : mod mm r/mxm to xm 0110 0110 : 0000 1111 : 1111 1011 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1111 1011 : mod xm r/m

PSUB xm1 to xm2 0110 0110 : 0000 1111 : 1111 10gg : 11 xm1 xm2

xm to mem 0110 0110 : 0000 1111 : 1111 10gg : mod xm r/m

PSUBS xm1 to xm2 0110 0110 : 0000 1111 : 1110 10gg : 11 xm1 xm2

FICOMP 16-bit mem 11011 110 : mod 011 r/m32-bit mem 11011 010 : mod 011 r/m

mem to xm 0110 0110 : 0000 1111 : 0110 10gg : mod xm r/m

PUNPCKHQDQ xm to xm 0110 0110 : 0000 1111 : 0110 1101 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0110 1101 : mod xm r/m

PUNPCKL xm to xm 0110 0110 : 0000 1111 : 0110 00gg : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0110 00gg : mod xm r/m

PUNPCKLQDQ xm to xm 0110 0110 : 0000 1111 : 0110 1100 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 0110 1100 : mod xm r/m

PXOR xm2 to xm1 0110 0110 : 0000 1111 : 1110 1111 : 11 xm1 xm2mem to xm 0110 0110 : 0000 1111 : 1110 1111 : mod xm r/m

MASKMOVDQU xm to xm 0110 0110 : 0000 1111 : 1111 0111 : 11 xm1 xm2

CLFLUSH mem 0000 1111 : 1010 1110 : mod r/mMOVNTPD xm to mem 0110 0110 : 0000 1111 : 0010 1011 : mod xm r/m

MOVNTDQxm to mem 0110 0110 : 0000 1111 : 1110 0111 : mod xm r/m

MOVNTI reg to mem 0000 1111 : 1100 0011 : mod reg r/mPAUSE 1111 0011 : 1001 0000LFENCE 0000 1111 : 1010 1110 : 11 101 000MFENCE 0000 1111 : 1010 1110 : 11 110 000F2XM1 11011 001 : 1111 0000FABS 11011 001 : 1110 0001FADD ST(0) ← ST(0) + 32-bit mem 11011 000 : mod 000 r/m

ST(0) ← ST(0) + 64-bit mem 11011 100 : mod 000 r/mST(d) ← ST(0) + ST(i) 11011 d00 : 11 000 ST(i)

FADDP ST(0) ← ST(0) + ST(i) 11011 110 : 11 000 ST(i)FBLD 11011 111 : mod 100 r/mFBSTP 11011 111 : mod 110 r/mFCHS 11011 001 1110 0000FCLEX 11011 011 : 1110 0010FCMOVcc Below (B) 11011 010 : 11 000 ST(i)

Equal (E) 11011 010 : 11 001 ST(i)Below or Equal (BE) 11011 010 : 11 010 ST(i)Unordered (U) 11011 010 : 11 011 ST(i)Not Below (NB) 11011 011 : 11 000 ST(i)Not Equal (NE) 11011 011 : 11 001 ST(i)Not Below or Equal (NBE) 11011 011 : 11 010 ST(i)Not Unordered (NU) 11011 011 : 11 011 ST(i)

FCOM 32-bit mem 11011 000 : mod 010 r/m64-bit mem 11011 100 : mod 010 r/mST(i) 11011 000 : 11 010 ST(i)

FCOMP 32-bit mem 11011 000 : mod 011 r/m64-bit mem 11011 100 : mod 011 r/mST(i) 11011 000 : 11 011 ST(i)

FCOMPP 11011 110 : 11 011 001FCOMI 11011 011 : 11 110 ST(i)FCOMIP 11011 111 : 11 110 ST(i)FCOS 11011 001 : 1111 1111FDECSTP 11011 001 : 1111 0110FDIV ST(0) ← ST(0) / 16-bit mem 11011 000 : mod 110 r/m

ST(0) ← ST(0) / 64-bit mem 11011 100 : mod 110 r/mST(d) ← ST(0) / ST(i) 11011 d00 : 1111 R ST(i)

FDIVP ST(0) ← ST(0) / ST(i) 11011 110 : 1111 1 ST(i)FDIVR ST(0) ← 32-bit mem / ST(0) 11011 000 : mod 111 r/m

ST(0) ← 64-bit mem / ST(0) 11011 100 : mod 111 r/mST(d) ← ST(i) / ST(0) 11011 d00 : 1111 R ST(i)

FDIVRP ST(0) ← ST(i) / ST(0) 11011 110 : 1111 0 ST(i)FFREE 11011 101 : 1100 0 ST(i)FIADD ST(0) ← ST(0) / 16-bit mem 11011 110 : mod 000 r/m

ST(0) ← ST(0) / 32-bit mem 11011 010 : mod 000 r/mFICOM 16-bit mem 11011 110 : mod 010 r/m

32-bit mem 11011 010 : mod 010 r/mFSUB ST(0) ← ST(0) – 32-bit mem 11011 000 : mod 100 r/m

ST(0) ← ST(0) – 64-bit mem 11011 100 : mod 100 r/mST(d) ← ST(0) – ST(i) 11011 d00 : 1110 R ST(i)

FIDIV ST(0) ← ST(0) / 16-bit mem 11011 110 : mod 110 r/mST(0) ← ST(0) / 32-bit mem 11011 010 : mod 110 r/m

FIDIVR ST(0) ← 16-bit mem / ST(0) 11011 110 : mod 111 r/mST(0) ← 32-bit mem / ST(0) 11011 010 : mod 111 r/m

FILD 16-bit mem 11011 111 : mod 000 r/m32-bit mem 11011 011 : mod 000 r/m64-bit mem 11011 111 : mod 101 r/m

FIMUL ST(0) ← ST(0) * 16-bit mem 11011 110 : mod 001 r/mST(0) ← ST(0) * 32-bit mem 11011 010 : mod 001 r/m

FINCSTP 11011 001 : 1111 0111FINIT 11011 011 : 1110 0011FIST 16-bit mem 11011 111 : mod 010 r/m

32-bit mem 11011 011 : mod 010 r/mFISTP 16-bit mem 11011 111 : mod 011 r/m

32-bit mem 11011 011 : mod 011 r/m64-bit mem 11011 111 : mod 111 r/m

FISUB ST(0) ← ST(0) - 16-bit mem 11011 110 : mod 100 r/mST(0) ← ST(0) - 32-bit mem 11011 010 : mod 100 r/m

FISUBR ST(0) ← 16-bit mem - ST(0) 11011 110 : mod 101 r/mST(0) ← 32-bit mem - ST(0) 11011 010 : mod 101 r/m

FLD 32-bit mem 11011 001 : mod 000 r/m64-bit mem 11011 101 : mod 000 r/m80-bit mem 11011 011 : mod 101 r/mST(i) 11011 001 : 11 000 ST(i)

FLD1 11011 001 : 1110 1000FLDCW 11011 001 : mod 101 r/mFLDENV 11011 001 : mod 100 r/mFLDL2E 11011 001 : 1110 1010FLDL2T 11011 001 : 1110 1001FLDLG2 11011 001 : 1110 1100FLDLN2 11011 001 : 1110 1101FLDPI 11011 001 : 1110 1011FLDZ 11011 001 : 1110 1110FMUL ST(0) ← ST(0) * 32-bit mem 11011 000 : mod 001 r/m

ST(0) ← ST(0) * 64-bit mem 11011 100 : mod 001 r/mST(d) ← ST(0) * ST(i) 11011 d00 : 1100 1 ST(i)

FMULP ST(0) ← ST(0) * ST(i) 11011 110 : 1100 1 ST(i)FNOP 11011 001 : 1101 0000FPATAN 11011 001 : 1111 0011FPREM 11011 001 : 1111 1000FPREM1 11011 001 : 1111 0101FPTAN 11011 001 : 1111 0010FRNDINT 11011 001 : 1111 1100FRSTOR 11011 101 : mod 100 r/mFSAVE 11011 101 : mod 110 r/mFSCALE 11011 001 : 1111 1101FSIN 11011 001 : 1111 1110FSINCOS 11011 001 : 1111 1011FSQRT 11011 001 : 1111 1010FST 32-bit mem 11011 001 : mod 010 r/m

64-bit mem 11011 101 : mod 010 r/mST(i) 11011 101 : 11 010 ST(i)

FSTCW 11011 001 : mod 111 r/mFSTENV 11011 001 : mod 110 r/mFSTP 32-bit mem 11011 001 : mod 011 r/m

64-bit mem 11011 101 : mod 011 r/m80-bit mem 11011 011 : mod 111 r/mST(i) 11011 101 : 11 011 ST(i)

FSTSW AX ¬ FPU Status Word 11011 111 : 1110 0000mem ¬ FPU Status Word 11011 101 : mod 111 r/m

mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0100

PFMIN mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0100

FSUBP ST(0) ← ST(0) – ST(i) 11011 110 : 1110 1 ST(i)FSUBR ST(0) ← 32-bit mem - ST(0) 11011 000 : mod 101 r/m

ST(0) ← 64-bit mem - ST(0) 11011 100 : mod 101 r/mST(d) ← ST(i) – ST(0) 11011 d00 : 1110 R ST(i)

FSUBRP ST(i) ← ST(i) – ST(0) 11011 110 : 1110 0 ST(i)FTST 11011 001 : 1110 0100FUCOM 11011 101 : 1110 0 ST(i)FUCOMP 11011 101 : 1110 1 ST(i)FUCOMPP 11011 010 : 1110 1001FUCOMI 11011 011 : 11 101 ST(i)FUCOMIP 11011 111 : 11 101 ST(i)FXAM 11011 001 : 1110 0101FXCH 11011 001 : 1100 1 ST(i)FXTRACT 11011 001 : 1111 0100FYL2X 11011 001 : 1111 0001FYL2XP1 11011 001 : 1111 1001FWAIT 1001 1011PAVGUSB mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 1111

mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 1111

PF2ID mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0001 1101mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0001 1101

PF2IW mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0001 1100mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0001 1100

PFACC mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 1110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 1110

PFADD mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 1110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 1110

PFCMPEQ mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0000mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0000

PFCMPGE mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0000mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0000

PFCMPGT mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0000mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0000

PFMAX mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0100

PFMAX mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0100

mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0100

PFMUL mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0100mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0100

PFNACC mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1000 1010mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1000 1010

PFPNACC mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1000 1110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1000 1110

PFRCP mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0110

PFRCPIT1 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0110

PFRCPIT2 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0110mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0110

PFRSQIT1 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0111mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0111

PFRSQRT mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0111mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0111

PFSUB mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 1010mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 1010

PFSUBR mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 1010mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 1010

PI2FD mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1101mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0000 1101

PI2FD mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1101mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0000 1101

PI2FW mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1100mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0000 1100

PMULHRW mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0111mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0111

PREFETCH mm2 to mm1 0000 1111 : 0000 1101 : 11 000 mmmem to mm 0000 1111 : 0000 1101 : mod 000 r/m

PREFETCHW mm2 to mm1 0000 1111 : 0000 1101 : 11 001 mmmem to mm 0000 1111 : 0000 1101 : mod 001 r/m

PSWAPD mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 1011mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 1011

FEMMS 0000 1111 : 0000 1110

Pentium 6th Generation & NetBurst Processor Micro-Architectures with Interface to Memory Subsystem:

System Bus (64-bit)←———–——→

1st Level Cache Architecture Diagram: Execution Units/Portsin Out-of-Order Core:

Load Unit(16 entry buffer)

Store Addr. (12 entry)

Store Data(12 entry)

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8 ↕

Reservation Station

−−−

───┘ Port 2 Port 3 ↑

↑ Port 4

Bus Interface Unit Banks interleaved on 4-byte memory boundaries−−−

−−−−−−−−−−

− −−−−┘ │

↕ 486 - 128 * 16-B lines * 4 sets = 8KPentium - 128 * 32-B lines * 2 sets = 8KP2/P3 - 128 * 32-B lines * 4 sets = 16KP4 - 32 * 64-B lines * 4 sets = 8K

−−−−−−−−−−−−−

−−−−−−−−

−−┘

3rd Level Cache(NB server option)

−−− −−−−−−−−−−

−−−−−−−− ┐

−−− ┐ Port 0 (U) ↓ Port 1 (V)

↕ NetBurst has only 4 ports. Integer/FP, addr. generate, MMX,P3 FP, NB ALU 0 (2x), FP Move

Integer, MMX, P3 FP, NB ALU1 (2x speed), Int. Operation (normal speed), FP Execute

2nd Level Cache (4-way P6, 8-way NB)

↔ 1st Level Cache (Pro Data 2-way; 4-way P2, P3, & NB)

It stores mem addresses in port 3 & data in port 0.

↓ ↕

1st Level Instruction Cache (Pro, P2, & P3 4-way set associative)

→←

Front End 12K µops 8-way

→ Execution (Out-Of-Order Core) →

Retirement(In-Order unit) ↔

IntelArchitecture Registers(Reg Retire File)

Fetch/Decode(In-Order issue)

→ NB Trace Cache Microcode Rom

IFU0 IFU1 IFU2 ID0 ID1 RAT ROB Rd RS Port 0-4 ROB Wb 3 µops in cycle

↑ ↑ Branch History Update │BTBs/Branch Prediction (P6 256 entry BTB, NB 512 entry) BTB0 BTB1 ←———–————————— ┘

Information Returned by CPUID InstructionInitial EAX Value Information Provided about the Processor

Basic CPU Information

0H

EAX Maximum Input Value for Basic CPUID InformationEBX “Genu”ECX “ntel”EDX “ineI”

1H

EAX Version Information (Type, Family, Model, and Stepping ID)EBX Bits 7-0: Brand Index

Bits 15-8: CLFLUSH line size. (Value returned * 8 = cache line size)Bits 23-16: ReservedBits 31-24: Processor local APIC physical ID

ECX ReservedEDX Feature Information

2H

EAX Cache and TLB Information Byte register AL indicates the number of times the CPUID instruction mustEBX Cache and TLB Information be executed with an input value of 2 to get a complete description of theECX Cache and TLB Information processor’s caches and TBLs. Bit 31 of each register indicates if it containsEDX Cache and TLB Information valid info. (cleared is 0, reserved is 1). Info. (any order) in 1 B descriptors.

3H

EAX ReservedEBX ReservedECX Bits 00-31 of 96-bit processor serial number. (Available in Pentium III only; otherwise reserved.)EDX Bits 32-63 of 96-bit processor serial number. (Available in Pentium III only; otherwise reserved.) Extended Function CPUID Information

80000000H

EAX Maximum Input Value for Extended Function CPUID InformationEBX Reserved.ECX Reserved.EDX Reserved.

80000001H

EAX Extended Processor Signature and Extended Feature Bits. (Currently Reserved.)EBX Reserved.ECX Reserved.EDX Reserved.

80000002H

EAX Processor Brand String.EBX Processor Brand String Continued.ECX Processor Brand String Continued.EDX Processor Brand String Continued.

80000003H

EAX Processor Brand String Continued.EBX Processor Brand String Continued.ECX Processor Brand String Continued.EDX Processor Brand String Continued.

80000004H

EAX Processor Brand String Continued.EBX Processor Brand String Continued.ECX Processor Brand String Continued.EDX Processor Brand String Continued.

Highest CPUID Source Operand for IA-32 Processors

IA-32 Processors Highest Value in EAX Basic Information Extended Function Information

Earlier Intel486 Processors CPUID Not Implemented CPUID Not ImplementedLater Intel486 and Pentium Processors 1H Not ImplementedPentium Pro, II, and Celeron Processors 2H Not ImplementedPentium III Processors 3H Not ImplementedPentium 4 Processors 2H 80000004HIntel Xenon Processors 2H 80000004H

31 28 27 20 19 16 15 14 13 12 11 8 7 4 3 0 Type Encoding

EAXExtended Family

Extended Model

Family Model Stepping ID

Original OEM Processor 00BIntel OverDrive Processor 01B

Processor Type ─────────────┘ Duel Processor 10B Processor Type Field Chart → Intel Reserved. 11B

CPUID Feature Flags Returned in EDX RegisterBit # Mnemonic Description 0 FPU Floating Point Unit On-Chip. The Processor contains an x87 FPU.

1 VMEVirtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.

2 DEDebugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.

3 PSEPage Size Extension. Large pages of size 4Mb are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.

4 TSC Time Stamp Counter. The RDTSC instruction is supported, including CR4.PSE for controlling privilege.

5 MSRModel Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.

6 PAEPhysical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2 Mb pages are supported instead if 4 Mb pages if PAE bit is 1. The actual number of address bits beyond 32 is not defined, and is implementation specific.

7 MCE

Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.

8 CX8 CMPXCHG8B Instruction. The CMPXCHG8B (64-bits) instruction is supported (implicitly locked & atomic).

9 APICAPIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory-mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default – some processors permit the APIC to be relocated).

10 Reserved Reserved 11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXITand associated MSRs are supported.

12 MTRRMemory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types, how many variable MTRRS, and whether fixed MTRRs are supported.

13 PGEPTE Global Bit. The global bit in page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.

14 MCAMacine Check Architecture. The machine Check Architecture, which provides a compatible mechanism for error reporting in Pentium 4 processors, P6 family processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.

15 CMOVConditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then FCOMI and FCMOV instructions are supported.

16 PATPage Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an OS to specify attributes of memory on a 4K granularity through a linear address.

17 PSE-3632-Bit Page Size Extension. Extended 4-Mb pages that are capable of addressing physical memiry beyond 4 Gb are supported. This feature indicates that the upper four bits of the physical address of the 4-Mb page is encoded by bits 13-16 of the page directory entry.

18 PSN Processor Serial Number. The processor supports the 96-bit processor ID number feature and it is enabled. 19 CLFSH CLFLUSH Instruction. CLFLUSH Instruction is supported. 20 Reserved Reserved

21 DSDebug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities.

22 ACPIThermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.

23 MMX Intel MMX Technology. The processor supports the Intel MMX technology.

24 FXSRFXSAVE and FXRSTOR Instructions. The FXSAVE and FXSTOR instructions are supported for fast save and restore of the floating-point context. Presence if this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXSTOR instructions.

25 SSE SSE. The processor supports the SSE extensions. 26 SSE2 SSE2. The processor supports the SSE2 extensions.

27 SSSelf Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.

28 Reserved Reserved 29 TM Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).30-31 Reserved Reserved

Encoding of Cache and TLB Descriptors Descriptor Value Cache or TLB Description 00H Null Descriptor 01H Instruction TLB: 4 Kb Pages, 4-way set associative, 32 entries 02H Instruction TLB: 4 Mb Pages, 4-way set associative, 2 entries 03H Data TLB: 4 Kb Pages, 4-way set associative, 64 entries 04H Data TLB: 4 Mb Pages, 4-way set associative, 8 entries 06H 1st level instruction cache: 8 Kb, 4-way set associative, 32 byte line size 08H 1st level instruction cache: 16 Kb, 4-way set associative, 32 byte line size 0AH 1st level data cache: 8 Kb, 2-way set associative, 32 byte line size 0CH 1st level data cache: 16 Kb, 4-way set associative, 32 byte line size 22H 3rd level cache: 512 Kb, 4-way set associative, 64 byte line size 23H 3rd level cache: 1 Mb, 8-way set associative, 64 byte line size 25H 3rd level cache: 2 Mb, 8-way set associative, 64 byte line size 29H 3rd level cache: 4 Mb, 8-way set associative, 64 byte line size 40H No 2nd level cache or, if processor contains a valid 2nd level cache, no 3rd level cache 41H 2nd level cache: 128 Kb, 4-way set associative, 32 byte line size 42H 2nd level cache: 256 Kb, 4-way set associative, 32 byte line size 43H 2nd level cache: 512 Kb, 4-way set associative, 32 byte line size 44H 2nd level cache: 1 Mb, 4-way set associative, 32 byte line size 45H 2nd level cache: 2 Mb, 4-way set associative, 32 byte line size 50H Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 64 entries 51H Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 128 entries 52H Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 256 entries 5BH Data TLB: 4 Kb and 4 Mb pages, 64 entries 5CH Data TLB: 4 Kb and 4 Mb pages, 128 entries 5DH Data TLB: 4 Kb and 4 Mb pages, 256 entries 66H 1st level data cache: 8 Kb, 4-way set associative, 64 byte line size 67H 1st level data cache: 16 Kb, 4-way set associative, 64 byte line size 68H 1st level data cache: 32 Kb, 4-way set associative, 64 byte line size 70H Trace cache: 12K-μop, 8-way set associative 71H Trace cache: 16K-μop, 8-way set associative 72H Trace cache: 32K-μop, 8-way set associative 79H 2nd level cache: 128 Kb, 8-way set associative, sectored, 64 byte line size 7AH 2nd level cache: 256 Kb, 8-way set associative, sectored, 64 byte line size 7BH 2nd level cache: 512 Kb, 8-way set associative, sectored, 64 byte line size 7CH 2nd level cache: 1 Mb, 8-way set associative, sectored, 64 byte line size 82H 2nd level cache: 256 Kb, 8-way set associative, 32 byte line size 84H 2nd level cache: 1 Mb, 8-way set associative, 32 byte line size 85H 2nd level cache: 2 Mb, 8-way set associative, 32 byte line size

Mapping of Brand Indices and IA-32 Processor Brand Strings Hexadecimal-Binary-Decimal ConversionBrand Index Brand String Hex Binary 000X 00X0 0X00 X000 0 This processor does not support the brand identification feature 0 0000 0 0 0 0 1 Celeron processor 1 0001 1 16 256 4096 2 Pentium III processor 2 0010 2 32 512 8192 3 Intel Pentium III Xeon processor 3 0011 3 48 768 12288 4 – 7 Reserved for future processor 4 0100 4 64 1024 16384 8 Intel Pentium 4 processor 5 0101 5 80 1280 20480 9 – 255 Reserved for future processor 6 0110 6 96 1536 24576

7 0111 7 112 1792 28672 32-Bit Register Review 8 1000 8 128 2048 32768

EAX/EDX General-purpose, MUL, DIV, port I/O, report Pentium cycles 9 1001 9 144 2304 36864EBX Great general-purpose use. No important special functions. A 1010 10 160 2560 40960ECX General-purpose, REP string inst. loop count, low B shift count B 1011 11 176 2816 45056EBP Address stack variables (stack-frame pointer), can borrow use C 1100 12 192 3072 49152ESI General purpose, source data pointer for REP string instructions D 1101 13 208 3328 5324

8EDI General purpose, destination pointer for REP string instructions E 1110 14 224 3584 57344

ESP Address stack parameters & variables, cannot use unless no int. F 1111 15 240 3840 61440