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8259a ProgrammableInterrupt Controller
8259a ProgrammableInterrupt Controller
Mr.Bhandari.Rajiv RAssistant ProfessorDepartment of Computer Engineering
NEED FOR 8259A
• 8085 Processor has only 5 hardware interrupts.• Consider an application where a number of I/O devicesconnected with CPU desire to transfer data using interruptdriven data transfer mode. In this process more number ofinterrupt pins are required.• In these multiple interrupt systems the processor will haveto take care of priorities.
• 8085 Processor has only 5 hardware interrupts.• Consider an application where a number of I/O devicesconnected with CPU desire to transfer data using interruptdriven data transfer mode. In this process more number ofinterrupt pins are required.• In these multiple interrupt systems the processor will haveto take care of priorities.
8259A PIC
• Able to handle a number of interrupts at a time.• Takes care of a number of simultaneouslyappearing interrupt requests along with theirtypes and priorities.• Compatible with 8-bit as well as 16-bit processors.
• Able to handle a number of interrupts at a time.• Takes care of a number of simultaneouslyappearing interrupt requests along with theirtypes and priorities.• Compatible with 8-bit as well as 16-bit processors.
8259A PIC- FEATURES• Manage 8 interrupts according to the instructions writteninto the control registers.• Vector an interrupt request anywhere in the memory map.However all the 8 interrupts are spaced at an interval offour to eight locations.• Resolve 8 levels of interrupt priorities in variety of modes.• Mask each interrupt request individually.• Read the status of pending interrupts, in-service interruptsand masked interrupts.
• Manage 8 interrupts according to the instructions writteninto the control registers.• Vector an interrupt request anywhere in the memory map.However all the 8 interrupts are spaced at an interval offour to eight locations.• Resolve 8 levels of interrupt priorities in variety of modes.• Mask each interrupt request individually.• Read the status of pending interrupts, in-service interruptsand masked interrupts.
8259A PIC- FEATURES• Be set up to accept either the level triggered or theedge triggered interrupt request.• Be expanded to 64 priority levels by cascadingadditional 8259As.• Compatible with 8-bit as well as 16-bit processors.• Be set up to accept either the level triggered or theedge triggered interrupt request.• Be expanded to 64 priority levels by cascadingadditional 8259As.• Compatible with 8-bit as well as 16-bit processors.
8259A PIC- BLOCK DIAGRAMIt includes 8 blocks.• Control logic• Read/Write logic• Data bus buffer• Three registers (IRR,ISR and IMR)• Priority resolver• Cascade Buffer
It includes 8 blocks.• Control logic• Read/Write logic• Data bus buffer• Three registers (IRR,ISR and IMR)• Priority resolver• Cascade Buffer
8259A PIC- PIN DIGRAM
8259A PIC- BLOCK DIAGRAM
8259A PIC- INTERRUPTS AND CONTROLLOGIC SECTIONThis section consists of• IRR (Interrupt RequestRegister)• ISR (In-ServiceRegister)• Priority Resolver• IMR (Interrupt MaskRegister)• Control logic block
IRR• 8 interrupt inputs setcorresponding bits ofIRR• Used to store theinformation about theinterrupt inputsrequesting service.
This section consists of• IRR (Interrupt RequestRegister)• ISR (In-ServiceRegister)• Priority Resolver• IMR (Interrupt MaskRegister)• Control logic block
IRR• 8 interrupt inputs setcorresponding bits ofIRR• Used to store theinformation about theinterrupt inputsrequesting service.
8259A PIC- INTERRUPTS AND CONTROLLOGIC SECTIONISR• Used to store informationabout the interruptscurrently being serviced.* OCWs Operation ControlWord.
PRIORITY RESOLVER• Determines the priorities ofinterrupts requesting services(which set corresponding bits ofIRR)• It determines the priorities asdictated by priority mode set byOCWs.• The bit corresponding tohighest priority input is set inISR during input.• Examines three registers anddetermines whether INT shouldbe sent to MPU.
ISR• Used to store informationabout the interruptscurrently being serviced.* OCWs Operation ControlWord.
PRIORITY RESOLVER• Determines the priorities ofinterrupts requesting services(which set corresponding bits ofIRR)• It determines the priorities asdictated by priority mode set byOCWs.• The bit corresponding tohighest priority input is set inISR during input.• Examines three registers anddetermines whether INT shouldbe sent to MPU.
8259A PIC- INTERRUPTS AND CONTROLLOGIC SECTIONIMR• This register can be programmed by an OCW tostore the bits which mask specific interrupts.• IMR operates on the IRR.• An interrupt which is masked by software (Byprogramming the IMR) will not be recognized andserviced even if it sets corresponding bits in theIRR.
IMR• This register can be programmed by an OCW tostore the bits which mask specific interrupts.• IMR operates on the IRR.• An interrupt which is masked by software (Byprogramming the IMR) will not be recognized andserviced even if it sets corresponding bits in theIRR.
8259A PIC- INTERRUPTS AND CONTROLLOGIC SECTIONCONTROL LOGIC• Has two pins:INT (Interrupt) Output( Interrupt Acknowledge) Input• INT Connected to Interrupt pin of MPU.When interrupt occurs this pin goes high.
CONTROL LOGIC• Has two pins:INT (Interrupt) Output( Interrupt Acknowledge) Input• INT Connected to Interrupt pin of MPU.When interrupt occurs this pin goes high.
8259A PIC- BLOCK DIAGRAMDATA BUS BUFFER• 8 bit• Bidirectional• Tri-state Buffer used to Interface the 8259 to thesystem data bus.• Control words, Status words and vectoring dataare all passed through the data bus buffer.
DATA BUS BUFFER• 8 bit• Bidirectional• Tri-state Buffer used to Interface the 8259 to thesystem data bus.• Control words, Status words and vectoring dataare all passed through the data bus buffer.
8259A PIC- READ/WRITE CONTROL LOGIC SECTION• Contains ICW and OCW registers which are programmedby the CPU to set up the 8259 and to operate it in variousmodes.• Also accepts read command from CPU to permit the CPU toread status words.• Chip Select Active Low input
Used to select the Device.• Read Active Low input Used by CPU to read the status ofISR,IRR,IMR or the Interrupt level.• Write Active Low input Used to write OCW and ICW onto the 8259.*ICW Initialization Control Word
• Contains ICW and OCW registers which are programmedby the CPU to set up the 8259 and to operate it in variousmodes.• Also accepts read command from CPU to permit the CPU toread status words.• Chip Select Active Low input Used to select the Device.• Read Active Low input Used by CPU to read the status ofISR,IRR,IMR or the Interrupt level.• Write Active Low input Used to write OCW and ICW onto the 8259.*ICW Initialization Control Word
8259A PIC- CASCADE BUFFER/COMPARATOR• Generates control signals for cascade operation.• Also generates buffer enable signals.• 8259 cascaded with other 8259s Interrupt handling capacity to 64 levels Former is called master and latter is slave.• 8259 can be set up as master or slave bypin in non-buffered mode or by software if it is tobe operated in the buffered mode of operation.
• Generates control signals for cascade operation.• Also generates buffer enable signals.• 8259 cascaded with other 8259s Interrupt handling capacity to 64 levels Former is called master and latter is slave.• 8259 can be set up as master or slave bypin in non-buffered mode or by software if it is tobe operated in the buffered mode of operation.
8259A PIC- CASCADE BUFFER/COMPARATORCAS 0-2• For master 8259 these pins are outputs and for slaves these are inputs.• When 8259 is a master the CALL op-code is generated by master inresponse to the first Interrupt acknowledge.• The vectoring address must be released by slave 8259.• The master puts out the identification code to select one of the slavefrom 8 slaves through these pins.• The slave accepts these three signals as inputs and compare the codeput out by the master with the codes assigned to them duringinitialization.• The slave thus selected puts out the address of ISR during second andthird interrupt acknowledge pulses from the CPU.
CAS 0-2• For master 8259 these pins are outputs and for slaves these are inputs.• When 8259 is a master the CALL op-code is generated by master inresponse to the first Interrupt acknowledge.• The vectoring address must be released by slave 8259.• The master puts out the identification code to select one of the slavefrom 8 slaves through these pins.• The slave accepts these three signals as inputs and compare the codeput out by the master with the codes assigned to them duringinitialization.• The slave thus selected puts out the address of ISR during second andthird interrupt acknowledge pulses from the CPU.
8259A PIC- CASCADE BUFFER/COMPARATORSlave Program/ Enable Buffer:• Used to specify whether 8259 is to act as a masteror a slaveHighMasterLow Slave• In Non-Buffered Mode, this pin is used to specifywhether 8259 is to act as a master or a slave.• In Buffered mode this pin is used as an output toenable the data bus buffer of the system.
Slave Program/ Enable Buffer:• Used to specify whether 8259 is to act as a masteror a slaveHighMasterLow Slave• In Non-Buffered Mode, this pin is used to specifywhether 8259 is to act as a master or a slave.• In Buffered mode this pin is used as an output toenable the data bus buffer of the system.
8259A PIC- INTERRUPT OPERATION• To implement interrupt, the interrupt Enable FF must beenabled by writing EI instruction.• 8259A should be initialized by writing control words inthe control register.• 8259 requires two types of control words:ICW Used to set up proper conditionsand specify RST vector address.OCW Used to perform functions such asmasking interrupts, setting up statusread operations etc.• After 8259A is initialized, the following sequence of eventsoccurs when one or more interrupt request lines go high.
• To implement interrupt, the interrupt Enable FF must beenabled by writing EI instruction.• 8259A should be initialized by writing control words inthe control register.• 8259 requires two types of control words:ICW Used to set up proper conditionsand specify RST vector address.OCW Used to perform functions such asmasking interrupts, setting up statusread operations etc.• After 8259A is initialized, the following sequence of eventsoccurs when one or more interrupt request lines go high.
8259A PIC- INTERRUPT OPERATION1. IRR stores the Interrupt requests.2. Priority Resolver Checks three registers: IRRfor interrupt requests.IMR for Masking bits.ISR for the interrupt request being serviced.It resolves the priority and sets the INT highwhen appropriate.3. MPU acknowledges the interrupt by sendinginterrupt acknowledge.
1. IRR stores the Interrupt requests.2. Priority Resolver Checks three registers: IRRfor interrupt requests.IMR for Masking bits.ISR for the interrupt request being serviced.It resolves the priority and sets the INT highwhen appropriate.3. MPU acknowledges the interrupt by sendinginterrupt acknowledge.
8259A PIC- INTERRUPT OPERATION4. After is received, the appropriate prioritybit in the ISR is set to indicate which level is beingserved and the corresponding bit in the IRR isreset to that request is accepted. Then op-code forCALL instruction is placed on the Data Bus.5. When MPU decodes the CALL instruction, it placestwo more signals on the data bus.
4. After is received, the appropriate prioritybit in the ISR is set to indicate which level is beingserved and the corresponding bit in the IRR isreset to that request is accepted. Then op-code forCALL instruction is placed on the Data Bus.5. When MPU decodes the CALL instruction, it placestwo more signals on the data bus.
8259A PIC- INTERRUPT OPERATION6. When 8259 receives second , itplaces lower order byte of CALL address onthe data bus.Third High order byte.The CALL address is the vector memorylocation for the interrupt. This address isplaced in control register duringinitialization.
6. When 8259 receives second , itplaces lower order byte of CALL address onthe data bus.Third High order byte.The CALL address is the vector memorylocation for the interrupt. This address isplaced in control register duringinitialization.
8259A PIC- INTERRUPT OPERATION7. During third pulse, the ISR bit is reset eitherautomatically (AEOI) or by a command word thatmust be issued at the end of the service routine(EOI). This option is determined by the ICW.8. The program sequence is transferred to thememory location specified by the CALLinstruction.AEOI Automatic End of Interrupt ModeEOI End of Interrupt Mode
7. During third pulse, the ISR bit is reset eitherautomatically (AEOI) or by a command word thatmust be issued at the end of the service routine(EOI). This option is determined by the ICW.8. The program sequence is transferred to thememory location specified by the CALLinstruction.AEOI Automatic End of Interrupt ModeEOI End of Interrupt Mode
8259A PIC- COMMAND WORDS• Two types: ICW, OCWICW:• Before start functioning, 8259 must be initializedby writing two to four command words into theirrespective command word registers.• A0=0,D4=1: The control word is ICW1. ICW1contains the control bits for edge/level triggeredmode, single/cascade mode, call address intervaland whether ICW4 is required or not etc.• A0=1: ICW2Store details interrupt vectoraddresses.
• Two types: ICW, OCWICW:• Before start functioning, 8259 must be initializedby writing two to four command words into theirrespective command word registers.• A0=0,D4=1: The control word is ICW1. ICW1contains the control bits for edge/level triggeredmode, single/cascade mode, call address intervaland whether ICW4 is required or not etc.• A0=1: ICW2Store details interrupt vectoraddresses.
8259A PIC- ICW1The following initialization procedure Carried out internallywhen ICW1 is loaded.a) The edge sense circuit is reset i.e. by default 8259Ainterrupts are edge sensitive.b) IMR is cleared.c) IR7 input is assigned lowest priority.d) Slave mode address is set to 7.e) Special mask mode is cleared and status read is set toIRR.f) If IC4=0, all functions of ICW4 are set to Zero.Master/slave bit in ICW4 bit is used in buffered modeonly.
The following initialization procedure Carried out internallywhen ICW1 is loaded.a) The edge sense circuit is reset i.e. by default 8259Ainterrupts are edge sensitive.b) IMR is cleared.c) IR7 input is assigned lowest priority.d) Slave mode address is set to 7.e) Special mask mode is cleared and status read is set toIRR.f) If IC4=0, all functions of ICW4 are set to Zero.Master/slave bit in ICW4 bit is used in buffered modeonly.
INITIALIZATION SEQUENCE OF 8259AICW1 & ICW2 areCompulsory commandWords in the initializationsequence.ICW3 & ICW4 areOptional.ICW3 is read only whenMore than one 8259 usedin the system ( SNGL bit inICW1 is 0).
ICW1 & ICW2 areCompulsory commandWords in the initializationsequence.ICW3 & ICW4 areOptional.ICW3 is read only whenMore than one 8259 usedin the system ( SNGL bit inICW1 is 0).
ADI=1 for 8086 based system
For 8086 Don’t Care
ADI=1 for 8086 based system
p
For 8085 system they are filled by A15-A11 of the interrupt vector address andLeast significant 3 bits are same as the respective bits of the vector address.For 8086 system they are filled by most significant 5 bits of interrupt type andthe least significant 3 bits are 0, pointing to IR0.
If BUF=0,M/S is to be neglected.
8259A- OPERATING MODESFULLY NESTED MODE:• General purpose mode.• All IRs are arranged from highest to lowest.• IR0 Highest IR7LowestAUTOMATIC ROTATION MODE:• In this mode, a device after being serviced, receives thelowest priority.SPECIFIC ROTATION MODE:• Similar to automatic rotation mode, except that the usercan select any IR for the lowest priority, thus fixing allother priorities.
FULLY NESTED MODE:• General purpose mode.• All IRs are arranged from highest to lowest.• IR0 Highest IR7LowestAUTOMATIC ROTATION MODE:• In this mode, a device after being serviced, receives thelowest priority.SPECIFIC ROTATION MODE:• Similar to automatic rotation mode, except that the usercan select any IR for the lowest priority, thus fixing allother priorities.
8259-INTERRUPT PROCESS IN FULLY NESTED MODE
8259A- OPERATING MODESEND OF INTERRUPT (EOI):• After the completion of an interrupt service, thecorresponding ISR bits needs to be reset to update theinformation in the ISR. This is called EOI command.It can be issued in three formats:NON SPECIFIC EOI COMMAND:• When this command is sent to 8259A, it resets the highestpriority ISR bit.SPECIFIC EOI COMMAND:• This command specifies which ISR bit is to reset.
END OF INTERRUPT (EOI):• After the completion of an interrupt service, thecorresponding ISR bits needs to be reset to update theinformation in the ISR. This is called EOI command.It can be issued in three formats:NON SPECIFIC EOI COMMAND:• When this command is sent to 8259A, it resets the highestpriority ISR bit.SPECIFIC EOI COMMAND:• This command specifies which ISR bit is to reset.
8259A- OPERATING MODESAUTOMATIC EOI:• In this mode, no command is necessary.• During the third interrupt acknowledgecycle, the ISR bit is reset.• DRAWBACK: The ISR does not haveinformation about which ISR is beingserviced. Thus, any IR can interrupt theservice routine, irrespective of its priority, ifthe interrupt enable FF is set.
AUTOMATIC EOI:• In this mode, no command is necessary.• During the third interrupt acknowledgecycle, the ISR bit is reset.• DRAWBACK: The ISR does not haveinformation about which ISR is beingserviced. Thus, any IR can interrupt theservice routine, irrespective of its priority, ifthe interrupt enable FF is set.
8259A- OPERATING MODESSPECIAL FULLY NESTED MODE:• Used in case of larger system where cascading is used, and the has tobe programmed in the master using ICW4• In this mode, when an interrupt request from a certain slave is inservice, this slave can further send requests to the master, if therequesting device connected to the slave has higher priority than theone being currently served.• In this mode, the master interrupts the CPU only when the interruptingdevice has the highest priority or the same priority than the onecurrently being served.• In normal mode, other requests than the one being served are masked.BUFFERED MODECASCADE MODE
SPECIAL FULLY NESTED MODE:• Used in case of larger system where cascading is used, and the has tobe programmed in the master using ICW4• In this mode, when an interrupt request from a certain slave is inservice, this slave can further send requests to the master, if therequesting device connected to the slave has higher priority than theone being currently served.• In this mode, the master interrupts the CPU only when the interruptingdevice has the highest priority or the same priority than the onecurrently being served.• In normal mode, other requests than the one being served are masked.BUFFERED MODECASCADE MODE
ADDITIONAL FEATURES OF THE 8259AINTERRUPT TRIGGERING:• 8259A can accept an interrupt request with either the edgetriggered or level triggered mode.• Mode is determined by initialization instructions.INTERRUPT STATUS:• The status of the three interrupt registers (IRR, ISR andIMR) can be read, and this status information can be usedto make the interrupt process versatile.POLL METHOD:• 8259A can be set up to function in polled environment.• MPU polls the 8259A rather than each peripheral.
INTERRUPT TRIGGERING:• 8259A can accept an interrupt request with either the edgetriggered or level triggered mode.• Mode is determined by initialization instructions.INTERRUPT STATUS:• The status of the three interrupt registers (IRR, ISR andIMR) can be read, and this status information can be usedto make the interrupt process versatile.POLL METHOD:• 8259A can be set up to function in polled environment.• MPU polls the 8259A rather than each peripheral.
• Thank You
