88DE3010 Pt 2 - amobbs.com

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Marvell. Moving Forward Faster

Doc. No. MV-S104738-02, Rev. A

March 31, 2010

CONFIDENTIAL

Document Classification: Proprietary Information

Cover

88DE3010 DatasheetHigh Definition Media Processor System on ChipPart 2: Functional Description

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Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to hardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Doc Status: Advance Technical Publication: 0.20

For more information, visit our website at: www.marvell.comDisclaimerNo part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 1999–2010. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.


Doc. No. MV-S104738-02 Rev. A CONFIDENTIAL Copyright © 2010 MarvellPage 2 Document Classification: Proprietary Information March 31, 2010, Advance

Not Approved by Document Control. For Review Only

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About this Document

Copyright © 2010 Marvell CONFIDENTIAL Doc. No. MV-S104738-02 Rev. AMarch 31, 2010, Advance Document Classification: Proprietary Information Page 3


Preface

About this DocumentThe 88DE3010 datasheet is a three-part set that includes the following documents:

88DE3010 Datasheet Part 1: Overview, Pinout, Applications, Mechanical and Electrical SpecificationsProvides a feature list and overview describing the 88DE3010. It also provides the pin description, pin map, mechanical drawings, and electrical specifications.

88DE3010 Datasheet Part 2: Functional DescriptionProvides a functional description of the 88DE3010 device core.

88DE3010 Datasheet Part 3: RegistersProvides a description of the registers of the 88DE3010 device.

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Doc. No. MV-S104738-02 Rev. A CONFIDENTIAL Copyright © 2010 MarvellPage 4 Document Classification: Proprietary Information April 1, 2010, Advance


Table of Contents

1 88DE3010 Overview.....................................................................................................................23

2 Global Unit ...................................................................................................................................252.1 Overview .........................................................................................................................................................25

2.2 Global Unit Functional Description..................................................................................................................262.2.1 Reset Module....................................................................................................................................26

2.2.1.1 Reset Sources....................................................................................................................262.2.1.2 Software Reset Scheme.....................................................................................................262.2.1.3 External Reset Sequence...................................................................................................26

2.2.2 Clock Module ....................................................................................................................................272.2.2.1 PLL and Oscillator ..............................................................................................................27

2.2.3 Clock Dividers and Switches ............................................................................................................292.2.3.1 Clock Switching Procedure ................................................................................................32

2.3 Boot Strap Module ..........................................................................................................................................33

3 System Manager (SM) .................................................................................................................343.1 Power Domain and Power Sequence .............................................................................................................34

3.1.1 Power Sequence ..............................................................................................................................353.1.1.1 Initial Power up Sequence (Cold Boot) ..............................................................................353.1.1.2 Power Down Sequence (Entering Standby) .......................................................................36

3.1.2 Standby Power Up Sequence (Exiting Standby; Warm Boot) ..........................................................36

3.2 Functional Description.....................................................................................................................................373.2.1 System Manager CPU ......................................................................................................................383.2.2 Clock and Reset Generation.............................................................................................................383.2.3 System Manager Address Map ........................................................................................................383.2.4 System Manager Hardware Devices ................................................................................................40

3.2.4.1 Interrupt Controller .............................................................................................................403.2.4.2 Timers ................................................................................................................................403.2.4.3 Watchdog Timer (WDT) .....................................................................................................403.2.4.4 SPI Master..........................................................................................................................413.2.4.5 TWSI Master ......................................................................................................................413.2.4.6 UART..................................................................................................................................413.2.4.7 GPIO ..................................................................................................................................41

3.2.5 Successive Approximate Register (SAR) ADC.................................................................................413.2.6 Temperature Sensor.........................................................................................................................41

4 SoC CPU.......................................................................................................................................424.1 SoC CPU Implementation Details ...................................................................................................................43

4.2 Data Abort Model ............................................................................................................................................444.2.1 Data Abort Sources ..........................................................................................................................444.2.2 Prefetch Abort Sources.....................................................................................................................44

4.3 Core Coprocessors .........................................................................................................................................44

4.4 SoC CPU Interrupt Timing ..............................................................................................................................45

4.5 Instruction set summary ..................................................................................................................................45

4.6 CP15 Coprocessor ..........................................................................................................................................45

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Table of Contents

Copyright © 2010 Marvell CONFIDENTIAL Doc. No. MV-S104738-02 Rev. AApril 1, 2010, Advance Document Classification: Proprietary Information Page 5


4.6.1 CP15 Register Summary ..................................................................................................................454.6.2 Address Types..................................................................................................................................474.6.3 CP15 Status Registers .....................................................................................................................48

4.6.3.1 [R0] ID Code Register ........................................................................................................484.6.3.2 [R0] Cache Type Register ..................................................................................................49

4.6.4 [R1] Control Register ........................................................................................................................514.6.4.1 Effects of R1 on Caches.....................................................................................................54

4.6.5 [R1] Auxiliary Control Register..........................................................................................................554.6.6 [R2] Translation Table Base Register ...............................................................................................574.6.7 [R3] Domain Access Control Register ..............................................................................................584.6.8 [R4] CP15 Reserved Register ..........................................................................................................594.6.9 [R5] Fault Status Registers (FSR) ....................................................................................................60

4.6.9.1 Data Fault Status Register .................................................................................................604.6.9.2 Instruction Fault Status Register ........................................................................................614.6.9.3 FSR bit [3:0] Encodings......................................................................................................614.6.9.4 FSR bit [10] Encodings for Data Aborts .............................................................................624.6.9.5 FSR bit [10] Encodings for Prefetch Aborts........................................................................62

4.6.10 [R6] Fault Address Register (FAR) ...................................................................................................634.6.11 [R7] CP15 Cache Operations Registers ...........................................................................................644.6.12 Summary of Cache Maintenance Instructions ..................................................................................64

4.6.12.1 Cache Maintenance using MVA Tags ................................................................................664.6.12.2 Cache Maintenance using Index or Set/Way .....................................................................664.6.12.3 D-Cache Test-and-Clean Operations.................................................................................68

4.6.13 [R8] TLB Operations Register...........................................................................................................694.6.14 [R9] Cache Lockdown Registers ......................................................................................................70

4.6.14.1 Cache Lockdown Procedures ............................................................................................714.6.14.2 Cache Unlock Procedures..................................................................................................72

4.6.15 [R10] TLB Lockdown Register ..........................................................................................................724.6.15.1 Example TLB Lockdown.....................................................................................................73

4.6.16 [R11] CP15 Reserved Register ........................................................................................................744.6.17 [R12] CP15 Reserved Register ........................................................................................................744.6.18 CP15 Process ID Registers ..............................................................................................................74

4.6.18.1 [R13] FCSE PID Register ...................................................................................................744.6.18.2 [R13] Context ID Register ..................................................................................................75

4.6.19 [R14] Reserved Register ..................................................................................................................764.6.20 Performance Counters......................................................................................................................76

4.6.20.1 [R15] Counter Operations Registers ..................................................................................764.6.20.2 [R15] Performance Counter Value Registers .....................................................................824.6.20.3 Performance Monitoring Unit..............................................................................................824.6.20.4 Counter Usage ...................................................................................................................854.6.20.5 Application Example...........................................................................................................85

4.6.21 CP15 Extra Features Registers ........................................................................................................864.6.21.1 [R15] Coprocessor Enable Register ...................................................................................864.6.21.2 [R15] Control Configuration Register .................................................................................884.6.21.3 [R15] Privileged Mode Access Register .............................................................................914.6.21.4 [R15] SoC CPU ID Code Extension Register .....................................................................914.6.21.5 [R15] BPU Operations Register .........................................................................................92

4.6.22 The Marvell® Nomenclature for Uniquely Identifying Coprocessor Registers..................................934.6.23 Abbreviations for Register Descriptions............................................................................................94

4.7 WMMX2 SIMD Coprocessor ...........................................................................................................................954.7.1 Introduction .......................................................................................................................................954.7.2 Enabling the SIMD Coprocessor ......................................................................................................954.7.3 WMMX2 General-purpose Registers................................................................................................95

4.7.3.1 Data Registers....................................................................................................................954.7.3.2 Control & Status Registers .................................................................................................95

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4.7.3.3 SIMD Coprocessor Pipeline Integration .............................................................................974.7.3.4 SIMD Coprocessor Datapath .............................................................................................97

4.7.4 SIMD Coprocessor Instruction Set ...................................................................................................974.7.4.1 SIMD MMX™ 2 Instructions ...............................................................................................984.7.4.2 SIMD SSE Instructions.......................................................................................................994.7.4.3 SIMD New Media Technology Instructions ......................................................................1004.7.4.4 SIMD Transfer Instruction Mapping (Wireless Extensions) .............................................1024.7.4.5 SIMD Other Instructions ...................................................................................................1034.7.4.6 SIMD Load/Store Instructions ..........................................................................................1044.7.4.7 SIMD Synthetic Instructions ............................................................................................104

4.7.5 SIMD Coprocessor Instruction Details ............................................................................................104

4.8 Memory Management Unit ............................................................................................................................1054.8.1 Overview.........................................................................................................................................1054.8.2 Architecture Model ..........................................................................................................................106

4.8.2.1 Address Translation Process ...........................................................................................1064.8.2.2 Page Table Descriptor Formats .......................................................................................1064.8.2.3 Memory Attributes ............................................................................................................1084.8.2.4 Memory Attribute Encodings ............................................................................................109

4.8.3 L1 Instruction Cache, Data Cache Behavior...................................................................................1164.8.4 Exceptions ......................................................................................................................................116

5 System Manager CPU (SM CPU) ..............................................................................................1175.1 Features ........................................................................................................................................................117

5.2 Programmer’s Model .....................................................................................................................................1195.2.1 88DE3010 SM CPU Programmer’s Model......................................................................................119

5.2.1.1 Data Abort Model .............................................................................................................1195.2.1.2 88DE3010 SM CPU abort sources...................................................................................119

5.2.2 88DE3010 SM CPU Memory Map..................................................................................................1205.2.3 Tightly-coupled Memory (TCM) Address Space.............................................................................1205.2.4 Bufferable Write Address Space.....................................................................................................120

5.3 SM CPU Register Description.......................................................................................................................1215.3.1 Register 0 - R0................................................................................................................................122

5.3.1.1 ID Code - R0 ....................................................................................................................1225.3.1.2 TCM size Register - R0 ....................................................................................................122

5.3.2 Control Register - R1 ......................................................................................................................1235.3.3 Core Control Register - R7 .............................................................................................................125

5.3.3.1 Wait for Interrupt...............................................................................................................1255.3.3.2 Drain Write Buffer .............................................................................................................125

5.3.4 Test and Configuration Register - R15 ...........................................................................................1265.3.4.1 Configuration Control Register .........................................................................................127

6 Boot ROM ...................................................................................................................................1296.1 ROM Code Flow............................................................................................................................................129

6.2 Flash Layout..................................................................................................................................................1326.2.1 NAND flash Layout .........................................................................................................................1326.2.2 SPI Flash layout for SPI-Secure Boot.............................................................................................134

6.3 Format of Image 2.........................................................................................................................................135

7 JTAG ...........................................................................................................................................1377.1 JTAG debug port configurations ...................................................................................................................137

7.2 Boundary scan support .................................................................................................................................138

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Table of Contents



8 SoC Connectivity and Access Control ....................................................................................1398.1 Connection Table ..........................................................................................................................................140

8.1.1 Address Map...................................................................................................................................1418.1.2 Secure Access Control ...................................................................................................................144

8.1.2.1 Un-secure and Secure Masters........................................................................................1448.1.2.2 Programming of Secure-Access Control ..........................................................................1448.1.2.3 Register Setting of Access Control...................................................................................144

9 DDR SDRAM Memory Controller..............................................................................................1469.1 Interface Configuration Options ....................................................................................................................146

9.2 Addressing Decoding ....................................................................................................................................1479.2.1 Single Channel, normal bank mode................................................................................................1489.2.2 Dual channel, normal bank, symmetric address mode...................................................................1489.2.3 Single channel, bank rolling mode..................................................................................................1489.2.4 Dual channel, bank rolling, symmetric address mode ....................................................................1499.2.5 Dual channel, bank rolling, asymmetric address mode ..................................................................1499.2.6 Dual channel, normal bank, asymmetric address mode.................................................................150

9.3 Supported DDR Features..............................................................................................................................151

9.4 Write Collection .............................................................................................................................................151

9.5 DRAM Controller Arbitration..........................................................................................................................152

9.6 Data Secure-Access Control .........................................................................................................................154

10 Programmable Interrupt Controller (PIC) ................................................................................155

11 Transport Stream Processor and Digital Right Management (DRMDMX) Subsystem........15811.1 DRMDMX Block Diagram..............................................................................................................................159

11.2 Transport Stream Processor Modules...........................................................................................................16011.2.1 Transport Stream Capture (TSC) module.......................................................................................160

11.2.1.1 TSC input routing .............................................................................................................16011.2.1.2 Packet Capture.................................................................................................................16011.2.1.3 PID Filtering......................................................................................................................16111.2.1.4 STC Time Stamping .........................................................................................................16111.2.1.5 Control Tags and Packet Status.......................................................................................161

11.2.2 Section Filter ...................................................................................................................................16211.2.3 Input and Output Packet Format.....................................................................................................16211.2.4 Section Filter Control ......................................................................................................................16311.2.5 Section Filter Rule Descriptor .........................................................................................................16311.2.6 Section Filter Rule Data..................................................................................................................164

11.3 Demux Micro-code ........................................................................................................................................165

11.4 DRM and Secure Boot ..................................................................................................................................16811.4.1 Architecture.....................................................................................................................................16811.4.2 OTP ................................................................................................................................................16811.4.3 RNG................................................................................................................................................17011.4.4 Crypto Accelerator ..........................................................................................................................17011.4.5 Figo Boot ROM ...............................................................................................................................17011.4.6 DRMDMX Bus Interface Firewall ....................................................................................................17111.4.7 On-chip Debug Interface Controller ................................................................................................172

11.5 DRMDMX Performance & Capability ............................................................................................................172

12 VMeta™ ......................................................................................................................................173

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12.1 Supported Video Formats and Performance.................................................................................................17412.1.1 Supported Video Decode Formats .................................................................................................174

12.2 Video Decoder Performance.........................................................................................................................175

13 Data Streaming Hub (dHub)......................................................................................................17613.1 dHub Command and Data ............................................................................................................................176

13.2 dHub channel arbitration ...............................................................................................................................177

13.3 dHub bus gate keeper...................................................................................................................................177

13.4 dHub interrupt and event synchronization.....................................................................................................177

13.5 dHub channel clear and flush........................................................................................................................178

13.6 dHub Channel Configuration.........................................................................................................................178

13.7 dHub Command ............................................................................................................................................17813.7.1 dHub command for linear buffers ...................................................................................................17813.7.2 dHub commands for 2D buffers......................................................................................................179

13.8 dHub in AVIO Subsystem .............................................................................................................................180

13.9 dHub in pBridge ............................................................................................................................................182

14 2D Graphics Engine ..................................................................................................................18314.1 Performance..................................................................................................................................................183

14.2 2D Graphics Sub-system Description ...........................................................................................................184

14.3 2D Graphics Engine Pipeline Description .....................................................................................................18514.3.1 Hardware Engine Primitives ...........................................................................................................186

14.3.1.1 Line Drawing ....................................................................................................................18614.3.1.2 Rectangle Fill and Clear ...................................................................................................18614.3.1.3 Stretch and Non-Stretch Bit Blit........................................................................................18614.3.1.4 Monochrome Expansion / Mask blit .................................................................................18714.3.1.5 Filter Blit ...........................................................................................................................187

14.3.2 Other Features................................................................................................................................18814.3.2.1 Rotation ............................................................................................................................18814.3.2.2 Transparency Mode .........................................................................................................18814.3.2.3 Clipping ............................................................................................................................18814.3.2.4 Data Formats....................................................................................................................18814.3.2.5 ARGB Data Conversion ...................................................................................................18914.3.2.6 YUV to RGB Conversion ..................................................................................................18914.3.2.7 Alpha Blending .................................................................................................................190

14.4 2D Graphics Engine Command DMA............................................................................................................19214.4.1 Command Stream Format ..............................................................................................................193

14.4.1.1 LOAD_STATE ..................................................................................................................19314.4.1.2 START_DE.......................................................................................................................19314.4.1.3 LINK .................................................................................................................................19414.4.1.4 WAIT ................................................................................................................................19414.4.1.5 END..................................................................................................................................194

14.5 Interrupts .......................................................................................................................................................195

15 Video Post Processing (VPP) ...................................................................................................19615.1 Video Post Processing Feature List ..............................................................................................................198

15.2 VPP Functional Description ..........................................................................................................................199

15.3 Main Video Plane ..........................................................................................................................................199

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Table of Contents



15.3.1 3D Video Noise Reducer (VNR) .....................................................................................................20115.3.2 3D De-interlacer (DEINT) ...............................................................................................................20215.3.3 Edge Enhancement (EE) – Detail Channel ....................................................................................203

15.4 PIP Video plane ............................................................................................................................................204

15.5 BG Plane.......................................................................................................................................................205

15.6 Graphic Planes..............................................................................................................................................205

15.7 AUX Channel ................................................................................................................................................207

15.8 Scaler ............................................................................................................................................................20715.8.1 Detail Scaler ...................................................................................................................................209

15.9 CPCB (Overlay and Timing Generator).........................................................................................................21115.9.1 CPCB0............................................................................................................................................21215.9.2 CPCB1............................................................................................................................................21615.9.3 CPCB2............................................................................................................................................217

15.10 Color Management Unit (CMU).....................................................................................................................21815.10.1 Input Color Space Converter ..........................................................................................................21815.10.2 Adaptive Contrast Enhancement (ACE) .........................................................................................21815.10.3 Intelligent Color Remapper (ICR) ...................................................................................................218

15.10.3.1Flesh Tone Detection and Correction (FTDC) .................................................................21915.10.3.2Hue – Saturation Calibration............................................................................................219

15.10.4 Gamut Compression.......................................................................................................................21915.10.5 Gamma Correction .........................................................................................................................22015.10.6 Film Gain Generator (FGG) ............................................................................................................220

15.11 Interlacer .......................................................................................................................................................220

15.12 Video Output Modules...................................................................................................................................22115.12.1 HDMI Output ...................................................................................................................................221

15.12.1.1HDMI VOP .......................................................................................................................22115.12.1.2HDMI Transmitter ............................................................................................................22115.12.1.3HDCP...............................................................................................................................22315.12.1.4CEC .................................................................................................................................22315.12.1.5HDMI-TX PHY .................................................................................................................224

15.12.2 HD Component and SD CVBS, S-Video Outputs ...........................................................................22415.12.2.1HD Component and SD CVBS, S-Video VOP.................................................................22415.12.2.2Video Encoder .................................................................................................................22515.12.2.3Video DAC .......................................................................................................................227

15.12.3 Digital Video Output (DVO).............................................................................................................229

15.13 Color Space Converter..................................................................................................................................232

15.14 VPP Pipeline Control.....................................................................................................................................23315.14.1 Register Interface ...........................................................................................................................23315.14.2 DRAM Interface ..............................................................................................................................23315.14.3 Interrupt scheme.............................................................................................................................233

15.15 VPP Clock Generation ..................................................................................................................................233

15.16 AVPLL ...........................................................................................................................................................237

16 Audio DSP ..................................................................................................................................23916.1 Function Description .....................................................................................................................................240

16.1.1 Audio DSP Block Diagram..............................................................................................................24016.1.2 Interfaces ........................................................................................................................................240

16.1.2.1 Register Access Interface ................................................................................................24016.1.2.2 Memory Access Interface.................................................................................................241

16.1.3 ITCM/DTCM and DMA....................................................................................................................241

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16.1.4 Interrupt ..........................................................................................................................................24216.1.4.1 Interrupt to audio DSP......................................................................................................24216.1.4.2 Interrupt to SoC CPU .......................................................................................................243

16.1.5 Audio DSP Initialization ..................................................................................................................244

17 Audio Post Processor (APP) ....................................................................................................24517.1 Operation Model............................................................................................................................................245

17.2 APP Functional Diagram...............................................................................................................................24717.2.1 APP DMA channels ........................................................................................................................24717.2.2 DMA Adaptor ..................................................................................................................................24817.2.3 Command Parser............................................................................................................................24817.2.4 Instruction Parser............................................................................................................................24817.2.5 Coherence Checker ........................................................................................................................24817.2.6 SRAM controller..............................................................................................................................24817.2.7 MAC Engine....................................................................................................................................248

17.3 APP commands ............................................................................................................................................24917.3.1 Atomic Instruction ...........................................................................................................................250

17.3.1.1 AppMov ............................................................................................................................25017.3.1.2 AppMac ............................................................................................................................25017.3.1.3 AppMax ............................................................................................................................25117.3.1.4 AppLmt .............................................................................................................................25217.3.1.5 AppDmaCmd....................................................................................................................25217.3.1.6 AppDmaDat......................................................................................................................253

17.3.2 AppCopy .........................................................................................................................................25417.3.2.1 AppFilter ...........................................................................................................................25417.3.2.2 AppSrc..............................................................................................................................25617.3.2.3 AppFader..........................................................................................................................25717.3.2.4 AppMixer ..........................................................................................................................25817.3.2.5 AppDownMix ....................................................................................................................26017.3.2.6 AppEqualizer ....................................................................................................................26117.3.2.7 AppInterleave ...................................................................................................................263

18 Audio Input Output....................................................................................................................26418.1 Audio Clock Generation ................................................................................................................................266

18.1.1 Audio Clock Scheme ......................................................................................................................266

18.2 Sampling rate and Bit Clock..........................................................................................................................267

18.3 AIO Transmitters and Receiver .....................................................................................................................268

18.4 Data formats..................................................................................................................................................26918.4.1 I2S mode ........................................................................................................................................26918.4.2 Left-Justified mode .........................................................................................................................26918.4.3 Right-Justified mode .......................................................................................................................26918.4.4 S/P-DIF ...........................................................................................................................................270

18.4.4.1 S/P-DIF internal Sub-Frame format..................................................................................271

19 Peripheral Sub System .............................................................................................................27219.1 Description ....................................................................................................................................................272

19.2 External interface controllers.........................................................................................................................27419.2.1 PCIe controller with integrated PHY ...............................................................................................27419.2.2 Ethernet MAC Controller Interface..................................................................................................27519.2.3 SATA Host Controller with integrated PHY.....................................................................................27519.2.4 USB Host Controller with integrated PHY.......................................................................................27519.2.5 NAND Flash Controller ...................................................................................................................276

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Table of Contents



19.2.6 Local Bus Controller (LBC) .............................................................................................................27619.2.7 SDIO host Controller.......................................................................................................................27619.2.8 Transport stream input interface.....................................................................................................27719.2.9 TWSI interface ................................................................................................................................27719.2.10 SPI interface ...................................................................................................................................27819.2.11 GPIO...............................................................................................................................................27819.2.12 PWM ...............................................................................................................................................278

19.3 Functional blocks ..........................................................................................................................................27919.3.1 DRMDMX engine............................................................................................................................27919.3.2 Timers.............................................................................................................................................27919.3.3 Watch dog.......................................................................................................................................27919.3.4 Embedded Interrupt controller ........................................................................................................27919.3.5 pBridge ...........................................................................................................................................279

20 pBridge .......................................................................................................................................28020.1 pBridge Block Diagram .................................................................................................................................281

20.2 pBridge descriptor format ..............................................................................................................................28220.2.1 CFGW.............................................................................................................................................28220.2.2 RCMD and RDAT ...........................................................................................................................28320.2.3 WCMD and WDAT..........................................................................................................................28520.2.4 SEMA..............................................................................................................................................28520.2.5 LDFN ..............................................................................................................................................28520.2.6 NULL...............................................................................................................................................286

21 NAND Flash Controller..............................................................................................................28721.1 Features ........................................................................................................................................................287

21.2 NAND Interface Configuration.......................................................................................................................28721.2.1 Stacked configuration .....................................................................................................................28721.2.2 LBC/NAND Pad Shared configuration ............................................................................................289

21.3 NAND Timing Diagrams................................................................................................................................29021.3.1 NAND Flash Program Timing .........................................................................................................29021.3.2 NAND Flash Erase Timing..............................................................................................................29121.3.3 NAND Flash Read Timing ..............................................................................................................29121.3.4 NAND Flash Status Read Timing ...................................................................................................29221.3.5 NAND Flash Read ID Timing..........................................................................................................29221.3.6 NAND Flash Reset Timing..............................................................................................................29321.3.7 NAND Flash Timing Parameters ....................................................................................................293

21.4 NFC Host Interface .......................................................................................................................................29421.4.1 NFC Host Features.........................................................................................................................29421.4.2 Command Interface ........................................................................................................................29521.4.3 Data Interface .................................................................................................................................29521.4.4 PIO and DMA operating Modes......................................................................................................295

21.4.4.1 PIO operating Mode .........................................................................................................29521.4.4.2 DMA operating Mode .......................................................................................................296

21.4.5 Error Handling.................................................................................................................................29621.4.5.1 Error Checking and Correction (ECC)..............................................................................29621.4.5.2 Bad Block Management Support......................................................................................296

22 Local Bus Controller (LBC) ......................................................................................................29722.1 Features ........................................................................................................................................................297

22.2 PAD arbitration between LBC and NFC........................................................................................................298

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22.3 Programming Local Bus Controller Registers ...............................................................................................299

22.4 External Device Interface ..............................................................................................................................29922.4.1 LBC Write Protocol .........................................................................................................................30022.4.2 LBC Read Protocol .........................................................................................................................301

23 SD2.0/SDIO 2.0 Host Controller................................................................................................30223.1 Key features ..................................................................................................................................................302

24 APB Components of Peripheral Interface ...............................................................................30524.1 GPIO .............................................................................................................................................................305

24.1.1 GPIO as I/O pins.............................................................................................................................30524.1.1.1 Controlling the GPIO ........................................................................................................30624.1.1.2 Reading External Signals .................................................................................................306

24.1.2 GPIO as Interrupt............................................................................................................................306

24.2 UART ............................................................................................................................................................307

24.3 Two-Wire Serial interface (TWSI)..................................................................................................................30824.3.1 Overview.........................................................................................................................................30824.3.2 TWSI Protocols...............................................................................................................................308

24.3.2.1 START and STOP Condition Protocol .............................................................................30924.3.2.2 Addressing Slave Protocol ...............................................................................................30924.3.2.3 Transmitting and Receiving Protocol................................................................................31024.3.2.4 START BYTE Transfer Protocol.......................................................................................311

24.3.3 Multiple Master Arbitration and Clock Synchronization...................................................................31224.3.3.1 Master Arbitration .............................................................................................................31224.3.3.2 Clock Synchronization......................................................................................................312

24.3.4 Operation Model .............................................................................................................................312

24.4 Low Speed Peripheral Interrupt Controller (ICTL).........................................................................................31324.4.1 Overview.........................................................................................................................................31324.4.2 IRQ Interrupt Processing ................................................................................................................31324.4.3 IRQ Interrupt Polarity ......................................................................................................................31424.4.4 IRQ Software-Programmable Interrupts .........................................................................................31424.4.5 IRQ Enable and Masking................................................................................................................31424.4.6 IRQ Interrupt Status Registers........................................................................................................31424.4.7 SoC ICTL source assignment.........................................................................................................315

24.5 Timers ...........................................................................................................................................................316

24.6 Watchdog Timers (WDT)...............................................................................................................................31724.6.1 Counter ...........................................................................................................................................31724.6.2 Interrupts.........................................................................................................................................31724.6.3 System Resets................................................................................................................................318

24.7 Serial Peripheral Interface (SPI) ...................................................................................................................31924.7.1 Overview.........................................................................................................................................31924.7.2 Clock Ratios....................................................................................................................................31924.7.3 Transmit and Receive FIFO Buffers ...............................................................................................32024.7.4 SPI Interrupts..................................................................................................................................32124.7.5 Transfer Modes...............................................................................................................................321

24.7.5.1 Transmit and Receive ......................................................................................................32224.7.5.2 Transmit Only ...................................................................................................................32224.7.5.3 Receive Only ....................................................................................................................32224.7.5.4 EEPROM Read ...............................................................................................................322

24.7.6 Operation Modes ............................................................................................................................32224.7.6.1 Operation Mode................................................................................................................32324.7.6.2 Serial-Master Mode ..........................................................................................................323

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Table of Contents



24.7.7 Data Transfers ................................................................................................................................32424.7.8 Serial Peripheral Interface (SPI) Protocol .......................................................................................324

25 SATA Host Controller................................................................................................................32725.1 PHY features.................................................................................................................................................327

25.2 Host controller features .................................................................................................................................327

26 Pulse Width Modulator (PWM) .................................................................................................32826.1 Overview .......................................................................................................................................................328

27 USB Host Controller ..................................................................................................................32927.1 PHY Features................................................................................................................................................329

27.2 Host Controller Features ...............................................................................................................................329

28 PCI Express................................................................................................................................33028.1 Master Memory Transactions........................................................................................................................330

28.2 Master I/O Transactions................................................................................................................................330

28.3 Master Configuration Transactions ...............................................................................................................33128.3.1 Configuration Requests Generation ...............................................................................................331

28.4 Target Memory Transactions ........................................................................................................................33128.4.1 Special Cases.................................................................................................................................332

28.5 Target I/O Transactions ................................................................................................................................332

28.6 Target Configuration Transactions................................................................................................................33228.6.1 Messages in RootComplex Mode...................................................................................................33228.6.2 Messages in EndPoint Mode ..........................................................................................................332

28.7 Locked Transactions .....................................................................................................................................333

28.8 Arbitration and Ordering................................................................................................................................333

28.9 Hot Reset ......................................................................................................................................................333

28.10 Error Handling ...............................................................................................................................................33428.10.1 Physical Layer Errors......................................................................................................................33428.10.2 Data Link Layer Errors....................................................................................................................33428.10.3 Transaction Layer Errors ................................................................................................................334

28.11 Address Translation ......................................................................................................................................33528.11.1 Target Address Translation ............................................................................................................33528.11.2 Initiator Address Translation ...........................................................................................................335

28.12 Internal PHY Access .....................................................................................................................................336

28.13 Interrupts .......................................................................................................................................................336

29 10/100MB ETHERNET Controller .............................................................................................33729.1 Functional Overview......................................................................................................................................337

29.2 Features ........................................................................................................................................................337

29.3 Operational Description.................................................................................................................................33829.3.1 Transmit Operation .........................................................................................................................339

29.3.1.1 Retransmission (Collision)................................................................................................33929.3.1.2 Zero Padding for short packets ........................................................................................33929.3.1.3 CRC Generation...............................................................................................................33929.3.1.4 TX DMA Descriptors.........................................................................................................340

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29.3.2 Receive Operation ..........................................................................................................................34229.3.2.1 RX DMA Descriptors ........................................................................................................342

29.3.3 Ethernet Address Recognition ........................................................................................................34529.3.3.1 Hash Mode 0 ....................................................................................................................34629.3.3.2 Hash Mode 1 ....................................................................................................................34629.3.3.3 Creating and using the Hash Table..................................................................................347

29.4 MII interface support .....................................................................................................................................347

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List of Tables



List of Tables

Table 1: PLLs and Output Frequency.............................................................................................................28Table 2: Main Clock Options...........................................................................................................................29Table 3: SM Memory Map ..............................................................................................................................39Table 4: System Manager I/O Device Address Map.......................................................................................39Table 5: Interrupt Sources Connected to Interrupt Controller .........................................................................40Table 6: CP15 Register Map ..........................................................................................................................45Table 7: Address Types..................................................................................................................................47Table 8: ID Code Register Bit-level Description .............................................................................................48Table 9: Cache Type Register Bit-level Description .......................................................................................49Table 10: Control Register Bit-level Description ...............................................................................................51Table 11: Effect of Control Register’s M, C, and I Bits on Caches ...................................................................54Table 12: Auxiliary Control Register Bit-level Description.................................................................................55Table 13: Translation Table Base Register Bit-level Description......................................................................57Table 14: Domain Access Control Register Bit-level Description .....................................................................58Table 15: Data Fault Status Register Bit-level Description...............................................................................60Table 16: Instruction Fault Status Register Bit-level Description......................................................................61Table 17: FSR Status Field Encoding...............................................................................................................61Table 18: Encoding of Fault Status Register Data Aborts ................................................................................62Table 19: Encoding of Fault Status for Prefetch Aborts....................................................................................62Table 20: Fault Address Register Bit-level Description.....................................................................................63Table 21: Cache Operations Register - R7 (CP15.0.R7.c{0-14}.{0-2}).............................................................64Table 22: Index Fields for Supported Cache Sizes ..........................................................................................67Table 23: TLB Operations - R8 (CP15.0.R8.c{5-7}.{0-1}) .................................................................................69Table 24: Format for Invalidating a Single Entry in the TLB .............................................................................69Table 25: Cache Lockdown Registers Bit-level Description .............................................................................70Table 26: TLB Lockdown Register Bit-level Description...................................................................................73Table 27: FCSE PID Register Bit-level Description ..........................................................................................75Table 28: Context ID Register Bit-level Description..........................................................................................76Table 29: R12 Values to Set the “Kinds of Performance” to Monitor ................................................................77Table 30: Kinds of Countable Events ...............................................................................................................78Table 31: Accessing the Performance Counter Interrupt Enable & FLAG (Overflow) Registers ......................83Table 32: Interrupt Enable Register (INTEN) Bit-level Description...................................................................83Table 33: Overflow Flag Status Register (FLAG) Bit-level Description.............................................................84Table 34: Coprocessor Enable Register Bit-level Description ..........................................................................86Table 35: Control Configuration Register Bit-level Description.........................................................................88Table 36: Privileged Mode Access Register Bit-level Description ....................................................................91Table 37: SoC CPU ID Code Extension Register Bit-level Description ............................................................91Table 38: BPU Operations Register Bit-level Description.................................................................................92Table 39: CP15 Abbreviations ..........................................................................................................................94

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Table 40: WMMX2 Status and Control Register Mappings ..............................................................................96Table 41: MMX™ 2 Compliant Instructions ......................................................................................................98Table 42: SIMD SSE Instructions .....................................................................................................................99Table 43: SIMD New Media Instructions ........................................................................................................100Table 44: SIMD Transfer Instruction Mapping Instructions.............................................................................102Table 45: SIMD Transfer Instruction Mapping Instructions.............................................................................103Table 46: SIMD Load/Store Instructions.........................................................................................................104Table 47: SIMD Synthetic Instructions............................................................................................................104Table 48: First-level Descriptors .....................................................................................................................106Table 49: Second-level Descriptors for Coarse Page Table...........................................................................106Table 50: Second-level Descriptors for Fine Page Table ...............................................................................107Table 51: Cache Attributes with L2 present, S=0 ..........................................................................................110Table 52: Cache Attributes with L2 present, S=1 ...........................................................................................111Table 53: LLR Page Attributes, L2 Present Case, S=0 ..................................................................................112Table 54: LLR Page Attributes, L2 Present Case, S=1 ..................................................................................112Table 55: Cache Attributes with no L2, S=0 ...................................................................................................113Table 56: Cache Attributes with no L2, S=1 ...................................................................................................114Table 57: LLR Page Attributes, no L2 case, S=0............................................................................................114Table 58: LLR page attributes, no L2 case, S=1 ............................................................................................115Table 59: Register Map ................................................................................................................................. 121Table 60: CP15 Abbreviations ....................................................................................................................... 121Table 61: CP15 Register Summary ............................................................................................................... 121Table 62: ID Code, Register 0 ....................................................................................................................... 122Table 63: TCM size, Register 0 ..................................................................................................................... 122Table 64: Control Register Format ................................................................................................................ 123Table 65: Test Register map ......................................................................................................................... 126Table 66: Configuration Control Register Map .............................................................................................. 127Table 67: SOC boot source ............................................................................................................................131Table 68: Supported NAND Flash Configurations ..........................................................................................133Table 69: NAND flash attributes table ............................................................................................................133Table 70: Format of Image 2 Header..............................................................................................................136Table 71: 88DE3010 Debug Port Configurations ...........................................................................................138Table 72: Boundary Scan Instructions............................................................................................................138Table 73: Master and Slave Pair Connection Levels ......................................................................................140Table 74: System Memory Map......................................................................................................................141Table 75: Register Space Memory Map .........................................................................................................142Table 76: Low-speed Register Memory Map..................................................................................................142Table 77: Fast-Access Register Memory Map................................................................................................143Table 78: Memory Interface Configurations....................................................................................................146Table 79: Single Channel, normal bank mode................................................................................................148Table 80: Dual Channel, normal bank, symmetric address mode ..................................................................148Table 81: Single channel, bank rolling mode..................................................................................................148Table 82: Dual Channel, bank rolling, symmetric address mode....................................................................149Table 83: Dual Channel, bank rolling, asymmetric address mode..................................................................149

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List of Tables



Table 84: When A[28] = 1, A[27] = 0 ..............................................................................................................149Table 85: Dual Channel, normal bank, asymmetric address mode ................................................................150Table 86: Dual Channel, normal bank, asymmetric address mode ................................................................150Table 87: Masters with write requests ............................................................................................................153Table 88: Interrupt Sources ............................................................................................................................156Table 89: DRMDMX Enabled Events .............................................................................................................167Table 90: DRMDMX Performance ..................................................................................................................172Table 91: VMeta Decoder Performance .........................................................................................................175Table 92: Still Image Performance .................................................................................................................175Table 93: Channel assignment and default memory allocation of vppDhub...................................................180Table 94: Channel assignment and memory allocation for agDhub ...............................................................181Table 95: Channel assignment and memory allocation for pBridge ...............................................................182Table 96: Graphics Engine Pipeline Performance..........................................................................................183Table 97: ROP Inputs .....................................................................................................................................186Table 98: Inputs for Monochrome Expansion .................................................................................................187Table 99: Inputs for Mask Blit .........................................................................................................................187Table 100: Fs/Fd Selection for different Blending Modes.................................................................................192Table 101: YUV422 Pixel Format in DRAM......................................................................................................200Table 102: ARGB/AYUV Pixel Format in DRAM ..............................................................................................206Table 103: Coefficient sets for horizontal scaling in Detail scaler.....................................................................209Table 104: Coefficient sets for vertical scaling in Detail scaler .........................................................................210Table 105: Source of different CPCB0 planes..................................................................................................215Table 106: Control Registers for HDMI-TX-PHY ..............................................................................................224Table 107: VBI data support .............................................................................................................................227Table 108: Supported output format on VDAC1P, VDAC2P and VDAC3P......................................................228Table 109: Supported output formats on VDAC4P, VDAC5P and VDAC6P ....................................................228Table 110: Output over-sampling rates ............................................................................................................228Table 111: 88DE3010 VPP and their coefficient/offset formats........................................................................232Table 112: AVPLL and Clock Divider settings for 8-bit and 12-bit color-depths of HDMI.................................235Table 113: AVPLL and Clock Divider Settings for 10-bit color-depth of HDMI .................................................236Table 114: Clock Outputs from AVPLL.............................................................................................................237Table 115: Audio DSP Performance.................................................................................................................239Table 116: Audio DSP Register Address Mapping...........................................................................................241Table 117: Audio DSP Memory Address Map ..................................................................................................242Table 118: Interrupts to Audio DSP ..................................................................................................................242Table 119: Audio DSP Generated Interrupt Sources........................................................................................243Table 120: APP Commands .............................................................................................................................249Table 121: AppMov Instruction Parameters .....................................................................................................250Table 122: AppMov Instruction .........................................................................................................................250Table 123: AppMac Instruction Parameters .....................................................................................................250Table 124: AppMac Instruction .........................................................................................................................251Table 125: AppMax instruction parameters ......................................................................................................251Table 126: AppMax instruction .........................................................................................................................252Table 127: AppLmt Instruction Parameters ......................................................................................................252

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Table 128: AppLMT Instruction Parameters .....................................................................................................252Table 129: AppDmaCmd Parameters...............................................................................................................253Table 130: AppDmaDat Parameters.................................................................................................................253Table 131: AppDmaDat Functions....................................................................................................................253Table 132: AppCopy Parameters .....................................................................................................................254Table 133: AppCopy functions..........................................................................................................................254Table 134: AppFilter parameters ......................................................................................................................254Table 135: AppFilter Functions.........................................................................................................................255Table 136: AppSrc Parameters ........................................................................................................................256Table 137: AppSrc function ..............................................................................................................................256Table 138: AppFader Parameter ......................................................................................................................257Table 139: AppFader Functions .......................................................................................................................258Table 140: AppMixer Parameters .....................................................................................................................258Table 141: AppMixer Functions ........................................................................................................................259Table 142: AppDownMix Parameters ...............................................................................................................260Table 143: AppDownMix functions ...................................................................................................................260Table 144: AppEqualizer Parameters...............................................................................................................261Table 145: AppEqualizer Functions..................................................................................................................261Table 146: AppInterleave Parameters ..............................................................................................................263Table 147: AppInterleave functions ..................................................................................................................263Table 148: Sampling Rate and Bit Clock Relationship .....................................................................................268Table 149: AIO Transmitter and Receiver Capabilities.....................................................................................268Table 150: Encoding for Preambles .................................................................................................................271Table 151: pBridge Descriptor Type .................................................................................................................282Table 152: CFGW.............................................................................................................................................282Table 153: RCMD .............................................................................................................................................283Table 154: RDAT ..............................................................................................................................................283Table 155: RDAT and WDAT Mode Definition .................................................................................................283Table 156: Device Data Access Sequence When endian = 0 (Little Endian) ..................................................284Table 157: Device Data Access Sequence When endian = 1 (Big Endian) .....................................................284Table 158: WCMD ............................................................................................................................................285Table 159: WDAT .............................................................................................................................................285Table 160: SEMA..............................................................................................................................................285Table 161: LDFN ..............................................................................................................................................285Table 162: Null..................................................................................................................................................286Table 163: NAND Flash Timing Parameters ....................................................................................................293Table 164: Mapping of LBC signals to 88DE3010 Pads...................................................................................298Table 165: Supported Protocol Types ..............................................................................................................304Table 166: TWSI Definition of Bits in the First Byte..........................................................................................310Table 167: ICTL interrupt source mapping .......................................................................................................315Table 168: Target Address Translation ............................................................................................................335Table 169: Ethernet TX Descriptor Format .......................................................................................................340Table 170: Ethernet TX Descriptor - Byte Count ..............................................................................................341Table 171: Ethernet TX Descriptor - Buffer Pointer ..........................................................................................341

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List of Tables



Table 172: Ethernet TX Descriptor - Next Descriptor Pointer ...........................................................................342Table 173: Ethernet RX Descriptor - Command/Status word ...........................................................................343Table 174: Ethernet RX Descriptor - Buffer Size / Byte Count .........................................................................345Table 175: Ethernet RX Descriptor - Buffer Pointer..........................................................................................345Table 176: Ethernet RX Descriptor - Next Descriptor Pointer...........................................................................345Table 177: Description of Hash Table Entry .....................................................................................................345Table 178: Acronyms and Abbreviations ..........................................................................................................348

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List of Figures

Figure 1: Simplified Block Diagram..................................................................................................................23Figure 2: Simplified Block Interface Diagram...................................................................................................24Figure 3: 88DE3010 Device Global Unit Block Diagram..................................................................................25Figure 4: 88DE3010 Device Reset Structure...................................................................................................26Figure 5: 88DE3010 Device Power Up Sequence...........................................................................................27Figure 6: 88DE3010 SoC Clock Structure .......................................................................................................31Figure 7: 88DE3010 Clock Divider and Clock Selection Logic ........................................................................33Figure 8: 88DE3010 Power Domain Partitions ................................................................................................35Figure 9: SM Block Diagram ............................................................................................................................37Figure 10: 88DE3010 SoC CPU Block Diagram................................................................................................43Figure 11: Bit Fields in MVA Mode ....................................................................................................................66Figure 12: Bit Fields in Set/Way Mode...............................................................................................................67Figure 13: MCR/MRC Instruction Encoding for Coprocessor Register Access .................................................93Figure 14: WMMX Data Register Organization..................................................................................................96Figure 15: Address Translation for Supersection.............................................................................................108Figure 16: 88DE3010 Block Diagram ..............................................................................................................118Figure 17: ROM Boot Flow ..............................................................................................................................130Figure 18: NAND flash layout for 88DE3010 ...................................................................................................132Figure 19: SPI flash layout for SPI-Secure boot ..............................................................................................134Figure 20: Image 2 Layout when using CMAC ................................................................................................135Figure 21: Image 2 Layout When Using RSA-PSS..........................................................................................135Figure 22: 88DE3010 JTAG Chain and Boundary Scan Diagram ...................................................................137Figure 23: SoC Subsystem ..............................................................................................................................139Figure 24: DRAM Controller Block Diagram ....................................................................................................152Figure 25: Write Arbitration Diagram ...............................................................................................................153Figure 26: Arbitration Mechanism ....................................................................................................................154Figure 27: 88DE3010 top level PIC diagram ...................................................................................................155Figure 28: Internal diagram of 88DE3010 top level PIC .................................................................................155Figure 29: 88DE3010 top level PIC interrupt source properties ......................................................................156Figure 30: DRMDMX Block Diagram ..............................................................................................................159Figure 31: TSC Input routing............................................................................................................................160Figure 32: Section Filter Rule ..........................................................................................................................162Figure 33: Section Filter Rule SRAM Memory Map .........................................................................................164Figure 34: Relations between Software API, Demux micro-code, and Hardware............................................166Figure 35: Hardware and Software layers for DRM Processing ......................................................................168Figure 36: OTP ................................................................................................................................................169Figure 37: Figo ROM Boot Flow ......................................................................................................................171Figure 38: VMeta Subsystem in a Video Playback System .............................................................................173Figure 39: Top Level Interfaces to VMeta™ Subsystem .................................................................................174

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List of Figures



Figure 40: dHub Block Diagram.......................................................................................................................176Figure 41: 2D Buffer Size Relationships ..........................................................................................................179Figure 42: 88DE3010 2D Graphics Block Diagram .........................................................................................184Figure 43: 88DE3010 2D Graphics Engine Pipeline........................................................................................185Figure 44: Alpha Blending Stages ...................................................................................................................191Figure 45: Interrupt Generation Scheme .........................................................................................................195Figure 46: High-level block Diagram of 88DE3010 device's Video Post Process Engine ...............................196Figure 47: Details of Main Video Plane pipeline ..............................................................................................200Figure 48: Block Diagram of Video Noise Reducer .........................................................................................202Figure 49: Block Diagram of Deinterlacer ........................................................................................................203Figure 50: Block Diagram of 88DE3010's Luma Edge Enhancement Solution ...............................................204Figure 51: PIP Post Processing Pipeline .........................................................................................................204Figure 52: Post Processing for BG Video Plane .............................................................................................205Figure 53: Post processing for Graphic Plane .................................................................................................206Figure 54: AUX Channel Connections .............................................................................................................207Figure 55: Internal Components of the scalar module .....................................................................................208Figure 56: Detailed Block Diagram of CPCB0 .................................................................................................213Figure 57: Block Diagram of Overlay Engine which is part of CPCB0/CPCB1................................................214Figure 58: Detailed Block Diagram of CPCB1 .................................................................................................216Figure 59: Detailed Block Diagram of CPCB2 .................................................................................................217Figure 60: High-level block Diagram of 88DE3010's Color Management Unit (CMU).....................................218Figure 61: Flesh Tone Correction ...................................................................................................................219Figure 62: Block Diagram of HDMI VOP module.............................................................................................221Figure 63: Block Diagram of the HDMI Transmitter along with the HDMI-TX PHY..........................................222Figure 64: Block Diagram of HD Component VOP module .............................................................................225Figure 65: Block Diagram of the Video Encoder and Video DACs ..................................................................226Figure 66: Block Diagram of the 88DE3010 device's Digital Video Output Scheme .......................................230Figure 67: DVO Interface Timing Diagram.......................................................................................................231Figure 68: Block Diagram of 88DE3010's VPP Clock-scheme ........................................................................234Figure 69: AVPLL Functional Diagram ............................................................................................................237Figure 70: Audio DSP Block Diagram..............................................................................................................240Figure 71: Functional Diagram.........................................................................................................................247Figure 72: MAC Engine Block Diagram ...........................................................................................................249Figure 73: Functional diagram of AIO module .................................................................................................265Figure 74: Audio Clock Generation Scheme....................................................................................................267Figure 75: I2S mode .......................................................................................................................................269Figure 76: Left-Justified mode ........................................................................................................................269Figure 77: Right-Justified mode ......................................................................................................................270Figure 78: S/P-DIF Frame Format ...................................................................................................................270Figure 79: S/P-DIF internal frame format .........................................................................................................271Figure 80: 88DE3010 Peripheral Block Diagram .............................................................................................273Figure 81: Peripheral Subsystem.....................................................................................................................280Figure 82: Major Components in pBridge operation ........................................................................................281Figure 83: Using the LDFN to link the scattered descriptor buffers .................................................................286

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Figure 84: Stacked configuration example using 2 Chip Selects and 1 Ready/Busy signal ............................288Figure 85: Stacked configuration example using 2 Chip Selects and 2 Ready/Busy signal ............................289Figure 86: NAND Flash Program Timing Diagram...........................................................................................290Figure 87: NAND Flash Erase Timing Diagram ...............................................................................................291Figure 88: NAND Flash Read Timing Diagram................................................................................................291Figure 89: NAND Flash Status Read Timing Diagram.....................................................................................292Figure 90: NAND Flash Read ID Timing Diagram ...........................................................................................292Figure 91: NAND Flash Reset Timing Diagram ...............................................................................................293Figure 92: NAND Flash Controller Block Diagram ..........................................................................................294Figure 93: Interconnection between LBC and other components....................................................................297Figure 94: An Example of External Device Interface .......................................................................................299Figure 95: LBC Write Protocol .........................................................................................................................300Figure 96: LBC Read Protocol .........................................................................................................................301Figure 97: SD2.0/SDIO2.0 Controller ..............................................................................................................303Figure 98: SD2.0/SDIO2.0 Block Diagram of Interactions of a Typical System...............................................303Figure 99: 88DE3010 GPIO Block Diagram ....................................................................................................305Figure 100: GPIO Interrupt Block Diagram ........................................................................................................307Figure 101: TWSI Start and Stop Condition.......................................................................................................308Figure 102: Start and Stop Condition.................................................................................................................309Figure 103: 7-bit Address Format ......................................................................................................................309Figure 104: 10-bit Address Format ....................................................................................................................310Figure 105: Master-Transmitter Protocol ...........................................................................................................310Figure 106: Master-Receiver Protocol ...............................................................................................................311Figure 107: Start Byte Transfer..........................................................................................................................311Figure 108: Normal Interrupt Generation – Interrupt 1 Example........................................................................313Figure 109: Example of a watchdog timer .........................................................................................................317Figure 110: Interrupt Generation........................................................................................................................318Figure 111: Counter Restart and System Reset ................................................................................................318Figure 112: Hardware Slave Selection ..............................................................................................................319Figure 113: Maximum SCLK_OUT/SPI_CLK Ratio ...........................................................................................320Figure 114: SPI Master Device ..........................................................................................................................323Figure 115: SPI Serial Format (SCPH = 0) ........................................................................................................324Figure 116: SPI Serial Format Continuous Transfers (SCPH = 0).....................................................................325Figure 117: SPI Serial Format (SCPH = 1) ........................................................................................................325Figure 118: SPI Serial Format Continuous Transfer (SCPH = 1) ......................................................................326Figure 119: PWM Block Diagram.......................................................................................................................328Figure 120: Waveform .......................................................................................................................................328Figure 121: Ethernet Descriptors and Buffers....................................................................................................338Figure 122: Ethernet TX Descriptor Structure....................................................................................................340Figure 123: Ethernet RX DMA Descriptor ..........................................................................................................343

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88DE3010 Overview



1 88DE3010 OverviewThe simplified block diagram of the 88DE3010 device is shown below

Figure 1: Simplified Block Diagram

32b DDR2/3 400 MHz

SDIO SPI

Dual channel HDMulti-Format

Decoder(H.264, VC1, MPEG2, WMV,

VP6, etc)

NAND

32b DDR2/3 400 MHz

Qdeo™Video Post Processor

Video Encoder &

6 DAC

AudioFormatter

HDMI v1.3Transmitter

2D GFX400 MHz

GC300

DRMDMXEngine400 MHz

Figo AES / DES

Multi2 / RSA

2560b OTP

System Manager

CPU

IRGPIO

SATA

x2 PCIe TWSIx4

FastEthernet

USB2.0 x2

Audio DSP500 MHzwMMX

32K+32K L1

AV Processor

32K+32K L1wMMX

Application Processor

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Figure 2: Simplified Block Interface Diagram

HDMI1.3

1+2/4 T/S Interface

DRM & DeMux Processing

7.1 I2S Stereo I2S

S/PDIF

HDMIMAC+PHY

6 Video DAC

EthernetController

Digitalvideooutput

YPbPrS-videoComposite

2 HDH.264/VC-1/

MPEG-2 Decoder

PCIe BusController

USB2.0Host

USB USBPCIe BusInterface

2D GraphicsEngine

32-bitDDR2

32-bitDDR2

Dual ChannelDDR2 Controller

Qdeo™ ProcessorDual-ScalerDe-interlacer

Noise Reducer

AudioFormatter

AudioDSP

GPIO

NANDSPI

VFDGPIO

SDIO

Local I/FController

SATA Controller

SATA SATA MII InterfaceUART TWSI

SystemManager

SDIO Controller

ApplicationProcessor

32 kB I-Cache32 kB D-Cache

32 kB I-Cache32 kB D-Cache

AVProcessor

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Global UnitOverview



2 Global Unit

2.1 OverviewThe 88DE3010 device relies on the Global Unit to provide on-chip clocking and reset signals. The Global unit also handles all the chip and system level control. The Global Unit includes clock module, reset module, boot strap module, and CPU Programmable Registers. Figure 3 depicts the relationships among these modules.

The reset module takes the system reset signal from the chip reset input pad and resets from CPU controlled registers to create individual resets to each sub-system. The boot strap module latches the strapping values from the pads 600 ns (15 cycles of 25 MHz clock) after the system reset (RSTIn) changes from low to high. The strap values will be kept in registers for CPU to read and the same registers are also directly used to configure the 88DE3010 device. In this way, the boot strap register values and the actual configuration are always consistent. The boot straps are used to select 88DE3010 clock generation options, JTAG debug options, and CPU boot options. The strap descriptions can be found in 88DE3010 Datasheet, Part 1. The clock module includes a 25 MHz crystal oscillator, 4 PLLs that generate required frequencies, and clock divider/switching logic for all the sub-systems of the 88DE3010 device. The clock parameters are controlled by CPU programmable registers. The detailed definitions of clock parameters can be found in the Global module’s register section of the 88DE3010 datasheet.

Figure 3: 88DE3010 Device Global Unit Block Diagram

Clock Module

Reset Module

CPU Programmable

RegistersConfig Bus

Boot Strap Module

External ResetRegister Values

Strap Values

ClockStraps

Clock Parameters

Oscillator PADs

Boot Strap Pads

StrapValues

Resets

Clocks

PLLResets

SW Resets

RCLKI, RCLKO

Strap LatchingSignal

(RSTIn)

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2.2 Global Unit Functional Description2.2.1 Reset Module

For each clock domain that a particular sub-system operates on, separate reset signals are generated.

2.2.1.1 Reset SourcesThere are three sources to generate each individual reset:

Reset input through external pad.Watch dog reset.Register controlled module reset.

Figure 4 shows the reset structure for the 88DE3010 device.

Figure 4: 88DE3010 Device Reset Structure

2.2.1.2 Software Reset SchemeThe 88DE3010 device utilizes a pair of reset registers namely, reset trigger register and reset status register to facilitate the software resets. When SW writes a ‘1’ to a reset trigger register bit, it results in the assertion of the corresponding reset for 16 reference clock cycles (25 MHz). The corresponding reset status bit will be set to 1 until cleared by software. Both reset trigger register and reset status register can be accessed by CPU.

2.2.1.3 External Reset SequenceDuring the hardware reset, the 88DE3010 device prevents the CPU from booting up earlier than the rest of the SoC by de-asserting the CPU reset after all other resets are de-asserted.

ResetCKT

CPU

Power Supply

WDT

GPIO

SM

ENB

0

SoC

EN

B

0

RSTInSM_RSTIn

SM_cpu_rstn

SM_sys_rstn

SM_SOC_RSTOn

ENB

0

PWR_EN(SM_GPIO[2])

SM_RSTOn

Glitch Filter Extend X Cycles

Extend Y Cycles

CPUx ResetWD Reset

WD ResetSW Module 1 Reset

Sync. &Test MUXCPUx Clock

Sync. &Test MUX

Module 1 Clock

RSTIn

WD ResetSW Module 2 Reset

Sync. &Test MUX

Module 2 Clock

RSTIn

. . . . .

Note: 25MHz CycleX Cycles = (Y + 32) Cycles.

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Global UnitGlobal Unit Functional Description



The power-up reset sequence is as follows:

1. External Reset pin is asserted, hardware reset takes place. The full 88DE3010 device is reset immediately.

2. External Reset is de-asserted. 88DE3010 device reset state machine starts to work.3. 88DE3010 internal reset state machine de-asserts PLL reset. PLL starts to oscillate and lock.4. 88DE3010 latches power-on setting from strap pins. 5. PLLs are locked and stable clocks are driven to the modules after 10 ms.6. Global reset is de-asserted to all modules (except CPU after 10 ms).7. De-assert CPU resets after 32 cycles (25 MHz).

Figure 5 shows the 88DE3010 power up sequence.

Figure 5: 88DE3010 Device Power Up Sequence

2.2.2 Clock ModuleClock module generates the clocks to each sub-system in 88DE3010 device using PLL and dividers.

2.2.2.1 PLL and OscillatorClock module has internal oscillator to generate stable reference clock to the PLLs using external 25 MHz crystal.

Table 1 lists the PLLs which are present in Clock modules and their corresponding frequency outputs.

Reset from PAD (RSTIn)

25MHzOSC Clock

Latching Strap Values from

PAD

PLL Reset(Active High)

PLL Lock

Module Reset Except CPUs (Active Low)

CPU Reset (Active Low)

Module Clock

PLLs Start Oscillate after de-asserting

PLL reset

1 2 3 4 5 6 7

(0 ns) (160 ns) (600 ns) (10.5 ms) (21.0 ms) (21.00128 ms)

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PLL frequencies can be adjusted without affecting the normal operation of the SoC with the following programming sequence:

1. Switch clock source to reference clock by setting the clock into bypass mode (Note: Using PLL generated clock registers to change PLL parameters is prohibited).

2. Program PLL to the new desired frequency by changing its corresponding parameters.3. Assert PLL Reset to have PLL re-LOCK with the new setting.4. Switch clock source back to PLL clock output.

Table 1: PLLs and Output Frequency

# PLL Frequency Output Range

Output Frequency Formula Notes

1 Memory PLL

75 MHz - 1.2 GHz CLKOUT = (FBDIV[8:0]+2) / 3 * 25 / VCODIV

User can change the Feedback divider “FBDIV” values and VCO divider “VCODIV” value to obtain the desired PLL frequency.The following blocks clocks are provided by this PLL during reset default:• DDR Memory Controller• DDR PHY

2 CPU1 PLL

100 Mhz - 1.6 GHz CLKOUT = FBDIV[8:0]/ 3 * 25 / VCODIV

User can change the Feedback divider “FBDIV” values and VCO divider “VCODIV” value to obtain the desired PLL frequency.CPU1 clock are provided by this PLL during reset default.

3 System PLL

75 MHz - 1.2 GHz CLKOUT = (FBDIV[8:0]+2) / 3 * 25 / VCODIV

User can change the Feedback divider “FBDIV” values and VCO divider “VCODIV” value to obtain the desired PLL frequency.The following blocks clocks are provided by this PLL during reset default:• VMeta™• Peripheral sub-system• Audio DSP• Audio Post-processor• Video Post-processor• CPU0• 2D Graphics

4 AVPLL Up to 2.22527 GHz CLKOUT = 25 * FBDIV_A/B[7:0] There are 2 independent PLLs (PLL_A and PLL_B) in AVPLL. User can change Feedback divider “FBDIV_A/B” values to obtain the desired PLL frequency for PLL_A and PLL_B respectively. The final clock output is also determined by its corresponding interpreter’s frequency offset and PPM offset setting.For details of the AVPLL parameters, refer to 88DE3010 register spec. Also for detailed audio video clocks, refer to AVPLL section of VPP Subsystem in 88DE3010 datasheet Part II.Audio and video pixel clocks are provided by this PLL during reset default.

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2.2.3 Clock Dividers and SwitchesThe 88DE3010 device’s clock divider creates divide by 1, divide by 2, divide by 3, divide by 4, divide by 6, divide by 8, and divide by 12 clocks for each individual module. To provide more flexibility of clock sources, the 88DE3010 device also allows each clock to select from different PLL outputs as their clock divider’s source clock. Table 2 lists the main clocks in 88DE3010 device and corresponding options available to select the clock sources.

Table 2: Main Clock Options

# Clock Clock Sources Options Clock Divider Options

Max Frequency

1 DDRPHY clock Memory PLL None 800 MHz

2 Memory Controller clock

Memory PLL divide by 2 None 400 MHz

3 CPU1 clock CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 1200 MHz

4 CPU0 clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 1200 MHz

5 VMeta™ clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 800 MHz

6 Graphics clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 400 MHz

7 System clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 400 MHz

8 APP clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 700 MHz

9 DRM clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 400 MHz

10 Peripheral System clock

System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 200 MHz

11 Register Configuration clock

System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 100 MHz

12 VPP System clock System PLL or CPU1PLL or 3 outputs from AVPLL Divide by 1/2/3/4/6/8/12 300 MHz

13 VPP HD Primary Video clock

AVPLL A[1] None 300 MHz

14 VPP 2nd Video Output clock

AVPLL A[2] or AVPLL B[2] None 300 MHz

15 VPP SD Auxiliary Video clock

AVPLL B[1] None 300 MHz

16 Audio HDMI clock AVPLL A[4] None 400 MHZ

17 Primary Audio clock AVPLL A[3] Divide by 1/2/3/4/6/8/12 200 MHZ

18 Audio S/PDIF clock AVPLL A[3] Divide by 1/2/3/4/6/8/12 200 MHZ

19 Audio MIC clock AVPLL A[3] Divide by 1/2/3/4/6/8/12 200 MHZ

20 Secondary Audio clock

AVPLL A[3] or AVPLL B[3] Divide by 1/2/3/4/6/8/12 200 MHZ

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The 88DE3010 device’s individual clock divider and clock mux settings could be changed during the operation dynamically. Refer to Figure 6 for the clock generation structure.

Note

The 3 outputs from AVPLL referred to above are: AVPLL A[6], AVPLL B [6], and AVPLL B[7]

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Figure 6: 88DE3010 SoC Clock Structure

A

B

Oscillator

External reference Clock :: DV0_FID (VCLKI[0])

Oscillator Bypass :: BYPS_OSC

0

1

MemoryPLL

memPLLSWBypass

25 MHz Crystal Clock in :: RCLKI

25 MHzReference

Clock

1

0Divide by

2

Clock Divider and

Clock Selection Logic

DDRPHY Clock

Memory Controller Clock

CPU1 Clock

CPU0 Clock

VMeta Clock

Graphics Clock

APP Clock

DRM Clock

Peripheral Clock

VPP System Clock

88DE3010 System Clock

88DE3010Register ConfigClock

CPU1PLL

SystemPLL

cpu1PLLSWBypass

1

0

sysPLLSWBypass

1

0

Clock Divider and


Clock Divider and


Clock Divider and


Clock Divider and


Clock Divider and


Clock Divider and


Clock Divider and


AVPLL

A6

B6B7

Clock Divider and


Clock Divider and


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2.2.3.1 Clock Switching ProcedureThe clock generation scheme provides dynamic clock switching capability. Here is the programming pseudo code to illustrate the dynamic clock frequency change sequence using clock switching circuit shown in Figure 7.

If (desired clock frequency is divided by 3 clock) {

Turn on divide by 3 clock switch (ClkD3Switch = 1);Clock selection done;

}

else if (desired clock frequency is 1x clock) {

Turn off divided clock switch (ClkSwitch = 0);Turn off divide by 3 clock switch (ClkD3Switch = 0); Clock selection done;

}

else {

Select desired divided clock (/2, /4, /6, /8, or /12 by setting ClkSel);Turn on divided clock switch (ClkSwitch = 1);Turn off divide by 3 clock switch (ClkD3Switch = 0); Clock selection done;

}

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Global UnitBoot Strap Module



Figure 7: 88DE3010 Clock Divider and Clock Selection Logic

2.3 Boot Strap ModuleThe 88DE3010 device’s boot strap pins are shared with digital video output and SPI output pins. The 88DE3010 device will be the only driver of those pins in the system. During the boot up, the 88DE3010 device sets those pins to input mode and external pull-up/pull-down resistors will pull the boot strap pins to desired levels. After boot strap latching window, those pins can be driven by the SoC to any level without affecting the boot straps.The strapping information, which can be read by CPU, will be used to configure the 88DE3010 device. Please refer to the 88DE3010 data sheet Part I for detailed definitions of boot strap pin assignments and functions.

AVPLL

A

B

6

6

7

1

2

3

4

0

1

*ClkPllSel *ClkPllSwitch

From CPU1 PLL

divider

2

4

6

8

12

3

*ClkSel

0

1

*ClkSwitch

1

2

3

4

5

0

1

*ClkD3Switch *ClkEn

From System PLL

Clock Out to 88DE3010

Sub-Systems

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3 System Manager (SM)1The 88DE3010 device’s System Manager is designed for front panel control and power management functions in a media player device. The SM's core and I/O power supply are isolated from the rest of the 88DE3010 device (SOC). In the standby mode, all the power rails of the SoC will be shut down while the SM is powered up. This will enable the SM to drive the front panel, receive wake up events from the remote control or the front panel buttons, and initiate the SOC power up sequence. SM also supports wake up events from CEC. By shutting down the SOC power, standby mode power consumption will be less than 50 mW.

The SM includes a low power CPU (ARMv5TE compatible) with on-chip instruction SRAM (ITCM) and data SRAM (DTCM), I/O controllers such as TWSI, SPI, UART and GPIOs. The SM also has an integrated A/D converter and temperature sensor. In addition to direct access by the SM CPU, these SM I/O devices can also be accessed by the SOC CPUs through the internal AHB bus interface.

3.1 Power Domain and Power SequenceThe 88DE3010 device has two power domains - System Manager as the “always on power domain” and the rest of 88DE3010 (SOC) as the “controlled power domain”. As shown in Figure 8, both power domains have the same supply voltage, but the SM’s power supply is separated from the SOC’s power supply. This will allow power up on the SM block only and put the SOC’s power supply in system standby mode, thus minimizing system standby power consumption.

1. System Manager will be referred to as SM in this document.

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System Manager (SM)Power Domain and Power Sequence



Figure 8: 88DE3010 Power Domain Partitions

3.1.1 Power SequenceTo power down the SOC block and to effectively and safely power up the system later, a specific power up/down sequence is required. SM supports three scenarios for power sequence:

Initial power up sequence (cold boot) Power down sequence (entering standby mode from normal operation mode)Standby power up sequence (exiting standby mode to normal mode; Warm Boot)

In each scenario, specific power sequence must be followed. This is achieved by utilizing a combination of hardware and software.

3.1.1.1 Initial Power up Sequence (Cold Boot) 1. System power supply applies power to SM2. System power supply provides power to SOC.3. System de-asserts SM reset (SM_RSTIn). SM CPU is kept in reset state by default after SM

reset is de-asserted.4. System de-asserts SOC reset (RSTIn), SOC boots up from the SOC boot ROM.5. SOC downloads SM firmware Flash to the SM ITCM6. SOC programs SM internal register to de-assert the SM CPU reset.7. SM boots from the ITCM8. SM notifies SOC about the boot-complete state.

88DE3010

System Manager

SM_SOC_RSTOn

SM Reset Module

System Manager

CPUSOC

System Power Control

RSTIn

SM Watchdog Timer

SM GPIO

SM_RSTIn

System levelSOC Reset Logic

Always on Power Controlled Power

SM_RSTOn

System levelReset Logic

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3.1.1.2 Power Down Sequence (Entering Standby) 1. SM receives the power down request from panel or remote control. 2. SM informs SoC and waits for the SoC to acknowledge the request.3. SM asserts SM_SOC_RSTOn to assert SOC reset (RSTIn) through the system. SM resets SoC

by asserting SM_SOC_RSTOn pin, which is connected to the RSTIn pin on the system level.4. SM notifies system power supply to shut down the SOC power.5. SM de-asserts SM_SOC_RSTOn to de-assert SOC reset (RSTIn) through the system.6. System enters standby mode. Only SM block is active.

3.1.2 Standby Power Up Sequence (Exiting Standby; Warm Boot) 1. SM receives power up command from front panel control through the GPIO or UART/IR

receiver.2. SM asserts SM_SOC_RSTOn to assert SOC reset (RSTIn) through the system.3. SM notifies system power supply to turn on the SOC power.4. SM de-asserts SM_SOC_RSTOn to de-assert SOC reset (RSTIn) through the system.

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System Manager (SM)Functional Description



3.2 Functional DescriptionThe System Manager (SM) includes the following main functional blocks. Figure 9 shows the block diagram of the SM.

ARM v5TE compatible CPU with JTAG interface Clock/Reset generation Interrupt controller, GPIOs, Watchdog timer, SPI controller, TWSI controller, UARTADC (A/D converter) and temperature sensor

Figure 9: SM Block Diagram

JTAG I/F

System Manager CPU

ITCM

DTCMClock/reset

Local Bus

GPIOs

Soc CPUs

ADC

Temp Sensor

Registers

Security SRAM

SM_CLKI

SM

SM_RSTIn

SM_RSTOn

SM_SOC_RSTOn

UARTs

SPI Master

WDTs

Timers

Interrupt CTL

TWSI

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3.2.1 System Manager CPUThe System Manager CPU is an ARM v5TE compatible Marvell® CPU, refer to Section 5, System Manager CPU (SM CPU), on page 117 for detailed description. The SM CPU is configured to support 32 Kbyte instruction SRAM (ITCM), and 16 Kbyte data SRAM (DTCM). To save system power consumption, this CPU runs up to 30 MHz.

After power up, the SM CPU will be kept in reset state. The SOC CPU will boot first and then download firmware image to the ITCM in SM. After the image is downloaded, it de-asserts the SM CPU reset for it to boot up.

The SM CPU supports JTAG based ICE debugging. The 88DE3010 device provides two options to access the System Manager debugging port:

Through its dedicated JTAG interface. In this mode, the SOC CPU and SM CPU will be on separate chains and require two debuggers, and there will be no communication between the two debuggers.The SM debugging port as part of the SOC CPU JTAG chain. In this case, cross CPU debug can be achieved, but SOC must always be powered in order to access SM debug port

For detailed information on ICE debug support, refer to the JTAG Section.

3.2.2 Clock and Reset GenerationThe 88DE3010 SM has its dedicated on-chip oscillator to provide clocks for the sub-system. An external crystal of up to 30 MHz is required. This clock is the only clock used through out the SM sub-system.

The SM can be reset by:

External system level reset generation circuitWatchdog timer Software programmable register

In addition to these reset sources, the SM CPU has its own software programmable reset register control bit. By default, the reset register bit will keep SM CPU in reset state until SOC finishes downloading the SM CPU’s binary code to ITCM and clears this bit.

SM also has a reset output, SM_SOC_RSTOn. It can be used to reset the 88DE3010 SOC and other system level components. The SM CPU can set this reset output. The reset output will also be driven to active level.

3.2.3 System Manager Address MapThe hardware devices in the 88DE3010 SM can be accessed by both SM CPU and SOC CPU0 or CPU1. Table 3 and Table 4 show the address map of these devices from both SM CPU and SOC CPU. Note that the memory map refers to the starting address of each module. Refer to the 88DE3010 Register Manual for actual effective register space defined by each module.

The 4K Bytes security SRAM is designed to store security information when the SOC is powered off, and can be retrieved after SOC is powered on again. This memory space is not accessible by SM CPU, and will be securely controlled by the SOC interconnect during boot up. Only secure masters can access this SRAM. For more information on secure access, refer to Section 8, SoC Connectivity and Access Control, on page 139.

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Table 3: SM Memory Map

Devices SM Address Range SOC Address Range

32 KBytes ITCM 0x0000_0000 0x0000_7FFF

0xF7F8_00000xF7F8_7FFF

Reserved 0x0000_80000x03FF_FFFF

0xF7F8_80000xF7F9_FFFF

16 KBytes DTCM 0x0400_00000x0400_3FFF

0xF7FA_00000xF7FA_3FFF

Reserved 0x0400_40000x0FFF_FFFF

0xF7FA_40000xF7FB_FFFF

I/O devices 0x1000_00000x1000_FFFF

0xF7FC_00000xF7FC_FFFF

4 Kbytes Security Memory Not accessible 0xF7FD_00000xF7FD_0FFF

Table 4: System Manager I/O Device Address Map

I/O devices Base Start ing Address for SM Access

Start ing Address for Soc CPU Access

Note

Interrupt Controller 0 0x1000_0000 0xF7FC_0000 System Manager hardware interrupt controller for SM CPU

Watchdog Timer 0 0x1000_1000 0xF7FC_1000



Timers 0x1000_4000 0xF7FC_4000

<reserved> 0x1000_5000 0xF7FC_5000

SPI master 0x1000_6000 0xF7FC_6000

TWSI0 master 0x1000_7000 0xF7FC_7000

TWSI1 master 0x1000_8000 0xF7FC_8000

UART0 0x1000_9000 0xF7FC_9000

UART1 0x1000_A000 0xF7FC_A000

UART2 0x1000_B000 0xF7FC_B000

GPIO 0x1000_C000 0xF7FC_C000

SM system control registers

0x1000_D000 0xF7FC_D000

Interrupt Controller 1 0x1000_E000 0xF7FC_E000 System manager devices interrupt controller for SOC CPUsInterrupt Controller 2 0x1000_F000 0xF7FC_F000

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3.2.4 System Manager Hardware DevicesThis section briefly describes the peripheral devices integrated in 88DE3010 SM subsystem. For detailed information of these devices, including interrupt controller, Timer, WDT timer, SPI, TWSI, UART, and GPIO controller, refer to the section Low Speed Peripheral Devices.

3.2.4.1 Interrupt ControllerSM has total 3 interrupt controllers. Each controller merges 16 interrupt inputs to generate a single IRQ request to SM CPU directly or to SOC interrupt controllers. All the interrupts are level triggered. The SM interrupt controller supports software interrupts, priority filtering, and vectorized interrupts which are not supported by 88DE3010 CPUs. The SM interrupt controller supports configurable input and output polarity.

The output of ICTL0 is connected to SM CPU, and the output of ICTL1, ICTL2 are connected to two SOC interrupt controller inputs (Refer to the SoC PIC document for further details).

Table 5 shows the interrupt sources connected to the interrupt controller.

3.2.4.2 TimersThis timer module in SM includes three identical but separately-programmable timers. These timers are driven by the SM clock. For each timer, software can program a 32-bit initial value. After it is kicked off, the timer will count down from this initial value. When it reaches zero, the timer will generate an interrupt and re-load the initial value and start count down again.

3.2.4.3 Watchdog Timer (WDT)The 88DE3010 SM provides watchdog timer to detect system hang from software or hardware issues.

Table 5: Interrupt Sources Connected to Interrupt Controller

Interrupt Number Interrupt Type Interrupt Source

0 IRQ Watchdog 0

1 IRQ Watchdog 1

2 IRQ Watchdog 2

3 IRQ Timers

4 IRQ <Reserved>

5 IRQ SPI Master

6 IRQ TWSI0 Master

7 IRQ TWSI1 Master

8 IRQ UART0

9 IRQ UART1

10 IRQ UART2

11 IRQ GPIO

12 IRQ ADC

13 SW IRQ Software programmable register bit

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The WDT counts down from a 32-bit preset timeout value. When the counter reaches zero, a system reset or CPU interrupt will be generated depends on software setting of the WDT mask register. After the WDT reaches zero, it will re-load the pre-set timeout value and start count down again.

Software can restart from the preset timeout value at any time.

There are three WDTs in the 88DE3010 SM, each of them can be separately enabled or disabled to trigger SM and SOC resets through the mask register. As shown in Figure 8, when any of the WDTs has timed out, and if its corresponding SM mask bit is disabled, the full SM module will be reset, the SM_RSTOn pin will also be asserted; On the other hand, if the corresponding SOC mask bit is disabled, the SM module will not be reset, only the SM_SOC_RSTOn pin will be asserted to reset the 88DE3010 SOC portion.

3.2.4.4 SPI MasterSPI Master supports multiple serial protocols. The protocols supported are:

Serial Peripheral Interface (SPI) – A four-wire, full-duplex serial protocol. There are four possible combinations for the serial clock phase and polarity. The serial transfer can begin at the falling edge of the slave select signal or at the first edge of the serial clock depending on register setting. Serial Protocol (SSP) – A four-wire, full duplex serial protocol. The slave select line used for SPI and Microwire protocols doubles as the frame indicator for the SSP protocol.Microwire – A half-duplex serial protocol, which uses a control word transmitted from the serial master to the target serial slave.

3.2.4.5 TWSI MasterTwo TWSI masters are implemented to support fast transfer mode and 10-bit addressing.

3.2.4.6 UARTThree UARTs are selected for the SM design. UART0 provides flow control and IrDA functions, UART1 supports IrDA, and UART2 is 16500 compatible UART without busy functionality.

3.2.4.7 GPIOThis block provides total 16 of generic input/output controls. GPIO[7:0] have interrupt support, and GPIO[15:8] have no interrupt support.

3.2.5 Successive Approximate Register (SAR) ADCThe 88DE3010 SM ADC is designed for low sampling rate applications. The ADC supports 8 channels (channel 0 to 7) with 10-bit precision and its operating frequency range is 0.2 MHz ~ 13.33 MHz. The ADC input voltage range is from 0 – 2V. Channel 6 is connected to the 88DE3010 internal temperature sensor, and channels 0 to 3 are connected to 4 external ADC inputs respectively. Channel 4, 5, and 7 are reserved.

Users can connect different analog sources to these 4 ADC inputs, such as front panel keypad, voltage supply monitoring, etc.

3.2.6 Temperature SensorThe 88DE3010 SM temperature sensor measures the silicon temperature inside the package. The voltage output of the temperature sensor is connected to ADC channel 6. By reading the ADC output registers, software can monitor the silicon temperature and take necessary actions. The range of the SM temperature sensor is from -40 degC (degree Celsius) to 125 degC, with accuracy of ±10 degC.

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88DE3010 DatasheetHigh Definition Media Processor System on Chip



4 SoC CPUThe 88DE3010 CPU is a Marvell® High-performance SheevaTM CPU Core that implements ARM v5TE architecture. The processor core components are suitable for Real-Time OS (RTOS) time-slice and Virtual-Memory (VM) embedded applications that require large memory spaces, on-chip cache, and hardware-based optimization of compiled microcode.

The 88DE3010 CPU sub-system integrates two identical Sheeva CPUs. Each of them has a SIMD accelerator, MMU, multilevel TLB, and Level 1 caches on a full Harvard bus architecture.

The 88DE3010 device CPU has 32-KByte direct mapped Instruction Cache and 32-KByte four-way set-associative Data Cache.

The Sheeva CPU core supports ARM and Thumb instructions, as well as hardware acceleration of Intel® Wireless MMXTM 2 v1.51 instructions (SSE 1.0 with New Media and Wireless extensions).

The core’s variable-length pipeline retires instructions in order, performing branch prediction and data forwarding in hardware, so existing applications do not require recompilation for higher instruction throughput. The Marvell® optimizing compilers can further enhance performance.

1. Referred to as WMMX2 in this document

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SoC CPUSoC CPU Implementation Details



Figure 10 shows the SoC CPU Block Diagram.

Figure 10: 88DE3010 SoC CPU Block Diagram

4.1 SoC CPU Implementation DetailsThe SoC CPU is compliant with the ARM v5TE instruction set architecture. Implementation-specific details are listed below:

Unsupported Instructions - The SoC CPU will initiate an “undefined” exception for the following unsupported instructions (when accessing coprocessors that are disabled or do not exist):• MCRR• MRCC• CDP• LDC• STC• MCR/MRCModes of Operations - User-mode access to CP15 causes an “undefined” exception, unless specified otherwise in this document.PLD Instructions - SoC CPU implements PLD instructions.The CPU has 4-entry PLD buffers such that it can have up to 4 outstanding PLDs without stalling LDST Pipeline.

Instruction / Data Processing Units

CPU Coprocessors

Write Buffer

Bus Interface

Debug Interface

ICE Interface I- Cache Unit D-Cache Unit

BISTInterface

CPU Core

To JTAGInterface

Instruction UnitDA

IA WD

ATA/

RDATA

L 1 Instruction Cache

L1 I - Cache Controller L 1 D - Cache Controller

CP 14 DebugCoprocessor

CP15 Control Coprocessor MMU

Load Store Unit

L1 Data Cache

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Bus Error Allowed only on Cache line Boundary - The SoC CPU assumes that a bus error for a cacheable region can only happen at a cache line boundary. If there is a bus error on only some of the words in the cache line during a line fill, the result is unpredictable.Cache Maintenance - If an instruction already resides in I-Cache and later on the cacheability bit is changed to 0, the software is responsible for flushing that cache line before changing the cacheability bit.Use of Memory Space - It must be ensured that the bus slaves cover all 4GB of the memory space. If there is any illegal space being accessed, the bus slave can return a bus error response. It is important not to let the bus hang without a response.

4.2 Data Abort ModelThe SoC CPU processor implements the base restored Data Abort model. When a Data Abort exception occurs, the processor hardware always restores the base register’s value to that before an instruction is executed. This removes the requirement for the Data Abort handler to unwind any base register.

If there is a data abort and base update is performed, the base register will not be updated. If PC is being used as Rd for STM and STR, the Rd value will be current PC+12. This can only happen for 32-bit mode. All other PC operands use PC+8 and PC+4 for 32-bit and 16-bit mode, respectively.

4.2.1 Data Abort SourcesThe following sources can cause Data Aborts:

Data transactions to an external memory space that return an error response. All aborts are precise. For buffered writes, the error is dropped and no abort taken. Unaligned data accesses (when data alignment checking is enabled).MMU translation error.Access permission fault.

4.2.2 Prefetch Abort SourcesThe following sources can cause Prefetch aborts1

Instruction fetches from an external memory space that returns an error response.Executing a Breaking Point (BKPT) Instruction causes the prefetch abort exception to be entered. MMU translation error.Access permission fault.

For general details about exceptions refer to the ARM® Architecture Reference Manual (Document Number DDI 0100I).

4.3 Core CoprocessorsThe 88DE3010 SoC CPU includes two built-in coprocessors for configuration and control, containing logic to enable, monitor, and control the processor core.

CP15 – Configures MMU, Caches, write buffer, performance counters, and other system options such as endianness. For details, see Section 4.6, CP15 Coprocessor, on page 45.CP14 – Enables software access to the debug communications channel. The coprocessor registers are accessible via MCR and MRC instructions.

1. Prefetch aborts can occur when the instruction fetch is carried out.

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SoC CPUSoC CPU Interrupt Timing



4.4 SoC CPU Interrupt TimingThe 88DE3010 SoC CPU Core does not allow interrupts to be taken on any instruction that will update CPSR. Each of the Thumb BL and BLX[1] instructions contain two back-to-back branches. The first branch does not actually do a branch but rather sets up an offset used by the second branch. The 88DE3010 does not allow interrupts to be taken between such two back-to-back branches.

4.5 Instruction set summarySee ARM® Architecture Reference Manual (Document Number DDI 0100I) for details of ARM Instruction Set and its encodings.

4.6 CP15 CoprocessorThe CP15 Processor provides control and configuration of the processor core components, including the MMU, Caches, BPU, MMU TLBs, Performance Counters, and Fault Status registers.

4.6.1 CP15 Register SummaryRegisters represented by Register Numbers (such as R0, R1 etc.) provide access to several deeper registers selected by register bank and opcode. Summary of these registers is provided in Table 6.

See also Section 4.6.23, Abbreviations for Register Descriptions for meaning of the abbreviations.

Note

The 88DE3010 SoC CPU allows an instruction in Reorder Buffer (ROB) entry 0 to finish when an interrupt comes in. Note that If this is an LDSTM, the CPU needs the whole LDSTM to be completed first. If this instruction in ROB entry 0 causes an exception, the exception will be taken before the interrupts are handled. The CPU takes the interrupts on the next valid instruction.

Table 6: CP15 Register Map

Register (R#)

Register (Full Path)

Read Write Page#

R0 CP15.0.R0.c0.{0, 3-7} ID Code Register UNP page 48

R0 CP15.0.R0.c0.1 Cache Type Register UNP page 49

R0 CP15.1.R0.c0.1 RSVD UNP -

R0 CP15.0.R0.c0.1 RSVD UNP -

R1 CP15.0.R1.c0.0 Control Register Control Register page 51

R1 CP15.0.R1.c0.{0-1} Auxiliary Control Register

Auxiliary Control Register

page 55

R2 CP15.0.R2.c0.0 Translation Table Base Register

Translation Table Base Register

page 57

R3 CP15.0.R3.c0.0 Domain Access Control Register

Domain Access Control Register

page 58

R4 CP15.0.R4.c{0-15}.{0-7} RSVD RSVD page 59

R5 CP15.0.R5.c0.0 Data Fault Status Register

Data Fault Status Register

page 60

R5 CP15.0.R5.c0.1 Instruction Fault Status Register

Instruction Fault Status Register

page 61

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R6 CP15.0.R6.c0.0 Fault Address Register

Fault Address Register

page 63

R7 CP15.0.R7.c{0-14}.{0-2} Cache Operations Registers

Cache Operations Registers

page 64

R8 CP15.0.R8.c{5-7}.{0-1} UNP TLB Operations Register

page 69

R9 CP15.0.R9.c0.0 D-Cache Lockdown Register

D-Cache Lockdown Register

page 70

R9 CP15.0.R9.c0.1 I-Cache Lockdown Register

I-Cache Lockdown Register

page 70

R10 CP15.0.R10.c0.0 TLB Lockdown Register

TLB lockdown Register

page 72

R11 RSVD RSVD RSVD page 74


R13 CP15.0.R13.c0.0 FCSE PID Register FCSE PID Register page 74

R13 CP15.0.R13.c0.1 Context ID Register Context ID Register page 75


SoC CPU Performance Monitor-related Registers:

R15 CP15.0.R15.c12.(0-3) Counter Operations Registers

Counter Operations Registers

page 76

R15 CP15.0.R15.c13.{0-7} Counter Value Registers

Counter Value Registers

page 82

R15 CP15.0.R15.c14.0 Interrupt Enable Register

Interrupt Enable Register

page 83

R15 CP15.0.R15.c14.1 Overflow Status Flag Register

Overflow Status Flag Register

page 84

Extra Features Registers (provides additional features to the SoC CPU):

R15 CP15.0.R15.c1.0 Coprocessor Enable Register

Coprocessor Enable Register

page 86

R15 CP15.1.R15.c1.1 Control Configuration Register

Control Configuration Register

page 88

R15 CP15.0.R15.c9.0 Privileged Access Register

Privileged Access Register

page 90

R15 CP15.1.R15.c12.0 CPU ID code Extension Register

UNP page 91

R15 CP15.1.R15.c12.4 UNP BPU Operations Register

page 92

Table 6: CP15 Register Map (Continued)

Register (R#)

Register (Full Path)

Read Write Page#

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SoC CPUCP15 Coprocessor



4.6.2 Address TypesTable 7 describes the address types in the SoC CPU when operating in MMU mode.

If in MMU mode, the following steps summarize the event sequence when the SoC CPU fetches an instruction:

1. The CPU core issues the instruction’s Virtual Address (VA).2. If the Fast Context-Switch Extension (“FCSE”) is enabled, the MMU translates the virtual

address into a Modified Virtual Address (“MVA”), created using the “[R13] FCSE PID Register” on page 74 PID value.

3. If the FCSE PID is disabled (0), then the VA is treated as an MVA. 4. The I-Cache, D-Cache, and MMU receive the MVA.5. If the MVA Tag is not found in the I-Cache or D-Cache, the MMU will take over the search

operations for the instructions or data.6. The MMU translates the MVA to a PA. If the address passes all protection checks, and the

addressed location has not been cached, then the processor core passes the PA to the bus interface, and the bus interface performs an external access at the supplied PA.

See also: “[R8] TLB Operations Register” on page 69.

Table 7: Address Types

Domain Address Type Acronym

CPU Core Virtual Address VA

Caches & MMU Modified Virtual Address MVA

CPU External Bus Physical Address PA

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4.6.3 CP15 Status RegistersThese registers read either the device ID, or the cache type, depending on the opcode_2 value:

opcode_2 = 0 --> ID

opcode_2 = 1 --> Instruction and data cache type

These registers are accessed with the following instructions:

MRC p15, 0, Rd, c0, c0, {0, 3-7} ; Read ID Code

MRC p15, 0, Rd, c0, c0, 1 ; Read Cache Type

When reading from these registers, the CRm field value should be 0. Writes to R0 are UNP.

SoC CPU ID Code Registers and Cache Type Register are described in the following sub-sections.

4.6.3.1 [R0] ID Code RegisterUnique ID: CP15.0.R0.c0.{0, 3-7}The ID Code Register returns a 32-bit device code.It is a Read-only register and can be accessed by reading Register R0 with opcode_2 set to any value other than 1 or 2.

The register is accessed by reading it with the following instructions:

MRC p15, 0, Rd, c0, c0, {0, 3-7} ; Read ID Code Register

Table 8 describes the bit-level details of the ID Code Register.

Table 8: ID Code Register Bit-level Description

Bits Field Access Reset Description

31:24 Impl RO 0x56 Implementerx56 = Marvell® as implementer

23:20 Variant RO 0X1 Major Revision Number

19:16 Arch RO 0x5 v5TE Architecture0x5 = V5TE

15:13 Core Generation RO b100 Part number

12:10 Core Revision RO b000 Core Revision NumberNOTE: This can change with specific silicon

implementation

9:4 Product Number RO b000000 Product Number

3:0 Product Revision Number

RO b0000 Product Revision Number

Note

Unique IDs like the one defined for this register (cp15.0.R0.c0.0) has been shown throughout this section and is based on Section 4.6.22, The Marvell® Nomenclature for Uniquely Identifying Coprocessor Registers

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4.6.3.2 [R0] Cache Type RegisterUnique ID: CP15.0.R0.c0.1The Cache Type Register contains information about the size and architecture of the Instruction Cache (I-Cache) and the Data Cache (D-Cache). This register helps operating systems to establish how to perform functions such as cache cleaning and lockdown. It is a Read-only register.

The register is accessed by reading it with the following instruction:

MRC p15, 0, Rd, c0, c0, 1 ; Read Cache Type Register

Table 9 describes the bit-level details of the Cache Type Register.

Table 9: Cache Type Register Bit-level Description


31:29 RSVD RO 0x0 Reserved.

28:25 cType RO b000 Cache TypeReports the field type. It also specifies if the cache supports lockdown and the cleaning of the cache. Note: cType is currently b000 in all implementations.

24 S RO SBO SplitThe S bit reveals if the cache is unified or separate.0 = Cache is unified. The iSize and dSize fields both describes the unified cache, and are identical.1 = Harvard architecture. I-Cache and D-Cache are separate.

23:22 RSVD RO 0x0 Reserved.

21:18 dSize RO b110 D-Cache SizeThe default implementation has a 32KB D-Cache size. b0011 = 4 KBb0100 = 8 KBb0101 = 16 KBb0110 = 32 KBb0111 = 64 KBb1000 = 128 KBReset value depends on implementation.

17:15 dAssoc RO b010. D-Cache Set AssociativityReports whether cache is direct mapped or has multiple ways. The default implementation is 4-way set associative. b000 = Direct mappedb001 = 2-way Set-Associativeb010 = 4-way Set-AssociativeReset value depends on implementation.

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14 dMode RO b0 D-Cache ModeThe dMode and the dSize fields together report the cache size. The dMode and dAssoc fields together report the cache associativity. dMode is currently 0 in all implementations.

13:12 dLen RO b10 D-Cache Line Lengthb10 = 8 words (32 bytes) per line.

11:10 RSVD RO 0x0 Reserved

9:6 iSize RO b110. I-Cache SizeThe default is 32KB. b0011 = 4 KBb0100 = 8 KBb0101 = 16 KBb0110 = 32 KBb0111 = 64 KBb1000 = 128 KBReset value depends on implementation.

5:3 iAssoc RO b010 I-Cache Set AssociativityOlder designs are direct mapped. Newer designs may have 4 ways. b000 = Direct mappedb001 = 2-way Set-Associativeb010 = 4-way Set-AssociativeReset value depends on implementation.

2 iMode RO b0 I-Cache ModeThe iMode and the iSize fields together report the cache size. The iMode and iAssoc fields together report the cache associativity. iMode is currently 0 in all implementations.

1:0 iLen RO b10 I-Cache Line Lengthb10 = 8 words (32 bytes) per line.

Table 9: Cache Type Register Bit-level Description (Continued)


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4.6.4 [R1] Control RegisterUnique ID: CP15.0.R1.c0.0The Control Register defines the configuration used to enable and disable the MMU, Caches, WB, and BPU. This register is also used to control a few other miscellaneous CPU functions. It is a Read/Write Register. Software should always access this register with a read-modify-write sequence.

Control register can be accessed with the following instructions:

MRC p15, 0, Rd, c1, c0, 0 ; Read Control Register

MCR p15, 0, Rd, c1, c0, 0 ; Write Control Register

Table 10 describes the bit-level details of the Control Register.

Table 10: Control Register Bit-level Description


31:27 RSVD UNP/SBZP UNP/SBZP ReservedNote: Reads are unpredictable, and writes should preserve the original value.

26 RSVD RW - Reserved.

25:19 RSVD UNP/SBZP UNP/SBZP Reserved

18 RSVD SBO SBO Reserved

17 RSVD SBZ SBZ Reserved

16 RSVD SBO SBO Reserved

15 L4 RW b0 PC Sets T BitDetermines if the T bit is set when load instructions change the PC:

1 = Loads to PC do not set bit T.0 = Loads to PC set bit T.

For further details refer to the ARM Architecture Reference Manual, Second Edition.

14 RR RO 0x0 Cache Replacement AlgorithmReports replacement strategy for I-Cache and D-Cache.

0 = Random replacement.1 = Round-robin replacement.

This bit is always zero and ignores writes.

13 V RW b1 Exception Vector AddressDefines the location of exception vectors.

1 = High exception vectors selected, address range = 0xFFFF 0000 to 0xFFFF 001C.

0 = Normal exception vectors selected, address range = 0x0000 0000 to 0x0000 001C.

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12 I RW b0 I-Cache EnableThe I-Cache is disabled by default.

1 = I-Cache enabled.0 = I-Cache disabled.

11 BPU RW b1 BPU EnableBranch prediction is enabled by default.

1 = If the branch prediction unit is enabled.

0 = If the branch prediction unit is disabled.

10 RSVD SBZ SBZ Reserved

9 R RW b0 ROM ProtectionThis bit disables ROM protection.

0 = ROM protection enabled. Unprivileged pages and sections are not permitted access to read-only areas.

1 = ROM protection disabled. Pages and sections with user permissions are permitted access to read-only areas.

Either the S or R bit may be 1, but not both, otherwise results for pages with AP bits set to 0 is UNP.

8 S RW b0 System ProtectionThis bit modifies the MMU protection system.

0 = System protection disabled.1 = If the access permission (AP) bits

in the page and section descriptors are both 0, then privileged pages and sections are read only.

Either the S or R bit should be enabled, but not both, otherwise results for pages with AP bits set to 0 is UNP.

7 B RW b0 Endianness1 = Big Endian operation.0 = Little Endian operation.

6:3 RSVD SBO SBO Write Buffer EnableException handlers entered in 32-bit modes and 26-bit address exception checking disabled. These bits should always be set to 1 in all implementations.

2 C RW b0 D-Cache EnableThe D-Cache is disabled by default.

1 = D-Cache enabled.0 = D-Cache disabled.

Table 10: Control Register Bit-level Description (Continued)


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1 A RW b0 Alignment Fault CheckingAlignment fault checking is disabled by default.

1 = Data address alignment fault checking enabled.

0 = Data address alignment fault checking disabled.

0 M RW b0 MMU EnabledThe MMU is disabled by default.

1 = MMU enabled.0 = MMU disabled.

Table 10: Control Register Bit-level Description (Continued)


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4.6.4.1 Effects of R1 on CachesThe I-Cache and D-Cache behavior are affected by the R1 register’s M, C, and I fields. The caches behave as shown in Table 11.

Table 11: Effect of Control Register’s M, C, and I Bits on Caches

I ( I -Cache Enable)

M (MMU Enable)

C (D-Cache Enable)

Behavior

0 X X All instruction fetches are from external memory (across the external bus).

X X 0 All data accesses are across the external bus.

X 0 X All data accesses are non-cacheable, non-bufferable. All addresses are flat mapped. That is VA = MVA = PA.

X 1 1 Data accesses can be cacheable or non-cacheable, and protection checks are performed. Depending on the MMU page entry, all addresses are translated from a VA to PA. (The VA is mapped to an MVA, and all addresses are translated from MVA to PA).

1 0 X All instruction fetches are cacheable, with no protection checks. All addresses are flat mapped. That is VA = MVA = PA.

1 1 X Instruction fetches can be cacheable or non-cacheable, and protection checks are performed. Depending on the MMU page entry, all addresses are translated from a VA to a PA. (The VA is mapped to an MVA, and all addresses are translated from an MVA to a PA).

Note

When software disables a cache, its contents are inaccessible. If software then enables a cache, its contents are the same as when it was disabled. As a result, software must clean the D-Cache before disabling it, to guarantee data coherency.

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4.6.5 [R1] Auxiliary Control RegisterUnique ID: CP15.0.R1.c0.1The Auxiliary Control Register contains the cache attribute bits for the L1 D-Cache for Low-Locality of Reference (LLR) memory regions. This register also contains a bit which allows an ASSP1 defined memory attribute to be applied to translation table walks.

The configuration of LLR cache attributes should be setup before any data access is made that may be cached in the L1 D-Cache. Once data is cached, software must ensure that the L1 Data Cache has been cleaned and invalidated before the LLR cache attributes are changed. Software must also invalidate the ITLB and DTLB.

The Page Table Memory Attribute (P) bit allows an ASSP defined attribute to be applied for memory requests generated by the hardware when doing a translation table walk. Example behavior may be enforcing ECC (Error Correction Code) on the memory access. Hardware will logically OR this bit with “[R2] Translation Table Base Register” on page 57 P bit (TTBR.P).

The P bit in the Auxiliary Control Register is deprecated; the page table memory attribute should be programmed through the TTBR.

The Auxiliary Control Register is accessed with the following instructions:

MRC p15, 0, Rd, c0, c0, 1 ; Read Auxiliary Control Register

MCR p15, 0, Rd, c0, c0, 1 ; Write Auxiliary Control Register

Table 12 describes the bit-level details of the ID Code Register

1. Application-specific Standard Product

Table 12: Auxiliary Control Register Bit-level Description



11:10 OC RW 0x0 LLR Outer Cache Attributes (OC)0x0 = Outer Non-cacheable0x1 = Outer Write back0x2 = Reserved 0x3 = Reserved


5:4 IC RW 0x0 LLR Inner (Data) Cache Attributes (IC)All configurations of LLR caching are cacheable, stores are buffered in the write buffer and stores may coalesce in the write buffer. Mapping LLR caching to shared memory will change the definition of this field.0x0 = Inner Write back0x1 = Inner Write back0x2 = Inner Write through0x3 = Inner Write back


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1 P RW 0x0 Page Table Memory Attribute (P)Hardware will logically OR the value of this bit with the P-bit of “[R2] Translation Table Base Register” on page 57. The P bit in the Auxiliary Control Register is deprecated.The effect of this bit is defined by an ASSP.0 = ASSP attribute not applied during page table access1 = ASSP attribute is applied during page table access

0 RSVD RO 0x0 Reserved

Table 12: Auxiliary Control Register (Continued)Bit-level Description


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4.6.6 [R2] Translation Table Base RegisterUnique ID: CP15.0.R2.c0.0The Translation Table Base Register (TTBR) specifies the base address of the first-level translation table. It is a Read/Write Register.

The register is accessed with the following instructions:

MRC p15, 0, Rd, c2, c0, 0 ; Read TTBR

MCR p15, 0, Rd, c2, c0, 0 ; Write TTBR

This register is also affected by bits in “[R1] Auxiliary Control Register” on page 55

Table 13 describes the bit-level details of the Translation Table Base Register

Table 13: Translation Table Base Register Bit-level Description


31:14 BASE RW 0x0.0000 Translation Table BasePhysical address of the base of the first-level table. Reading this field returns the pointer to the currently active first-level translation table. Writing this field updates the pointer to the first-level translation table.

13:5 RSVD UNP/SBZ UNP/SBZ ReservedNote: Reads are unpredictable; writes should be zero

4:3 OC RW b00 Table Walk Outer Cache Attributes0x0 = Outer Non-cacheable0x1 = Reserved0x2= Outer Non-cacheable (Note: This is defined by ARM as outer write-through, which the SoC CPU downgrades to Outer Non-cacheable)0x3 = Outer Write back

2 P RW b0 Table Walk Memory AttributeThe effect of this bit is defined by the ASSP.0 = ASSP attribute not applied during page table access1 = ASSP attribute is applied during page table access

Hardware will logically OR the value of this bit with the “[R1] Auxiliary Control Register” on page 55 P bit.

ASSP Note: An ASSP may use this bit to direct the external bus controller to perform some special operation on the memory access.

1 S RW b0 Table Walk Shared Attribute0 = Page table walk is not shared1 = Page table walk is shareable

0 RSVD UNP/SBZ UNP/SBZ Reserved

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4.6.7 [R3] Domain Access Control RegisterUnique ID: CP15.0.R3.c0.0The Domain Access Control Register defines 16 2-bit fields.Each 2-bit field defines the access permissions for one of 16 domains (D0-D15). It is a Read/Write register.

MMU accesses are primarily controlled through the use of domains. Faults created during MMU accesses are returned in “[R5] Fault Status Registers (FSR)” on page 60.


MRC p15, 0, Rd, c3, c0, 0 ; Read domain access permissions

MCR p15, 0, Rd, c3, c0, 0 ; Write domain access permissions

Table 14 describes the bit-level details of the Domain Access Control Register.

Table 14: Domain Access Control Register Bit-level Description


31:30 D15 RW b00 Domain 15Access permissions for this domain, encoded as follows:

b00 = No Domain Access.b01 = Client Domain Access.b10 = Reserved.b11 = Manager Domain Access.

With the following semantics:No Domain Access (b00) If software accesses D15, the SoC CPU generates a domain fault. Client Domain Access (b01)If software accesses D15, the SoC CPU compares the access permission bits to the section or page descriptor access permissions.Manager Domain Access (b11)Access permission bits are not compared against accesses. Permission faults are not generated.The value b10 is reserved. If set, behavior is currently the same as for “No Domain Access”.

29:28 D14 RW b00 Domain 14 See the description for D15

27:26 D13 RW b00 Domain 13 See the description for D15,








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4.6.8 [R4] CP15 Reserved RegisterThis register causes UNP behavior if accessed.







Note

Software must program this register before enabling the MMU. If this register is not programmed before enabling the MMU, then the default value, “No Domain Access” causes data or instruction aborts on all subsequent accesses.

Table 14: Domain Access Control Register Bit-level Description (Continued)


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4.6.9 [R5] Fault Status Registers (FSR)Unique ID: CP15.0.R5.c0.{0-1}These Read/Write Registers provide the source of the last instruction or data fault. The processor contains separate FSRs for instructions and data. The opcode_2 field selects between instruction and data FSRs:

opcode_2 = 0 => Data Fault Status Register (DFSR)

opcode_2 = 1 => Instruction Fault Status Register (IFSR)

When the MMU is disabled, the processor core still updates alignment faults and external aborts in the FSR as Fault Status (Data) and Fault Status (Instruction). MMU need to be enabled for logging Domain Fault (Data) and Domain Fault (Instruction) since domains are used by MMU accesses.

4.6.9.1 Data Fault Status RegisterThe Data Fault Status Register (DFSR) is for debug only. It is a Read/Write register.

The DFSR is accessed with the following instructions:

MRC p15, 0, Rd, c5, c0, 0 ; Read DFSR

MCR p15, 0, Rd, c5, c0, 0 ; Write DFSR

Table 15 describes the bit-level details of the DFSR

Table 15: Data Fault Status Register Bit-level Description



10 S RW 0 Status Field ExtensionThis bit extends the encoding of the Status field for prefetch aborts and certain types of data aborts. The encoding of this field is provided in:1) “FSR bit [10] Encodings for Data Aborts” on page 62, and 2) “FSR bit [10] Encodings for Prefetch Aborts” on page 62.

9 - RW 0 Not Applicable for this SoC CPU Core (CPU status will not update this bit). Reading and writing to this bit is allowed but has no effect on the processor.

8 RSVD Read-as-zero 0 Always read as zero; writes are ignored

7:4 Domain RW b0 Domain Fault (Data)Specifies which of the 16 domains was being accessed.See “[R3] Domain Access Control Register” on page 58

3:0 Status RW b0 Fault Status (Data)Type of data abort that occurred. See “FSR bit [3:0] Encodings” on page 61.

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4.6.9.2 Instruction Fault Status RegisterThe Instruction Fault Status Register (IFSR) is for debug only. It is a Read/Write register.

The IFSR is accessed with the following instructions:

MRC p15, 0, Rd, c5, c0, 1 ; Read IFSR

MCR p15, 0, Rd, c5, c0, 1 ; Write IFSR

Table 16 describes the bit-level details of the IFSR

4.6.9.3 FSR bit [3:0] EncodingsTable 17 shows how the processor core encodes the fault type in the Fault Status (Data) (DFSR bits [3:0]) and also in the Fault Status (Instruction) (IFSR bits [3:0])

Table 16: Instruction Fault Status Register Bit-level Description



8 RSVD Read-as-zero 0 Always read as zero; writes are ignored

7:4 Domain RW b0000 Domain Fault (Instruction)Specifies which of the 16 domains was being accessed.See “[R3] Domain Access Control Register” on page 58

3:0 Status RW b0000 Fault Status (Instruction)Type of prefetch that occurred. See “FSR bit [3:0] Encodings” on page 61.

Table 17: FSR Status Field Encoding

Value Domain Source Size Priori ty

b00111

1. The ARM specifications permit either b0001 or b0011 for alignment faults. Marvell implements b0011.

Invalid. Alignment. - Highest.

b1100 Invalid. External abort on translation. First level.

b1110 Valid. Second level.

b0101 Invalid. Translation. Section.

b0111 Valid. Page.

b1001 Valid. Domain. Section.

b1011 Valid. Page.

b1101 Valid. Permission. Section.

b1111 Valid. Page.

b1000 Invalid. External Abort. Section.

b1010 Invalid. Page. Lowest.

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4.6.9.4 FSR bit [10] Encodings for Data AbortsTable 18 shows how the processor core encodes bit 10 (Status Field Extension) for Data Aborts.

* All other encodings not listed in the table are reserved.

4.6.9.5 FSR bit [10] Encodings for Prefetch AbortsTable 19 shows how the processor core encodes bit 10 (Status Field Extension) for Prefetch Aborts.

* All other encodings not listed in the table are reserved.

Table 18: Encoding of Fault Status Register Data Aborts

Priori ty Sources - FS[10,3:0]* Domain FAR

Highest Alignment 0b00011 invalid valid

- External Abort on Translation

First level Second level

0b01100 0b01110

invalid valid

valid valid

- Translation Section Page

0b00101 0b00111

invalid valid

valid valid

- Domain Section Page

0b01001 0b01011

valid valid valid valid

- Permission Section Page

0b01101 0b01111

valid valid valid valid

- Lock Abort 0b10100 invalid invalid

- Co-processor Data Abort 0b11010 invalid invalid

- Imprecise External Data Abort 0b10110 invalid invalid

Lowest Data Cache Parity Error Exception** 0b11000 invalid invalid

Table 19: Encoding of Fault Status for Prefetch Aborts

Priori ty Sources FS[10,3:0]* Domain FAR

Highest Instruction MMU ExceptionSeveral exceptions can generate this encoding: - translation faultsexternal abort on translation - domain faults, and- permission faults It is up to software to figure out which one occurred.

0b10000 invalid invalid

- External Instruction Error Exception 0b10110 invalid invalid

Lowest Instruction Cache Parity Error Exception 0b11000 invalid invalid

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4.6.10 [R6] Fault Address Register (FAR)Unique ID: CP15.0.R6.c0.0The Fault Address Register (FAR) returns the MVA for the address being accessed when a data abort occurs. It is a Read/Write register.


MRC p15, 0, Rd, c6, c0, 0 ; Read FAR

MCR p15, 0, Rd, c6, c0, 0 ; Write FAR

Writing a data to the FAR is useful for debugging purposes to restore the value of FAR to a previous state. When reading or writing to FAR, CRm and opcode_2 should be zero.

When the MMU is disabled, any alignment faults and external data aborts that occur are still updated in the FAR. Instruction aborts are not updated in the FAR.

Table 20 describes the bit-level details of the FAR.

Table 20: Fault Address Register Bit-level Description


31:0 fAddr RW - Data Fault AddressThe MVA of the data that caused a fault. If the MMU is disabled, the processor still updates this register for data aborts (but not for prefetch aborts).

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4.6.11 [R7] CP15 Cache Operations RegistersThe Cache Operations Registers constitute a set of registers used to control and manage the Level 1 Caches and the Write Buffer. One register supports Wait for Interrupt for power-saving operation. These are programmed using write (MCR) instructions; in two cases read (MRC) instructions are used.

To perform a cache operation, write one of these registers as follows:

MCR p15, 0, Rd, c7, c{0-14}, {0-6} ; Perform a Cache Operation

The CRm (c{0-14}) and opcode_2 (0-2) fields in above instructions define the cache operation performed1.

Except during “D-Cache Test-and-Clean Operations” on page 68, reading this set of R7 registers results in unpredictable results.

A write to a R7 Cache Operations Register can perform certain operations listed below:

Flush the I-Cache and D-CachePrefetch an I-Cache lineDrain the write bufferClean and flush the D-Cache

Operations can access cached data using either one of the two methods:

Via its MVA Tag (see “Cache Maintenance using MVA Tags” on page 66)Via its index (and its way, if the cache is not direct mapped) (see “Cache Maintenance using Index or Set/Way” on page 66).

4.6.12 Summary of Cache Maintenance InstructionsTable 21 shows the available cache operations. The Rd column indicates how the Rd value is interpreted2.

1. Not all CRm and opcode_2 fields are supported. Writing unsupported opcode_2 or CRm values yields unpredictable results.

2. Wait for Interrupt instruction is included as part of R7 operations.

Table 21: Cache Operations Register - R7 (CP15.0.R7.c{0-14}.{0-2})

Operation Rd Description

MCR p15, 0, Rd, c7, c0, 4 X Wait for InterruptSets the core into power-saving mode. The core ensures the write buffer has been drained, the bus has completed all pending transactions, and blocks all further requests onto the bus before putting the core in sleep mode. Upon receiving an IRQ or FIQ interrupt, the core resumes regular operation.

MCR p15, 0, Rd, c7, c5, 0 X I-Cache InvalidateInvalidates all data in the I-Cache and also flushes BPU. See also “[R15] BPU Operations Register” on page 92

MCR p15, 0, Rd, c7, c5, 1 MVA I-Cache Invalidate Single EntryInvalidates a single I-Cache line.

MCR p15, 0, Rd, c7, c5, 2 Set/Way

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MCR p15, 0, Rd, c7, c5, 6 X BPU InvalidateThis operation is similar to that BPU Flush History Table defined in the “[R15] BPU Operations Register” on page 92

MCR p15, 0, Rd, c7, c6, 0 X D-Cache InvalidateInvalidates all data in the D-Cache, including dirty data.

MCR p15, 0, Rd, c7, c6, 1 MVA D-Cache Invalidate Single EntryInvalidate a single D-Cache line and also throws away dirty data.MCR p15, 0, Rd, c7, c6, 2 Set/Way

MCR p15, 0, Rd, c7, c7, 0 X D-Cache and I-Cache InvalidateInvalidates all data in both caches and also in the BPU, discarding any dirty data.

MCR p15, 0, Rd, c7, c10, 0 X D-Cache Clean AllCleans all lines in the D-Cache.

MCR p15, 0, Rd, c7, c10, 1 MVA D-Cache Clean Single EntryIf the D-Cache line is marked valid and dirty, then the selected D-Cache line is written back to main memory. The line is marked as not dirty. The valid bit is the same.


MRC p15, 0, Rd, c7, c10, 3 X D-Cache Test and CleanTests the whole D-Cache for dirty lines. The operation stops when it finds the first dirty line and cleans the cache line. The operation returns the status of the cache in bit 30 (this bit is set to 1 if no dirty lines are found). See also “D-Cache Test-and-Clean Operations” on page 68

MCR p15, 0, Rd, c7, c10, 4, orMCR p15, 0, Rd, c7, c10, 51

X Drain Write Buffer(available in user mode also)Writes all the contents of the write buffer (from memory stores) into the main memory before allowing any further instruction from being executed.

MCR p15, 0, Rd, c7, c13, 1 MVA Prefetch I-Cache LineBrings a specific instruction (by providing the virtual address of the instruction) into the I-Cache. The address of the instruction to be prefetched has to be cacheable. For direct-mapped caches, lockdown must be enabled before prefetching a cache line. For Set-Associative caches, lockdown does not need to be enabled. To lock down the cache, see “[R9] Cache Lockdown Registers” on page 70.

See also “Cache Lockdown Procedures” on page 71

Table 21: Cache Operations Register - R7 (CP15.0.R7.c{0-14}.{0-2}) (Continued)


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For instructions accessing only one cache entry or line, the value of Rd provides the destination operand. If Rd is set to R15 in an MRC instruction, then the value read does not affect the PC.

4.6.12.1 Cache Maintenance using MVA TagsFigure 11 shows the bit fields for the Cache Operations Register in MVA mode.

Figure 11: Bit Fields in MVA Mode

Refer (return) to Section 4.6.11, [R7] CP15 Cache Operations Registers, on page 64 for instructions that use MVA and Set/Way modes of Cache Maintenance.

4.6.12.2 Cache Maintenance using Index or Set/WayFigure 12 the bit fields for the Cache Operations in index (or Set/Wayif the cache is not direct mapped) mode.

MCR p15, 0, Rd, c7, c14, 1 MVA D-Cache Clean and Invalidate Single EntryIf the D-Cache line is marked valid and dirty, then this operation writes the selected D-Cache line to main memory. Then the line is marked as invalid.


MRC p15, 0, Rd, c7, c14, 3 X D-Cache Test, Clean and InvalidateTests the whole D-Cache for dirty lines. The operation stops when it finds the first dirty line and cleans the cache line. The operation returns the status of the cache in bit 30 (this bit is set to 1 if no dirty lines is found). The operation then invalidates the whole D-Cache when there are no dirty lines found. See also “D-Cache Test-and-Clean Operations” on page 68

MCR p15, 0, Rd, c7, c14, 0 X D-Cache Clean All and InvalidateCleans all lines in the D-Cache, then invalidates the cache. See also: “Test-and-Clean Example” on page 68.

MCR p15, 0, Rd, c7, c5, 4 X Prefetch Flush(Available in user mode also). Flushes the pipeline. The command is typically used after the flush all I-Cache command.

MCR p15, 0, Rd, c7, c5, 5 X D-Cache line allocate(available in user mode also)Implemented as NOP.

1. Both instructions can be used to drain Write Buffer.

Table 21: Cache Operations Register - R7 (CP15.0.R7.c{0-14}.{0-2}) (Continued)


31 N+1 N 5 4 2 1 0

Tag Index Word SBZ

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Figure 12: Bit Fields in Set/Way Mode

The tag and word fields define the MVA. Word should be zero (SBZ) for all cache operations.

Table 22 shows the index field and corresponding Cache size for cases of Direct-mapped and 4-way Set-Associative Caches.

Refer (return) to Section 4.6.11, [R7] CP15 Cache Operations Registers, on page 64 for instructions that use MVA and Set/Way modes of Cache Maintenance.

31 30 29 N+1 N 5 4 2 1 0

Way SBZ Set (=Index) Word SBZ

NoteFor direct-mapped caches, Way = 00

Table 22: Index Fields for Supported Cache Sizes

Cache size Direct-Mapped Cache index 4-way Cache Index

4 KBytes ADDR[11:5] ADDR[9:5]






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4.6.12.3 D-Cache Test-and-Clean OperationsThe test-and-clean operations provide a way to clean the entire D-Cache with a simple program loop. These operations are different from virtually all other CP15 operations in that they are invoked by MRC, rather than MCR, instructions.

There are two cache operations invoked by MRC instead of MCR instructions:

D-Cache Test and Clean (MRC p15, 0, r15, c7, c10, 3) D-Cache Test, Clean and Invalidate (MRC p15, 0, r15, c7, c14, 3)

These instructions have a special encoding that uses r15 as a destination operand. However, the PC is not changed by using this instruction. These MRC instructions also set the condition code flags.

Test-and-Clean ExampleThis example tests the whole D-Cache for dirty lines. It stops when it finds the first dirty line and cleans the cache line. It returns the status of the cache in bit 30 of r15. This bit is set to 1 if no dirty lines are found. However, if the cache contains any dirty lines, bit 30 is set to 0. Thus, the following loop cleans the entire D-Cache:

tc_loop ->MRC p15, 0, r15, c7, c10, 3 ; Test and clean

BNE tc_loop

The test, clean and invalidate D-Cache instruction is the same as test and clean D-Cache, except that when the entire cache has been cleaned, it is also invalidated.Thus, the following loop cleans and invalidates the entire D-Cache.

tci_loop ->MRC p15, 0, r15, c7, c14, 3 ; Test, clean and invalidate

BNE tci_loop

Refer (return) to Section 4.6.11, [R7] CP15 Cache Operations Registers, on page 64 to see all other instructions used in Cache Maintenance.

Note

The above examples are simple to use, because the software does not need to know the cache type or size. However, they are not recommended, because these operations scan the D-Cache from the beginning of the cache line to the first dirty line found in each loop, which can degrade performance. Instead, use “Clean (and Invalidate) by Set/Way”, or “Clean (and Invalidate) All”. In order to clean and invalidate all of the D-Cache, the D-Cache Clean All and Invalidate instruction is recommended.

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4.6.13 [R8] TLB Operations RegisterUnique ID: CP15.0.R8.c{5-7}.{0-1}The TLB Operations Register controls the Translation Lookaside Buffer (TLB). It is a Write-only registerThe register can be accessed for writing with the following instruction:

MCR p15, 0, Rd, c8, c{5-7}, {0-1} ; Perform a TLB operation

The function to be performed is decided by the opcode_2 and CRm in the MCR instruction. Writing unsupported opcode_2 or CRm values yields unpredictable results. Attempting to read this register yields unpredictable results.

Table 23 describes the available TLB operations.

Table 24 shows the format for the MVA data in Rd of Table 23.

Refer to “[R10] TLB Lockdown Register” on page 72 for operations involving TLB Lockdown.

Table 23: TLB Operations - R8 (CP15.0.R8.c{5-7}.{0-1})

Operation Data Set-Associat ive Operation

MCR p15, 0, Rd, c8, c7, 0 X Invalidate All Entries in TLB

MCR p15, 0, Rd, c8, c7, 1 MVA Invalidate Single Entry in TLB

MCR p15, 0, Rd, c8, c5, 0 X Invalidate All Instruction Entries in TLB

MCR p15, 0, Rd, c8, c5, 1 MVA Invalidate Single Instruction Entry in TLB

MCR p15, 0, Rd, c8, c6, 0 X Invalidate All Data Entries in TLB

MCR p15, 0, Rd, c8, c6, 1 MVA Invalidate Single Data Entry in TLB

Table 24: Format for Invalidating a Single Entry in the TLB


31:16 MVA WO - Modified Virtual AddressFor more information about MVA definition, see “Address Types” on page 47.

15:4 RSVD SBZ SBZ Reserved

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4.6.14 [R9] Cache Lockdown RegistersUnique ID: CP15.0.R9.c0.{0-1}There are two R9 registers that control D-Cache and I-Cache lockdown and described as follows.

The D-Cache Lockdown Register is a Read/Write register that supports lockdown features of the Data Cache.

The register can be accessed with the following instructions:

MRC p15, 0, Rd, c9, c0, 0 ; Read D-Cache lockdown register.

MCR p15, 0, Rd, c9, c0, 0 ; Write D-Cache lockdown register

The I-Cache Lockdown Register is a Read/Write register supports lockdown features of the Instruction Cache.

The register can be accessed with the following instructions:

MRC p15, 0, Rd, c9, c0, 1 ; Read I-Cache lockdown register.

MCR p15, 0, Rd, c9, c0, 1 ; Write I-Cache lockdown register.

Table 25 describes the bit level details of the two Cache Lockdown Registers.

Notes:

1. See also: Prefetch I-Cache Line instruction which is affected by Cache Lockdown operation.

Table 25: Cache Lockdown Registers Bit-level Description


31:16 RSVD UNP/SBZP UNP/SBZP ReservedNote: Reads are unpredictable, and writes should preserve the original value.

15:4 RSVD SBO SBO Reserved

3 L3 RW – L Bit, Way 3. Lock bits. The purpose of locking the cache line is so that the line cannot be replaced with another line fill. For a 4-way cache, the L bits indicate which set/way is to be allocated during a line fill. If all of the L bits are 1, then Way 3 will be used for line-fill allocation.

0 = Allocation to the cache way is determined by the standard replacement algorithm.

1 = No allocation is performed.For a direct-mapped Cache, the L bits are used to lock a cache line during line fills. If any of the L bits are set to 1, then the lock is set. For locked lines in a direct-mapped I-Cache, another line fill can replace the locked portion if the new line fill is an I-Cache prefetch instruction with its lockdown bit set.

2 L2 RW – L Bit, Way 2.



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4.6.14.1 Cache Lockdown ProceduresFor predictable code behavior in embedded systems, software can lock code and data in the I-Cache and D-Cache. Some examples where lockdown is particularly useful include:

Keeping high-priority interrupt routines in the cache (if there are real-time constraints)Holding coefficients for a DSP filter routine (to reduce external bus traffic).

A software routine to lock down code or data must meet the following requirements:

The lockdown routine must be in a non-cachable area of memory (to avoid the lockdown code itself code from being locked into the cache). The instructions or data to lock down must be in a cacheable area of memory and not already in the cache. The cache must be enabled. Interrupts must be disabled.If the caches have been used after the last reset, the software must ensure that the cache in question is cleaned, if appropriate, and then flushed.

When locking instructions in an I-Cache, the lockdown routine uses MCR instructions on a previously locked cache. When locking data in a D-Cache, the lockdown routines use LDR instructions to fill an unlocked cache way.

The procedure is as follows:

1. For a direct-mapped cache, set any or all L bits to 1. For example:When locking instructions in a direct-mapped I-Cache:

MRC p15, 0, r3, c9, c0, 1ORR r3, r3, #0xFMCR p15, 0, r3, c9, c0, 1

When locking instructions in a direct-mapped D-Cache: MRC p15, 0, r3, c9, c0, 0ORR r3, r3, #0xFMCR p15, 0, r3, c9, c0, 0

For a 4-way cache, make sure that L=0 for the way to lock: For example:

When locking down I-Cache Way 3:MRC p15, 0, r3, c9, c0, 1MOV r2, r3 --> Save old value

to restore after lockdown completesBIC r3, r3, #0x8 --> Clear L bit for Way 3ORR r3, r3, #0x7 --> Set L bits to 1 for Way 0, 1, 2MCR p15, 0, r3, c9, c0, 1

When locking down D-Cache Way 3:MRC p15, 0, r3, c9, c0, 0MOV r2, r3 --> Save old value

to restore after lockdown completesBIC r3, r3, #0x8 --> Clear L bit for Way 3ORR r3, r3, #0x7 --> Set L bits to 1 for Way 0, 1, 2MCR p15, 0, r3, c9, c0, 0

2. Initialize a pointer to the address of the first word that is to be locked in the cache, and align the pointer to the first word in the line. For an address in r1:

BIC r1, r1, #0x7F

3. For an I-Cache, force a linefill, so that the instructions can be allocated into that way: MCR p15, 0, r1, c7, c13, 1

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The resulting line fill is trapped in the I-Cache (for more information, see Prefetch I-Cache Line).

For D-Cache lockdown, load a word from memory with an LDR or PLD instruction, for example:

LDR rd, [r1, #0]

or:

PLD [r1]

The load instruction forces a line fill of eight words that are trapped in the cache.

4. Increment the pointer by the number of bytes in a cache line (32 by default): ADD r1, r1, #0x20

5. Repeat steps 3 and 4, until all words are loaded in the cache. 6. For a direct-mapped cache, set all L bits to 0. For example:

After locking instructions in a direct-mapped I-Cache: BIC r3, r3, #0xFMCR p15, 0, r3, c9, c0, 1

After locking instructions in a direct-mapped D-Cache: BIC r3, r3, #0xFMCR p15, 0, r3, c9, c0, 0

For a 4-way cache, restore the L bits from before the lockdown and set L bit to 1 for the way to lock. For example:

When locking down I-Cache Way 3: MOV r3, r2ORR r3, r3, #0x8MCR p15, 0, r3, c9, c0, 1

When locking down D-Cache Way 3:

MOV r3, r2ORR r3, r3, #0x8MCR p15, 0, r3, c9, c0, 0

4.6.14.2 Cache Unlock ProceduresTo unlock a locked line in a direct-mapped cache, software must invalidate the cache line. If performing a prefetch and lockdown act, software can replace the I-Cache locked line by another line fill. For operations that control cache flush and prefetch, see Table 25, Cache Lockdown Registers Bit-level Description, on page 70.

To unlock a Set-Associative cache, software can simply reprogram the lockdown register. For example, to unlock I-Cache Way 3:

MRC p15, 0, r3, c9, c0, 1BIC r3, r3, #0x8MCR p15, 0, r3, c9, c0, 1

4.6.15 [R10] TLB Lockdown RegisterUnique ID: CP15.0.R10.c0.0The TLB lockdown Register allows software lock down up to 8 TLB slots. Its V field selects a slot to lock down, the P bit decides if the slot should be locked. Rd contains the MVA for the locked down entry in the TLB. It is a Read/Write register.

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TLB Lockdown Register is accessed with the following instructions:

MRC p15, 0, Rd, c10, c0, 0 ; Read TLB Lockdown Register (Rd = MVA)

MCR p15, 0, Rd, c10, c0, 0 ; Write TLB Lockdown Register (Rd = MVA)

The main TLB is unified, meaning that it holds entries for both data and instructions. The main TLB has two zones:

Lockable zone, containing 8 slotsUnlockable zone, containing all other slots

In the legacy Feroceon® architecture, both zones are fully associative. The legacy Feroceon® architecture also includes two mini TLBs (an 8-entry instruction TLB and an 8-entry data TLB) which speed up address translation and save power.

The “[R8] TLB Operations Register” on page 69) can be used to invalidate the entire TLB, or individual entries. When invalidating the entire TLB, locked-down TLB entries are preserved. When invalidating single TLB entries, the victim automatically increments after any entry is placed in the TLB lockdown region.

Table 26 describes the bit level details of the TLB Lockdown Register.

4.6.15.1 Example TLB LockdownThe following example locks down a single entry in the TLB.

ADR r1,LockAddr ; Set r1 to the value of the address to be locked downMCR p15,0,r1,c8,c7,1 ; Invalidate single entry so Addr is not in TLB

Table 26: TLB Lockdown Register Bit-level Description

Bits Field Access Reset Descript ion

31.29 RSVD SBZ SBZ Reserved

28:26 V RW b0 VictimTLB slot to write or lock down.

b000 = Slot 1b001 = Slot 2b010 = Slot 3b011 = Slot 4b100 = Slot 5b101 = Slot 6b110 = Slot 7b111 = Slot 8

The TLB contains a lockable region and an unlockable region. The 8 lockdown slots may be anywhere in the lockable region of the TLB.

25:1 RSVD UNP/SBZ UNP/SBZ Reserved. Note: Reads are unpredictable; writes should be zero.

0 P RW b0 Preserve. Sets whether the slot should be locked or unlocked.

0 = Subsequent page-table walks place the entry in the unlocked region.

1 = Locks the next address translation into the selected lockable slot.

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MRC p15,0,r0,c10,c0,0 ; Read TLB lockdown registerORR r0,r0,#1 ; Set the preserve bitMCR p15,0,r0,c10,c0,0 ; Write TLB lockdown registerLDR r1,[r1] ; Read address. TLB misses & entry is loadedMRC p15,0,r0,c10,c0,0 ; Read the lockdown register (V will have incremented)BIC r0,r0,#1 ; Clear the P bitMCR p15,0,r0,c10,c0,0 ; Write TLB lockdown register

The above example does not preserve the r0-r1 registers. If they are needed by other software and their contents could be corrupted, preserve their state before the example starts, and restore the contents upon subroutine completion.

4.6.16 [R11] CP15 Reserved RegisterThese registers cause “unpredictable” behavior if accessed.

4.6.17 [R12] CP15 Reserved RegisterThese registers cause “unpredictable” behavior if accessed.

4.6.18 CP15 Process ID RegistersThese Read/write Registers access the process ID and context ID, as determined by the operating system, to determine the current process or context. The opcode_2 field determines if the register returns the Process ID or Context ID:

If opcode_2 = 0, the Fast Context Switch Extension (FCSE) Process IDentifier (PID) register is selected.If opcode_2 = 1, the Context ID register is selected.

At reset, the process identifier is set to 0.

The following sections describe the two Process ID Registers.

4.6.18.1 [R13] FCSE PID RegisterUnique ID: CP15.0.R13.c0.0The FCSE PID Register is a 7-bit field for mapping the processor’s 32MB Virtual Address (VA) into one of 128 segments in a 4GB range and thereby Performing a Fast Context Switch.

FCSE PID Register is accessed with the following instructions:

MRC p15, 0, Rd, c13, c0, 0 ; Read FCSE PID

MCR p15, 0, Rd, c13, c0, 0 ; Write FCSE PID

Table 27 describes the bit level details of the FCSE PID Register.

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Performing a Fast Context SwitchSoftware can perform a fast context switch by writing a new PID to the [R13] FCSE PID Register. After a fast context switch, the contents of the caches and the TLB still have valid address tags, so they do not need to be flushed. However, after writing the FCSE PID, some instructions may have been prefetched for the previous context, and should be discarded. In the following example, X1, X2, and X3 are the three instructions following the fast context switch instruction:

{FCSE PID}M0V r0, #1:SHL:25 ; Fetched with FCSE PID = 0MCR p15, 0, r0, c13, c0, 0 ; Changes FCSE PID to 1 X1 ; Fetched with FCSE PID = 0X2 ; Fetched with FCSE PID = 0X3 ; Fetched with FCSE PID = 1

4.6.18.2 [R13] Context ID RegisterUnique ID: CP15.0.R13.c0.1The Context ID Register provides the context ID for real-time trace tools.

The Context ID Register is accessed with the following instructions:

MRC p15, 0, Rd, c13, c0, 1 ; Read Context ID

Table 27: FCSE PID Register Bit-level Description


31.25 PID RW 0x0 Process IDThe SoC CPU issues addresses in the range 0~32 MB. These addresses are translated in accordance with the value contained in this register. Address X is converted to:

X + (PID x 32).

This address is then received by the MMU and the caches.

If PID = 0, then there is a flat mapping between the virtual address (VA) output by the SoC CPU and the VA used by MMU and the caches.

FCSE translation is not applied for addresses used for any entry-based cache or TLB maintenance operations.

24:0 RSVD SBZ SBZ Reserved.Note: Reads as zero; writes should be zero.

Note

The MMU should not be disabled for the FCSE PID translation to occurSee “Address Types” on page 47 for details about VA to Modified Virtual Address (MVA)

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MCR p15, 0, Rd, c13, c0, 1 ; Write Context ID

Table 28 describes the bit field in the Context ID Register.

4.6.19 [R14] Reserved RegisterThese registers cause “unpredictable” behavior if accessed.

4.6.20 Performance Counters There are two sets (bank c12 and bank c13) of four R15 performance counter related registers. Bank c12 set of four registers control enable / disable of a set of four counters defined by Bank c13 registers. The four c13 counters can monitor up to four events at the same time. Each counter is 64 bits and increment each time a selected event occurs.

Software can configure the counters to count different kinds of events, but each counter may only track one kind of event at a given time.

Each counter has a different overlapping1 set of events that it can log. Attempting to track two kinds of event using one counter yields unpredictable results

Section 4.6.20.1 describes how to enable the counters and how to acquire counters to log specific events using R15 c12 registers.Section 4.6.20.2 describes the actual Performance Counters (defined by R15 c13 registers). The counters can be preloaded with a specific value or reset to zeroSection 4.6.20.3 describes the Performance Counter Monitor2.

The access mode for all registers related to performance counters/monitors is programmable through the “[R15] Privileged Mode Access Register” on page 91.

4.6.20.1 [R15] Counter Operations RegistersUnique ID: CP15.0.R15.c12.{0-3}The Counter Operations Registers bank c12 contains four Read/Write registers to select four specific counters at a given time and enable their count operation. The Counter Operations Registers can turn each counter on and off, and they can set each counter to count a particular kind of event.

To perform a counter operation, the following write instructions can be used:

MCR p15, 0, Rd, c15, c12, 0 -> Write to counter 0 ops registerMCR p15, 0, Rd, c15, c12, 1 -> Write to counter 1 ops registerMCR p15, 0, Rd, c15, c12, 2 -> Write to counter 2 ops registerMCR p15, 0, Rd, c15, c12, 3 -> Write to counter 3 ops register

The following instructions can be used to read the current counter configuration:

Table 28: Context ID Register Bit-level Description


31.0 ID RW 0x0 Context IDThis ID allows real-time trace tools to identify the currently executing process in multi-tasking environments.

1. Note there are only four counters; at any given time the counters can be set (using the c12 registers) to log up to four events (see Table 29) from among the many different events of Table 30

2. The Performance Counter Monitor tracks if the counters have reached their maximum values

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MRC p15, 0, Rd, c15, c12, 0 -> Read counter 0 configurationMRC p15, 0, Rd, c15, c12, 1 -> Read counter 1 configurationMRC p15, 0, Rd, c15, c12, 2 -> Read counter 2 configurationMRC p15, 0, Rd, c15, c12, 3 -> Read counter 3 configuration

Bit 0 in the bank 12 registers enable and disable the counters. The other bits program which kind of performance each of the four counter tracks. Setting bit 0 and one other event bit will program the counter to log each time that event occurs. Setting more than one event bit will have unpredictable results.

Table 29 lists the values for Rd to program (using c12 registers) the kinds of performance that each of the four c13 counter tracks (note: bit 0 =1 enables the counter; one other event bit is also set).

Table 29: R12 Values to Set the “Kinds of Performance” to Monitor

Counter Sets

Value Counter 0(c0)

Counter 1(c1)

Counter 2(c2)

Counter 3 (c3)

- 0x0000.0000 Disable Counter. Does not affect counter value.

- 0x0000.0001 Enable Counter. (the counter starts to count the last programmed kind of event. If the counter was not previously programmed to count a particular kind of event, results are unpredictable.

Set 01 0x0000.0003 Cycle Count Cycle Count Cycle Count Cycle Count

Set 02 0x0000.0005 D-Cache Read Hit I-Cache Read Miss

– D-Cache Read Miss

Set 03 0x0000.0009 D-Cache Read Miss

D-Cache Read Miss

D-Cache Access

D-Cache Write miss

Set 04 0x0000.0011 D-Cache Write Hit D-Cache Write miss

DTLB Miss TLB Miss

Set 05 0x0000.0021 D-Cache Write miss

ITLB Miss – –

Set 06 0x0000.0041 Retired Instruction Single Issue – –

Set 07 0x0000.0081 – – – –

Set 08 0x0000.0101 – Branch Retired

Branch Predict Miss

Branches Taken

Set 09 0x0000.0201 – ROB FULL WB Write Beat

WB Full

Set 10 0x0000.0401 MMU Bus Request (Read Latency)

MMU Read Beat

A1 Stall –

Set 11 0x0000.0801 I-Cache Bus Request (Read Latency)

I-Cache Read Beat

D-Cache Read Latency

D-Cache Read Beat

Set 12 0x0000.8001 Hold IS

Set 13 0x0000.1001 WB Bus Request (Write Latency)

WB Write Beat D-Cache Write Latency

D-Cache Write Beat

Set 14 0x0000.2001 Hold LDM/STM – – –

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Table 30 describes the kinds of performance listed in Table 29.

Set 15 0x0001.0001 – Data Read Access Count

BIU Simultaneous Access

BIU Any Access

Set 16 0x0004.0001 Data Write Access Count

– – –

Set 17 0x0008.0001 Data Read Access Count

– – –

Set 18 0x0040.0001 – – – Data Write Access Count

Set 19 0x0100.0001 SIMD Cycle CountNote: counter has no meaning for version without WMMX2 support.

SIMD Retired InstructionsNote: counter has no meaning for version without WMMX2 support.

SIMD Hold ISNote: counter has no meaning for version without WMMX2 support.

SIMD HOLD Writeback StageNote: counter has no meaning for version without WMMX2 support.

Set 20 0x0200.0001 Predicted Branch Count

SIMD Store FIFO FullNote: counter has no meaning for version without WMMX2 support.

SIMD Instr Buffer FullNote: counter has no meaning for version without WMMX2 support.

SIMD Retire FIFO FullNote: counter has no meaning for version without WMMX2 support

Note

Only one feature of each counter can be set. All counters can be enabled at the same time.

Table 30: Kinds of Countable Events

Description Counts Ops Register Value(c0, c1, c2, c3)

A1 StallCounts the number of cycles ALU A1 is stalled

Events c2: 0x401(Set 10)

Table 29: R12 Values to Set the “Kinds of Performance” to Monitor (Continued)

Counter Sets

Value Counter 0(c0)

Counter 1(c1)

Counter 2(c2)

Counter 3 (c3)

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BIU Any AccessCounts the number of cycles the BIU is accessed by any unit.

Cycles c3: 0x10001(Set 15)

BIU Simultaneous AccessCounts the number of cycles the bus is requested by more than one master.


Branch Predict MissCounts the number of times branch prediction causes the wrong branch to be prefetched.


Branch RetiredCounts the number of times one branch retires.


Branches TakenCounts the number of times branch prediction correctly prefetches the required branch.


Cycle CountCounts the number of clock cycles. Every clock cycle increments the counter

Cycles c0: 0x3c1: 0x3c2: 0x3c3: 0x3(Set 01)

Data Read Access CountCounts all data reads

Events c0: 0x8.0001c1: 0x1.0001(Set 15)(Set 17)

Data Write Access CountCounts all data writes.

Events c0: 0x4.0001c3: 0x40.0001(Set 16)(Set 18)

D-Cache AccessCounts the number of data-cache accesses (read hits / misses and write hits / misses).


D-Cache Read BeatCounts the number of times the bus returns data to the data cache during read requests.


D-Cache Read HitCounts the number of data-cache read hits.


D-Cache Read LatencyCounts the number of cycles the data cache requests the bus for a read.


D-Cache Read MissCounts the number of data-cache read misses (including non-cacheable and non-bufferable cache accesses).

Events c0: 0x9c1: 0x9c3: 0x5(Set 02)(Set 03)

Table 30: Kinds of Countable Events (Continued)


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D-Cache Write BeatCounts the number of times the bus returns ready to the data cache during write requests.


D-Cache Write BeatCounts the number of times the bus returns ready to the data cache during write requests


D-Cache Write HitCounts the number of data-cache write hits.


D-Cache Write LatencyCounts the number of cycles the data cache requests the bus for a write.


D-Cache Write missCounts the number of data-cache write misses (including non-cacheable and non-bufferable misses).

Events c0: 0x21c1: 0x11c3: 0x9(Set 03)(Set 04)(Set 05)

DTLB MissCounts the number of TLB misses for data entries.


Hold ISCounts the number of cycles the instruction issue is stalled.


Hold LDM/STMCounts the number of cycles the pipeline is blocked because of multiple load/store operations.


I-Cache Bus Request (Read Latency)Counts the number of cycles the Instruction cache requests the bus until the data returns.


I-Cache Read BeatCounts the number of times the bus returns RDY to the instruction cache, useful to determine the cache’s average read latency (also known as “read miss” or “read count”).


I-Cache Read MissCounts the number of instruction-cache read misses.


ITLB MissCounts the number of Instruction TLB misses.


MMU Bus Request (Read Latency)Counts the number of cycles to complete a request via the MMU bus. This request can derive from multiple masters.

Cycles c0: 0x401 (Set 10)

MMU Read BeatCounts the number of times the bus returns RDY to the MMU, useful when determining bus efficiency. A user can use the signal that the MMU is requesting the bus and how long it takes on average for the data to return. (mmu_bus_req / mmu_read_count).

Events c1: 0x401 (Set 10)



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Predicted Branch CountCounts the number of times a branch is predicted successfully.

Events c0: 0x0200.0001(Set 20)

Retired InstructionCounts every time an instruction is retired.


ROB FULLCounts the number of cycles the ROB is full.


SIMD Cycle CountCounts the number of SIMD cycles.

Cycles c0: 0x0100.0001 (Set 19)

SIMD Instr Buffer FullCounts the number of cycles the SIMD coprocessor instruction buffer is full.

Cycles c2: 0x0200.0001(Set 20)

SIMD Hold ISCounts the number of cycles the SIMD coprocessor holds in its Issue (IS) stage

Cycles c2: 0x0100.0001(Set 19)

SIMD HOLD Writeback StageCounts the number of cycles the SIMD coprocessor holds in its writeback stage.

Cycles c3: 0x0100.0001(Set 19)

SIMD Retire FIFO FullCounts the number of cycles the SIMD coprocessor retire FIFO is full.

Cycles c3: 0x0200.0001 (Set 20)

SIMD Store FIFO FullCounts the number of cycles the SIMD coprocessor store FIFO is full.

Cycles c1: 0x0200.0001 (Set 20)

SIMD Retired InstructionsCounts the number of retired SIMD instructions.

Events c1: 0x0100.0001(Set 19)

Single IssueCounts the number of cycles the processor single-issues instructions.


TLB MissCounts the number of instruction and data TLB misses.


WB Bus Request (Write Latency)Counts the number of cycles the write-back buffer requests the bus until the data is written to the bus


WB FullCounts the number of cycles WB is full.


WB Write BeatCounts the number times the bus returns RDY to the write buffer, useful to determine the write buffer’s average write latency (WB Write Latency/ WB Write Beat).

Events c1: 0x1001c2: 0x201 (Set 09)(Set 13)



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4.6.20.2 [R15] Performance Counter Value RegistersUnique ID: CP15.0.R15.c13.{0-7}The Counter Value Registers is a set of R15 bank c13 registers that can be used to program (or read) the counter values. Each counter is 64 bits, so it takes two read/write operations to get/set the entire value in a counter. After selecting a combination of four counters with the R15 bank c12 registers, typically software resets the a counter to 0 via a write to the R15 bank 13 register at the time the count operation is to start. Writes to a R15 bank c13 register can also set the counter to a desired value at any time.

After changing1 the kind of event being counted via the bank c12 registers, the count continues from whatever previous value was present in the counter until the counter value is reset. A hardware reset always sets all Performance Counter values to 0. Each of the 64-bit counter is represented by:

Counter 0 => {C1[31:0], C0[31:0]}Counter 1 => {C3[31:0], C2[31:0]}Counter 2 => {C5[31:0], C4[31:0]}Counter 3 => {C7[31:0], C6[31:0]}

The following example shows how to read values of all four counters:

MRC p15, 0, Rd, c15, c13, 0 ; Reads the lower 32 bits of counter 0MRC p15, 0, Rd, c15, c13, 1 ; Reads the upper 32 bits of counter 0MRC p15, 0, Rd, c15, c13, 2 ; Reads the lower 32 bits of counter 1MRC p15, 0, Rd, c15, c13, 3 ; Reads the upper 32 bits of counter 1MRC p15, 0, Rd, c15, c13, 4 ; Reads the lower 32 bits of counter 2MRC p15, 0, Rd, c15, c13, 5 ; Reads the upper 32 bits of counter 2MRC p15, 0, Rd, c15, c13, 6 ; Reads the lower 32 bits of counter 3MRC p15, 0, Rd, c15, c13, 7 ; Reads the upper 32 bits of counter 3

The following example shows how to write values to all four counters:

MCR p15, 0, Rd, c15, c13, 0 ; Writes the lower 32 bits of counter 0MCR p15, 0, Rd, c15, c13, 1 ; Writes the upper 32 bits of counter 0MCR p15, 0, Rd, c15, c13, 2 ; Writes the lower 32 bits of counter 1MCR p15, 0, Rd, c15, c13, 3 ; Writes the upper 32 bits of counter 1MCR p15, 0, Rd, c15, c13, 4 ; Writes the lower 32 bits of counter 2MCR p15, 0, Rd, c15, c13, 5 ; Writes the upper 32 bits of counter 2MCR p15, 0, Rd, c15, c13, 6 ; Writes the lower 32 bits of counter 3MCR p15, 0, Rd, c15, c13, 7 ; Writes the upper 32 bits of counter 3

4.6.20.3 Performance Monitoring Unit

The Registers involved in Monitoring Performance CountersThis unit will monitor counter values and alert if a performance counter reaches its maximum value. When a performance counter reaches its maximum value, 0xFFFF_FFFF, the next event it needs to count will cause it to roll over to zero and set the overflow flag (bits 1-4) in the [R15] Overflow Flag Status Register (called FLAG).

An interrupt request indicated by pmu_interrupt signal of System Interface will occur if the corresponding bit in the [R15] The Interrupt Enable Register is set.

The Interrupt Enable register and the FLAG (overflow) Register can be accessed by CP15 instructions and are described in the following Table:

1. That is, selecting and enabling a different combination of four counters

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[R15] The Interrupt Enable RegisterUnique ID: CP15.0.R15.c14.0The Interrupt Enable Register enables interrupt requesting of the Performance Monitoring Unit for each counter. Each counter can cause an interrupt request to occur on an overflow.

Table 31: Accessing the Performance Counter Interrupt Enable & FLAG (Overflow) Registers

Function CRm (Register #)

CRm (Register #)

Instruction

Read INTEN b1111 b1110 MRC p15, 0, Rd, c15, c14, 0

Write INTEN b1111 b1110 MCR p15, 0, Rd, c15, c14, 0

Read FLAG b1111 0b1110 MRC p15, 0, Rd, c15, c14, 1

Write FLAG b1111 0b1110 MCR p15, 0, Rd, c15, c14, 1

Table 32: Interrupt Enable Register (INTEN) Bit-level Description

Bits Field(short)

Access Reset Description


3 - RW 0x0 Counter3 Interrupt Enable (C3)0 = interrupt on Counter3 overflow disabled1 = interrupt on Counter3 overflow enabled




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[R15] Overflow Flag Status RegisterUnique ID: CP15.0.R15.c14.1The Overflow Status Flag Register identifies which counter of the Performance Monitoring Unit has overflowed and also indicates an interrupt is being requested if the overflowing register’s corresponding interrupt enable bit is asserted. An overflow is cleared by writing a ‘1’ to the overflow bit. Hence, a back to back read/write will clear any overflow bits.

Table 33: Overflow Flag Status Register (FLAG) Bit-level Description

Bits Field(short)

Access Reset Descript ion


3 - RW 0x0 Counter3 Overflow Flag (C3)Read Values:0 = no overflow on Counter3 1 = overflow on Counter3 occurred

Write Values:0 = no change1= clear this bit

2 - RW 0x0 Counter2 Overflow Flag (C2)Read Values:0 = no overflow on Counter21 = overflow on Counter2occurred


1 - RW 0x0 Counter1 Overflow Flag (C1)Read Values:0 = no overflow on Counter11 = overflow on Counter1 occurred


0 - RW 0x0 Counter0 Overflow Flag (C0)Read Values:0 = no overflow on Counter0 1 = overflow on Counter0 occurred


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4.6.20.4 Counter UsageUsage of the counters normally involves the following:

1. Reset the counter values.2. Write to one of the R15 registers to activate the counters and select the type of event to track.3. Run a program.4. Write to the counter control registers to stop the count.5. Read the counter registers to obtain the results of the counters.Be careful when counting events exactly, as the code to set up and read the counters may itself cause some countable events.

4.6.20.5 Application ExampleTo configure the counters, before starting the program to monitor:

LDR r0, = 0x5LDR r1, = 0x9LDR r2, = 0x101LDR r3, = 0x3LDR r4, = 0x0MCR p15, 0, r4, c15, c13, 0 ; Resets c0 low wordMCR p15, 0, r4, c15, c13, 1 ; Resets c0 high wordMCR p15, 0, r4, c15, c13, 2 ; Resets c1 low wordMCR p15, 0, r4, c15, c13, 3 ; Resets c1 high wordMCR p15, 0, r4, c15, c13, 4 ; Resets c2 low wordMCR p15, 0, r4, c15, c13, 5 ; Resets c2 high wordMCR p15, 0, r4, c15, c13, 6 ; Resets c3 low wordMCR p15, 0, r4, c15, c13, 7 ; Resets c3 high wordMCR p15, 0, r0, c15, c12, 0 ; Enable c0. D-Cache read hit is trackedMCR p15, 0, r1, c15, c12, 1 ; Enable c1. D-Cache read miss is trackedMCR p15, 0, r2, c15, c12, 2 ; Enable c2. Branch misprediction is trackedMCR p15, 0, r3, c15, c12, 3 ; Enable c3. Cycle count is tracked

After running the program to monitor:

MCR p15, 0, r4, c15, c12, 0 ; Disable c0MCR p15, 0, r4, c15, c12, 1 ; Disable c1MCR p15, 0, r4, c15, c12, 2 ; Disable c2MCR p15, 0, r4, c15, c12, 3 ; Disable c3

MRC p15, 0, r0, c15, c13, 0 ; Read c0’s lower wordMRC p15, 0, r1, c15, c13, 1 ; Read c0’s upper wordMRC p15, 0, r2, c15, c13, 2 ; Read c1’s lower wordMRC p15, 0, r3, c15, c13, 3 ; Read c1’s upper wordMRC p15, 0, r4, c15, c13, 4 ; Read c2’s lower wordMRC p15, 0, r5, c15, c13, 5 ; Read c2’s upper wordMRC p15, 0, r6, c15, c13, 6 ; Read c3’s lower wordMRC p15, 0, r7, c15, c13, 7 ; Read c3’s upper word

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4.6.21 CP15 Extra Features RegistersThe other R15 registers, besides those for the performance counters, provide additional extra features.

4.6.21.1 [R15] Coprocessor Enable RegisterUnique ID: CP15.0.R15.c1.0The Coprocessor Enable Register provides control of whether coprocessors CP0 to CP13 are, if present, enabled. It is a Read/Write register.

Current implementation:

Supports “WMMX2 SIMD Coprocessor” on page 95Does not affect “Integer Division” on page 117 (it is not a coprocessor)


MRC p15, 0, Rd, c15, c1, 0 ; Read Coprocessor Enable Register

MCR p15, 0, Rd, c15, c1, 0 ; Write Read Coprocessor Enable Register

Table 34 describes the bit level details of the Coprocessor Enable Register.

Table 34: Coprocessor Enable Register Bit-level Description


[31:14] RSVD RO 0x0 Reserved

13 cp13En RW b0 Coprocessor EnableEnables CP13, if present. 0 = Coprocessor disabled.1 = Coprocessor enabled.






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1 cp1En RW b0 Coprocessor EnableEnables CP1, if present. 0 = Coprocessor disabled.1 = Coprocessor enabled.See “WMMX2 SIMD Coprocessor” on page 95

0 cp0En RW b0 Coprocessor EnableEnables CP0, if present. 0 = Coprocessor disabled.1 = Coprocessor enabled.See “WMMX2 SIMD Coprocessor” on page 95

Table 34: Coprocessor Enable Register Bit-level Description


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4.6.21.2 [R15] Control Configuration RegisterUnique ID: CP15.1.R15.c1.0The Control Configuration Register provides access and control of additional the SoC CPU specific features. It is a Read/Write register.


MRC p15, 1, Rd, c15, c1, 0 ; Read control configuration register setting

MCR p15, 1, Rd, c15, c1, 0 ; Write control configuration register setting

When writing to this register, it is recommended to perform the read-modify-write operation so that only the required bits are set or reset. Writing to reserved bits will not have any effect. For example, if the user wants to enable write allocate, the following instruction sequence is recommended:

MRC p15, 1, R0, c15, c1, 0 ; Read current control configuration settingORR r0, r0, #0x10000000 ; Set bit 28 (write allocate enable bit)MCR p15, 1, R0, c15, c1, 0 ; Update control configuration setting

Table 35 describes the bit level details of the Control Configuration Register.

Table 35: Control Configuration Register Bit-level Description


31 - - 0x0 - (This bit is not used - it is removed from the original the SoC CPU implementation)

30 ncnb_wait RW 0x1 NCNB Wait FlagFor a non-cacheable non-bufferable (NCNB) access (Read/Write), this flag status indicates whether to wait until the write buffer is drained before the request is sent to the bus.

1 = NCNB accesses have to wait until the write buffer is empty.

0 = NCNB can go on as long as there is no data conflict in the write buffer.

This feature was made programmatically selectable so that users can determine the best setting for their application.

29 stream_en RW 0x1 D-Cache Streaming SwitchChanges D-Cache streaming behavior.

1 = Any missed word that is observed during line fill will be forwarded to the core. Execution then continues without waiting for the rest of the cache line to fill.

0 = Missed words are forwarded to the core after the cache line fills.

The switch is for D-Cache streaming only. I-Cache streaming is always enabled.

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28 wr_alloc_en RW 0x0 Enable Write AllocateSets behavior on write misses.

1 = A write that is a cache miss, cacheable, and bufferable causes a line fill. Enable this when there are many sequential writes (back-to-back writes within a region of memory).

0 = A write miss writes to the write buffer. If the write from the write buffer is too slow (due to slow memory latency), the write buffer can fill up easily, introducing processor stall if there are more writes. Higher performance can result if the write buffer does not fill frequently, or if not writing to sequential memory addresses.

If expecting sequential writes, store multiple (STM) instructions can take advantage of write-buffer bursts.Single stores cannot burst from the write buffer.

27:24 RSVD UNP/SBZP UNP/SBZP Reserved.

23 I2c_errd_en RW b0 1: Enable ECC error detection0: Disable ECC error detectionInitial value takes the value of twsi_errd_init (a bit field within a register defined at the system-level for configuring the SoC CPU).NOTE: Not Applicable for 88DE3010 since

optional L2C is not supported


19 Return stack disable

RW 0x0 1 = Disable branch return stack0 = Enable branch return stack

The return stack is used to speed up the returning from a subroutine through a prediction. An entry is pushed into the return stack entry on a jump to subroutine (unconditional BL). An entry is popped out of the return stack entry on a return from subroutine (unconditional BX R14). The return stack allows “BX R14” to get a target address from its entry at an earlier stage of the pipeline before the BX instruction is resolved. When BX finally resolves, it will flush and refetch from the correct target in case the return stack predicts incorrectly.

Table 35: Control Configuration Register Bit-level Description (Continued)


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18 Conditional indirect branch hold

RW 0x0 1 = Holds the instruction fetch after a conditional indirect branch instruction has been detected0 = Does not hold the instruction fetch after a conditional indirect branch instruction has been detected

In the case when the SoC CPU has detected an unconditional indirect branch, the instruction fetch is stopped until this branch instruction has been resolved. This makes sense because the target PC is going to change for sure and there is no need to fetch the sequential instruction that won’t be executed. In case this indirect branch is a conditional instruction, the sequential instruction could be valid if the condition of the indirect branch is false. Therefore, there is a switch for user to decide whether to hold the pipe or not depending on the performance expectation and the system usage. Indirect branch instructions are BX, BLX, and any ALU or LDST instructions updating PC.


8 WB_COALESCE_EN

RW b0 1=enable Write Buffer coalescing0=disable Write Buffer coalescing

7 wb_sparse_wstrb_disable

RW b0 b1 = disable sparse write strobes when merging store datab0 = enable sparse write strobes when merging store data

6:4 wb_wait_cycle RW 0x0 3’h0 = No wait cycle3’h1 = 2 wait cycle3’h2 = 4 wait cycles3’h3 = 8 wait cycles3’h4 = 16 wait cycles

For the pre-FIFO: 3’h5-7 = 16 wait cycles

For the main FIFO:3’h5 = 32 wait cycles3’h6-7 = 64 wait cycles


Table 35: Control Configuration Register Bit-level Description (Continued)


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4.6.21.3 [R15] Privileged Mode Access RegisterUnique ID: CP15.0.R15.c9.0The Privileged Access Register provides control of whether internal features may be accessed when in user mode. It is a Read/Write register.


MRC p15, 0, Rd, c15, c9, 0 ; Read Privileged Mode Access Register

MCR p15, 0, Rd, c15, c9, 0 ; Write Privileged Mode Access Register

Table 36 describes the bit level details of the Privileged Mode Access Register.

4.6.21.4 [R15] SoC CPU ID Code Extension RegisterUnique ID: CP15.1.R15.c12.0The CPU ID code Extension Register provides extra information on the processor architecture. It is a Read-only register.

The register can be read with the following instruction:

MRC p15, 1, Rd c15, c12, 0 ; Read SoC CPU ID Code Extension Register

Table 37 describes the bit fields in the SoC CPU ID Code Extension Register.

Table 36: Privileged Mode Access Register Bit-level Description


[31:1] RSVD SBZ SBZ Reserved

0 cAccess RW b0 Counter AccessEnables user-mode access to “Performance Counters” on page 760 = Privilege mode required1 = User mode access permitted.

Table 37: SoC CPU ID Code Extension Register Bit-level Description


[31:0] H RO 0x3 It reports the width of the hrdata bus. 0x2 = hrdata bus is 32 bits wide. 0x3 = hrdata bus is 64 bits wide.

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4.6.21.5 [R15] BPU Operations Register Unique ID: CP15.1.R15.c12.4The BPU Operations Register is a Write-only register and provides control of the processor’s Branch Prediction Unit (BPU). The processor core implements three-level branch prediction:

First, a 4-entry Branch Target Buffer (BTB) with 0-cycle penaltySecond, a 1,024-entry branch history tableThird, static branch prediction.

To write the BPU Operations Register, the following instruction is used:

MCR p15, 1, Rd, c15, c12, 4 ; Flush the BPU History Table

Table 38 describes the operations available in the BPU Operations Register.

Table 38: BPU Operations Register Bit-level Description

Function Descriptions

Bflush BPU Flush History TableThis command flushes the Branch Prediction Unit (BPU) history table. After reset, the processor automatically flushes the BPU history table. If, later in a program, the software remaps the instruction space, then it is recommended that the BPU be flushed. If not flushed, the misprediction does eventually correct itself. The flush may take several cycles. During a flush, the BPU does not use the BPU history table, so at that time, the branch prediction is on the Branch Target Buffer and static branch prediction only.The same operation is available in the Cache Operations Register (See “BPU Invalidate” on page 65.)I-Cache Invalidate operation also affects BPU (See “I-Cache Invalidate” on page 64.)

Note

Only the second level 1,024-entry is flushed. BTB is self-checking and will self-flush in case of context-switching or when a self-modifying code runs.

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4.6.22 The Marvell® Nomenclature for Uniquely Identifying Coprocessor RegistersFigure 13 illustrates the 32-bit instruction encoding for access to coprocessor registers in the 88DE3010 processor core.

The 15 primary coprocessor register numbers follow the style as shown in the heading for [R0] ID Code Register which is a CP15 R0 register.

A coprocessor register is identified with a unique ID. For example, a coprocessor register R1 with opcode2 = 0 is identified as follows:

Unique ID: CP15.0.R1.c0.0

The complete format is as follows:

The following notation is employed to describe the unique locations of each register:

Unique ID = CPx.opcode1.Rn.Cm.opcode2

Where:

The following example represents CP15 Control Register 1, when the register is at register number 1, bank 0, and both opcodes are 0:

Control Register 1 = CP15.0.R1.C0.0

The following example represents a register CP15.0.R1.C0.x that is accessible at a range of opcode2 values (1,4,5,6, and 7):

Control Register 3 = CP15.0.R1.C0.{1,4-7}

The following example represents a register accessible at a location other than a specified value. If CP15 Control Register 2 is accessed by opcode1=0, Rn=1, Cm=0, and when opcode2 is any other value than 2, then a circumflex prefix represents the negated set:

Control Register 2 = CP15.0.R1.C0.^2

Figure 13: MCR/MRC Instruction Encoding for Coprocessor Register Access

31 28 27 24 23 21 20 19 16 15 12 11 8 7 5 4 3 0

Cond b1110 op1 x CRn Rd px op2 1 CRm

CPx = Coprocessor number

Rn = Register number (represents CRn in Figure 13)

opcode1 = Value for opcode1 in MRC/MCR instructions

Cm = Register bank (represents CRm in Figure 13)

opcode2 = Value for opcode2 in MRC/MCR instructions

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4.6.23 Abbreviations for Register DescriptionsTable 39 describes abbreviations for CP15 registers

Table 39: CP15 Abbreviations

Abbreviat ion Descript ion

UNP UnpredictableRead: Unpredictable data is returned when reading from here. Any value can be assigned to this location.Write: Unpredictable behavior or an unpredictable change in device configuration is caused when writing to this location.

UND UndefinedAny instruction that accesses CP15 in the method implied takes the undefined instruction exception.

RO Read-Only

RW Read / Write

RC Read-Clear - the location is cleared upon read

WO Write-Only

SBZ Should be ZeroAll bits of the field should be zero when writing to this location.

SBO Should be OneAll bits of the field should be one when writing to this location.

RAZ Read as Zero Returns all bits as 0s when read

SBZP Should be Zero or PreservedAll bits of the field should be zero when writing to this location or preserved by writing the same value that has been previously read from the same field.

RSVD Reserved - the register filed is reserved for future implementation.

R# A Register Bank Number. For example R1 = Register Bank Number 1.

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SoC CPUWMMX2 SIMD Coprocessor



4.7 WMMX2 SIMD Coprocessor4.7.1 Introduction

The WMMX21 SIMD2 Coprocessor implements the Intel® Wireless MMX™ 2 (WMMX2) instructions. The WMMX2 SIMD Coprocessor maps onto two ARMTM-defined coprocessors identified as Coprocessor 0 and Coprocessor 1.

The ARMTM architecture supports up to 16 coprocessors in the standard coprocessor space, with each coprocessor having a unique number. The coprocessors typically have their own state in the form of a register file. In general, coprocessor instructions can be conditionally executed on flags set in the main ARMTM-defined status register3. Conditional execution allows the elimination of some branches.

The two coprocessors support the number of instructions, and provide elegant support of WMMX2 Coprocessor data and control registers using standard ARMTM coprocessor MCR / MRC transfer instructions. The coprocessor interface supports both a 32- and 64-bit interface to the core (to support MRC and MRCC class of coprocessor data transfer instructions).

The SIMD architecture accelerates functions where the same instruction frequently applies to a sequential series of data values. Such functions frequently occur in vector, array, and DSP manipulations; as an example, WMMX2 SIMD instruction sets improve SoC CPU support for real-time graphics.

4.7.2 Enabling the SIMD CoprocessorTo use the WMMX2, the coprocessors need to be enabled in the CP15 Coprocessor Access Register. After power-up and reset, the SIMD coprocessor is disabled by default. To enable SIMD acceleration, the SIMD coprocessor can be turned on by enabling <CP0> and <CP1> of the [R15] Coprocessor Enable Register.

Both bits 0 and 1 of this register (corresponding to coprocessor 0 and 1) should be set to a 1 to enable access to the WMMX2 Coprocessor. If the coprocessor is not enabled in this way, all WMMX2 Coprocessor instructions take the undefined instruction trap.

4.7.3 WMMX2 General-purpose Registers

4.7.3.1 Data RegistersThere are 16 main 64-bit data registers. The main register file is organized as sixteen 64-bit registers and numbered from wR0 through wR15 (See Figure 14, “WMMX Data Register Organization). The registers are located in Coprocessor 0.

4.7.3.2 Control & Status RegistersIn addition to the 16 main data registers, there are also a number of status and control registers, including saturation and arithmetic flag registers, and 4 general-purpose registers used for alignment and shift. The status and control registers map into the registers of Coprocessor 1 (see Table 40), which allows the standard MRC and MCR ARMTM instructions to read and write to these registers.

1. WMMX2 is an optional feature in SoC CPU.2. SIMD = Single-Instruction Multiple Data 3. This is a feature of the ARMTM architecture not present in the Intel® Wireless MMX™ 2 technology/SSE architecture

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Figure 14 shows the organization of the WMMX2 Data registers:

Figure 14: WMMX Data Register Organization

Table 40 provides a list of the WMMX2 Status and Control registers and their mappings in the Coprocessor 1.

The status registers include SIMD arithmetic flags and SIMD saturation flags.

Table 40: WMMX2 Status and Control Register Mappings

Mnemonic Register Name CP1 Register Number

wCID Coprocessor ID, Revision, Status 0

wCon Control 1

wCSSF Saturation SIMD Flags 2

wCASF Arithmetic SIMD Flags 3

- Reserved 4

- Reserved 5

- Reserved 6

- Reserved 7

wCGR0 General Purpose register 0 8




- Reserved 12

03164

wR0

wR15

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The control registers include:Saturation status (wCSSF)wCGR0-wCGR3 (32-bit general-purpose registers used for alignment, and shift)Coprocessor ID (wCID)Coprocessor Control register (wCon)

4.7.3.3 SIMD Coprocessor Pipeline IntegrationSo that instructions can be issued and retired in the correct sequence, the SIMD pipeline is directly integrated into the SoC CPU core.

4.7.3.4 SIMD Coprocessor DatapathThe SIMD coprocessor contains multiple bus multiplexers for rapid movement of data between the functional units.

4.7.4 SIMD Coprocessor Instruction SetThe SIMD coprocessor is fully compliant with the Intel® Wireless MMXTM 2 v1.5 instruction set. Supported instructions include:

MMX™ 2 Instructions1: WADD, WADDBHUS, WAND, WANDN, WCMPEQ, WCMPGT, WMUL, WMADD, WOR, WPACK, WSLL, WSRA, WSRL, WSUB, WUNPCKEH, WUNPCKIH, WUNPCKEL, WUNPCKIL, and WXORSSE instructions: WAVG2, WMAX, WMIN, WSAD, and WSHUFHNew Media instructions: WABS, WABSDIFF, WADDSUBX, WAVG4, WMERGE, WMIAWxy, WMIAWxy, WMULW, WQMIAXY, WQMULM, WQMULWM, WSUBADDX, and TORVSC Transfer Instruction Mapping instructions: TANDC, TBCST, TEXTRC, TEXTRM, TINSR, TMCR, TMCRR, TMIA, TMIAPH, TMIAXY, TMOVMSK, TMCRR, TMRRC, and TORCOther Instructions: WACC, WALIGNI, WALIGNR, WMAC, and WRORLoad/Store Instructions: WLDR and WSTR Synthetic Instructions: WMOV and WZERO

Note

When any wCGRn register is used as an argument, the encoding for the register is the coprocessor register number shown in Table 40. For example, encoding for wCGR0 = 0b1000. Using a non-valid encoding for a wCGRn register results in unpredictable behavior.

1. MMX™ 2 includes the original Intel® Multimedia Extension instructions; the other six categories are extensions to MMX™ 2; WMMX2 includes all the original MMX™ 2 instructions platform plus other extension instructions.

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The following tables describe the instructions available with the SIMD coprocessor:

4.7.4.1 SIMD MMX™ 2 Instructions

Table 41: MMX™ 2 Compliant Instructions

Instruction Description

WADD Performs vector addition of wRn and wRm for vectors of 8-, 16-, or 32-bit signed or unsigned data, and places the result in wRd. Saturation can be specified as signed, unsigned, or no saturation. The use of the carry flags from the wCASF register may be optionally supplied as the Carry-in to the addition operation using the C-qualifier. The add with carry-in option is valid for 16- and 32-bit operands only.

WADDBHUS Performs vector mixed mode addition of four 16-bit signed elements and four 8-bit zero-extended unsigned elements from wRn and wRm. The result of the operation places four 8-bit values saturated to the unsigned limits, for example 0-255, into the upper or lower half of wRd. The M and L qualifiers are used to select the upper or lower half of the source register containing the packed unsigned byte operands and the upper or lower half of the destination register wRd.

WAND Performs a bitwise logical AND between wRn and wRm, and places the result in the destination register, wRd.

WANDN Performs a bitwise logical “AND” between wRn and “NOT” wRm, and places the result in the destination register, wRd.

WCMPEQ Performs vector-equality comparison of wRn and wRm for vectors of 8-, 16-, or 32-bit data, setting the corresponding data elements of wRd to all ones when source operands are equal; else all zeros.

WCMPGT Performs vector-magnitude comparison of wRn and wRm for vectors of 8-, 16-, or 32-bit data, setting the corresponding data elements of wRd to all ones when corresponding fields of wRn and greater than wRm; else all zeros; operation can be performed on either signed or unsigned data.

WMUL Performs a vector multiplication of wRn and wRm on vectors of 16-bit data only; M-qualifier indicates that the higher order 16 bits of the result are to be stored in wRd, the L-qualifier indicates that the lower 16 bits of the result are to be stored in wRd; can be performed on signed or unsigned data. Biased rounding is available with the M-qualifier through the use of the R-qualifier.

WMADD Performs a 16-bit vector multiplication and then sums the lower two products into the bottom word of wRd, and the upper two products into the upper word of wRd; intermediate products are 32 bit; can operate on either signed or unsigned data. The operands may be cross multiplied with the use of the X-qualifier and may be optionally subtracted with the use of the N-qualifier. The X-qualifier may only be used with the default multiply-add operation.

WOR Performs a bitwise logical “OR” between wRn and wRm and places the result in the destination register, wRd

WPACK Packs data from wRn and wRm into wRd, with wRm being packed into the upper half, and wRn being packed into the lower half for vectors of 16, 32-, or 64-bit data, and saturate the results and place in the destination register wRd; packing can be performed with signed saturation or unsigned saturation

WSLL Performs vector logical shift-left of wRn by wRm, or a control register (wCx), or a 5-bit immediate for vectors of 16-, 32-, or 64-bit data and places the result in wRd.

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4.7.4.2 SIMD SSE Instructions

WSRA Performs vector arithmetic shift-right of wRn by wRm, or a control register (wCx), or a 5-bit immediate for vectors of 16-, 32-, or 64-bit data and places the result in wRd.

WSRL Performs vector logical shift-right of wRn by wRm, or a control register (wCx), or a 5-bit immediate for vectors of 16-, 32-, or 64-bit data and places the result in wRd.

WSUB Performs vector subtraction of wRm from wRn for vectors of 8-, 16-, or 32-bit signed or unsigned data, and places the result in wRd. Saturation can be specified as signed, unsigned, or no saturation.

WUNPCKEH Unpacks 8-bit, 16-bit, or 32-bit data from the top half of wRn (the source register), and either zero or signed- extends each field, and places the result into the destination register, wRd.

WUNPCKIH Unpacks either 8-bit, 16-bit, or 32 bit data from the top half of wRn, interleaves with the top half of wRm, and places the result into the destination register, wRd.

WUNPCKEL Unpacks either 8-bit, 16-bit, or 32 bit data from the lower half of wRn (the source register), and either zero- or sign- extends each field, and places the result into the destination register, wRd.

WUNPCKIL Unpacks either 8-bit, 16-bit, or 32 bit data from the lower half of wRn and the lower half of wRm, and places the result into the destination register, wRd.

WXOR Performs a bitwise logical “XOR” between wRn and wRm, and places the result in wRd.

Table 41: MMX™ 2 Compliant Instructions (Continued)


Table 42: SIMD SSE Instructions


WAVG2 Performs a 2-pixel average of wRn and wRm on unsigned vectors of 8- or 16-bit data with optional biased rounding and places the result in the destination register, wRd.

WMAX Performs vector maximum selection of elements from wRn and wRm for vectors of 8-, 16-, or 32bit data and places the maximum fields in the destination register, wRd; can be performed on signed or unsigned data.

WMIN Performs vector minimum selection of elements from wRn and wRm for vectors of 8-, 16-, or 32bit data, and places the minimum fields in the destination register, wRd; can be performed on signed or unsigned data.

WSAD Performs the sum of absolute differences of wRn and wRm, and accumulates the result with wRd; can be applied to 8-bit or 16-bit unsigned data vectors.

WSHUFH Select (shuffle) 16-bit data values in destination register, wRd, from 16-bit fields in source register specified by the 8-bit immediate value.

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4.7.4.3 SIMD New Media Technology Instructions

Table 43: SIMD New Media Instructions


WABS Performs a vector absolute value of wRn on 8-bit, 16-bit, or 32-bit signed data and places the result into the destination register, wRd.

WABSDIFF Performs a vector absolute value of the differences of wRm and wRn for vectors 8-bit, 16-bit, or 32-bit unsigned data, and places the result in wRd.

WADDSUBX Performs complex vector addition/subtraction of wRn and wRm for vectors of 16-bit data, and places the result in wRd. The four operands from each of the source registers are alternately added and subtracted using a cross selection in each of the parallel operations. The result of the operation is saturated to the signed limits, for example, 0x8000 to 0x7fff or -32768 to 32767.

WAVG4 Performs seven 4-pixel averages of unsigned 8-bit operands obtained from the bytes of the wRn and wRm source registers. Biased rounding is supported through the use of the R-qualifier. The seven 4-pixel averages are packed into the lower seven bytes of the destination register with the most significant byte written with 0x00.

WMERGE Extracts a 64-bit value that contains elements from the two 64-bit source registers (wRn, wRm), and places a merged 64-bit result in the destination register, wRd. The number of adjacent elements from each register is represented with a 3-bit immediate.

WMIAxy Performs a signed parallel 16-bit multiply, or multiply-negate, followed by 64-bit accumulation. The upper or lower 16-bits of each source register half is selected by specifying either the B (bottom) or T (top) in each of the xy positions of the mnemonic. The xy selection is the same for both the upper and lower halves of the 64-bit operand source registers, wRn and wRm. The resulting product for the upper and lower halves are then added to the 64-bit accumulator which occupies the destination register wRd. The N-qualifier optionally provides for a multiply-negater accumulate operation instead of the default multiply-accumulate.

WMIAWxy Performs multiply-accumulate using signed 32-bit operands from the two source wRm and wRn, and accumulates the result with the destination register, wRd. The upper or lower 32-bits of each source register half is selected by specifying either the B (bottom) or T (top) in each of the xy positions of the mnemonic.The N-qualifier optionally provides for a multiply-negate-accumulate operation instead of the default multiply-accumulate.

WMULW Performs a vector multiplication of wRn and wRm on vectors of 32-bit data only; UM-qualifier indicates that the higher order 32 bits of the result of the unsigned multiplication are to be stored inwRd, the SM-qualifier indicates that the higher order 32 bits of the signed multiplication are to be stored in wRd, and the L-qualifier indicates that the lower 32 bits of the result are to be stored in wRd. Biased rounding is available with the UM and SM options through the use of the R-qualifier.

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WQMIAXY Performs a signed fractional parallel 16-bit multiply, or multiply-negate, followed by parallel 32-bit accumulation. The upper or lower 16-bits of each Intel® Wireless MMXTM 2 coprocessor source register half is selected by specifying either the B (bottom) or T (top) in each of the xy positions of the mnemonic. The xy selection is the same for both the upper and lower halves of the 64-bit operand source registers, wRn and wRm. The resulting product for the upper and lower halves are then added to the two 32-bit accumulators which occupy the upper and lower halves of the 64-bit destination register wRd. A left shift correction is applied following the multiplication and saturation is provided with the addition for 32-bit signed operands.

WQMULM Performs a vector multiplication of wRn and wRm on vectors of signed fractional 16-bit Qm.n values. The upper half of the results are stored in wRd with a left shift correction to renormalize the fractional data. Biased rounding, “round to nearest” is supported with the R-qualifier with truncation as the default behavior.

WQMULWM Performs a vector multiplication of wRn and wRm on vectors of signed fractional 32-bit Qm.n values. The upper half of the results are stored in wRd with a left shift correction to renormalize the fractional data. Biased rounding, “round to nearest” is supported with the R-qualifier with truncation as the default behavior.

WSUBADDX Performs complex vector subtraction/addition of wRn and wRm for vectors of 16-bit data, and places the result in wRd. The four operands from each of the source registers are alternately added and subtracted using a cross selection in each of the parallel operations.The result of the operation is saturated to the signed limits, for example, 0x8000 to 0x7fff or -32768 to 32767.

TORVSC Performs “OR” across the fields of the SIMD saturation flags (wCSSF) and sends the result to the ARM* CPSR Overflow, (V), flag; operation can be performed after a byte, half-word or word operation that sets the flags.

Table 43: SIMD New Media Instructions (Continued)


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4.7.4.4 SIMD Transfer Instruction Mapping (Wireless Extensions) These instructions are mapped onto the coprocessor transfer instructions.

Table 44: SIMD Transfer Instruction Mapping Instructions


TANDC Performs “AND” across the fields of the SIMD processor status register (PSR) (wCASF) and sends the result to the ARM* CPSR; can be performed after a byte, half-word or word operation that sets the flags.

TBCST Broadcasts a value from the ARM* source register, Rn, or to every SIMD position in the Intel® Wireless MMXTM 2 coprocessor destination register, wRd; can operate on 8-, 16-, and 32-bit data values.

TEXTRC Extracts 4-/8-/16-bit field specified by the 3-bit immediate field data from the SIMD PSR (wCASF), and transfers to the ARM* CPSR.

TEXTRM Extracts 8-/16-/32-bit field specified by the 3-bit immediate field data from Intel® Wireless MMXTM 2 coprocessor source register, wRn, and transfers to the specified ARM* core register, Rd.

TINSR Transfers and inserts 8-/16-/32-bit data from ARM* source register, Rn, to the position in Intel® Wireless MMXTM 2 coprocessor destination register, wRd, specified by the 3-bit immediate.

TMCR TMCR is a pseudo-instruction that maps onto ARM* MCR instruction, and is provided for convenience; TMCR transfers the contents of the Rn ARM* core registers to a 32-bit wCx Intel® Wireless MMXTM 2 coprocessor control register.

TMCRR TMCRR is a pseudo-instruction that maps onto an ARM* MCRR instruction and is provided for convenience; TMCRR transfers the contents of the two ARM* registers (RdHi and RdLo) to wRd (the 64-bit Intel® Wireless MMXTM 2 coprocessor destination register).

TMIA Provides the same functionality as the XScale® micro architecture MIA instruction; performs multiply-accumulate using signed 32-bit operands from the two source ARM* core registers (Rm, Rs), and accumulates the result with the Intel® Wireless MMXTM 2 coprocessor destination register, wRd.

TMIAPH Provides the same functionality as the Intel XScale® micro architecture MIAPH instruction; performs multiply-accumulate using signed 16-bit operands from the two source ARM* core registers (Rm.Rs), and accumulates the result with the Intel® Wireless MMXTM 2 coprocessor destination register, wRd.

TMIAXY Provides same functionality as Intel XScale® micro architecture MIAXY instruction; performs a 16- bit multiply-accumulate using two signed operands from the ARM* core registers (Rm, Rs) and accumulates the result with the Intel® Wireless MMXTM 2 coprocessor destination register; upper or lower 16-bits of each source register is selected by specifying either a B (bottom) or T (qualifier) in each of the xy positions of the mnemonic.

TMOVMSK Transfers the most significant bit of each SIMD field of the Intel® Wireless MMXTM 2 coprocessor source register (wRn) to the least significant 8, 4, or 2 bits of the specified ARM* destination register (Rd); this instruction operates on 8-,16-, and 32-bit data values.

TMRC TMRC is a pseudo- instruction that maps onto an ARM* core MRC instruction and is provided for convenience; TMRC transfers the contents of the 32-bit Intel® Wireless MMXTM 2 coprocessor control register (wCx) to the ARM* core destination register (Rd).

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4.7.4.5 SIMD Other Instructions

TMRRC TMRRC is a pseudo-instruction that maps onto a standard ARM* MRRC instruction and is provided for convenience; TMRRC transfers the contents of the wRn 64-bit Intel® Wireless MMXTM 2 coprocessor data register to two ARM* core destination registers (RdHi, RdLo).

TORC Performs “OR” across the fields of the SIMD PSR (wCASF) and sends the result to the ARM* CPSR; operation can be performed after a byte, half-word or word operation that sets the flags. Other Instructions

Table 44: SIMD Transfer Instruction Mapping Instructions (Continued)


Table 45: SIMD Transfer Instruction Mapping Instructions


WACC Performs an unsigned accumulate across the source register (wRn) fields, and writes result to destination register, wRd; operation can be performed on fields of byte, half-word, and word size.

WALIGNI Extracts an 64-bit value from the two 64-bit source registers (wRn, wRm), and places the result in the destination register, wRd; instruction uses a 3-bit immediate value to specify the byte offset of the value to extract.

WALIGNR Extracts a 64-bit value from the two 64-bit source registers (wRn, wRm), and places the result in the destination register, wRd; instruction uses a 3-bit value stored in the specified general-purpose register to specify the byte offset of the value to extract.

WMAC Performs a vector multiplication of wRn and wRm and can accumulate the result with wRd on vectors of 16-bit data only.

WROR Performs vector logical rotate-right of wRn by wRm, or a control register (wCx), or a 5-bit immediate for vectors of 16-, 32-, or 64-bit data and places the result in the destination register, wRd. Load/Store Instructions

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4.7.4.6 SIMD Load/Store Instructions

4.7.4.7 SIMD Synthetic Instructions These instructions are aliases to specific forms of other instructions:

4.7.5 SIMD Coprocessor Instruction DetailsFor more details, refer to the “Intel XScale® Technology: Intel® Wireless MMX™ 2 Coprocessor Programmers Reference Manual, Revision 1.5", (Intel Corp, July, 2006) at

ftp://download.intel.com/design/intelxscale/31451001.pdf

Appendix D in the above document is not relevant to the Marvell implementation.

Table 46: SIMD Load/Store Instructions


WLDR Performs a load from memory into either a data register (wRd) or a control register (wCx); 8-,16-, 32-, and 64-bit data values can be loaded in the data registers and 32-bit values only can be loaded into the control registers; loaded data is zero-extended. The immediate offset addressing mode is provided for data and control register load operations. The register offset addressing mode is provided for 64-bit loads to the data registers. A left shift may be optionally applied to the offset when using the register offset addressing mode.

WSTR Performs a store from the source register (either wRm or wCx) into the memory location whose address is specified by the Rn register and corresponding address modifiers; 8-, 16-, 32-, and 64bit data values can be stored from the data registers (wRm), and 32-bits only can be stored from the control registers (wCx). The immediate offset addressing mode is provided for both data and control register store operations. The register offset addressing mode is provided for 64-bit store operations from the data registers. A left shift may be optionally applied to the offset when using the register offset addressing mode.

Table 47: SIMD Synthetic Instructions


WMOV This pseudo-instruction moves register wRn to register wRd; this instruction is a form of WOR.

WZERO This pseudo-instruction zeros the Intel® Wireless MMXTM 2 coprocessor destination register, wRd; this instruction is a form of the WANDN instruction.

ftp://download.intel.com/design/intelxscale/31451001.pdf

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SoC CPUMemory Management Unit



4.8 Memory Management Unit4.8.1 Overview

The CPU implements the ARM Memory Management Unit (MMU) defined by the ARM Architecture Version 5TE Specification with some extensions, including support for shared memory and an L2 cache1.This chapter describes the CPU specific MMU features and assumes the reader has prior knowledge of the ARM MMU Architecture.

The CPU supports the multi-level page table structure and page table entries defined by the ARM MMU Architecture. The page table allows various size regions of memory to be defined with similar attributes. The individual entries in the table (known as descriptors) specify the virtual to physical address translation, memory protection, and memory attribute information for a specific region of memory.

The CPU extends the ARM MMU Architecture with two new descriptor types: supersection and extended small page. A supersection provides a 16MB memory page (see Section , Supersection Descriptor ); the extended small page is similar to a small page, except it allows additional memory attributes to be specified for 4KB pages of memory (see "Extended Small Page Descriptor" on page 108).

The memory protection used by the CPU is the same as that defined by the ARM MMU Architecture (see ARM Architecture Version 5TE Specification).

The CPU extends the memory attributes defined by the ARM MMU Architecture to support additional capabilities such as an L2 cache and shared memory. The CPU page tables allow system software to associate the following attributes with regions of memory:

Cacheable in Level 1 (L1) instruction cache and data cache (see Section 4.8.3)Cacheable in L2 cache (not applicable for 88DE3010)Shared memory (downgrades cacheable accesses to non-cacheable) (see Section )Write-back vs. write-through L1 data cache write policy (see Section 4.8.2.4)Coalescing (see Section 4.8.2.4)

To accelerate virtual to physical address translation, the CPU uses a unified main TLB along with two separate 8-entry mini TLBs to cache the latest translation information for data and instruction access. In addition to the address translation, the TLBs contain memory access permissions and memory region attributes. The TLBs can be managed using the TLB functions available in CP15 Section 4.6.13, [R8] TLB Operations Register and Section 4.6.15, [R10] TLB Lockdown Register .

On a TLB miss, the core invokes a hardware mechanism, known as a table walk. The table walk reads the page table in backing memory to get the virtual to physical address mapping, as well as memory attributes for the region of memory being accessed.

Following a table walk, the address translation and memory attribute information is placed in the TLB.

For additional details on the address translation process refer to Section 4.8.2.1.

The MMU may report prefetch aborts (for instruction fetches) or data aborts (for data accesses) during the address translation process. The types of aborts which may be generated are described in Section 4.8.4. Software may control and manage the MMU using registers and functions in Section 4.6, CP15 Coprocessor .

1. This product does not support L2 Cache; only data relevant to “L2 Cache not present” is applicable

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4.8.2 Architecture Model

4.8.2.1 Address Translation ProcessThe MMU accesses the TLB and does table walks based on the modified virtual address (MVA). This means that all operations which operate on a virtual address (instruction fetches, data accesses, DC line allocate) are first remapped by the Section 4.6.18, CP15 Process ID Registers . It is this remapped address, the MVA, that is used when searching the TLB or, in the case of a TLB miss, for reading the page table in memory.

When an MVA does not hit in the TLB, a table walk is required. During a page table walk, bits in the Translation Table Base Register can be used to specify certain memory attributes to use during the table walk. In particular - the shared memory attribute, the ASSP specific attribute and L2 cacheability - may be applied to the table walk. For more information on programming these attributes, refer to Section 4.6.6, [R2] Translation Table Base Register .

4.8.2.2 Page Table Descriptor FormatsThe CPU extends the descriptors defined in ARM MMU Architecture with the supersection and extended small page descriptors. Table 48 through Table 50 show the page table descriptor formats supported by the CPU.

Table 48: First-level Descriptors

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

SBZ 0 0

Coarse page table base address P Domain SBZ 0 1

Section base Address SBZ

0 SBZ

S SBZ

TEX AP P Domain 0 C B 1 0

Supersection base address Base address [35:32]

SBZ

1 SBZ

S SBZ

TEX AP P SBZ 0 C B 1 0

Fine page table base address SBZ P Domain SBZ 1 1

Table 49: Second-level Descriptors for Coarse Page Table

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

SBZ 0 0

Large page base address S TEX AP3 AP2 AP1 AP0 C B 0 1

Small page base address AP3 AP2 AP1 AP0 C B 1 0

Extended small page base address SBZ S TEX AP C B 1 1

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Supersection DescriptorThe CPU defines a first-level descriptor, known as a superstition, to support physical addressing of up to 36 bits. Note that SoC CPU only implements 32 bits of physical address. The supersection descriptor, shown in Table 48 is based on the section descriptor format, with bit 18 of the descriptor used to differentiate between the two.

Figure 15, Address Translation for Supersection, on page 108 shows the process for translating a 32-bit virtual address into a 36-bit physical address using a supersection descriptor.

A supersection defines a 16 MB region of memory and must start on a 16 MB boundary. Supersections always use Domain 0.

Note in Figure 15, the virtual address shows the lower 4 bits of the first-level table index overlapping with the upper four bits of the supersection index. Since a supersection covers 16 MB of memory, it consumes 16 consecutive descriptor entries in the first level page table. All 16 entries must be programmed with the same descriptor value, otherwise the results are unpredictable.

Table 50: Second-level Descriptors for Fine Page Table

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9 8 7 6 5 4 3 2 1 0

SBZ 0 0

Large page base address S TEX AP3 AP2 AP1 AP0 C B 0 1

Small page base address AP3 AP2 AP1 AP0 C B 1 0

Tiny Page Base Address SBZ

TEX AP C B 1 1

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Extended Small Page DescriptorThe CPU defines a second level descriptor, known as an extended small page, to allow memory attributes to be specified on a 4 KB page size. Note that the extended small page is only defined for a coarse second level page table (refer to Table 49).

The address translation for an extended small page is the same as for a small page (refer to the ARM Architecture Version 5TE Specification).

4.8.2.3 Memory AttributesThe attributes associated with a region of memory are configured in the page table and control the behavior of accesses to the L1 caches (instruction and data), L2 cache, and write-buffers.

When the MMU is disabled, the memory attributes defined in the page table are ignored. All instruction fetches default to L1 cacheable and L2 uncacheable. Data accesses default to strongly ordered (refer to Section 4.8.2.4 for a definition of strongly ordered).

Refer to Section 4.8.3, L1 Instruction Cache, Data Cache Behavior, on page 116 for more information on L1 cache behavior.

Figure 15: Address Translation for Supersection

31 14 13

31 14 13 2 1 0

Translation base SBZ

First-leveltable index Supersection index

0

Translation base First-leveltable index 0 0

Supersection Supersection indexPhysicalAddress

First-leveldescriptor

VirtualAddress

Translationtable base

Address offirst-level

descriptor

31 24 23 0

First-level fetch

31 2019 02324

3235Base addr

[35:32]

Supersection 1 0

31 23 5 4 3 211 10 9 8 1 0

APBase

C B

14

TEX P 0

201918171615

addr[35:32]

S1SBZ

SBZ

24

base addressSBZ

SBZ

base address

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Inner/Outer CacheabilityThe CPU provides support for multiple layers of cache, referred to as the inner and outer caches. Inner/Outer refers to the levels of caches that may be built in a system. Inner refers to the inner-most caches, including L1. Outer refers to the outer-most caches. Inner cache on CPU is defined to be the L1 instruction and data caches. The outer cache is defined to be the L2 cache, when present.

The inner/outer cacheability attributes are not controlled by any individual bits but rather by a combination of descriptor bits and also by whether the L2 is present or not. For memory regions defined as Low Locality Reference (see Section , Low Locality of Reference (LLR) ) attribute bits in the Auxiliary Control Register (see Section 4.6.4, [R1] Control Register and Section 4.6.5, [R1] Auxiliary Control Register ) also control inner/outer cacheability.

Coherent Memory Attribute (S-bit)The coherent memory attribute is used to define a region of memory as being shared by multiple agents. The CPU downgrades cacheable memory regions to non-cacheable based on whether the region is defined to be shared.

The shared attribute is supported for all page types, except for small pages and tiny pages. It is represented by the S bit in the descriptors (see Table 48, Table 49, and Table 50).

Low Locality of Reference (LLR)Certain page table encodings define the L1 data cache to be LLR. This feature allows an application to confine data in LLR memory regions to a single way of the L1 data cache, instead of polluting the entire cache. Note that the current SoC CPU implementation does not treat LLR memory regions any differently than normal cacheable regions.

The L1 and L2 cache write policies for LLR regions are defined in the Section 4.6.5, [R1] Auxiliary Control Register 1.

ASSP Specific Attribute (P-bit)This bit is only present in the first level descriptors, so the attribute can only be used to specify behavior at 1 megabyte and 16 megabyte (supersection) memory granularity.

It provides a method for allowing ASSPs to define their own attribute for a region of memory. ASSPs can use the P bit in the 1st level descriptors to assign its own page attribute to a memory region2.

4.8.2.4 Memory Attribute EncodingsThe memory attributes are encoded within the page table descriptors using the C, B, and shared (S) bits, and type extension (TEX) field. Table 48, Table 49, and Table 50 show the location of these bits in the descriptors.

Table 51 through Table 58 are complete listing of the CPU page attributes. These tables use the following terms for non-cacheable memory:

Strongly ordered defines a non-cacheable, non-coalesceable memory region to which memory accesses behave as bi-directional fences. This means that all agents in a system will see explicit memory accesses in program order relative to a strongly ordered memory access. Explicit memory access refers to instructions which do loads and/or stores. Also note that strongly ordered memory is implied to be shared (regardless of the S bit value in the descriptor).Device memory is non-cacheable memory well suited for memory mapped peripherals. The processor will not coalesce writes to device memory. Instruction fetches to non-shared device

1. LLR is introduced as a new concept; however, current version of SoC CPU does not implement LLR2. SoC CPU bus transactions are never influenced by this ASSP attribute, so it will never by used by any ASSP (SOC)

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memory may result in unpredictable behavior. However, for compatibility with previous processors, instruction fetches may be done to shared device memory.Inner/Outer Uncacheable is non-cacheable memory which allows writes to coalesce and be re-ordered.

In the following tables usage of ‘X’ in a bit position (i.e., 1X0) indicates that bit may be 1 or 0.

Table 51: Cache Attributes with L2 present, S=0

TEX C B L1 I-cache Cache-able

L1 D-cache Cache-able

L1 DCWrite Pol icy

L2 Cache-able

Writes May Coalesce

Descript ion

000 0 0 N N - N N Strongly ordered (shared)

000 0 1 N N - N Y Shared Inner/Outer uncacheable1

000 1 0 Y Y WT N Y Inner write-throughOuter uncacheable

000 1 1 Y Y WB Y Y Inner write-backOuter write-back

001 0 0 N N - N Y Inner/Outer uncacheable

001 0 1 N N - N N Shared Device

001 1 0 Y Y See Description

See Description

Y Low Locality of Reference (LLR) MemoryAuxiliary Control Register specifies L1 D-cache write policy and L2 cacheability. See Table 53 for details

001 1 1 Y Y WB Y Y Inner write-backOuter write-back

010 0 0 N N - N N Non-shared device

010 0 1 N/A N/A N/A N/A N/A RESERVED



011 X X N/A N/A N/A N/A N/A RESERVED

1X0 0 0 N N - N Y Inner/Outer uncacheable

1X0 0 1 Y Y WB N Y Inner write-backOuter uncacheable

1X0 1 0 Y Y WT N Y Inner write-throughOuter uncacheable

1X0 1 1 Y Y WB N Y Inner write-backOuter uncacheable

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1X1 0 0 N N - Y Y Inner uncacheable; Outer write-back

1X1 0 1 Y Y WB Y Y Inner write-backOuter write-back

1X1 1 0 Y Y WT Y Y Inner write-throughOuter write-back

1X1 1 1 Y Y WB Y Y Inner write-backOuter write-back

1. The inner/outer uncacheable behavior for TEX CB encoding ‘000 01’ is deprecated on CPU. TEX CB encoding ‘001 00’ should be used instead if inner/outer uncacheable memory is required.

Table 52: Cache Attributes with L2 present, S=1

TEX C B L1 I-cache Cacheable

L1 D-cache Cacheable

L1 D-cache Write Policy

L2 Cacheable

Writes May Coalesce

Description

000 0 0 Y Y - Y N Strongly ordered (shared)

000 0 1 Y Y - Y Y Inner/Outer uncacheable




001 0 1 Y Y - Y N Shared Device

001 1 0 Y Y Y Y Y Inner/Outer uncacheable


010 0 0 Y Y - Y N Inner/Outer uncacheable




011 X X N/A N/A N/A N/A N/A RESERVED

1X0 0 0 Y Y - Y Y Inner/Outer uncacheable


Table 51: Cache Attributes with L2 present, S=0 (Continued)

TEX C B L1 I-cache Cache-able

L1 D-cache Cache-able

L1 DCWrite Pol icy

L2 Cache-able

Writes May Coalesce

Descript ion

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1X0 1 1 Y Y Y Y Y Inner/Outer uncacheable

1X1 0 0 Y Y Y Y Y Inner/Outer uncacheable




Table 53: LLR Page Attributes, L2 Present Case, S=0

Auxil iary Control Register Sett ing

L1 I -cache Cacheable


L1 D-Cache Write Policy

L2 Cacheable

Writes May Coalesce

Description

Inner write-throughouter uncacheable

Y Y WT N Y -

Inner write-throughouter write-back, write allocate

Y Y WT Y Y -

Inner write-backouter uncacheable

Y Y WB N Y -

Inner write-backouter write-back, write allocate

Y Y WB Y Y -

Table 54: LLR Page Attributes, L2 Present Case, S=1




L1 D-cache Write Pol icy

L2 Cacheable

Writes May Coalesce

Description


Y Y Y Y Y Inner/Outer uncacheable


Y Y - Y Y Inner/Outer uncacheable


Y Y Y Y Y Inner/Outer uncacheable

Table 52: Cache Attributes with L2 present, S=1 (Continued)




L2 Cacheable

Writes May Coalesce

Description

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Y Y - Y Y Inner/Outer uncacheable

Table 55: Cache Attributes with no L2, S=0




Writes May Coalesce

Description

000 0 0 N N - N Strongly Ordered (shared)

000 0 1 N N - Y Shared Inner uncacheable1

1. The inner/outer uncacheable behavior for TEX CB encoding ‘000 01’ is deprecated on CPU. TEX CB encoding ‘001 00’ should be used instead if inner/outer uncacheable memory is required.

000 1 0 Y Y WT Y Inner write-through

000 1 1 Y Y WB Y Inner write-back

001 0 0 N N - Y Inner uncacheable

001 0 1 N N - N Shared Device

001 1 0 Y Y See Description

Y Low Locality of Reference (LLR) memoryAuxiliary Control Register specifies L1 D-cache write policy.See Table 57 for details.

001 1 1 Y Y WB Y Inner write-back

010 0 0 N N - N Non-shared device

010 0 1 N/A N/A N/A N/A RESERVED



011 X X N/A N/A N/A N/A RESERVED

1XX 0 0 N N - Y Inner uncacheable

1XX 0 1 Y Y WB Y Inner write-back

1XX 1 0 Y Y WT Y Inner write-through

1XX 1 1 Y Y WB Y Inner write-back

Table 54: LLR Page Attributes, L2 Present Case, S=1 (Continued)





L2 Cacheable

Writes May Coalesce

Description

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Table 56: Cache Attributes with no L2, S=1




Writes May Coalesce

Descript ion

000 0 0 Y Y Y N Strongly ordered (shared)

000 0 1 Y Y Y Y Inner/Outer uncacheable




001 0 1 Y Y Y N Shared Device



010 0 0 Y Y Y N Inner/Outer uncacheable




011 X X N/A N/A N/A N/A RESERVED

1XX 0 0 Y Y Y Y Inner uncacheable

1XX 0 1 Y Y Y Y Inner/Outer uncacheable



Table 57: LLR Page Attributes, no L2 case, S=0





Writes May Coalesce

Description


Y Y WT Y -


Y Y WT Y -


Y Y WB Y -

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Y Y WB Y -

Table 58: LLR page attributes, no L2 case, S=1


L1 I-cache Cacheable



Writes May Coalesce

Description


Y Y Y Y Inner/Outer uncacheable







Table 57: LLR Page Attributes, no L2 case, S=0 (Continued)





Writes May Coalesce

Description

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4.8.3 L1 Instruction Cache, Data Cache BehaviorWhile the MMU is disabled all page table attributes are ignored. All instruction accesses are considered to be cacheable and are cached in the L1 instruction cache when it is enabled. Data accesses are treated as strongly ordered.

When the MMU is enabled, the following conditions must be met in order to enable L1 instruction caching:

Specified address must be marked as L1 cacheable in the page table attributes

Similarly, the following conditions must be met in order to enable L1 data caching:

Data cache must be enabled (bit 2, register 1 of CP15 Control Register is set)Specified address must be marked as L1 cacheable in the page table attributesThe S bit must not be set

The cache attributes in the page table also tell the caches how to handle write data that hits the L1 data cache. The two methods of handling write data are write-back and write-through. Write-back updates the data only in the L1 data cache, while write-through updates the data both in the L1 data cache and the backing memory. The L1 Instruction Cache only allocates a line in the cache for instructions that miss the cache (i.e., L1 Instruction Cache only supports read-allocate). If the Enable Write Allocate bit in the CP15 Control Configuration Register is cleared, writes to addresses not contained in the L1 data cache will never cause a cache line to be allocated. If the Enable Write Allocate bit is set, a cache line will be allocated on write misses.

4.8.4 ExceptionsThe MMU may generate aborts on instruction fetches or data accesses.

For an instruction fetch, the MMU generates a prefetch abort for:

Translation faultsExternal abort on translationDomain faultsPermission faults

On a data access, the MMU generates a data abort for:

Alignment faultsTranslation faultsExternal abort on translationDomain faults Permissions faults.Lock abort (data abort on TLB lock or IC fetch and lock)

Data address alignment checking is enabled by setting bit 1 of the Control Register (CP15, register 1). Alignment faults are still reported when the MMU is disabled. No other MMU exceptions are generated when the MMU is disabled.

Specific information about which abort was generated is reported in the Fault Status Register. In some cases, the target address is also reported in the Fault Address Register. More information on these registers can be found in Section 4.6, CP15 Coprocessor, on page 45.

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System Manager CPU (SM CPU)Features



5 System Manager CPU (SM CPU)

This chapter describes the features of the 88DE3010 SM CPU. The 88DE3010 SM CPU is simpler than the SoC CPU. It does not have I-Cache and D-Cache, runs at much lower frequency, and consumes much less power, yet provides sufficient processing power for system control functions with user friendly C language programming environment.

5.1 Features32-bit and 16-bit RISC architecture1

• Supports 32-bit instruction set for performance and flexibility• Supports 16-bit instruction set for code density• Supports DSP-extended instructions to boost performance for signal processing applications• Supports co-processor instructionsv5TE ARM architectureSupports tightly instruction-coupled-Memory (ITCM) and data-tightly-coupled-memory (DTCM) 6-stage pipeline (IF, ID, IS, EX, MEM, WB)Branch prediction unitConfigurable 4/8-entry AHB write buffer

1. 88DE3010 supports v5TE (32-bit, 16-bit, and enhanced DSP) except for the following instructions (an UNDEFINED is issued):

-- 32-bit: CDP, LDC, MCR (SM CPU supports CP14 & CP15 -- DSP: MCRR, MRRC-- PLD is treated as NOP instruction. --88DE3010 implements Base Restored Abort Model (i.e. if a data abort occurs in an instruction that specifies base register

writeback, the value of the base is unchanged).-- If an R15 is stored to a memory, the value stored is instr_PC + 12 for ARM. For the rest of instructions that use R15 as

operand, the value used is instr_PC + 8 for ARM and instr_PC + 4 for Thumb.

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Figure 16: 88DE3010 Block Diagram

SM CPUCPU Core

ICE Debugger

System Controller

Coprocessor CP-15

WB ITCM DTCMBank 0

DTCMBank 1

AHBi/f for DMAAHB Bus Unit

SM AHB bus SoC AHB bus

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System Manager CPU (SM CPU)Programmer’s Model



5.2 Programmer’s ModelThe programmer’s model for the 88DE3010 CPU consists of the SM CPU programmer’s model with additions made as required to control its operation of the internal co-processors, and any co-processor connected to the external co-processor interface.

There are two Internal co-processors within the 88DE3010 CPU:

CP14 CP15

The CP14 co-processor enables software access to the debug communications channel.

The CP15 co-processor enables the configuration of the Tightly-Coupled Memory (TCM) and write buffer and other system options such as big-endian or little-endian operation.

The registers described in the CP14 and CP15 processors are accessible via MCR and MRC instructions. Any other co-processors connected to the external co-processor interface are accessible with appropriate co-processor instructions.

5.2.1 88DE3010 SM CPU Programmer’s ModelThe 88DE3010 SM CPU processor executes the ARM architecture v5TE, which includes the 32-bit ARM instruction set and the 16-bit Thumb instruction set. For further details on the instruction sets refer to the “ARM Architecture Reference Manual”.

5.2.1.1 Data Abort ModelThe 88DE3010 SM CPU executes the base restored data abort model, that differs from the base updated data abort model implemented by ARM7TDMI.

The difference in the Data Abort does not affect the user code. It affects only a small section of the operating system code called the Data Abort handler.

For the base restored data abort model, the base register is always restored by the processor hardware to the value the register contained before the instruction was executed. The base register is restored when a Data Abort exception occurs during the execution of a memory access instruction. This removes the requirement for the Data Abort handler to unwind any base page register updates that might have been specified by the aborted instruction. This base restored data abort model simplifies the Data Abort handler.

5.2.1.2 88DE3010 SM CPU abort sourcesThe following sources can cause Data Aborts:

Data transactions to the AHB memory space that return an AHB ERROR response (except for buffered writes).Data TCM reads for which the DTCMERROR input is asserted.Instruction TCM data reads for which the ITCMERROR input is asserted.Unaligned data accesses whenever data alignment checking is enabled.

The following sources can cause Prefetch aborts1:

Instruction fetches from the AHB memory space that return an AHB ERROR response.Instruction fetches from the instruction TCM for which the ITCMERROR input is asserted.

1. This is possible if the instruction fetch is carried out.

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5.2.2 88DE3010 SM CPU Memory Map

The 88DE3010 SM CPU combines Instruction and Data TCM memories. This causes high-speed operations without diminishing the performance and power of accessing the system bus. Write buffers are used to separate the 88DE3010 SM CPU from wait states incurred when writing to the AHB bus, and from tightly-coupled memories.

I/O based control interface is provided in addition to the TCM and AHB write buffer by implementing a fixed memory map. Refer to Table 59 for the 88DE3010 SM CPU address map.

5.2.3 Tightly-coupled Memory (TCM) Address SpaceThe TCM is located at the bottom of the memory map. The Instruction TCM (ITCM) and Data TCM (DTCM) are each allotted 64 MB address space, the bottom 64 MB space mapping to ITCM and the next 64 MB range mapping to DTCM.

Each TCM is likely to be smaller than the 64 MB allowable range and the address decode is implemented so that each memory is aliased throughout its 64 MB range.

All access to addresses above the 128 MB combined TCM address space result in AMBA AHB transfers controlled by the Bus Interface Unit (BIU).

An Instruction Fetch (IF) from the 88DE3010 SM CPU to the DTCM address space goes to the AHB, regardless of whether the DTCM is enabled. Both the DTCM and ITCM can be accessed by a data interface access from the 88DE3010 SM CPU. The ability to access the ITCM is also required to enable the fetching of inline literals within code, for programming of the instruction ITCM, and for debugging purposes.

In 88DE3010 SM CPU, the CPU initial vector is 0, i.e., right after reset, the CPU will start to load it's first instruction from address 0x0, which is located in the ITCM.

5.2.4 Bufferable Write Address SpaceThe use of the 88DE3010 AHB write buffer is controlled by both the CP15 control register and the fixed address map.

When the 88DE3010 SM CPU comes out of reset, the write buffer is disabled by default. All data writes to the AHB are performed as unbuffered. The 88DE3010 SM CPU is halted until the BIU has written to the AHB Interface.

When the AHB write buffer is enabled by writing to bit 3 of the CP15 control register, the data address DA[31:0] from the 88DE3010 SM CPU controls whether the AHB write buffer is used. If bit 28 of DA is set, the write is treated as unbuffered. If the bit 28 of DA is clear, the write is treated as a buffered write and the bus write buffer FIFO is used. Buffered writes enable the SM CPU to continue program execution while the write is performed on the AHB. If the write buffer is full, the SM CPU is halted until space becomes available in the FIFO.

Note

Writes to the TCM address space do not get sent to the AHB if the TCM being accessed is enabled. If either TCM is disabled and a write is performed to its address space, the write is performed as a buffered AHB write if the write buffer is enabled. If not, the write is performed as unbuffered.

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System Manager CPU (SM CPU)SM CPU Register Description



5.3 SM CPU Register Description

Table 60 describes CP15 abbreviations

The 88DE3010 CPU incorporates a CP15 processor for system control. Table 61 describes the CP15 Register Summary.

Table 59: Register Map

Register Name Register Address Page Number

ID Code Register R0 page 122

TCM size Register R0 page 122

Control Register R1 page 123

Core control Register R7 page 125

Test and Configuration Register R15 page 126

Table 60: CP15 AbbreviationsTerm Abbreviation Description

Unpredictable UNP Read: Unpredictable data is returned when reading from here. Any value can be assigned to this location.Write: Unpredictable behavior or an unpredictable change in device configuration is caused when writing to this location.

Undefined UND Any instruction that accesses CP15 in the method implied takes the undefined instruction exception.

Should be zero SBZ All bits of the field should be zero when writing to this loca-tion.

Should be one SBO All bits of the field should be one when writing to this loca-tion.

Should be zero or Preserved SBZP All bits of the field should be zero when writing to this loca-tion or preserved by writing the same value that has been previously read from the same field.

Table 61: CP15 Register SummaryRegister Read Write

0 ID Code Unpredictable

0 TCM status Unpredictable

1 Control Control

2-6 Unpredictable Unpredictable

7 Unpredictable Core Control

8-12 Unpredictable Unpredictable

13 Trace Processor Identifier Trace Processor Identifier

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Register 0 and 15 provide access to several registers. The value of the opcode_2 determines the accessed register.

5.3.1 Register 0 - R0

5.3.1.1 ID Code - R0Register R0 is a read only register that accesses an ID code and returns a 32-bit device ID Code. This register reads device ID with the opcode_2 value set to any value other than 2.

The instruction used is as follows:

MRC p15, 0, Rd, c0, c0, {0, 1, 3-7}; --> Returns ID register

Table 62 shows the bit assignments for Register 0.

5.3.1.2 TCM size Register - R0Register R0 is a read only register that accesses a TCM size register and returns the size of the tightly-coupled instruction and data memories attached to the 88DE3010 device. This register reads TCM size with the opcode_2 value set to 2.

The instruction used is as follows:

MRC p15, 0, Rd, c0, c0, 2; --> Returns Tightly coupled memory size register

Table 63 shows the bit assignments for Register 0.

14 Unpredictable Unpredictable

15 Test configuration Test configuration

Table 61: CP15 Register Summary (Continued)Register Read Write

Table 62: ID Code, Register 0

Bits Rst/Value Description

31:24 0x56 Implementor Code for Marvell

23:20 0x1 Specification revision

19:16 0X05 Architecture (ARM v V5TE)

15:4 0x101 Part number

3:0 Revision specific

Silicon revision number

Table 63: TCM size, Register 0


31:23 b000000000 Reserved.

22:18 Data TCM size Introduces the DTCM size

17:15 Reserved b000.

14 Data TCM absent Always 0 in 88DE3010 SM CPU

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5.3.2 Control Register - R1The control register defines all the global control bits of the 88DE3010 device. It is recommended that all reserved bits must be written using read-modify-write sequence. The reserved bits have an unpredictable value when read.

The following instructions are used for reading and writing:

MRC p15, 0, Rd, c1, c0, 0 --> Read control register

MCR p15, 0, Rd, c1, c0, 0--> Write control register

Table 64 shows a Control register format.

13:11 Reserved b000.

10:6 Instruction TCM size

Introduces the ITCM size

5:3 Reserved b000.

2 Instruction TCM absent

Always 0 in 88DE3010 SM CPU

1:0 Reserved b00.

NoteIf TCM size is set to zero, the TCM absent bit is set to 1.

Table 63: TCM size, Register 0 (Continued)


Table 64: Control Register Format

Bits Field Rst Descript ion

31:16 Reserved (should be zero) -- --

15 Configurable disable loading TBIT Zero When HIGH, the ability to change from ARM to Thumb state by loading data to the PC is disabled. This bit is cleared LOW during reset to provide ARMv5TE compatibility.

14 Reserved (should be zero) -- --

13 Alternate vector select Value of VINITHI This bit controls the base address used for the exception vectors. When LOW, the base address for the exception vectors is 0x0000 0000. When HIGH, the base address is 0xFFFF 0000.Bit 13 is LOW by default for 88DE3010 SM CPU. It should not be reprogrammed to HIGH since there is no ITCM at the high vector address.

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12 Instruction TCM enable Value of INITRAM This bit controls the behavior of the tightly-coupled instruction TCM interface. When HIGH, all accesses to the fixed instruction memory space accesses the instruction TCM interface. When LOW, all accesses to the instruction memory space access the AMBA AHB.

Bit 12 is HIGH for 88DE3010 SM CPU. It should not be programmed to HIGH since there is no instruction memory on it's AMBA AHB interface.

11 Branch Prediction enable 1 High = Branch prediction unit (BPU) is enabledLow = Branch prediction unit (BPU) is disabledThe BPU will predict whether the currentbranch instruction will be taken or not.

10:8 Reserved (should be one) -- --

7 Endianness Zero Selects the endian configuration of the 88DE3010 CPU. When this bit is HIGH, big-endian configuration is selected. When LOW, little-endian configuration is selected. This bit is cleared LOW during reset.

For further information on endianness refer to the ARM Architecture Reference Manual.

6:4 Reserved (should be one) -- --

3 BIU write buffer enable Zero This bit controls the use of the write buffer. When HIGH, all stores to the fixedbufferable space of the AMBA AHB are treatedas buffered writes. When LOW, all stores to the AMBA AHB are treated as nonbufferable.If the write buffer is disabled having previously been enabled, any writes already in the write buffer FIFO complete as buffered writes.This bit is cleared LOW during reset.

2 Data TCM enable Value of INITRAM This bit controls the behavior of the tightly-coupled Data TCM interface. When HIGH, all data interface accesses to the fixed data memory space access the Data TCM interface. When LOW, all accesses to the data memory space access the AMBA AHB.

Bit 2 is HIGH by default for 88DE3010 SM CPU.

Table 64: Control Register Format (Continued)


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5.3.3 Core Control Register - R7The Core Control register performs

Wait for interrupt Drain write buffer operation

5.3.3.1 Wait for InterruptThe Wait for Interrupt operation enables the 88DE3010 CPU to enter a low-power standby mode. When the operation is performed, the clock enable to the processor SM CPU is not activated until either an interrupt or a debug request occurs. This function is called by a write to Register 7.

The following instruction is the cause:

MCR p15, 0, Rd, c7, c0, 4 --> Wait for interrupt

New software must use this preferred encoding. For compatibility with existing software, the 88DE3010 device also supports the following instruction that has the same affect:

MCR p15, 0, Rd, c15, c8, 2 --> Wait for interrupt

The Wait for Interrupt halts the processor from the time that the instruction is executed until nFIQ, nIRQ, or EDBGRQ are asserted. Also, if the debugger sets the debug request bit in the EmbeddedICE-RT control register, the wait-for-interrupt condition will end.

In the case of nFIQ and nIRQ, the processor SM CPU is awakened regardless of whether the interrupts are enabled or disabled (that is, independent of the I and F bits in the processor CPSR).

The debug-related waking occurs if DBGEN is HIGH, i.e., only when debug is enabled.

By enabling the 88DE3010 SM CPU, the SM CPU is guaranteed to take the interrupt before performing the instruction after the wait for interrupt. If a debug request is used to wake up the system, the processor enters debug-state before performing any other instructions.

Wait for interrupt does not prevent the write buffer from emptying.

5.3.3.2 Drain Write BufferThe Drain Write Buffer CP15 operation makes the execution instruction stall until the AHB and TCM write buffers are emptied. This operation is useful in real-time applications since the processor must wait for writes to a peripheral component to be completed before program execution continues. An example is where a peripheral component in a bufferable region is the source of an interrupt. When the interrupt has been carried out, the request must be removed before interrupts can be re-enabled. This can be ensured if a drain write buffer operation separates the store to the peripheral component and the enable interrupt functions.

1 Alignment fault check enable Zero This bit controls the generation of data aborts for unaligned data accesses. When HIGH, data accesses to addresses that are not aligned to the transfer size generate a data abort.When LOW, data aborts will not be generated for unaligned accesses.

This bit is cleared LOW at reset.

0 Reserved (should be zero) -- --

Table 64: Control Register Format (Continued)


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The drain write buffer operation is called by a write to Register 7 using the following instruction:

MCR p15, 0, Rd, c7, c10, 4 --> Drain write buffer

5.3.4 Test and Configuration Register - R15This register provides access to:

The Instruction and Data TCM test featuresThe configuration control features

Table 65 shows the register map for test registers.

Note

The Drain Write Buffer stalls the processor SM CPU until any outstanding accesses in the write buffers have been completed, i.e., until all data has been written to memory.

Table 65: Test Register map

Register Read Write

Configuration and control register MRC p15, 1, Rd, c15, c1, 0 MCR p15, 1, Rd, c15, c1, 0

BIST control register (optional) MRC p15, 1, Rd, c15, c1, 1 MCR p15, 1, Rd, c15, c1, 1

Instruction BIST address register (optional) MRC p15, 1, Rd, c15, c1, 2 MCR p15, 1, Rd, c15, c1, 2

Instruction BIST general register (optional) MRC p15, 1, Rd, c15, c1, 3 MCR p15, 1, Rd, c15, c1, 3

Data BIST address register (optional) MRC p15, 1, Rd, c15, c1, 6 MCR p15, 1, Rd, c15, c1, 6

Data BIST general register (optional) MRC p15, 1, Rd, c15, c1, 7 MCR p15, 1, Rd, c15, c1, 7

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5.3.4.1 Configuration Control RegisterThe configuration control register allows modification of the default behavior of the 88DE3010 CPU. Modification of the default behavior might be necessary in situations where the behavior of previous revisions of the 88DE3010 is required, or where particular features are not compatible with a system design.

Table 66 shows the register map of the configuration control register.

Table 66: Configuration Control Register Map

Bits Field Description

31:28 Reserved (should be zero) --

27 Write buffer 4/8 entry This bit configures whether to use a 4 entry or an 8 entry bus write buffer. HIGH = 4 entries of the write buffer are usedLOW = All 8 entries of the write buffer are used

26 Bus Access Order When HIGH, this bit ensures that the write and read accesses over the bus interface are performed in order. This ensures that writes are saved to the bus memory before any subsequent read. The SM CPU is stalled for any bus read access that occurs while the bus write buffer is not empty. If this bit is asserted while data is still in the buffer, any subsequent access to the bus is stalled until the buffer is empty. At reset this bit is set to HIGH.


18 Instruction TCM order When HIGH, this bit ensures that read and write accesses over the Instruction TCM interface are performed in the order generated by the 88DE3010 SM CPU. This ensures that writes are saved to the memory before any subsequent read. The SM CPU is stalled for any TCM read access that occurs while the TCM write buffer is not empty.

If this bit is asserted while data is still in the buffer, any subsequent access to the TCM is stalled until the buffer is empty. At reset this bit is cleared LOW.

17 Data TCM order When HIGH, this bit ensures that read and write accesses over the Data TCM interface are performed in the order generated by the 88DE3010 SM CPU. This ensures that writes are saved to the memory before any subsequent read. The SM CPU is stalled for any TCM read access that occurs while the TCM write buffer is not empty.

If this bit is asserted while data is still in the buffer, any subsequent access to the TCM is stalled until the buffer is empty. At reset this bit is cleared LOW.

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16 AHB instruction prefetch buffer disable When HIGH, this bit disables the AHB instruction prefetch buffer. All instruction accesses to the AHB are carried out as nonsequential transfers as required by the88DE3010 SM CPU. This results in a number of idle cycles between each access.

At reset this bit is cleared to enable instruction prefetching.


Table 66: Configuration Control Register Map (Continued)

Bits Field Description

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Boot ROMROM Code Flow



6 Boot ROMThe 88DE3010 device’s ROM boot flow, the layout of flash image, and secure boot scheme are described below. The related hardware modules are:

DRMDMX engine (Refer to Section 11 for details about the DRMDMX engine)Boot strap SoC CPU0 and CPU1NAND controller

6.1 ROM Code FlowThe 88DE3010 device can boot based on the following three different scenarios depending on boot strap options:

NAND flashThe SoC boots from the 88DE3010 internal ROM, and it loads an encrypted image from NAND flash, upon decryption and security verification, the decrypted image takes control of CPU for the rest of boot up.

SPI-Secure

The SoC boots from the 88DE3010 internal ROM. The ROM code loads an encrypted image from SPI flash, upon decryption and security verification, the decrypted image takes control of CPU for the rest of boot up.

The same ROM code is used for both SPI-Secure and NAND flash boot.

Figure 17 illustrates the ROM boot flow:

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Figure 17: ROM Boot Flow

Reset

Enter SVC modeDisable all Interrupts

Invalidate CachesDisable MMU

Is this SOC_CPU1?SOC_CPU0 halts

Configure D-Cache as 32KB scratch memory

Install Vector Table

CPU-1 halts

1

Install NAND flash driverA

valid Magic Number?

Valid NAND Attributes?

YN

Copy Image-2 from flash to FIGO SRAM up to 12k

(Copy uses NAND driver or from SPI Flash)

bSecure = TRUE?

Call Figo to Verify Image-2

Is Image-2 valid?

H0

H1

N

N

Y

N

N

Y

B

B

Jump to Image-2

Stage_1(iFlashType)

S2

H1

iFlashType = NAND?

Y(N

AND

)

N(SPI)

iBootBlockAddr = 0;

Y

iBootBlockAddr ++;

iBootBlockAddr < 8?

N

Y

This is the NAND flash image failure case. This will happen only at a

probability of 6x10e-11.

iFlashType is indicated by Boot_Src fields in bootStrap register for SOC boot source. NAND: boot from ROM, copy image-2 from NANDSPI:: boot from ROM, copy image-2 from SPI.

1

Halt means waiting for waking up by interrupt under interrupt disabled mode.B

NAND flash driver checks magic number and attributes in block 0.A

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Boot ROMROM Code Flow



After boot up from ROM, the CPU continues the boot flow with Image-2 stored in SPI or NAND flash. Since the boot flow of Image-2 is completely flexible and independent of the 88DE3010 device, it is not covered as part of this data sheet.

During the boot up, ROM code will load Image-2 into DTCM of DRMDMX Figo and will request DRMDMX security engine to process the image. After verification and descrambling by the DRMDMX security engine. SOC_CPU1 will start executing Image-2 from the Figo DTCM. Since ROM code has configured D-Cache as data scratch pad memory, the SOC_CPU1 can run Image-2 without DRAM access.

Because of the limitation of Figo DTCM size (12KB) and scratch pad memory size (32KB), it is highly recommended to have Image-2 only handle basic functions such as the DDR initialization and NAND driver.

The source of the Image-2 (SPI or NAND flash) is determined by boot strap pins. The boot source supported by the 88DE3010 device is shown in Table 67. For more detailed boot strap mapping refer to 88DE3010 Data Sheet Part I: Reset Strapping Interface Section.

Table 67: SOC boot source

Boot UP Boot_src Definit ions

SPI-Secure 00 Boot from ROM, and load image-2 from SPI Flash devices

NAND 01 Boot from ROM, and load image-2 from NAND Flash devices

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6.2 Flash LayoutWhen ROM code loads Image-2 from different sources, the Image-2 have different layouts.

6.2.1 NAND flash Layout The ROM code requirement for the NAND flash layout is shown in Figure 18.

Figure 18: NAND flash layout for 88DE3010

Bloc

k 0

Magic Number ( 4 bytes) NAND flash attribute ( 4 bytes)

Reserved

Bloc

k9

-72

Bloc

k13

7-8

191

JFFS / YAFFS

Bloc

k73

-136

Stores an Image- 3 with a different version number

Bloc

k 2-

8

Each block stores one copy of Block 1

Image-3

32 copies of the first 12 bytes

ECC Attributes ( 4 bytes)

Reserved

Image-2

Bloc

k 1

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Boot ROMFlash Layout



Block 0 will only store the Magic number, flash parameters, and ECC attributes, the same data has 33 copies in the 1st page of Block 0. The flash parameters and ECC attributes are used to configure NAND flash driver inside the ROM code to read Image-2.

During the read of the NAND attribute data structure, the 88DE3010 boot ROM will assume the number of error bits in the 1st page of Block 0 will not exceed 16. The ROM code will use all the supported configurations to scan all the 33 copies in the 1st page of Block 0 to find the magic number. If in certain configuration, the ROM code finds more than 17 identical copies of attribute data structure, this attribute will be used to read Image-2. Otherwise, the NAND boot is considered as failed and the 88DE3010 device will go to the halt state. Table 68 shows all supported configurations.

After Block 0 checking is completed, the ROM code will start to load Image-2 from Block 1 to Block 8 (they store 8 identical copies of Image-2). The ROM code will copy Image-2 into DRMDMX Figo DCTM for integrity check. If the integrity check failed on one image, the ROM code will continue to read the next Block. If all 8 images failed integrity check, the 88DE3010 will go to the halt state. Using 8 identical Image-2 copies ensures NAND flash bit failure rate will not affect 88DE3010 boot up.

Image-3 and JFFS/YAFFS is shown as an example of the NAND layout. The 88DE3010 ROM boot code does not have any restrictions on these sections.

Table 68: Supported NAND Flash Configurations

Page Size Address Cycle 4

Address Cycle 5

Address Cycle 6

Address Cycle 7

512 Byte yes yes yes yes

2 k Byte yes yes yes yes

4 KByte yes yes yes yes

8 k Byte yes yes yes yes

Table 69: NAND flash attributes table

Address Value Description

0x00 0xF1 Magic Number for self adaptive NAND device recognition

0x01 0xA3

0x02 0xAD

0x03 0xD2

0x04 0/1/2/3 Page sizeThe value of page size is defined as follows - 0 = 512 bytes, 1 = 2048 bytes, 2 = 4096 bytes, 3 = 8192 bytes

0x05 4/5/6/7 Number of address cycleThe value of number of address cycle is defined as follows - 4: 4 cycles, 5: 5 cycles, 6: 6 cycles, 7: 7 cycles

0x06 0x00-0xFF Bit [7:0] of Block size (in number of KBytes)

0x07 Bit [15:8] of Block size (in number of KBytes)

0x08 0/1 ECC enable (Using for reading Image-2.) 0 = ECC is disabled1 = ECC is enabled

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6.2.2 SPI Flash layout for SPI-Secure BootThe image layout for SPI Flash boot mode is defined in following diagram:

Figure 19: SPI flash layout for SPI-Secure boot

0x09 0/1 ECC algorithm (Using for reading Image-2.)This byte is valid when ECC is enabled. It indicates which ECC algorithm is used

0 = Hamming ECC1 = BCH

0x0a 0/1 Spare area enable (Using for reading Image-2)This byte indicates whether spare area is enabled or disabled.0 = SPARE_EN = FALSE1 = SPARE_EN = TRUE

0x0b Reserve Reserve

Table 69: NAND flash attributes table

Address Value Description

Image-2

12K

B

0xF000-0000

Designed by application

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Boot ROMFormat of Image 2



6.3 Format of Image 2 Image 2 is stored at Block 0 for SPI-Secure and Block 1 to Block 8 for NAND boot. The size of Image 2 is limited to 12 Kbytes due to the size limitation of DRMDMX Figo DTCM.

Although not a requirement, the Image 2 is recommended to perform the following functions:

Device specific NAND driver to maximize boot performanceNAND bad block handling capabilityDRAM sub-system initialization

The 88DE3010 device ROM boot code requires that Image-2 always be signed to assure its integrity. It supports two signature algorithms: CMAC and RSA-PSS. If the signature in the image does not match with the signature calculated by the DRMDMX Figo, SoC CPU1 will terminate the boot process and enter halt state.

For CMAC signature, Image 2 has two areas:

Header, including signature of Image-2 (Byte 72-95 in Figure 20)Encrypted and Signed Code/Data Area

Figure 20: Image 2 Layout when using CMAC

When RSA-PSS is used for signature, the Image-2 has three areas:

128 bytes Header128 bytes SignatureEncrypted & signed Code/Data Area.

Figure 21: Image 2 Layout When Using RSA-PSS

Image - 2 Code/ Data( 12 KByte – 128Byte)

Header ( 128 byte)

Header ( 128 byte)

Image-2 Code/Data( 12KByte – 256Byte)

RSA SigHeader ( 128 byte) If RSA-PSS is set in Header

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Table 70 shows the format of the Image 2 Header.

While image data may be encrypted, the Image-2 header is required to be in clear text.

Table 70: Format of Image 2 Header

Byte Description

0 Root Key ID0x00 and 0xFF = Image body is original and not encrypted Other values = Specific Key ID, RKEK: 0x1, SIGNK: 0x2, AESK = 0x3, ROM KEY: 0x10~0x7f, USER KEY: 0x80~0xfe

2-7 Reserved AreaPadding data for 64 bits alignment

8-63 Encrypted Sub Key dataEncryption Sub Key is used to decrypt the image context and it is encrypted through Parent Key indicated by Root Key ID

64 Signature Key IDSpecific Key ID, RKEK = 0x1, SIGNK: 0x2, AESK:0x3, ROM KEY = 0x10~0x7f, USER KEY: 0x80~0xfe

65-67 Reserved AreaPadding data for 32 bit alignment

68 Signature type0x00 = CMAC 0x02 = RSA-PSS

69 Signature LengthCMAC =16 bytesRSA-PSS =128 bytes

70-71 Reserved AreaPadding data for 64 bits alignment

72-95 Digest ValueCMAC = The signature of the image 2RSA-PSS = The digest of the image 2

96-111 Bind InfoPlatform binding information which indicates what type of underlying hardware is needed to run this firmware.

112-123 Reserved AreaPadding data for fixed image 2 header size

124-127 The length of the image 2 Code/Data area.

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JTAGJTAG debug port configurations



7 JTAGThe 88DE3010 implemented a standard IEEE 1149.1 compliant JTAG interface to support ICE (In-Circuit Emulation) based debugging for the SM_CPU, SOC_CPU0, SOC_CPU1, and the Audio DSP. In addition, this JTAG interface can also support boundary scan (BSCAN) TAP controller. The boundary scan ID code for 88DE3010 is 0x03010B11 (Revision ID = 0; Part Number = 0x3010; Manufacture ID = 0x588 for Marvell).

7.1 JTAG debug port configurationsFigure 22 shows the 88DE3010 JTAG chain connection for both debugger and BSCAN mode.

Figure 22: 88DE3010 JTAG Chain and Boundary Scan Diagram

The 88DE3010 device has two JTAG based debug ports to support two power domains debugging, one on SOC power domain (SOC_TDI, SOC_TCK, SOC_TMS, SOC_TRSTn, and SOC_TDO), and one on SM power domain (SM_TDI, SM_TCK, SM_TMS, SM_TRSTn, and SM_TDO). To support multiple power domains debug, When SOC is power off, only SM_CPU chain can be accessed, e.g. SM_JTAG_SEL[1:0] must be set to 2’b01 as shown in Table 71. For details of power domain, refer to System Manager.Section. Table 71 shows the different configurations of debug ports in the 88DE3010 device.

System Manager Power Domain

SOC Power Domain

BCELLS

SM_TDI

SM CPU TAP

BCELLS BCELLS

CPU0 TAP CPU1 TAP

SM_TCK

BSCAN TAP

SM_TDO

SM_TRSTn

SM_TMSConnects to

all TAP controllers

SM_JTAG_SEL[0]

SM_JTAG_SEL[1]

bscan_sel

ice_sm_sel

SOC_TDI

SOC_TCK

SOC_TRSTn

SOC_TMS

SEL_SOC_JTAGBSP

PIN MUX

SOC_TDO

bscan_sel

BIST

Audio DSP TAP

ZSP_EN & SOC_TDO_OEN

0

1

1

0

1

0

1

0

CPU1_EN

1

0

1

0

1

0

DSP_EN & SOC_TDO_OEN

1

2

3

DRMDMXSecure Processor

CP

U0_

EN

CP

U1_

EN

DSP

_EN

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The JTAG debugger accessibility on 88DE3010 devices are controlled by the Figo RISC processor in DRMDMX sub-system. The debug access to SM CPU is always enabled, while the debug access to SOC_CPU0, SOC_CPU1, and Audio DSP are all disabled after reset.

If the associated OTP status allows debugging access, then a special Marvell authenticated security processor firmware can be downloaded to enable the JTAG access for SOC_CPU0 or SOC_CPU1, or Audio DSP. If the associated OTP status is programmed to disable the debugging access, then only SM_CPU can be accessed through SM JTAG port; SOC_CPU0, SOC_CPU1, and Audio DSP JTAG access will be always disabled.

When multiple devices are chained in one port, to enable a device in the chain, all the previous device(s) must be enabled. For example, to access Audio DSP through SM JTAG port, all SM_CPU, SOC_CPU0, and SOC_CPU1 must be enabled. To access SOC_CPU1 through SM JTAG port, SM_CPU and SOC_CPU0 must be enabled.

7.2 Boundary scan supportThe 88DE3010 supports IEEE 1149.1 compliant boundary scan (BSCAN) interface. Below is a list of instructions supported.

Table 71: 88DE3010 Debug Port Configurations

SM_JTAG_SEL SocJtagFromSM BSP

Software_strap[6] Boot Strap Pin

SOC JTAG Chain Device Sequence

SM JTAG Chain Device Sequence

2'b00 1'b1 0 Audio DSP only SM_CPU -> SOC_CPU0 -> SOC_CPU1

2'b00 1'b1 1 Not used SM_CPU -> SOC_CPU0 -> SOC_CPU1 -> Audio DSP

2'b01 1'b1 0 or 1 Not used SM_CPU

2'b01 1'b0 0 Audio DSP SM_CPU

2'b01 1'b0 1 SOC_CPU0-> SOC_CPU1

SM_CPU

2'b10 1'b1 0 or 1 Not used Boundary SCAN

All others Reserved Reserved

Table 72: Boundary Scan Instructions

Instruction Code

BYPASS 5’b11111

EXTEST 5’b00000

SAMPLE/PRELOAD 5’b00101

IDCODE 5’b00110

HIGHZ 5’b00100

CLAMP 5’b00011

Reserved All others

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SoC Connectivity and Access Control



8 SoC Connectivity and Access ControlThe main function of SOC subsystem is to link CPU and hardware engines with various slaves, including DRAM, PCIe, memory mapped external Flash device and internal configuration bus. The destination of each transaction is decided solely on the transaction address. The 88DE3010 SoC sub-system handles 32-bit address space. There are four slaves that are shared among the bus masters such as hardware DMA engines and CPUs. Simultaneous access to the same slave from different masters are arbitrated and sent to the addressed slave in sequence. Access to different slaves are independent and can be served concurrently. In addition to address-based routing, the SOC subsystem is also capable of protecting sensitive data content by rejecting un-trusted transactions to DDR SDRAM or register spaces, including low-speed and fast-access registers.

Figure 23 shows the bus masters and slaves in the 88DE3010 device.

Figure 23: SoC Subsystem

SoC Subsystem

Low-speed Device

Registers

Fast-Access Device

Registers

External SDRAM

PCIe Slave

Appl

icat

ion

CP

U

AV C

PU

AV D

MA

Gra

phic

s

VM

eta

DR

M/D

MX

Perif

DM

A

Audi

o D

SP

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8.1 Connection TableThere are four transaction target regions in the 88DE3010 device:

DDR SDRAM memory• System memoryPCI-Express interface• PCI-Express master port connecting to off-chip PCI-Express devices.Low-speed registers• Normal device registers running at 100MHzFast-access registers • Latency-sensitive device registers running at system clock frequency (400 MHz)

Possible masters for these four targets are:

Application CPU• SoC CPU running application softwareAV CPU• SoC CPU running audio/video decoding related softwareAV DMA• Direct-Memory Access engine fetching display video and audio outputs data.Peripheral DMAs and low-speed PIO DMA engine• Direct Memory Access engines for storing received data or loading transmitted data through

various interfaces including SATA, USB, Ethernet, NAND flash, SDIO and PCI-Express slave.

VMeta™ decoder• Video decoderAudio DSP• Audio decoding and post processingDRM/DMX Engine• Storing source streams or accessing encrypted/decrypted data.Graphic Engine• storing or fetching graphic data

Table 73 shows the connection levels of various master and slave pairs. “Full” means the master can access full range of target slave without constraint. “Controlled” means the master’s accessing to the slave may be limited based on secure-access control setting. “No Access” means there is no logical connection for the master/slave pair.

Table 73: Master and Slave Pair Connection Levels

Masters DDR SDRAM PCI-Express Port

Fast-Access Registers

Low-Speed RegistersSlaves

Application CPU Controlled Full Controlled Controlled

AV CPU Full Full Full Full

AV DMA engine Full Full No Access No Access

Perif DMA Controlled No Access Controlled Controlled

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SoC Connectivity and Access ControlConnection Table



8.1.1 Address Map

VMeta™ Decoder

Full Full No Access No Access

DRM/DMX Full Full Full Full

Graphic Engine Full Full No Access No Access

Audio DSP Full No Access No Access No Access

Table 73: Master and Slave Pair Connection Levels (Continued)

Masters DDR SDRAM PCI-Express Port

Fast-Access Registers

Low-Speed RegistersSlaves

Table 74: System Memory Map

Address Range in Hexidecimal Address Space Size

DDR SDRAM Memory (Cacheable)

0x0000_0000 ~ 0x3FFF_FFFF 1 GByte

DDR SDRAM Memory (Uncacheable)

0x4000_0000 ~ 0x7FFF_FFFF 1 GByte

PCIe Device memory 0x8000_0000 ~ 0x9FFF_FFFF 512 MByte

Reserved 0xA000_0000 ~ 0xEFFF_FFFF -

SPI Flash 0xF000_0000 ~ 0xF3FF_FFFF 64 MByte

Reserved 0xF400_0000 ~ 0xF7BB_FFFF -

Register Space 0xF7BC_0000 ~ 0xFF7F_FFFF 130 MByte

Low ROM 0xFF80_0000 ~ 0xFF80_FFFF 64 KByte

Reserved 0xFF81_0000 ~ 0xFFFE_FFFF -

Boot vectors 0xFFFF_0000 ~ 0xFFFF_FFFF 64 KByte

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Table 75: Register Space Memory Map


Low-speed Registers 0xF7BC_0000 ~ 0xF7FF_FFFF 32 MByte

Fast-Access Registers & ROM

0xF800_0000 ~ 0xFFFF_FFFF 128 MByte

Table 76: Low-speed Register Memory Map


SPI Flash 0xF000_0000 ~ 0xF3FF_FFFF 64 MByte

SOC Registers 0xF7CA_0000 ~ 0xF7CA_FFFF 64 KByte

DDR Controller 0xF7CB_0000 ~ 0xF7CB_FFFF 64 KByte

TSI Registers 0xF7CC_0000 ~ 0xF7CF_FFFF 256 KByte

AG_DHub Registers 0xF7D0_0000 ~ 0xF7D2_FFFF 128 KByte

APP Registers 0xF7D3_0000 ~ 0xF7D3_FFFF 64 KByte

SPU Registers 0xF7D4_0000 ~ 0xF7D4_FFFF 64 Kbyte

SDIO Registers 0xF7D5_0000 ~ 0xF7D5_FFFF 64 KByte

PTP Registers 0xF7D6_0000 ~ 0xF7D6_FFFF 64 KByte

pBridge Registers 0xF7D7_0000 ~ 0xF7D7_FFFF 64 KByte

SxBar Registers 0xF7D8_0000 ~ 0xF7D8_FFFF 64 KByte

MxBar Registers 0xF7D9_0000 ~ 0xF7D9_FFFF 64 KByte

NxBar Registers 0xF7DA_0000 ~ 0xF7DA_FFFF 64 KByte

VOP PG Register 0xF7DB_0000 ~ 0xF7DB_FFFF 64 KByte

VOP Mixer Registers 0xF7DD_0000 ~ 0xF7DD_FFFF 64 KByte

Main Video Registers 0xF7DE_0000 ~ 0xF7DE_FFFF 64 KByte

VOP PIP Registers 0xF7DF_0000 ~ 0xF7DF_FFFF 64 KByte

VOP OSD Registers 0xF7E0_0000 ~ 0xF7E0_FFFF 64 KByte

Audio DSP Registers 0xF7E1_0000 ~ 0xF7E1_FFFF 64 KByte

PCI-Express Registers 0xF7E4_0000 ~ 0xF7E4_FFFF 64 KByte

Ethernet Registers 0xF7E5_0000 ~ 0xF7E5_FFFF 64 KByte

SPDIF Registers 0xF7E6_0000 ~ 0xF7E6_FFFF 64 KByte

I2S Registers 0xF7E7_0000 ~ 0xF7E7_FFFF 64 KByte

APB Perif Registers 0xF7E8_0000 ~ 0xF7E8_FFFF 64 KByte

SATA Registers 0xF7E9_0000 ~ 0xF7E9_FFFF 64 KByte

Chip Control Registers 0xF7EA_0000 ~ 0xF7EA_FFFF 64 KByte

AVIO Semaphore Reg 0xF7EC_0000 ~ 0xF7EC_FFFF 64 KByte

USB0 Registers 0xF7ED_0000 ~ 0xF7ED_FFFF 64 KByte

USB1 Registers 0xF7EE_0000 ~ 0xF7EE_FFFF 64 KByte

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Graphics Registers 0xF7EF_0000 ~ 0xF7EF_FFFF 64 KByte

NAND Flash Registers 0xF7F0_0000 ~ 0xF7F0_FFFF 64 KByte

LBC Registers 0xF7F1_0000 ~ 0xF7F1_FFFF 64 KByte

Pulse Width Modulator 0xF7F2_0000 ~ 0xF7F2_FFFF 64 KByte

VPP Registers 0xF7F3_0000 ~ 0xF7F3_FFFF 64 KByte

VPP DHub Registers 0xF7F4_0000 ~ 0xF7F5_FFFF 128 KByte

System Manager Reg 0xF7F8_0000 ~ 0xF7FF_FFFF 512 KByte

Table 77: Fast-Access Register Memory Map


VMeta™ 0xF800_0000 ~ 0xF841_FFFF 4224 Kbyte

PIC Controller 0xF842_0000 ~ 0xFB42_FFFF 64 Kbyte

ROM 0xFF80_0000 ~ 0xFF80_FFFF 64 Kbyte

Boot-Vector 0xFFFF_0000 ~ 0xFFFF_FFFF 64 Kbyte

Table 76: Low-speed Register Memory Map (Continued)


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8.1.2 Secure Access ControlIn order to maintain system integrity and protect important data, SOC sub-system has built-in secure-access designed to limit the data and register access from un-secure masters. There are three protected slaves: DDR system memory, low-speed registers and fast-access registers. Portions of address regions in these protected slaves can be specified as protected regions and accessing these regions from un-secure masters are prohibited. Programmable registers are used to define the starting address and the size of protected regions. If an access transaction is ever issued from an un-secure master that hits any of the protected regions, an error bus response will be returned by SOC subsystem back to the initiator.

8.1.2.1 Un-secure and Secure MastersThe un-secure masters in the system are

Application CPUPeripheral DMA

All other masters are defined as secure masters with no security control. Transactions from Application CPU and Peripheral DMA are deemed non-secured because the software running on Application CPU and commands issued to Peripheral DMA may come from un-trusted sources. The designated tasks for these two hardware engines should not involve accessing the protected regions. Therefore, rejecting or blocking transactions from them to the protected slaves will not affect their normal functionalities. One the other hand, software running on AV CPU and drivers of the secure hardware engines like DRM/DMX, VMeta™ decoder, Graphic Engine, and AV DMA are developed by fully trusted sources and all the transactions from those modules are treated as secure with no accessing control.

8.1.2.2 Programming of Secure-Access ControlThe secure-access in SOC subsystem is implemented by sets of control registers. AV CPU and DRM/DMX are the only two masters that can change access to the control settings.

Immediately after system reset, the secure-access control logic is turned off and slaves are opened to all masters. The system has to go through the boot-up sequence first with AV CPU and DRMDMX. At this moment, the Application CPU and most hardware engines are in sleep or idle states. Only AV CPU and DRM/DMX modules are active, checking and preparing the system for target applications. All transactions happening during this time frame are secured therefore no access control is needed. After executing necessary tasks, AV CPU will specify protection regions and turn on access control before enabling Application CPU and Peripheral DMA. The whole procedure should guarantee the security of data in the system.

8.1.2.3 Register Setting of Access ControlSOC subsystem provides the following six register sets to secure parts of DDR memory and register spaces:

Application CPU Read to DDR memory access-control setApplication CPU Write to DDR memory access-control setPeripheral DMA Read to DDR memory access-control setPeripheral DMA Write to DDR memory access-control setApplication CPU or Peripheral DMA Read/Write to low-speed registers access- control setApplication CPU or Peripheral DMA Read/Write to fast-access registers access-control set

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Each register set is composed of 8 independent access control registers. Each access control register specifies a protected region with a starting address, and a window. The starting address must be window size aligned. The window size supported are: 64 KB, 128 KB,256 KB, 512 KB, 1 MB, 2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB, and 512 MB.

An enabled secure-control register turns on hardware address comparison to check transaction addresses. Any match of the 8 independent comparisons will trigger the access-control logics to reject and block the access. For software programming convenience, the protected regions in an access-control register set can be overlapping.

Specific engine behavior after rejecting or blocking an access depends on the error recovery mechanism available at the bus master. For Application CPU, it will trigger instruction (if the transaction type is instruction fetch) or data (if the transaction type is data access) abort exception. For Peripheral DMA, an error bus response will be returned to external host devices if it is defined in the interface protocol. For the masters not capable of error handling, a dummy read or a dummy write response is returned for the transaction.

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9 DDR SDRAM Memory ControllerThe DDR SDRAM controller in 88DE3010 supports the following features

JEDEC-compatible DDR2/DDR3 interfacesIndependent dual-channel or single channel interface16- or 32-bit data bus width for each channelProvides 14 bit DDR address bits and 3 bit bank address, supporting up to four 2 Gbit x16 DDR2/DDR3 devices. Up to 400 MHz (800 Mbit per pin data rate) operationSelf-refresh for power-saving modeAsymmetric addressing mode in dual-channel configurationFixed burst length of 8Compatible with both 4 bank or 8 bank DRAM devicesConfigurable timing parameters to operate at different memory frequencies and device speed gradesOn-Die Termination (ODT) control to improve signal integrityProgrammable Posted CAS additive latency for optimal command bus efficiencyByte masks are supported for write transactions8 burst (32Byte) write data collection buffer for each channel with read coherency checkBank status aware arbitration to maximize data bus utilizationFlexible arbitration scheme based on 3-level round-robin algorithm with starving prevention

9.1 Interface Configuration OptionsIn order to provide maximal flexibility for memory demands of various applications, the DDR controller supports the following memory interface configurations:

Table 78: Memory Interface Configurations

Device Type Configuration Option(Depth x Width x number of parts)

Total Size

Symmetric Address Mode

512 Mb DDR2/3 Single Channel 32-bit Data Width 64 Mb x 8 x 4 256M Byte

32 Mb x16x 2 128M Byte

Dual Channel 32-bit Data Width 64 Mb x 8 x 8 512M Byte


Dual Channel 16-bit Data Width 64 Mb x 8 x 4 256M Byte


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DDR SDRAM Memory ControllerAddressing Decoding



The dual-channel mode provides two independent memory channels. Transaction requests issued to the DDR controller will be dispatched based on their address. Transactions to different memory channels are concurrent therefore if two masters are requesting accesses to two different channels, they will be served simultaneously. Between the two channels, properties such as data-bus width, memory type (DDR2 or DDR3), CAS latency, timing parameters etc., have to be the same. However, number of column address bits, the number of row address bit and number of banks configurations for the two channels can be programmed differently in asymmetrical addressing mode.

9.2 Addressing DecodingThe 88DE3010 device uses 32-bit internal addresses with 4 GB address space, out of which address 0 to 1 GB are mapped to DRAM as cacheable space, and 1-2 GB are mapped to DRAM as non-cacheable space. Total supported physical DRAM size is 1 GB. The address decoding from internal address (logical address) to the device address (physical address) is done in the DRAM controller, determined by DRAM size parameter settings such as the number of column address bits, the number of row address bits and bank mode etc. For desired memory mapping, these parameters should not be programmed to exceed the actual device capabilities. For example, with 4-bank devices, the controller parameters cannot be set to an 8-bit bank. The address decoding models supported by 88DE3010 device are:

Dual-Channel or Single-Channel Mode: There is one effective memory channel (Single-Channel Mode) or two memory channel (dual-Channel Mode) available.Normal Bank or Bank-Rolling Mode: Bank address is above column address (Normal Bank Mode) or above 128 Byte boundary (Bank-Rolling Mode).Symmetric or Asymmetric Addressing Mode: Same effective memory size (Symmetric Addressing Mode) or different effective memory sizes (Asymmetric Addressing Mode).

The exact address decoding in various modes are illustrated as following example with 16-bit 1 Gbit DDR2 chip, which has 3-bit Bank address (BA), 13-bit Row address (RA), and 10-bit Column address (CA).

1 Gb DDR2/3 Single Channel 32-bit Data Width 128 Mb x 8 x 4 512 MByte

64 Mb x16x 2 256 MByte

Dual Channel 32-bit Data Width 128 Mb x 8 x 8 1 GByte

64 Mb x16x 4 512 MByte

Dual Channel 16-bit Data Width 128 Mb x 8 x 4 512 MByte

64 Mb x16 x 2 256 MByte

2 Gb DDR2/3 Single Channel 32-bit Data Width 128 Mb x16x 2 512 MByte

Dual Channel 32-bit Data Width 128 Mb x16x 4 1 GByte

Dual Channel 16-bit Data Width 128 Mb x16x2 512 MByte

Asymmetric Address Mode

1 Gb + 512 MbDDR2/3

Dual Channel 32-bit Data Width 64 Mb x16x 232 Mb x16x 2

384 MByte

Table 78: Memory Interface Configurations (Continued)

Device Type Configuration Option(Depth x Width x number of parts)

Total Size

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9.2.1 Single Channel, normal bank modeIn this mode, 2 16-bit DDR2 devices are controlled by same Chip Select (CS) to provide 32-bit data width. Total memory size is 256 MB, total data pin transfer rate is 25.6 Gbps. Depending on the application, actual available DRAM bandwidth will be 50% to 80% of the total pin transfer rate.

9.2.2 Dual channel, normal bank, symmetric address modeIn this mode, each of the two independent channels have 2 16-bit DDR2 1 Gbit devices activated by the same CS to provide 32-bit data width. Total memory size is 512 MB, total data pin transfer rate is 51.2 Gbps

9.2.3 Single channel, bank rolling modeIn this mode, 2 16-bit 1 Gbit DDR2 devices are activated by the same CS to provide 32-bit data width. Total memory size is 256 MB, total data pin transfer rate is 25.6 Gbps.

Table 79: Single Channel, normal bank mode

Internal address DRAM Address

A[27:15] RA[12:0]

A[14:12] BA[2:0]

A[11:7] CA[9:5]

A[6:2] CA[4:0]

Table 80: Dual Channel, normal bank, symmetric address mode


A[28:16] RA[12:0]

A[15:13] BA[2:0]

A[12] Channel[0:0]

A[11:7] CA[9:5]

A[6:2] CA[4:0]

Table 81: Single channel, bank rolling mode


A[27:15] RA[12:0]

A[14:10] CA[9:5]

A[9:7] BA[2:0]

A[6:2] CA[4:0]

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DDR SDRAM Memory ControllerAddressing Decoding



9.2.4 Dual channel, bank rolling, symmetric address modeIn this mode, each of the two independent channels has 2 16-bit DDR2 1 Gbit devices activated by the same CS to provide 32-bit data width. Total memory size is 512 MB, total data pin transfer rate is 51.2 Gbps

9.2.5 Dual channel, bank rolling, asymmetric address modeIn this mode, one channel has 2 1 Gbit 16-bit DDR2 devices, and the other channel has 2 512 Mbit 16-bit DDR2 devices. Total memory size is 384 MB, from 0 – 256 MB, total data pin transfer rate is 51.2 Gbps, from 256 MB to 384 MB, total data pin transfer rate is 25.6 Gbps.

Table 82: Dual Channel, bank rolling, symmetric address mode


A[28:16] RA[12:0]

A[15:13] CA[9:7]

A[12] Channel[0:0]

A[11:10] CA[6:5]

A[9:7] BA[2:0]

A[6:2] CA[4:0]

Table 83: Dual Channel, bank rolling, asymmetric address modeFrom 0 - 256 MB (A[28] = 0)


A[28]=0 RA[12]

A[27:16] RA[11:0]

A[15:13] CA[9:7]

A[12] Channel[0:0]

A[11:10] CA[6:5]

A[9:7] BA[2:0]

A[6:2] CA[4:0]

Table 84: When A[28] = 1, A[27] = 0From 256 MB- 384 MB


A[28] = 1 RA[12]

A[26:15] RA[11:0]

A[14:10] CA[9:5]

A[9:7] BA[2:0]

A[6:2] CA[4:0]

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9.2.6 Dual channel, normal bank, asymmetric address modeIn this mode, one channel has 2 1 Gbit 16-bit DDR2 device, and the other channel has 2 512-Mbit 16-bit DDR2 devices. Total memory size is 384 MB, from 0 – 256 MB, total data pin transfer rate is 51.2 Gbps, from 256 MB to 384 MB, total data pin transfer rate is 25.6 Gbps.

Table 85: Dual Channel, normal bank, asymmetric address modeFrom 0 – 256 MB (when A[28:27]=00 or 01)

Internal address DRAM Address 512-Mbit Device

DRAM Address 1Gbit Device

A[28]=0 N/A RA[12]=0

A[27:16] RA[11:0] RA[11:0]

A[15:13] BA[2:0] BA[2:0]

A[12] Channel[0:0] Channel[0:0]

A[11:8] CA[9:6] CA[9:6]

A[7:2] CA[5:0] CA[5:0]

Table 86: Dual Channel, normal bank, asymmetric address modeFrom 256 MB to 384 MB (when A[28:27]=10)

Internal address DRAM Address 512 Mbit Device

DRAM Address 1Gbit Device

A[28] N/A RA[12]=1

A[26:15] N/A RA[11:0]

A[14:12] N/A BA[2:0]

A[11:8] N/A CA[9:6]

A[7:2] N/A CA[5:0]

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DDR SDRAM Memory ControllerSupported DDR Features



9.3 Supported DDR FeaturesThe DDR Memory Controller supports most of the features defined in the JEDEC DDR2 SDRAM Specification and DDR3 SDRAM Specification. Notably, the following features are supported:

CAS latency 3 to 7 clock cycles for DDR2 and 5 to 11 clock cycles for DDR3Additive posted CAS latency 2 to 6 cycles for DDR2 and CAS latency -1 or CAS -2 for DDR3Auto-prechargeProgrammable On-Die TerminationPosted Auto-RefreshSelf-Refresh for power-savingOnly one chip-select pin is available per memory channelBurst length is always set to 8, any other burst lengths are not supportedOnly sequential addressing burst mode is supportedOff-Chip Driver (OCD) calibration is not supportedFor power-saving, only Self-Refresh mode is supported.For DDR3, write-leveling is not supported.

9.4 Write CollectionThe characteristics of the DDR SDRAM internal pipeline requires extra switch delays for a READ command after a WRITE command. This delay introduces additional idle cycles and decreases the utilization on the DDR bus when there are multiple high bandwidth masters reading or writing DDR data. To minimize this impact, the 88DE3010 memory controller has an internal write buffer that collects up to 8 32-Byte write bursts. Any write transaction issued to the controller is firstly buffered in the write collection buffer. When the Write Buffer is full or when a read transaction address collision is detected against any of the buffered write requests, the DRAM controller will flush all the write requests to external DDR memory before any READ command is issued. This way coherency among write transactions in the buffer and subsequent read transactions is guaranteed by the memory controller.

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9.5 DRAM Controller ArbitrationFigure 24 illustrates the arbitration among all the masters in DRAM controller.

Figure 24: DRAM Controller Block Diagram

The DRAM read and write requests from all the masters are mapped either to channel 0 or channel 1 controller depending on their address.

All the write requests are arbitrated directly and their write data is collected in the write data buffer. After the arbitration, the collected write requests will participate in arbitration with all the read requests, in this stage, the arbitration is done based on the properties of the requests and DRAM bank status.

The scheme of write arbitration is a two level round robin - priority level and best effort level. The arbitration will serve the requests from the priority level first, and when idle cycles are available, the requests from best effort level are served. Table 87 shows all the masters with write requests.

Mas

ter i

nter

face

s

DRAM Controller 0

Write DataBuffer

Other H/WRead Interfaces

High BandwidthRead Interfaces

Real time (QoS)Read Interfaces

Write Arbitration

CPU0 Read

CPU1 Read

RequestArbitration

DDR Command & Scheduling

Queue

BankStatus

ReadData Path

DDR2/3 PHY

DRAM Controller 1

channel0

channel1

PERIF write requestAVIO0 write requestAVIO1 write requestGraphics write requestVMeta write request

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DDR SDRAM Memory ControllerDRAM Controller Arbitration



The output of the first write arbiter joins the arbitration with write requests from CPU0 and CPU1. Figure 25 illustrates the write request arbitration scheme.

Figure 25: Write Arbitration Diagram

After write arbitration and collection, the DRAM write requests join all the read requests for further arbitration. This arbitration is based on a three level round robin arbiter. Figure 26 illustrates the arbitration mechanism.

Table 87: Masters with write requests

Write Master Arbitrat ion level Operat ions

AVIO PRIORITY 3D VNR / De-interlacer, Down scaler write back

VMeta™ PRIORITY Decoded video frames

Peripheral and audio DSP Best effort Received data from SATA, USB, SDIO, Ethernet,.etc

Graphics Engine Best effort Compose graphics buffers

CPU0 Round robin S/W data access

CPU1 Round robin S/W data access

VMeta (QoS)

PriorityRoundRobinArbiterLevel1

RoundRobinArbiterLevel2

ArbitrationoutputCPU0 write

CPU1 write

Graphics Engine

Peripherals

AVIO (QoS)

Write Collection

buffer

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Figure 26: Arbitration Mechanism

The 88DE3010 DRAM controller arbitration is based on three cascaded round-robin arbiters. The Request Priority Selection Matrix will map the requests to arbiter inputs on different levels. The arbitration result of the lower level inputs will be sent to the high level arbiter. There it will be arbitrated with the other requests. The behavior of the arbitration engine is controlled by the Priority Level register in DRAM controller.

The factors that will determine the mapping are:

Register settings: S/W can force the mapping of a selected request source onto a desired arbiter levelBank status: when not overwritten by the S/W, the request source with favorable bank status will be raised by one arbitration levelQoS property: when not overwritten by S/W, the request source with QoS property flag raised (only applies to AVIO and VMeta™ masters) will be raised by one arbitration level. When a request with QoS also has favorable bank status, it will be raised by two arbitration levels.When the arbitration mode is set to QoS preferred mode, the request source with QoS property flag raised will be raised by two levels – regardless of the DRAM bank status.Starvation prevention: The selection matrix has built in starvation prevention. If the request(s) on a lower level has not be served in a certain period of time, all the requests will be raised by one level. This period of time is controllable by S/W through the Priority Level register in memory controller.

Since the two memory controller requests maybe intensively interleaved (when the channel selection is mapped to a low internal address bit), the two controllers will always have same arbitration settings by sharing the same Priority Level register.

9.6 Data Secure-Access ControlRefer to Section 8 for details about data secure-access control on DDR controller.

Req

uest

Prio

rity

Sele

ctio

n M

atrix

With

Sta

rvin

g Pr

even

tion

VMeta (QoS) Port 3




Arbitration output

Collected Write Port 0

CPU0 read

CPU1 read

Graphics Engine Port 4

Peripherals Port 5

AVIO (QoS) Port 1/2

Bank Status

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Programmable Interrupt Controller (PIC)



10 Programmable Interrupt Controller (PIC) The 88DE3010 top level programmable interrupt controller (PIC) is a highly programmable interrupt controller. It gets interrupt sources from different 88DE3010 internal modules and merge them into fast and normal interrupt requests to SoC CPU0, CPU1, and to on chip PCIe End Point controller. Each interrupt source can be enabled by software. When an interrupt is received by PCIe End Point Controller, a message packet will be generated and sent to the PCIe Root Complex in the system. When the interrupt is serviced, software can read the PIC status and control registers to get the interrupt information.

Figure 27 and Figure 28 illustrates the 88DE3010 top level PIC.

Figure 27: 88DE3010 top level PIC diagram

Figure 28: Internal diagram of 88DE3010 top level PIC

There are a total of 5 interrupts generated by the 88DE3010 top level PIC:

CPU0 fast interrupt

Sub

-sys

tem

leve

l har

dwar

e in

terru

pt s

ourc

es

88DE3010 Top Level Interrupt Controller

PIC0

PIC status and control registers

PIC1

PIC2

Har

dwar

e m

odul

es

fastnormal SOC CPU 0

normal SOC CPU 1fast

PCIe E/P Controller

From CPU0/CPU1/PCIe E/P Controller

Register access

20

20

20

20

20 Interrupts from modules & lower level PICs

InterruptPropertycontrol

Fast interrupt

Slow interrupt

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CPU0 normal interruptCPU1 fast interruptCPU1 normal interruptPCIe E/P interrupt

Each of the two 88DE3010 SoC CPUs supports fast interrupt and normal interrupt inputs. By separating into two groups, the software can provide faster response time for selected interrupts. Software can program the PIC to route each interrupt source to the desired group. For each such interrupt group, this selection can be made independently.

There are total of 20 high level interrupts routed to the top level interrupt controller. Some of the interrupts are generated directly by one of the hardware engines while some of the interrupt sources are the combined output of a sub-system level interrupt controller. The complete list of top level interrupt sources are listed in Table 88. The 88DE3010 top level PIC supports a self clearing scheme. Once an interrupt source is inactive, the related interrupt status will be cleared automatically.

For each interrupt source, following is a list of properties that can be programmed:

Enable: If the interrupt will be seen by the PICPolarity: If the interrupt trigger is either active high or active low

For each of the interrupt source, the PIC controller implements 5 identical sets of the above register controls, one for each interrupt output. By using the appropriate enabling controls, software can route the interrupt source to the desired destination. The 88DE3010 only supports level triggered interrupts.

Figure 29: 88DE3010 top level PIC interrupt source properties

Table 88 illustrates the list of interrupt sources.

polarity

enable

Table 88: Interrupt Sources

IRQ Number Description Notes

0 Interrupt from AVIO vppDhub Combined interrupts of the DMA engines for display and QDEO TM processing

1 Interrupt from AVIO agDhub Combined interrupts of the DMA engines of display and audio I/O and audio post processing engines

2 Interrupt from VMetaDHub Combined interrupt of the various blocks of the video decoding engine

3 Interrupt from apbPerif Interrupt controller

Combined interrupts from low speed I/O peripherals

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Programmable Interrupt Controller (PIC)



Refer to each individual module’s chapter for details regarding the combined interrupt sources.

4 Interrupt from PCIe Link (when 88DE3010 is in RootComplex mode)

5 Error event from PCIe controller

6 Interrupt from 2D graphics engine

7 Interrupt from SATA Controller

8 Interrupt from 10/100 Ethernet controller

9 Interrupt from DRM Engine

10 Interrupt from DRM FIGO

11 Interrupt USB0 Controller

12 Interrupt USB1 Controller

13 Interrupt from System Manager Combined interrupt from System Manager CPU and its peripherals*

14 Reserved Reserved for Marvell internal use only



17 Interrupt from SDIO

18 Interrupt from pBridgeDHub

19 Interrupt from Audio DSP

20-29 Reserved

30 Inter-CPU interrupts Used for inter CPU communication between SOC CPU 0 and 1. 31

Table 88: Interrupt Sources (Continued)

IRQ Number Description Notes

Note

System Manager interrupt is a combination of multiple peripherals. Having 3 identical interrupts enables SOC CPU 0/1/PCI-E host to conveniently split and share the System Manager peripherals.

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11 Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemThe Transport Stream processor and digital right management (DRMDMX) subsystem is designed to process the Blu-ray data packets, DVD data packets, and MPEG-2 transport stream (ISO/IEC standard 13818-1). The source of the MPEG-2 Transport stream can be either from DRAM or from on-chip transport interfaces (TSI). The transport streams can be either an unscrambled format or a scrambled format with AES, DES or Multi-2. During the boot up, the DRMDMX subsystem provides security functions such as on chip one time programmable memory (OTP) controller, secure boot image verifier / loader and debugger interface controller.

The Transport Stream Processor in DRMDMX subsystem includes 4 transport stream data capturing modules with PID filtering and time stamping function. It also has a section data match engine that supports up to 128 rules for PSI data filtering, a demux engine that supports TS/PS/PES to elementary stream de-multiplexing, and a flexible DMA engine. The Transport stream processor supports ISO/IEC 13818-1 transport stream and program stream. It captures transport stream from an off-chip demodulator through one of the 4 Transport Stream interfaces (TSI) or from DRAM data buffers through the DMA engine. Based on the PID settings these transport packets are filtered. Part of the packets can be output directly to the DMA buffers for further processing by the CPU (e.g., PSI streams and A/V streams for PVR recording). The rest of the packets can be further parsed into ES streams. The ES streams and the events detected during the parsing will be output to individual DMA buffers.

The stream capture, PID filter, section filter and DMA engine are hardware blocks, while the Demux and security function is based on a simple 16-bit Marvell® Figo1 RISC processor running micro-code with special H/W acceleration instructions for various crypto algorithms. The function of the DRMDMX can be extended through micro-code upgrade based on application requirements. The dynamic load of the DRMDMX micro-code is always protected by the Figo ROM based secure image verifier using OTP or ROM keys.

1. Figo is Marvell® proprietary MIPS processor

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemDRMDMX Block Diagram



11.1 DRMDMX Block DiagramFigure 30: DRMDMX Block Diagram

In the DRMDMX module, the Figo RISC has access to 24KB ROM + 12KB SRAM for instructions. The ROM image contains micro-code for OTP content read, secure image verifier and some basic crypto functions for boot image authentication and decryption, such as AES, HMAC, and RSA-PSS. The 12 KB SRAM is for dynamically loaded Figo F/W for descrambling and/or transport or program stream demux functions.

There is separate 16 KB local scratch pad DTCM in the DRMDMX. This memory is shared between several functions:

Communication with CPU: Part of the on-chip DTCM is used to store command and response for Figo-CPU communication, an interrupt to CPU can also be generated by the Figo to indicate a response or an event. FIFO based data exchange with H/W modules such as Section Filter, transport stream capture module (TSC) and DMA engine. The rest of the local DTCM is used by Figo exclusively for local data storage

After reset, the CPU access to the DRMDMX internal module/DTCM access is disabled. The secure boot ROM code for DRMDMX Figo will configure a memory mapped access window for CPU.

16KB DTCM

Command/Response

OTP

RNG

Data ROM

12KBInstruction

SRAM

Figo RISC

DMA Engine

AHB bus I/F with Firewall control

H/WFifo

Channels

FigoLocal Data

memory

SectionFilter

TSC with PID filter

4 serialOr 1 parallel + 2 serial

Transport Stream Interface

Crypto Accelerator

24KBInstruction

ROM

Debug interfaceEnable

Interrupt to CPU

JTAG control

Filter RuleSRAM

To DRAM controllerthrough SoC interconnect

Register AccessFrom CPU

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Through that window, the CPU will be able to securely download Figo micro-code image for further operations. If OTP information is required during the operation, the DRMDMX figo will check the OTP status to be valid before the operation.

11.2 Transport Stream Processor Modules11.2.1 Transport Stream Capture (TSC) module

TSC module has following functions:

Input routingInterface synchronization and valid data detection 32 PID filtering Pack TS data and send to TSP FIFO when there is a PID match Incoming packet time stamping with local STC counter for video output clock tracking Generate control tags about the status of the packet

11.2.1.1 TSC input routing

Figure 31: TSC Input routing

There are 4 TSC modules. Each of them can be programmed to capture data from one of the four input ports independently. So it’s possible to have each TSC module programmed to capture data from each different TS interface or have multiple TSC modules to capture data from one TS interface (with their own PID filters).

11.2.1.2 Packet CaptureThe TSC packet capture logic is capable of detecting and capturing ISO/IEC-13818-1 MPEG-2 transport stream with packet size 188 bytes.

The packet capture logic is designed to handle error conditions when the tuner and demodulator changes channels. The error conditions are listed below:

Temporary disappearance and/or glitches of the TS interface clock after channel change Temporary disappearance and/or glitches of the TS Sync signal on the TS interfaceFraction of packets in async FIFO upon channel changeMissing of the Transport sync word (0x47) while TS Sync signal is valid

TSC0

4 serialOr 1 parallel + 2 serial

Transport Stream Interface

TSC1

TSC2

TSC3

4x4 Full input

switch

STC w/Video Clock 0

STC w/Video Clock 1

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemTransport Stream Processor Modules



Software can program the number of toggles of TS sync signal before the TSC module start to capture data in automatic mode.

The TSC module will also detect the data when the sync signal is valid. Even though the sync data is not a programmed value (default is 0x47) it will start the data capturing, but it will set the status in the TSCmd to sync error.

To enhance stability, the clock signal of the TS interface is not used as a clock in the TSC module, instead, the TSC module detects the rising edge of the TSClk, and uses that as an event to start capturing other signals. The phase difference between the TSClk detection and data latch can be programmed at 2.5 ns steps.

At any time, software can reset TS Capture state machine by disabling the TSC module and enabling it again. In this case, there could be residue data in the output FIFO and the S/W needs to flush the FIFO.

11.2.1.3 PID Filtering When PID field is detected in the transport stream, each capture module will compare it with up to 32 PID filters. Only the packets matching one of the PID TSC module will write these packets into FIFO. The TSC can also be programmed to bypass all the PID filters. In this case, the TSC will capture all the TS packets regardless of their PIDs.

For each of the PID filters, there are:

13 bit target PID to be matched1 enable bit1 bit to select the STC counter clock source

11.2.1.4 STC Time Stamping On receiving the 12th byte of a transport packet, the TSC will capture a STC counter (driven by video clocks) for current packet. There are two 42-bit STC counter driven by two video output clock. The counter to be used for STC stamping can be specified per PID basis. For each of the PID filter, a bit specifies which STC counter is used to make the time stamp of the captured transport packet.

11.2.1.5 Control Tags and Packet Status After filtering, each TSC module will send the packets to it's associated output FIFO in the local DTCM for further processing (demux) by the 16-bit Figo RISC processor. At the same time, the TSC module will generate a 64-bit event packet after a full T/S packet is captured. The event packets from all the TSC modules are merged into one single event FIFO to Figo, it will specify the following information about the packet:

Matched PID valueIndex of the matched PIDFrom which TS port the packet is received Error status of the packetIf payload_unit_start bit is set in packetIf no error is detected during the capture, 42 bit STC time stamp is includedIf error is detected, error type is included • Error indicated by demodulator through the TS interface• Sync word not received• Wrong size of packet between sync pulse on TS interface• FIFO overflow happened during capture

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11.2.2 Section Filter The hardware section filter is designed to off load CPU from searching and matching section table headers in the transport streams. Up to 128 section filter rules can be programmed by S/W. The section filter hardware engine will match the incoming section data headers against these filter rules one by one. If a match is found the section filter will copy the input data to output FIFO, and update the section IF filter event with matched section ID field. If no match is found, the input data will be ignored. When the output FIFO reaches to pre-programmed threshold, an interrupt will be generated to the CPU if enabled.

Each of the individual section filter rules supports up to 32-bit range filtering or 1 to 128-bit exact pattern match filtering selected from 256 bit input section data. Simple filtering rules can be cascaded to build more complex rules.

Figure 32 illustrates all the elements involved in set up a section filter rule:

Figure 32: Section Filter Rule

The input and output data format is a 2 DW filter command/event with 8DW section data to be matched. Each section data match rule has it’s individual enable/disable register bit. A local SRAM stores rule descriptor and rule data. The rule descriptor is fixed length of 2 DW. It describes the matching mode, section data selection information and the address pointer of the associated rule data. The rule data is of variable length, it stores the patterns to be matched.

11.2.3 Input and Output Packet Format The input data to section filter are section filter commands, the output data are section filter event packets. The input/output data is from a 64-bit wide FIFO, they can be read by the CPU through 32-bit register access. The depth of the command and event FIFO can be configured during initialization. By default they are configured to be 16 8-byte entries. The command and event packets share the same format. The only difference is that in the event packets, the match bit and filter ID field are updated according to the match result.

Rule descriptor2 DW

Rule descriptor2 DW

Rule Data3-9 DW

Rule Data3 -9 DW

128x Rule control

registers128x Rule descriptors

Variable Rule Data

HardwareRule-section data

match engine

Rule Data3 -9 DW

Section Filter Rule

SRAM

Filter Command2 DW

Section Data8 DW

Input Fifo

Filter Event 2 DW

Section Data8 DW

Output FIFO

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemTransport Stream Processor Modules



The total size of packet is 10 DW. The first 2 DW are filter command and the next 8 DW are section header data to be matched.

The filter command/event includes following information:

13 bit PID - This is PID of the TS packet, 2 bit TSID - This is used to identify the originating transport interface where the packet is captured8 bit TID (table ID) - This table ID enables the Table ID match and the S/W needs to fill this field with the table ID information acquired during the section data parsing.

The PID, TSID and TID can be used as a pre-qualifier by the match engine before the section data is matched against the pattern based section filtering rules.

1 bit match result7 bit matched section filter ID

11.2.4 Section Filter Control Software can control the section filter to perform following rule management functions.

Global enable/disable of all section filter rulesIndividual enable / disable per section filter rule, if an associated rule is a “one-shot” rule, the enable bit will be cleared by the match engine automatically after one successful matchMechanism to initialize and reset the filter engineMechanism to add and remove a ruleStatus to show the filter engine activity, through a status register, the S/W can get debugging information which rule the section filtering is currently matching with, and what SRAM address it's reading the rule from, and what state the section filter main state machine is in.

The rules can only be changed when section filter input FIFO is empty and main state machine is in idle state.

11.2.5 Section Filter Rule DescriptorAll the section filtering rules can be programmed into the section filter rule SRAM by CPU. For each rule, there is 2 DW filter rule descriptor and variable length (3 -9 DW) rule data. As shown in Figure 33, the rule descriptors are stored in SRAM from address 0x0 to 0x3FF. the rule data are stored starting from address 0x400. The total rule SRAM is 2K DW. Since the rule data have variable size, each of the rule descriptor has a field pointer to the start address of it’s associated rule data in the rule SRAM.

The driver is responsible for SRAM resource allocation and management.

The rule descriptor includes the following information:

If the rule is a one shot rule, i.e., it will be disabled automatically once a match is found unless the S/W turns it on again through enable register bit If match of the PID and TSID and TID necessary before the rule is applied, the target PID, TSID, and TID are included in the rule descriptor SRAM address pointer to the associated rule data

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Figure 33: Section Filter Rule SRAM Memory Map

11.2.6 Section Filter Rule Data Section filter rule data has the following data fields:

MODE: Indicate one of the following modes for section filtering: inRange, outRange, positiveMatch and negativeMatchBYTEOFFSET: Byte offset to selection up to 4 double word from 8 double word section table header BITOFFSET: Offset within a byte for section header match, only used in inRange and outRange matching modes LAST: Indicates a rule is the last rule of a cascaded section filter rule NXT: Address pointer to the next rule in rule SRAMLEN: In positive/negativeMatch mode, this field specifies the length of match pattern, from 1 to 4 DW, If MODE is in/outRange, length of the filter is always 1 DWPATTERN: 2 DW to 8 DW pattern and mask data• In In/OutRange mode, the PATTERN is 2 double word long, with minimum value

PATTERN(MIN) and maximum value PATTERN(MAX) • In positive match or negative match mode, the PATTERN can be variable (even) number of

double words. The first half of the double words specifies the pattern to match PATTERN(COEFF), and second half of the double words specifies the mask bits PATTERN(MASK)

The MODE field specifies the 4 mode supported by each rule:

In range mode: In range match, up to 32-bits of the section data can be chosen to compare with a range. Since the input section data is 32 bytes, the BYTEOFFSET and BITOFFSET fields are combined to select this 32-bit data from any bit boundary for range comparison. The filtering result is a match if the selected section header data is greater than or equal to minimum AND less than or equal to maximum specified by 2 DW pattern: • PATTERN(MAX) >= (sectionHeader >> (BYTEOFFSET*8+ BITOFFSET)) >=

PATTERN(MIN);

Rule Dscp 0Rule Dscp 1

Rule Dscp 127

Rule Data 0

Rule Data 1

Rule Data 127

Addr=0x0Addr=0x8

Addr=0x400

Variable Addr

Variable Addr 2K DW

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemDemux Micro-code



Out range mode: the filter result is a match if the selected section header data is less than minimum OR greater than maximum specified by 2 DW pattern.• (SectionHeader>>(BYTEOFFSET*8 +BITOFFSET)) > PATTERN(MAX) or • (SectionHeader>>(BYTEOFFSET*8+ BITOFFSET)) < PATTERN(MIN)Positive match mode: In positive/negativeMatch mode, up to 16 bytes of section header data, selected by BYTEOFFSET are compared against pattern with mask bits specified in the rule data. In exact match mode, the length of the selected section header data can vary from 1 DW to 4 DW, this is specified by the LEN field in the rule data. All selected bits in section header data equal to the non-masked pattern, while the masked pattern bits are ignored. • (SectionHeader>>(BYTEOFFSET*8)) & PATTERN(MASK) == PATTERN(COEFF) &

PATTERN(MASK)Negative match mode: at least 1 bit of the selected bits in the section header data does not equal to the specified pattern, while the masked pattern bits are ignored.• (SectionHeader>>(BYTEOFFSET*8)) & PATTERN(MASK)!=PATTERN(COEFF) &

PATTERN(MASK)

The NXT field is a rule SRAM address pointer. It can be used to cascade multiple rules into a filter chain. The LAST field is used to indicate it’s the last rule of a chain. For cascaded rules, the overall rule comparison result will be determined by the last rule. During the filtering, if any of the cascaded rules has a mismatch, the whole filter chain will be considered not match and filter engine will move on to next rule.

11.3 Demux Micro-codeAfter PID filtering and descrambling (if necessary), transport stream packets are further processed / de-multiplexed by the 16-bit Figo RISC processor. Based on the packet headers, the Figo processor (running Demux micro-code) extracts Packetized Elementary Streams (PES) or Elementary Streams (ES) for audio and video, user data such as Program Service Information (PSI) into individual buffers. It also detects various events during Demux and outputs to a separate event buffer.

For transport stream demux, the 88DE3010 SoC CPU does not directly program any hardware modules. All required operations are achieved through Software API calls to the Demux micro-code. Figure 34 illustrates the relations between the software API, the Demux micro-code and the hardware.

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Figure 34: Relations between Software API, Demux micro-code, and Hardware

The overall demux function is built upon the following basic filters and functions:

Capture: Capture a transport stream through TSC module with PID filtering DMA input: Load a filtered transport stream from DRAM buffer through DMA DMA output: Store a filtered transport stream to DRAM buffer through DMAES / PES filter: Demux TS stream into multiple ES stream and store to DRAM buffer through DMACrypto filter: Descramble or scramble a filtered transport stream Event collection: Store events to DRAM buffer through DMA

Except for the event store, the demux engine can be configured to cascade of any listed filters by a shared internal data buffer between two filters or functions. This can be done to meet the application requirement through the driver. For details of the set up procedures and dynamic control of the filters, please refer to “88DE3010 API User Manual”.

The 88DE3010 Demux engine is capable of processing up to 4 input streams, they can be processed directly from the on-chip transport stream input interface (TSI interface) or loaded from DRAM buffers through DMA engine (in case of Blu-ray or DVD play back). The input stream format can either be MPEG-2 transport stream or program stream (ISO/IEC standard 13818-1). Based on the S/W setting, total up to 32 output elementary streams can be demuxed and saved to DRAM buffers simultaneously. The total output stream rate will depends on the total loading of the Figo processor. When playing back AACS (with AES encryption) enabled, the maximum output rate is 60 Mbps.

During the demux process, the Demux engine will detect all enabled events, and these events will be saved to an event buffer in DRAM. All events from DRMDMX engine go to a shared event buffer, these events will be processed or dispatched by the driver.

Resource management

S/W Demux API

DMA / local Buffer Management Figo Demux

micro-code

Event handler

Task Scheduler

Basic DemuxFilters

DMAEngine TSC

Section FilterLocal TCMStorage

DRAM Buffer Management

InterfaceWith SoC CPU

DemuxH/W

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemDemux Micro-code



* These event detections are for broadcasting environment only. They are not included for Blu-ray applications.

The total resource constraints of the demux micro-code are:

The maximum input source is up to 4, this includes transport data source from both TSC modules and from DRAM The maximum number of output DMA buffer is 32The total internal buffers shared between filters are 4Total maximum number of filters is 8

Table 89: DRMDMX Enabled Events

Even name Description

eBS_UnitStart Event generated by DEMUX filter when find a payload_unit_start from input stream, it will carry PTS and DTS value if they are available in the PES header.

eBS_UnitEnd Event generated by DEMUX filter when a PES packet finish.

eBS_TransportError * Event generated by DEMUX filter when it detect transport_error_indicator bit is set in a TS packet header.

eBS_ContinuityError * Event generated by DEMUX filter when it detect countinuity_counter is not in correct sequence.

eBS_PcrInfo * Event generated by DEMUX filter when it find a valid PCR value carried in adaptation field. It carries PCR value.

eBS_TsScramChg* Event generated by DEMUX filter when it detect the scrambling control bits in TS header have changed from previous value. It carries the new scrambling control mode.

eBS_PesScramChg* Event generated by DEMUX filter when it detect the scrambling control bits in PES header have changed from previous value. It carries the new scrambling control mode.

eIN_BufferFlush Flush event is input and output event for all filters. When DEMUX manager on CPU need to stop a source safely at a specific data position, it need to push a Flush event to the DSIn control buffer of the first filter in the chain. The whole data path is stopped safely on the intended data position when DEMUX manager receives this event from all the output channels of that source.

eIN_StopCmd Stop event is input and output event for all filters. When DEMUX manager on CPU need to stop a source safely and immediately at filters earliest convenience, it need to push a Stop event to the DSIn control buffer of the first filter in the chain. The whole data path is stopped safely when DEMUX manager receives this event from all the output channels of that source.

eBS_SyncLost Event generated by DEMUX filter when it detect TS sync loss.

eBS_SyncLock Event generated by DEMUX filter when it find TS sync. Two consecutive sync word in the right place is viewed as a sync lock.

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11.4 DRM and Secure Boot11.4.1 Architecture

The DRM and secure boot processor is shared with the 16-bit Figo RISC processor. In the 88DE3010 SoC connections, the DRM Figo processor has full access to all the internal registers (refer to Section 8, SoC Connectivity and Access Control for further details). This will enable the Figo processor to program the SoC secure access registers to set up access restrictions for SoC CPUs and HW DMA engines. It also enables the Figo processor to directly program HDCP key information into HDMI HW modules without SoC CPU intervention. During the boot up stage, the Figo processor runs on it’s local ROM boot image to provide secure boot support for full SoC. After secure boot, the Figo processor can authenticate and run application level F/W, including DRM related services as well as demux filters.

Figure 35 shows the hardware and software layers for DRM processing.

Figure 35: Hardware and Software layers for DRM Processing

11.4.2 OTP The OTP module on the 88DE3010 device is designed to store up to 2560-bit unique data during or after chip is manufactured. It has the following regions:

Root key region: it is used to store two secret 128-bit numbers (RKEK and AESK) that can be used as symmetric keys to decrypt boot image or establish root trust. This region can be programmed during ASIC manufacturing or system manufacturing.

Hash

AACS

Certification management

Figo Secure Processor HAL

communicaton

WMDRM CPPMCPRM

DVD-CSS

User ApplicationsUser

ApplicationDRM

Middleware &Applications

Crypto-APILibraries

SignatureGeneration & verification

Encryption & Decrytion Key management

Figo Secure Processor

micro-Code Key processing Security level managment

DESAES Multi-2 C2 RC4 SHA1 RSA

Figo Secure Processor Hardware

Firewall

Figo processor Data and Instruction RAM/ROM

Crypto Instructions

RNG OTPDMA engine

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemDRM and Secure Boot



Verification key region (SIGNK): This region can be used to store a RSA public key or an AES key (for HMAC) for certification verification. A total of 1536 bits are allocated to store 1024 bit modulos and 512-bit public exponent.This region can be programmed during ASIC manufacturing or system manufacturing.BindInfo: 128-bit field of security level control, product life cycle management information, and chip binding information, secure boot options. this region is pre-programmed by Marvell.UserInfo: 128-bit user definable fields, such as serial ID for chip/system or market segment identificationProhibited region: the 64-bit prohibited region are reserved, they should not be used for any purposes

Figure 36: OTP

After reset, the ROM based micro-code on Figo will read the OTP content into it’s local SRAM, after checking the integrity of the OTP content, it will enforce the security rules indicated by the security level control fields in the OTP.

The OTP can be programmed by the 88DE3010 SoC CPU through a set of OTP control registers. For security concerns, there’s no mechanism for CPU to directly read back the OTP content it programmed. The CPU must rely on the micro-code in Figo to check if the programming is successful.

For each of the OTP control signals, there’s CPU accessible register bits to control it, the required programming timing will be generated by CPU S/W programming utility. The whole OTP module is organized by 40 64-bit cells, for each 64-bit cell a security bit can be blown to disable any further programming.

Hamming Code for SIGNK (256bit)

CRC and key descriptor for SIGNK (64bit)

SIGNK (1536bit)

RKEK(128bit)

AESK Info(Hamming code, CRC,

Key descriptor)

AESK (128bit)

bindInfo (128bit)

userInfo(128bit)

prohibited(64bit)

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11.4.3 RNGThe RNG is designed to provide physical random source for the secure processor. The physical random source is derived from phase noise of an on-chip PLL across the chip and VDD supply noise through a local ring oscillator. The random source can be directly obtained in raw format or filtered through a Linear Finite Shift Register with improved cryptographically property. The random data sampling rate can be adjusted by S/W between 12.5 Kbps to 3.18 Mbps.

11.4.4 Crypto AcceleratorThe Figo RISC has a generic acceleration instruction set to speed up common crypto operations. It can support different crypto engines through dynamic loaded micro-code. Following cryptographic algorithm accelerations are supported:

AES encryption and decryptionSHA1 DES and 3-DES encryption and decryptionRC4CSSC2 encryption and decryptionMulti-2 RSA

11.4.5 Figo Boot ROM The Figo ROM code provides crucial security functions needed for CPU and full system to boot up with authentic image. The function of the Figo boot ROM code includes:

OTP Reader and Verifier: It can read and verify the OTP content, Hamming error correction and CRC32 are supported for boot key related information (PRVK and AESK). For both of the OTP regions, there are 3 possible states: not programmed (clean), programmed but detected error (invalid), programmed and no error detected (valid). Figo and CPU binary image verifier: after successfully verifying the OTP content, the Figo ROM code will set up minimal Firewall access for CPU processor. The CPU processor can copy any binary image into part of the Figo local memory. Figo ROM code will verify the image integrity, if it’s a CPU image, it will send the response for the verification result. And if it is a Figo micro-code, it will copy the image to instruction SRAM and start to execute the image. Both AES based HMAC and RSA-PSS are supported.Figo and CPU executable decryption: After signature verification, the Figo ROM code can also decrypt the image using AES with assigned key if needed.

128-bit AES key and 1024-bit RSA keys are supported in Figo boot ROM for image authentication and decryption. Based on command, Figo ROM code can select the keys from the OTP for customer owned image or it’s internal data ROM for Marvell owned image.

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Transport Stream Processor and Digital Right Management (DRMDMX) SubsystemDRM and Secure Boot



Figure 37 shows the Figo ROM boot flow:

Figure 37: Figo ROM Boot Flow

11.4.6 DRMDMX Bus Interface FirewallThe DRMDMX bus interface firewall is designed to provide an isolated secure environment for the secure processor subsystem to prevent unauthorized access to sensitive hardware recourses and DTCM contents by the CPU. The firewall can be configured only by Figo RISC. It can provide the following 3 types of access rules for a defined access window:

Read-onlyRead and WriteInaccessible

Each window can be set to a double word boundary, maximum size of an access window is 64 Kbyte, and up to 8 windows can be defined.

After reset, all the access windows are disabled by default, only after Figo ROM code finishes it’s boot up sequence it will set up the access windows according related security level information in CHIP_INFO OTP fields.

FigoF/W

Check OTP Status of RKEK and CHIP_INFO

Valid/Clean OTP

Initialize H/W Firewall

Reset

Polling CPU command buffer

Update security status register

Verify & Decrypt Image

Update CPU response buffer

Run on Figo Image

Figo ROM

Figo Image

CPUImage

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11.4.7 On-chip Debug Interface ControllerBased on the values in OTP CHIP_INFO field, the Figo ROM code will set the control of the on chip debug interface in one of the three modes:

OpenPassword protectedClosed

In password protected mode, the JTAG debug interface is initially disabled after chip reset. To enable it, a special signed Figo Image needs to be downloaded by the CPU during boot stage. This Figo macro-code image will communicate with the CPU processor to get the per-chip unique password to enable the debug port.

In the open mode, the JTAG debug interface will have full access to any of the connected CPU cores.

In the closed mode, the JTAG debug interfaces are permanently disabled.

The OTP programming will only allow one way to change - from open to password protected to closed.

11.5 DRMDMX Performance & Capability During the boot time, the DRMDMX provides secure boot based on OTP key settings. After the application is loaded the DRMDMX provides all the functions necessary for transport stream processing, such as key generation, packet descrambling and demux. The actual number of streams and configurations of the data path are configurable through the driver.

All these functions share the same Figo RISC processor, the total capacity of the processing power is limited to 400 million cycles per second.

Table 90 is a reference of the cycles needed for various operations:

Table 90: DRMDMX Performance

Operation RISC cycles needed

TSC capture with PID filter 1 cycle /bit

Transport stream loading from DMA

1 cycle /bit

DMX filter 0.5 cycle /bit

Data output to DMA buffers including buffer management

1 cycle/bit

AES decryption/encryption 2.3 cycle /bit

DES decryption/encryption 3.7 cycle /bit

Multi-2 decryption for ARIB 5.8 cycle/bit

RC4 4.6 cycle/bit

SHA-1 3.6 cycle/bit

CSS 6.4 cycle/bit

1024-bit RSA signature verification 37 mS

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VMeta™



12 VMeta™The 88DE3010 device’s video decoder is based on Marvell® VMeta™ technology. It is a multiple format high-definition video decoder. It supports decoding of most of the major video formats, such as H.264, VC-1, MPEG-2, MPEG-4, and H.263 in high definition. It is capable of decoding multiple video streams with various resolutions1 and formats simultaneously.

Figure 38 shows the interactions between the VMeta subsystem and other components in a conceptual video playback system. The VMeta subsystem decodes the compressed video elementary streams to produce the reconstructed video frames in YUV422 format for display or further processing. Both the input video elementary stream and output frames are stored in DRAM.

Figure 38: VMeta Subsystem in a Video Playback System

The VMeta subsystem contains the following two standard interfaces for communicating with the rest of the system, as shown in Figure 39. There’s one CPU control interface for VMeta internal register and SRAM access, and one DRAM Data interface for VMeta to access compressed, decompressed video, and intermediate data buffers.

1. VMeta supports resolutions up to 1080p. Refer to Section 12.2 for more information about resolution and performance.

DRAMVideo Elementary Streams Decoded Video Frames

Video Post-Processing

Display

Decryption/Demux

- Broadcast- Storage- Network

VMeta Decoder

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Figure 39: Top Level Interfaces to VMeta™ Subsystem

Besides these two interfaces, VMeta also has an interrupt connection to the SOC CPU. The interrupt is used to communicate with the CPU regarding the VMeta decoder’s internal status and events that may require the CPU’s intervention. Interrupts are generated for the following events:

Insufficient input dataStream processing finishes for current decoding unit.Pixel processing finishes for current decoding unit.

12.1 Supported Video Formats and Performance12.1.1 Supported Video Decode Formats

The VMeta™ decoder supports decoding in the video formats:

MPEG-2 Main Profile, up to High LevelH.264 High Profile/Main Profile/Constrained Baseline, up to Level 4.1VC_1 Advanced Profile, up to Level 3H.264 Baseline Profile, up to Level 3MPEG-1VC-1 Simple Profile/Main Profile, up to High LevelJPEG BaselineMPEG-4 Advanced Simple ProfileDivX 3.11VP6 (Standard Definition only)H.263 Profile 0/Profile 3

The VMeta decoder can switch between video streams with any supported format and resolutions. The stream switching should only take place at the frame boundary. There is no limitation to the

64-bit DRAM Data Interface

CPU Control Interface32-bit

VMeta Subsystem

Video Elementary Streams Decoded/Reference Video Frames

DRAM Controller

CPU

DRAM

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VMeta™Video Decoder Performance



number of simultaneous streams the VMeta decoder can support, as long as the total performance requirements are within the constraints described in Section 12.2.

The VMeta decoder has a built-in error resilience function. Video bitstream errors can be handled inside the VMeta decoder without high level application’s intervention.

12.2 Video Decoder PerformanceTable 91 and Table 92 below show the clock speed and DRAM bandwidth requirements for decoding one channel of various video formats at various resolutions. The majority of decoding tasks are done inside VMeta, and the SOC CPU only oversees the high level operations of video decoding. A typical SOC CPU requires about 30 million cycles per second processing power per stream for overseeing the video decoding process.

The maximum capability of VMeta decoder in 88DE3010 SOC is to decode two video bitstreams with1080p resolution simultaneously at 800 MHz VMeta clock rate.

Table 91: VMeta Decoder Performance

Video Format 1080p Video Resolution at 30 fps

720p Video Resolution at 30 fps

480p Video Resolution at 30 fps

Bandwidth (Gbps)

Clock Rate1 (MHz)

Bandwidth (Gbps)

Clock Rate (MHz)

Bandwidth (Gbps)

Clock Rate (MHz)

H.264 High Profile/ Main Profile/Constrained Baseline Profile decoder

Read: 3.0 Write: 2.0

400 Read: 1.3 Write: 0.9

200 Read: 0.7 Write: 0.3

100

H.264 Baseline Profile decoder*


400 Read: 1.3 Write: 1.8

200 Read: 0.7 Write: 0.6

100

MPEG-4 Advanced Simple Profile decoder


400 Read: 1.3 Write: 0.9

200 Read: 0.5 Write: 0.3

100

MPEG-2 Main Profile decoder


300 Read: 1.3 Write: 0.9

150 Read: 0.5 Write: 0.3

75

VC-1 Advanced Profile decoder


400 Read: 1.3 Write: 0.9

200 Read: 0.5 Write: 0.3

100

VC-1 Simple Profile/Main Profile decoder


400 Read: 1.3 Write: 0.9

200 Read: 0.5 Write: 0.3

100

1. H.264 Baseline Profile decoding write bandwidth increases mainly due to FMO (Flexible Macroblock Ordering).

Table 92: Still Image Performance

Video Format 16M pixels at 1 fps Bandwidth (Gbps) Clock Rate1 (MHz)

JPEG Baseline decoder Read: 0.1 Write: 0.3

200

1. The clock rate shown in Table 91 and Table 92 is referring to two VMeta subsystem clocks: VScope clock and PCube clock. Both clocks are corresponding to VMeta clock in global unit.

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13 Data Streaming Hub (dHub)The Data Streaming Hub (dHub) modules in the 88DE3010 device provide DMA services for data transfers between Hardware modules and the memory controller. The function of dHub includes data collection & buffering, channel arbitration, and buffer address management. Figure 40 shows the block diagram of the dHub module.

Figure 40: dHub Block Diagram

In 88DE3010, there are total of four dHub modules used with different configurations. They are included in AVIO sub-system, peripheral sub-system (pBridge), and in VMeta video decoder.

13.1 dHub Command and Data Software can set up a dHub channel for DMA operation to/from a DRAM buffer through a dHub command. Each dHub command is an 8-byte data structure specifying the address, size of the DMA buffer, and bus transactions parameters. Each dHub channel has its own FIFO to store the dHub commands. Software can issue multiple commands for each channel simultaneously.

For each dHub channel, there is also a dedicated data buffer between the DMA engine and hardware devices. For a dHub read channel, the full burst of DRAM data is read and buffered in the channel data buffer and then sent to the hardware device upon request. For a dHub write channel, the data from hardware device are collected in its corresponding channel data buffer, usually to the maximum transfer unit (MTU) before sending the internal bus transfer request.

In a dHub module, the dHub command buffers and data buffers are separated into a few on-chip SRAMs. The size allocation of each buffer is programmable. Based on different application requirements, software can allocate the buffer resources during the dHub initialization stage.

Channel control & Synchronizatoin Bus InterfaceConfigurable FIFO

wCmdQ

Rea

dA

rbitr

atio

n

semaphore

BusTransaction

Fifo

wDatQ

wCmdQ

wDatQ

rCmdQ

rDatQ

rCmdQ

rDatQ

ChannelControl

ChannelControl

ChannelControl

ChannelControl

Writ

eA

rbitr

atio

n

BusTransaction

Fifo

Bus

Mas

ter w

ith G

ate

Kee

per

To InterconnectFabricInterconnect

to H/WModules

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Data Streaming Hub (dHub)dHub channel arbitration



Each dHub channel supports linear addressing mode and 2D addressing mode. In 2D addressing mode, the dHub channel can load data from a rectangle region in DRAM buffer defined by horizontal start address, horizontal size and stride, and vertical size. A detailed 2D command is described in Section 13.7.2.

13.2 dHub channel arbitrationHardware data transfer requests are sliced down to programmable MTU for arbitration. Whenever possible, the dHub channel will issue arbitration request with MTU size. Once granted, the dHub channel will be able to finish the full MTU data transfer before releasing the control of the bus. The supported MTU sizes are: 8-byte, 32-byte, 128-byte, and 1024-byte.

When a dHub channel is ready for internal bus transfer (having one MTU transfer data ready in the corresponding data buffer for a write channel or having one MTU space in corresponding data buffer for a read channel), it will send the request to the dHub channel arbiter. The arbitration winner will gain the control of the internal bus to fabric connection and can start the data transfer. In the 88DE3010 dHub, there are two arbiters; one for read requests and the other one for write requests, i.e. read and write channel winners can start their internal bus transfer simultaneously. The supported arbitration is a 2-level round–robin scheme. The 2-level round-robin arbiter is implemented based on the regular round-robin arbiter, with one priority bit for each channel. The priority bits categorize the requests into two groups, high priority group and normal priority group. The arbitration is always favoring the high priority group. If there is no request from the high priority group, then the arbitration will move through the normal priority group.

For real time hardware devices, the read data buffer underflow or write data buffer overflow will cause significant system functional degradations. For the channels related to audio, video and graphics output, dHub provides QoS signaling. When those buffers’ levels reach a software programmed threshold, the QoS property of the dHub bus transactions will be set and based on user’s setting, DRAM controller may provide highest priorities for these transfers.

13.3 dHub bus gate keeperThe dHub bus gate keeper provides the block-level or subsystem-level integrity during reset. The bus gate keeper acts as a bus monitor during normal function mode. When the CPU wants to reset a subsystem including the dHub module, it needs to notify the subsystem before the real reset happening. Once notified, the dHub bus gate keeper will takeover the bus master to finish all the pending transactions for both read and write channel. After finishing all the bus transactions, the bus gate keeper will notify the CPU that the bus is idle by setting a register bit. This will ensure there are no pending bus transactions when the CPU resets the subsystem.

13.4 dHub interrupt and event synchronizationThe 88DE3010 dHub provides a mechanism to synchronize the data transfer between dHub channels, which can help to offload the CPU power for frequently serving the channels. For example, in the video decoding process, the horizontal context data can be stored in the DRAM, and later fetched back by the decoder engine for the next macro block line decoding. With the synchronization mechanism, one read channel and one write channel can be composed as a virtual FIFO in addition with the DRAM buffer, the CPU only need to do the channel setup and issue one dHub command for each channel once during each slice decoding. This synchronization can be achieved on dHub command level as well as MTU level. The synchronization is done through centralized semaphore counters in dHub. Each dHub Command or dHub MTU transfer can choose to wait for, increase, or decrease a semaphore counter. For read channels, the interrupt will be raised when the last beat of the data for that dHub command has been written into the dHub channel data buffer. For a write channel, the interrupt will be generated when the last internal bus transfer of the MTU had reached the write collection buffer of the DRAM controller. This will ensure the data coherency between the interrupt event and actual data in memory. The dHub interrupt generation is also based on the semaphore counter: based on user’s setting, an interrupt can be generated when

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certain semaphore reaches a pre-programmed level. The DMA data transfer and the interrupt coherency are based on the same semaphore mechanism.

13.5 dHub channel clear and flushClear is a feature applied for each dHub channel. When CPU programs the corresponding register to clear the selected channel, dHub will stop processing the current command, wait for all outstanding MTU transactions to be finished, and then update the corresponding register bit field to indicate that the clearing process has completed. The clear operation will also discard all the commands left inside the corresponding command FIFO, for write channel, all data left inside the corresponding data buffer will also be discarded.

Flush is a feature specific for write channel. It is used when the CPU can not predict how many data the producer will generate before it issues a dHub command. When the producer finishes, and there is not enough data left in the corresponding data buffer to compose one MTU, a flush is need to write the data left inside the data buffer to DRAM.

When CPU programs the corresponding register to flush a write channel, dHub will flush out the rest data inside the data queue and optionally generate the interrupt depending on the current dHub command.

13.6 dHub Channel ConfigurationEach channel has one configurable register including the following feature settings.

MTU: Configure the channel maximum transfer unit (MTU) size. It could be 8-byte, 32-byte, 128-byte or 1024-byte. The MTU size can only be changed when the channel is idle.QoS: Qos is an option that can be applied to any dHub channel. Once it is turned on, a channel will get higher arbitration priority over other channels when the data queue level reaches a certain level (half full for write data queue and half empty for read data queue).selfLoop: When selfLoop is enabled, the single dHub command will be repeated automatically until software stops and clears the dHub channel. intrCtl: This option is used as the interrupt generation scheme. By default, it is set to “0” which indicate the channel interrupt source is from the finish of the dHub command. When set to “1”, it will pick the channel idle status to generate the interrupt. START: Program “1” to this bit will enable the corresponding dHub channel.CLEAR: Write “1” to this bit will clear the dHub channel. Any extra data in the corresponding data queue and command in the command queue will be discarded. A detailed channel clear sequence is provided in the later chapter (software programming guide).FLUSH: Like CLEAR, all the command in the command queue will be discarded. Unlike CLEAR, this feature only applies to the write channel, and all the data left inside the data queue will be flushed out to DRAM.

13.7 dHub Command 13.7.1 dHub command for linear buffers

Each of the dHub command has a 4-byte header and 4-byte address pointer.

The 4-byte address pointer specifies the starting address on the DMA buffer. The DMA buffer can start at any byte address without any alignment limitation.

The dHub command header specifies the following:

size: size of DMA buffer supports 1 to 65535 transfer unit. Each transfer unit can be 1 byte or 1 MTU as specified by sizeMTU

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Data Streaming Hub (dHub)dHub Command



sizeMTU: data unit size, indicates whether byte or MTU is used as data unit where specifying the buffer size.semaOpMTU: semaphore operation level selection between MTU level or dHub command level. When command level is selected, the semaphore check will gate a dHub command start, or a semaphore update will happen after the DMA buffer operation is finished, otherwise the semaphore operation will happen for every MTU transfer. chkSemId and updSemId: specifies which semaphore the dHub command should update or check. There are totally 31 semaphores supported for each dHub. Setting the chkSemId and updSemId to be “0” will disable the semaphore operation. Interrupt: when enabled, an interrupt will be generated after the dHub command is finished

13.7.2 dHub commands for 2D buffers2D dHub channels can be used to load data from a rectangle buffer.

In addition to the data structure defined in normal dHub commands, the 2D dHub command has few extra parameters to specify the rectangle buffer in DRAM:

numLine: number of lines for a DMA bufferstride: number of bytes in each horizontal line, from 4 bytes to 65545 bytes; together with the size information, this specifies a rectangle buffer cropped out from a larger frame buffer, as illustrated in Figure 41.

Figure 41 shows relations among stride, numLine, start address, and size in a 2D buffer.

Figure 41: 2D Buffer Size Relationships

hdrLoop: It need to be set to “1”. A fixed dHub command header and the address generated from the 2D parameters are used to compose the 1D dHub command. start: Used to start the 2D command.clear: Used to stop and clear a 2D dHub command.interrupt: When this bit is set, an interrupt will be generated after the 2D command is finished.

DMA buffer

Source frame buffer

num

Line

stride

sizeStarting Address

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13.8 dHub in AVIO SubsystemAVIO subsystem includes Video Post Processor (VPP), Audio Post Processor (APP), Audio input and output (AIO), and Run-Length decoding Engine (RLE) for sub-title decoder acceleration for Blu-ray and DVD. 2 dHub engines (vppDhub and agioDHub) provide DMA read and write functionality for this sub-system.

Table 93: Channel assignment and default memory allocation of vppDhub

ChannelName

Channel Number

Channel Type

ChannelDirection

dHub Channel Function Bank*/Shared Size

MV.rd 0 2D R main video plane read #0 -- 8KB

MVfrc.rd 1 2D R main video plane FRC (frame rate conversion) read

MVfrc.wr 2 2D W main video plane FRC write

PIP.rd 3 2D R pip video plane read #1-- 8KB

PIPfrc.rd 4 2D R pip FRC read

PIPfrc.wr 5 2D W pip FRC write

DI0.rd 6 2D R de-interlacer read channel #0 #2 -- 8KB

DI1.rd 7 2D R de-interlacer read channel #1 #3 -- 8KB

DI.wr 8 2D W de-interlacer write channel #4 -- 8KB

BIU.rd 9 1D R BIU (bus interface unit) configuration channel

#5 – 8KB

HDMI.audio 10 1D R HDMI audio read channel

AUXfrc.rd 11 2D R AUX FRC read

AUXfrc.wr 12 2D W AUX FRC write

BG.rd 13 2D R background video read

TT.rd 14 1D R tele-text read channel

Note

The Bank number shows what dHub channels are sharing same buffer banks. The buffer size allocation among channels is only possible when they share the same bank.

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Data Streaming Hub (dHub)dHub in AVIO Subsystem



Table 94: Channel assignment and memory allocation for agDhub

ChannelName

Channel Number

Channel Type

ChannelDirection

dHub Channel Function Bank*/Shared Size

APPcmd.rd 0 1D R APP (audio post processing) command input

#0 – 8KB

A0.rd 1 1D R audio channel #0 read






A.wr 7 1D W audio write (MIC input)

APPdata.rd 8 1D R APP data input

APPdata.wr 9 1D W APP data output

MOSD.rd 10 2D R machine OSD (on screen display) read

#1 – 8KB

cursor.rd 11 2D R cursor plane read #2 – 8KB

GFX.rd 12 2D R graphic plane read #3 – 8KB

PG.rd 13 2D R PG/IG (presentation graphic and interactive graphic) read

#4 – 8KB

PGE.rd 14 1D R PG (RLE) engine stream load

PGE.wr 14 2D W PG(RLE) engine frame output

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13.9 dHub in pBridgeThe pBridge in the low speed peripheral sub-system provides the DMA capabilities and is based on dHub module. Table 95 shows the dHub channel assignment for pBridge.

Table 95: Channel assignment and memory allocation for pBridge

ChannelName

Channel ID

Buffer Type

Channel Type

Function Bank

DMA.rd 0 1D R pBridge DATA read channel #0 – 1.5KB

DMA.wr 1 1D W pBridge DATA write channel

DES0.rd 2 1D R descriptor channel #0 read






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2D Graphics EnginePerformance



14 2D Graphics EngineThe 88DE3010 2D Graphics engine is a high-performance 2D graphics core. It is designed to accelerate the GUI (Graphics User Interface) and menu display rendering.

The 88DE3010 2D Graphics engine supports the following features:

Bit blit, stretch blit, pattern blit, and fast clearLine drawingRectangle fillMono expansion for text renderingROP2, ROP3, ROP4Alpha blending90 degree rotationVideo data format conversionHigh quality scalingMaximum frame size of 32K x 32KClipping window

14.1 PerformanceTable 96 lists the performance summary of the 88DE3010 2D Graphics engine. Note that this is the maximum pipeline capability. The overall graphics system performance of 88DE3010 will also depend on the loading of SoC CPU, memory bandwidth, and internal bus. The 88DE3010 Graphics engine clock speed can be adjusted at any time. The maximum clock frequency is 400 MHz. For the details of clock selection, refer to 88DE3010 Datasheet part 2, Global Unit Section.

Table 96: Graphics Engine Pipeline Performance

Primitive Performance Source/Destination Overlap

Clipping

Lines 1 pixel/cycle N/A supported

Rectangle 4 pixels/cycle for 16 bpp2 pixels/cycle for 32 bpp

N/A supported

Clear 4 pixels/cycle for 16 bpp2 pixels/cycle for 32 bpp

N/A supported

Blit 4 pixels/cycle for 16 bpp2 pixels/cycle for 32 bpp

If rotation operation is needed between source and destination, then performance is 1 pixel/cycle.

Overlap is allowed supported

Stretch blit 1 pixel/cycle No overlap allowed supported

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14.2 2D Graphics Sub-system DescriptionFigure 42: 88DE3010 2D Graphics Block Diagram

The 88DE3010 2D Graphics engine is connected to the SoC through a register access interface and a memory access interface.

The 88DE3010 2D Graphics engine occupies 256 KB of memory mapped space for register access. An error response will be returned if an illegal access is detected to an undefined address location. Only 4-byte aligned reads and writes are permitted in the register interface. The register access interface is used for control, configure, and status access of the graphics engine hardware modules.

The memory access interface is used by the graphics engine to read/write data from the DRAM. The 2D graphics engine will use this interface to:

Load commands by Command DMA EngineRead and write source and destination data by the Pixel Engine

Monochromeexpansion

1 pixel/cycle No overlap allowed supported

Filter bit 1 pixel/cycle N/A N/A

Table 96: Graphics Engine Pipeline Performance

Primitive Performance Source/Destination Overlap

Clipping

Memory Requests Arbiter

2D EngineRegisters

DebugTest

DMA Read

Src Cache Read

Return Bus

Memory Bus

Register Access

Interface

Memory Access

Interface

Dst Cache Read

Dst Cache Write

Reg

iste

r Bus

SOC Xbar

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2D Graphics Engine2D Graphics Engine Pipeline Description



14.3 2D Graphics Engine Pipeline DescriptionFigure 43 illustrates the functional diagram of the 88DE3010 2D graphics engine pipeline.

Figure 43: 88DE3010 2D Graphics Engine Pipeline

Mask

6464

64

6464

64 64

Memory AccessInterface

MemoryRequestArbiter

DMA

DrawingEngine

PrefetchSourceCache

DestinationCache

YUV/RGBTo

ARGB8Conversion

FilterBlit

ROP/Blender/Fill

ARGB8To

Destination Format

Conversion

ARGB8To

Destination Format

Conversion

PatternMemory

6464

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14.3.1 Hardware Engine PrimitivesAll the primitives support one rectangle clipping area. Only the pixels within the clipping area are included in the clipping operation. The pixels outside the area are not affected. All the primitive operations are done based on 8x8 pixel tiles.

14.3.1.1 Line DrawingLines are rendered using Bresenham algorithm and only Binary Raster Operation (ROP2) is supported. The inputs of ROP2 are from internal pattern memory and the destination buffer in DRAM. The color values are decided by the ROP2 operation and the destination locations to be updated are decided by the Bresenham algorithm.

14.3.1.2 Rectangle Fill and ClearRectangle fill fills a rectangle area with a given color. To fill a rectangle, an 8x8 pixel pattern memory in the graphics engine has to be filled with a solid color. Then ROP2 (pattern, destination) is used to fill the rectangle.

Clear can also be achieved by rectangle fill.

14.3.1.3 Stretch and Non-Stretch Bit BlitBit Block Image Transfer (BLIT) transfers data from one area of a memory (source) to another area of the memory (destination). The source and destination can be from the same or different memory spaces. Both source and destination must be described by a rectangular area. The source and destination rectangles can be the same size or different sizes, in which case, it becomes a stretch or shrink blit.

Bit blit supports ROP2, ROP3, and ROP4 which includes source, destination, pattern, and an optional transparency color. For bit blits where the source rectangle is the same size of the destination rectangle, the performance can be 2 pixel per cycle if any of the source or destination buffer is in 32 bpp format, and 4 pixel per cycle only if both the source and the destination buffers are in 8 bpp format or 16 bpp format.

Table 97 shows the inputs for each ROP for bit blit.

The source and destination are image buffers. The pixel data from both source and destination buffers can be loaded as the blitter inputs. The pattern is the 8x8 pixel pattern memory inside the Graphics engine. For ROP4 operation, the mask input is one bit per pixel data loaded from internal mask buffer, which is loaded by command stream. It is used to conditionally select one of the two ROP3 operations.

For stretch blits where source and destination rectangle sizes are different, the performance is one pixel per clock cycle. The modified Bresenham algorithm is used for fast stretching. The stretch factor is expressed in unsigned 15.16 fixed-point format (15 bits of integer part and 16 bits fractional part). This allows the stretch blits to scale up/down the source image by a factor of up to 32768 times on each direction. The granularity of the scaling ratio is 1/32768. The source buffer and the destination buffer addresses of the stretch blit are not allowed to overlap. If the stretch is not involved, then the source and destination buffers are allowed to overlap.

Table 97: ROP Inputs

Source Pattern Destination Mask

ROP2 X X

ROP3 X X X

ROP4 X X X X

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The tile operation sequence for bliting is not fixed and is determined automatically by the hardware depending on the relative position of the source and destination rectangles. So that if rectangles overlap, the operation would still be performed correctly.

14.3.1.4 Monochrome Expansion / Mask blitMonochrome expansion is used to expand 1 bpp information into 16 bits or 32 bits color information. It’s done by using ROP3 or ROP4 operation with monochrome source and mask map from command streams as shown in Table 98.

Masked blit is achieved using ROP4 bit blit with monochrome mask for selection. Each output pixel is a combination of source, pattern, monochrome mask map, and destination. The 1 bit mask map is used to select two (foreground or background) ROP3.

14.3.1.5 Filter BlitFilter blit takes a source image in rectangle form and maps it into a destination rectangle with a different size. It supports a high quality re-sampling filter with kernel sizes of 1, 3, 5, 7, and 9. The stretch factor format is expressed in unsigned 15.16 fixed-point format. If the stretch factor is less than 0x00010000, the image is shrunk. The smallest that image can be shrunk is 1/32768 and the maximum that an image can be stretched is 32768 – 1/32768. Filter blit does not support any ROP. The 88DE3010 graphics engine uses a 9 tap filter for the filter blit operation. The actual number of taps can be configured by software is either 1, 3, 5, 7, or 9, which means it takes 1, 3, 5, 7, or 9 source input pixels to generate a single destination pixel. The filter kernel is programmed by software into a coefficient table. The coefficient table has up to 9 (taps) x 32 (phases) entries. Each entry is a signed 15-bit coefficient. For each filter blit operation, only one dimension filtering (X or Y) can be applied.

For each filter blit operation, if the coefficient table is not reprogrammed, the previous filter kernel will be used. Programming of the coefficient table is achieved through the command stream.

To calculate a pixel in the destination buffer, the source pixels could start from a fractional location because of scaling factor. In this case, software can program a source origin fraction register to indicate what fractional location in the source buffer the filter blits should start from.

The actual coefficient value filter blit engine used for each pixel is calculated from the coefficient table, scaling ratio, and starting phase. This calculation is performed by hardware.

Table 98: Inputs for Monochrome Expansion

Input Source

Source 1 Source 2 Source 3 Source 4

ROP3 1bpp Monochrome source from command stream

Internal 8x8 pattern memory

Destination Buffer from DRAM

NA

ROP4 1bpp Monochrome source from command stream



1bpp mask map from command stream

Table 99: Inputs for Mask Blit

Input Source Source 1 Source 2 Source 3 Source 4

ROP4 Source buffer from DRAM



1 bpp mask map from command stream

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On the rectangle boundary of filter blit operation, some out of boundary pixels may be needed for filtering. In this case, software can program the hardware to ignore the boundary and to load the data beyond the boundary in the source buffer. Otherwise, hardware will repeat the existing boundary pixels for processing.

14.3.2 Other Features

14.3.2.1 Rotation90° clockwise/counter-clockwise rotation is supported for all primitives.

14.3.2.2 Transparency ModeIn 88DE3010 2D Graphics Engine, it supports three different transparency modes for the pixel data from the source buffer:

Opaque: No transparencyMasked transparency: A pixel in the destination buffer won’t be modified if the associated mask bit is zero.Conditional transparency: A pixel in the destination buffer won’t be modified if the associated input pixel from source buffer matches the specified value. The specified value is programmable by software. This mode is not available in monochrome expansion.

14.3.2.3 ClippingThe 88DE3010 2D graphics engine only supports one clipping rectangle for all primitives except for Filter Blits. The filter blit operation doesn’t support clipping.

14.3.2.4 Data FormatsThe 88DE3010 2D graphics engine supports little endian data formats. The source data formats supported by the 88DE3010 2D graphics engine are:

A1R5G5B5 (1 bit Alpha component followed by 5 bits Red, 5 bits Green, and 5 bits Blue components)A4R4G4B4A8R8G8B81-bit monochromeR5G6B5X1R5G5B5 (1 don’t care bit followed by 5 bits Red, 5 bits Green, and 5 bits Blue components)X4R4G4B4X8R8G8B8UYVYYUY2

The destination data formats supported by the graphics engine are:

A1R5G5B5A4R4G4B4A8R8G8B8R5G6B5X1R5G5B5X4R4G4B4X8R8G8B8

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14.3.2.5 ARGB Data ConversionThe ARGB primitive operations are 32 bits ARGB, i.e. 8 bits for alpha and each color component. For source input that is less than 8 bits, it will be up-sampled by replicating existing bits to higher-order bits. For destination output that is less than 8 bits, the final result will be down-sampled by truncating the lower-order bits.

14.3.2.6 YUV to RGB ConversionFor the filter blit, YUV data can be converted into 8-bit per component RGB format before the filter blit operation. Filter blit doesn’t support YUV format in destination buffer.

The YUV to RGB conversion is done using the following hard-coded approximation:

16 < Y < 235

16 < U < 240

16 < V < 240

A = Y – 16

B = U – 128

C = V – 128

R = clip ((298*A + 409*C + 128) >> 8)

G = clip ((298*A – 100*B – 208*C + 128) >> 8)

B = clip ((298*A + 516*B + 128) >> 8)

The Y, U and V components are clamped prior to the conversion. Y is clamped between 16 and 235 inclusively. U and V are clamped between 16 and 240 inclusively.

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14.3.2.7 Alpha BlendingThe 88DE3010 2D graphics engine supports the following alpha blending equations:

Cd = Fs * Cs’ + Fd * Cd’------------ (1)

Ad = Fs * As” + Fd * Ad”----------------(2)

Where

Cs’ is the source color component (adjusted for Non Pre-Multiply (NPM) if specified)

Cd’ is the destination color component (adjusted for NPM if specified)

As” is the modified source alpha component

Ad” is the modified destination alpha component

Fs is fraction of the source that contributes to the final value

Fd is fraction of the destination that contributes to the final value

As shown in equation (1) and (2), the Cd and Ad outputs of 88DE3010 alpha blending engine are pre-multiplied format.

The color components of the above equation are 8 bits and the alpha value is 9 bits (unsigned 1.8 fix point format; alpha value cannot greater than 0x100). The intermediate results are varies to prevent any bit lost. The final result will be truncated to 8 bits for color components and 9 bits for alpha value.

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Figure 44: Alpha Blending Stages

The alpha blending is done in 5 logical stages:

In transparent/opaque conversion stage, the incoming alpha (source or destination independently) can be inverted if needed to match the internal alpha rule. Internally, an alpha of 0 means transparent, while an alpha of “0xFF” means opaque. External content might follow the opposite rule. The output of the block is either As (Ad for destination) or 1-As (1-Ad for destination).

1-

1-0 1

As Ags

As’

As’’

Cs

Cs’

Fd

1-

1-0 1

Ad Agd

Ad’

Ad’’

Cd

Cd’

Fs

Transparent/Opaque

conversion

GlobalValue

Substitution

BlendingFactor

Ganeration

NPMAdjustment

FinalBlending

Cd Ad

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In global value substitution stage, a global alpha value from a register can be used to substitute or scale the incoming alpha. An incoming alpha As can pass-through, be directly substituted by Ags (global alpha) or scaled by the global alpha value (As * Ags). The source and destination have distinct global alpha values.

In blending factor generation stage, the blending factors are generated (refer to Table 100). Each alpha can take the values 0, 1, A or 1-A depending on the blending mode.

In the NPM adjustment stage, for non-pre-multiplied color components, the actual color component value is generated by multiplying the incoming color component with the modified alpha value: Cs’ = Cs * As”, Cd’ = Cd * Ad” for destination color components. For pre-multiplied components, they directly pass-through the next stage.

The final blending stage implements the operations described by equations (1) and (2).

Table 100 shows how the fractions (Fs and Fd) take values in different blending modes.

To control the blending modes, the following register fields are present:

1 bit for transparent/opaque conversion for source alpha1 bit for transparent/opaque conversion for destination alpha2 bits for source alpha modifications, to specify the 3 cases (As, Ags, As*Ags)2 bits for destination alpha modifications, to specify the 3 cases (Ad, Agd, Ad*Agd)4 bits to select between the 12 blending modes1 bit for source NPM / PM mode1 bit for destination NPM / PM mode8-bits for global source alpha8-bits for global destination alpha

14.4 2D Graphics Engine Command DMAThe 88DE3010 2D Graphics engine has dedicated DMA engine to load commands from DRAM. To start DMA engine to fetch commands, CPU should program the starting address into AQCmdBufferAddr register and then kick off DMA engine by programming the enable bit in AQCmdBufferCtrlRegAddrs register. For the details of the register definition, please refer to DS-III,

Table 100: Fs/Fd Selection for different Blending Modes

Blending Modes Fs Fd

Clear 0 0

SRC 1 0

DST 0 1

SRC_OVER 1 1 – As”

DST_OVER 1 – Ad” 1

SRC_IN Ad” 0

DST_IN 0 As”

SRC_OUT 1 – Ad” 0

DST_OUT 0 1 – As”

SRC_ATOP Ad” 1 – As”

DST_ATOP 1 – Ad” As”

XOR 1 – Ad” 1 – As”

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2D Graphics Engine2D Graphics Engine Command DMA



88DE3010 Register Definition. User should prepare Graphics commands and data buffers before enables DMA engine to load the command stream.

The 88DE3010 2D Graphics Engine provides the flexibility of setting up any number of buffers asynchronously as the DMA engine starts. These buffers can be chained by placing a WAIT and LINK command at the end of each buffer. WAIT/LINK gives the DMA engine the start address of the next buffer to process, and DMA engine will wait until a signal arrives indicating that data in the next buffer is ready for processing.

Graphics DMA engine will keep processing data until it reaches an END command. When END is received, DMA engine switches to idle state and remains in idle until AQCmdBufferCtrlRegAddrs enable bit is programmed again.

14.4.1 Command Stream FormatThe command parser processes loaded command streams and controls the various hardware modules to complete the operations. This section describes the type of commands supported by the command parser. All the command buffer starting address must be 8 bytes aligned.

14.4.1.1 LOAD_STATEDescription: Load command to program one or more 2D Graphics engine registers.

Parameters:

Address: Starting address of the registers to be programmed by LOAD_STATE command. It’s a 13 bits internal 4-byte register address.Count: The number of registers to be programmed. The registers to be programmed by the LOAD_STATE command must have continuous addresses. The maximum count is 4095.Values: The register values that need to be programmed. For a LOAD_STATE command with Count = N, there must have N 4-byte register values following LOAD_STATE command.

14.4.1.2 START_DEDescription: Start command for the 2D drawing/Blit engine. Proper states for sources and destination buffers must be loaded before this command is issued.

Parameters:

Rectangle Count: The number of rectangles in operation.Rectangle parameters: The parameters for the rectangles need to be processed. The START_DE command rectangle Count = N, there must have N parameter sets. For each parameter set, there are:• Left: 16 bits horizontal pixel location for upper left corner of destination rectangle.• Top: 16 bits vertical pixel location for upper left corner of destination rectangle• Right: 16 bits horizontal pixel location for lower right corner of destination rectangle• Bottom: 16 bits vertical pixel location for lower right corner of destination rectangle

When a START_DE command has multiple destination rectangles, the operation states must be the same for each rectangle, except source and destination coordinates.

The 88DE3010 2D Graphics engine supports absolute and relative source addressing modes. In absolute mode, the source coordinates are treated as absolute coordinates inside the source surface. In relative mode, the source coordinates are used as the offsets from the destination coordinates. For each destination rectangle, its associated source rectangle coordinates are calculated from destination coordinate plus the offset.

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14.4.1.3 LINKDescription: LINK command provides the address pointer to the next command buffer to be loaded.

Parameters:

Prefetch: Number of 64-bit words to fetch.Address: 32 bits address of the next command to link to. The address must be 8-byte alignment.

14.4.1.4 WAITDescription: WAIT command notifies command loading engine to wait before loading the next command.

Parameters:

Delay: 16 bits; number of clock cycles to wait.

14.4.1.5 ENDDescription: END command instructs the DMA engine to stop command buffer execution. Set the OPCODE field to END.

Parameter: None

The last command in each command buffer should be either an END command or a LINK command.

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2D Graphics EngineInterrupts



14.5 Interrupts Figure 45: Interrupt Generation Scheme

The Graphics can send an interrupt signal to the SoC CPU. The interrupt will remain asserted until the SoC CPU clears the interrupt by reading the interrupt acknowledge register. Each bit of the acknowledge register represents one of the 32 possible events that the 2D Graphics engine can signal to the SoC CPU.

By setting or clearing the bits of the interrupt enable register, the programmer can also control which of those events will generate an interrupt. The reset default value of all the interrupt enable bits are 0, e.g., all the interrupts are disabled to SoC CPU after reset.

The meaning of interrupt events are all user defined by software and they are not link to any hardware event/status.

The interrupt is triggered by programming the AQEvent register through a LOAD_STATE command. Once AQEvent register is programmed, an interrupt will be triggered after either completion of command loading or completion of pixel engine operation of the last command. This can be enabled by the event source bit fields in AQEvent register.

Command Generation

DRAM

CMD1

CMD2

LOAD_STATE (AQEvent)

CMD Buffer

2D Grphics Engine

5 bitsEvent ID

Int Enable Reg

Int Ack. Reg

Interrupt toSoC CPU

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Doc. No. MV-S104738-02 Rev. -- CONFIDENTIAL Copyright © 2010 MarvellPage 196 Document Classification: Proprietary Information April 1, 2010, Draft

Not Approved by Document Control. For Review Only.

15 Video Post Processing (VPP)

Figure 46: High-level block Diagram of 88DE3010 device's Video Post Process Engine

3D VNR +3D DI +

DET

Main16-bit YUV

PIP16-bitYUV

IG8/32-bit

Main

PIP

IG

AUX

Scalingstage

CPCB0

pl-1

pl-2pl-3

pl-3a

CPCB2(only TG)

pl-1

PROG0

INT0

PROG1

PROG2

INT2

HDMIVOP

HDMITX

AHDVOP

ASDVOP

HDMIPHY

6-chVideoDAC

DV0VOP

DV1VOP

DV08-bit data+

4-bit ctrl

Color Processing

&Channel Blending

stage

Format Conversionstage Video Output

stage

dHub0dHub1

SWITCH

HDMI

HD Y

BG16-bit YUV

LUT

PG8/32-bit

PGLUT

Cursor8/32-bit

MOSD8/32-bit LUT+CSC

DV18-bit data+

4-bit ctrl

pl-3b

pl-3c

pl-3d

CPCB1(no CMU)

pl-1

pl-2pl-3

pl-3a

pl-3b

pl-3c

pl-3d

3d

1

2

3

3a

3c

Memory BusdHub0

Memory Bus

dHub1

3b

Detail

det

LUT+CSC

SDEncoder

HDEncoder

Interrupt

BIU

Register Bus

Data Loadingstage

HD PbHD Pr

CVBSS-Video YS-Video C

CMU

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Video Post Processing (VPP)

Copyright © 2010 Marvell CONFIDENTIAL Doc. No. MV-S104738-02 Rev. --April 1, 2010, Draft Document Classification: Proprietary Information Page 197


The VPP (video post processing) module in the 88DE3010 device loads up to 7 planes of video or graphics data from DRAM frame buffers at the desired refresh rate, applies QDEOTM video processing to enhance the video quality, converts various input format/resolution into target format and resolution, position and finally blends the associated planes to form one or two independent high definition video outputs to HDMI transmitter and HD component encoder. The maximum refresh rate is 60P at 1920x1080 resolution. One of the high definition output can also be down converted and simultaneously output through 88DE3010’s NTSC/PAL Composite and S-Video output ports. Figure 47 illustrates the VPP pipe-line structure in 88DE3010.

The video post processing in 88DE3010 have the following stages:

Data loading stageFormat conversion stageScaling stageColor processing stageBlending stageOutput stage

In the data loading stage (dHub1), video and graphics data are loaded from DRAM buffers, for each of the input plane, there is one SRAM based anti-jitter buffer to tolerate the DRAM bandwidth fluctuations. The allocation of the SRAM between planes can be re-configured for different applications through S/W initialization.

In the format conversion stage, the data depth conversion (LUT, Look Up Table), color space conversion (CSC) and data sequence conversion for graphic planes are performed, so that the data can be further processed by the scalers. For main and PIP video plane, the QDEO™ video processing elements, including motion-adaptive 3D de-interlacing (3D-DI), motion-adaptive 3D noise reduction (3D-VNR), and part of the detail edge enhancement (DET) are applied in this stage.

The VPP supports the following 7 plane inputs: 3 Video planes (Main, PIP and BG) and 4 graphic planes (PG, G0, G1 and G2)

Main Video, input data format is 16-bit YUV 4:2:2, support up to 1080p or 1080i resolutionPIP Video, input data format is 16-bit YUV 4:2:2, support up to 1080p resolutionBack Ground (BG), input data format is 16-bit YUV 4:2:2, support up to 1080p resolutionInteractive Graphics (IG or C0), input data format is 8-bit LUT index or 32-bit ARGB/AYUV, up to 1080p resolutionCursor (G1), input data format is 8-bit LUT index or 32-bit ARGB/AYUV, up to 1080p resolutionMachine OSD (G2), input data format is 8-bit LUT index or 32-bit ARGB/AYUV, up to 1080p resolutionPresentation Graphics (PG or G3), input data format is 8-bit LUT index, or 32-bit ARGB/AYUV, up to 1080p resolution

In addition, the 88DE3010 VPP supports AUX input which is downscaled version (720x576p for PAL, and 720x480p for NTSC) of one of the blenders. The AUX video input channel directly drives the NTSC/PAL S-video & Composite output after interlacing.

The 88DE3010 has 5 scalers in scaling stage - the Main video, PIP video, IG, and PG planes can be scaled before selected for blending. The scaler in Auxiliary channel can be used to down-scale one of the blenders output to DRAM frame buffer for simultaneous NTSC/PAL output. Part of the edge enhancement processing for main video plane happens in the scaling stage too.

In the color management stage, the Main and overlayed PIP video is processed by a CMU (Color Management Unit). The processing includes Adaptive Contrast Enhancement (ACE™), Intelligent Color Remapping (ICR™) and independent three-channel gamma manipulation.

1. Data Streaming Hub (dHub) is the multi-channel DMA Engine of 88DE3010 device.

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In the blending stage, the two main blenders (CPCB0 and CPCB1) can select any of the 7 input planes, through the switch, and blend them into two outputs. The Z-order of the blending is completely programmable through the layer-to-plane selection inside the blenders. Part of the edge enhancement processing for main video plane happens in the CPCB0 too. The additional auxiliary blender (CPCB2) simply loads the downscaled SD data from DRAM and send to standard definition TV encoder.

In the output stage, the output of two main blenders (CPCB0 and CPCB1) can be switched to HDMI transmitter, H/SD component encoder and two digital video output ports. The data from the auxiliary blender can only be sent to the SD encoder for S-video and Composite output.

The video output timing generators can be driven by three independent clock sources. All the three clock sources are generated through an internal AVPLL locked to a 25 MHz crystal oscillator. All required frequencies for driving audio and video output from 27 MHz to 297 MHz can be generated through the AVPLL. Each of the clock sources can be adjusted with in ± 1.5%, the granularity of the adjustment is 2 PPM. The adjustment can be made through AVPLL register interface.

The VPP supports the following video output interfaces:

HDMI 1.3a compliant, supports 480i/p, 576i/p, 720p, 1080i/pHD YPbPr component output, supports 480p, 576p, 720p, 1080i/pSD composite (CVBS) and S-Video outputs (NTSC/PAL)BT656/SMPTE standard digital video output supporting up to 1080p, when in Marvell proprietary DDR output mode, supports 2 digital video outputs up to 1080p resolution.

15.1 Video Post Processing Feature ListAt input format conversion stage, main video plane supports: • 3D spatio-temporal noise reduction for SD and HD video

• Motion-adaptive• Fleshtone adaptive• Automatic noise metering• Edge-preserving impulse noise reduction

• 3D de-interlacing for SD and HD video• Per-pixel motion-adaptive• Automatic film-mode with edit and mixed content detection• Manual film-mode option using repeat field flag (RFF) from 88DE3010's video decoder• Vector Interpolation (VI™) for clean, angled moving edges

• Luma detail enhancement and Transient improvement (luma & chroma)At input format conversion stage, all the graphics planes support• LUT based 8 bit to 32bit AYUV and ARGB color look up• Direct AYUV444 or ARGB444 input with various byte sequencesFor all the video planes, the scalers can be set in in-line mode or offline mode. In in-line mode, the scaled output is directly sent to next stage. In off-line mode, the scaled output is sent to next stage through a frame buffer in DRAMScalers in Main and PIP video channel support:• 12 taps horizontal, 8 taps vertical for SD video, 12 taps horizontal, 5 taps vertical for HD• Non-linear 3-zone horizontal aspect ratio correctionThe auxiliary video path can be used to provide simultaneous standard definition version of the main high definition outputTwo graphics channel has scalers with:

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Video Post Processing (VPP)VPP Functional Description



• 12 taps horizontal, 8 taps vertical for SD video, 12 taps horizontal, 3 taps vertical for HD• Non-linear 3-zone horizontal aspect ratio correctionIn the blending stage, 88DE3010 has 2 independent blenders in YUV domain (CPCB0 and CPCB1); the AUX blender (CPCB2) is a simple data formatter with timing generator. Full selection of the 7 processed input planes to either CPCB0 or CPCB1 in any Z order (with limitation that no plane can be selected for both blenders simultaneously) CPCB0 features• Supports up to 7 plane blending in YUV color domain• High definition up to 1080p timing generator• Simultaneous output in interlaced and progressive output format Color management on CPCB0 channel:• Adaptive Contrast Enhancement (ACE™), Intelligent Color Remapping (ICR™) and

independent three-channel gamma manipulation for Main & PIP planes• Adaptive Contrast Enhancement (ACE™) expands dark regions without over-enhancing or

clipping brighter regions (for Main & PIP planes)• Intelligent Color Remapping (ICR™) enhances visual quality using all of the available gamut

(for Main & PIP planes)• Independent three channel gamma LUTs (RGB or YCbCr) (for Main & PIP planes)• Film Grain Generator (for Main & PIP planes)CPCB1 features• Supports up to 7 plane blending in YUV color domain• High definition up to 1080p timing generator• Output in progressive output format onlyCPCB2 features• Standard definition timing generator only• Input data is directly loaded from DRAM• CPCB2 can be used to drive simultaneous SD output of the HD output on HDMI and/or

Component

15.2 VPP Functional DescriptionThis chapter describes all the functions of VPP in detail. The dHub in Data Loading stage is described under dHub section of the datasheet.

15.3 Main Video PlaneFigure 47 shows the components of the Main video pipeline:

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Figure 47: Details of Main Video Plane pipeline

Main video pipeline processing includes 3D De-interlacer, 3D-VNR (Video Noise Reducer), Detail/Edge Enhancer and scaler (Main video scaler and Detail scaler).

The input data from DRAM are buffered in tolerance buffers before loaded by the data loader and sent to 3D-DEINT and VNR engine. The expected input data format is YUV422 with flexible data orders as shown in the Table 101.

vppDHub (dHub0)

Loader

3D VNR +3D DEINT +DETAIL (EE)

26-bit

26-bit

26-bit

16-bit

16-bit

SWITCH

Bank01024x64

1-portSRAM

Bank21024x64

1-portSRAM

AXI64-bit

Bank31024x64

1-portSRAM

Bank41024x64

1-portSRAM

Data Loading stage Format Conversion stage Scaling stage

Loader

Loader

Loader

16-bit

Color Processing &Channel Blending stage

MainVideoScaler

DetailScaler to CPCB0

Loader

Loader

pl-1 (Main)

Table 101: YUV422 Pixel Format in DRAM

Format DescriptionAddress in system Memory

Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0

0 UYVY Y3 V2 Y2 U2 Y1 V0 Y0 U0

1 VYUY Y3 U2 Y2 V2 Y1 U0 Y0 V0

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Video Post Processing (VPP)Main Video Plane



All the 7 VPP planes are of 2D-type – software can select a window of DRAM frame buffer for VPP to load. The Main video pipeline requires that the first pixel data in system memory starts with a clean chroma boundary (i.e., it has to start with pixel that has Cb). Also, the no. of pixels per a line has to be an even number.

The pixel data from Data Loading stage is fed to Format Conversion stage which includes 3D DEINT, 3D VNR and DETAIL (Edge Enhancer) functions. When the video input is non-interlaced, the 3D DEINT function is bypassed. In the interlaced input case, the 3D DEINT generates progressive frames at its output. In any case, scaler is always fed with progressive input.

The Main video scaler can operate in 2 modes: inline and offline modes (please refer to Scaler section for more details). The offline scaler write-back and read channels (of Main & PIP scalers) are also of 2D-type, meaning user can choose to write the scaled image in a 2D-fashion in lieu of linear order (could be used to draw thumb-nails in DRAM). The no. of pixels per line of scaled image has to be multiple of 4 when 2D features of the offline scalers are used. The multiplexer after Main video scaler decides whether data from scaling stage or from Data Loading stage goes to the Blending stage (inline vs offline mode of Main video scaler). The output of multiplexer goes to the switch which decides whether Main video is routed to CPCB0 or CPCB1 of Blending stage. The Detail scaler is a part of the 88DE3010’s Edge Enhancement solution and its output directly goes to CPCB0 of Blending stage.

15.3.1 3D Video Noise Reducer (VNR)The 3D video noise reducer reduces Gaussian noise present in the incoming video. The noise reduction is done on 4:2:2 YCbCr data. This block is capable of accepting interlaced and progressive data.

The noise reduction can be done in spatial domain, temporal domain, or a mix of both.

A spatial domain filter is used for moving areas of the video. A temporal filter is used to clean static regions. A spatio-temporal blender detects the motion in the video and blends the outputs of the spatial and temporal filters for best results.

Temporal noise reduction requires off chip field buffer storage. This memory is shared with the 3D De-interlacer, helping in optimal usage of DDR memory and bandwidth. There is also an on-chip noise estimator which estimates the amount of noise present in the incoming video. The estimated noise can be used by software to control the amount of noise reduction.

The block diagram of 3D Noise Reducer is shown in Figure 48.

2 YUYV V2 Y3 U2 Y2 V0 Y1 U0 Y0

3 YVYU U2 Y3 V2 Y2 U0 Y1 V0 Y0

Table 101: YUV422 Pixel Format in DRAM

Format DescriptionAddress in system Memory


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Figure 48: Block Diagram of Video Noise Reducer

15.3.2 3D De-interlacer (DEINT)All interlaced SD/HD video signals in the main video channel are de-interlaced using QDEOTM 3D motion-adaptive technology with film cadence handler block to detect the different types of pull down for video.

The de-interlacer employs proprietary vector interpolation algorithm that eliminate the jaggies usually generated on angled edges in moving video sequences.

The Film Cadence Handler is capable of detecting the 3:2, 2:2, 2:2:2:4, 2:3:3:2, 3:2:3:2:2, 5:5, 6:4, 8:7, and two programmable cadence in parallel by using pull down detection algorithms that employ frame based and field based motion to correctly detect fields originating from the same film frame, and dropping back into video mode when the input changes to video. Also, there is two-region cadence detection. This allows for optimal handling of very common case of film with video news ticker.

There is a delay of one input field/frame when 3D De-interlacer/ 3D VNR is turned on in the path. Block diagram of 3D De-interlacer is shown in Fig 2-3.

FleshTone

Blender

SpatioTemporalBlender

MotionEstimator

Output Data

Frame Buffer

Input Data

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Video Post Processing (VPP)Main Video Plane



Figure 49: Block Diagram of Deinterlacer

15.3.3 Edge Enhancement (EE) – Detail ChannelThe edge enhancer (EE) consists of two independent modules, luma detail enhancement circuit and transient improvement (LTI & CTI) circuit.

In 88DE3010, luma edge enhancement is a combination of the detail enhancement, video scaling and luminance transition improvement. Application of detail enhancement is intended only for fine details and LTI kicks in only for large amplitude transitions. Detail EE is placed before scaler and LTI is placed after scaler as shown in Figure 50. Detail enhancer produces two outputs. One is the video signal Ydet which may or may not be enhanced. Second output is the detail signal ΔYdet which represents the gained fine details of the video frame. Both Ydet and ΔYdet get scaled through separate scalers. Luminance transient improvement is computed on the scaled video Yscl. The final edge enhancer output is the sum of the scaled video, LTI improvement and the scaled detail enhancement signal (Eqn 1).

Chroma edge enhancement consists only of CTI post scaler. CTI can be applied only on 444 chroma signal. So, CTI module is preceded by a 422 to 444 upsampler which can be enabled when required.

Vector Interpolation

Motion Engines

SpatioTemporalBlender

Film CadenceHandler

Current Field

Next Field

Previous Field

Current Field

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Figure 50: Block Diagram of 88DE3010's Luma Edge Enhancement Solution

YEE_OUT = YSCL + ΔYDET-SCL + ΔLTI (Eqn 1)

Detail channel applies only to Main video plane input. EE has logic scattered in Format Conversion stage (Detail EE), Scaling stage (Detail scaler) and Blending stage (CPCB0 – LTI, CTI and merge detail scaler output with Main video scaler output).

15.4 PIP Video planeFigure 51 describes the PIP post processing pipeline of 88DE3010.

Figure 51: PIP Post Processing Pipeline

PIPScaler

SWITCH

Bank11024x64SRAM

AXI64-bit

vppDHub (dHub0)

Data Loading stage Format Conversion

stage

Scaling stage Color Processing &Channel Blending stage

Loader

Loader

Loader

pl-2 (PIP)

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Video Post Processing (VPP)BG Plane



Unlike Main video plane, PIP video plane doesn't have Video Noise Reducer, De-interlacer or Edge Enhancement. PIP input data format is 16-bit YUV 4:2:2. PIP input channel is of 2D type allowing user to process part of the image.

The PIP channel implements Scaler which can work in both in-line and off-line modes. PIP offline scaler connections also support 2D write/read. This feature can be used to draw thumb-nails in DRAM using PIP channel and later any video channel could be used to show the thumb-nail pattern on the screen.

15.5 BG PlaneFigure 52 describes the post-processing for BG video plane:

Figure 52: Post Processing for BG Video Plane

BG input data format is 16-bit YUV 4:2:2 and supports all the flexible data order explained under Main video plane section. The chroma up-samplers required to convert 4:2:2 BG data to 4:4:4 BG data (before overlay) are implemented in CPCB0/1.

There is no scaler function in BG plane.

15.6 Graphic PlanesFigure 53 illustrates the graphic plane post-processing in 88DE3010. All 4 graphic planes support either 8-bit LUT index or 32-bit ARGB/AYUV input formats. When the input format is chosen to be LUT, the loader unpacks the input 64-bit data to 8-pixels; unpacks to 2 pixels when the input format is 32-bit. The LUT block implements 256x32 SRAM which is loaded by software with the appropriate look-up table. All 4 graphic planes have dedicated Color Space Converter (CSC) - for Cursor (G1) and MOSD (G2) planes the CSC is part of “Format Conversion” stage. The CSC for PG & IG (G0) planes is part of their respective scaler. The CSC coefficients can be programmed independently for different planes.

Only PG & IG (G0) graphic planes have scaling capability. Only the in-line scaling mode is supported for graphics planes – the scaler output is directly sent to the blenders without going through DRAM buffer.

SWITCH

Bank51024x64SRAM

AXI64-bit

vppDHub (dHub0)


stage

Scalingstage

Color Processing &Channel Blending stage

Loader

pl-3d (BG)

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The graphic loader supports 8-bit LUT index or 32-bit ARGB/AYUV format inputs. The data that is written to each 32-bit LUT entry should be in the following order: Byte0 is A, Byte1 is V/R, Byte2 is Y/G, and Byte3 is U/B. When the input to loader is in 32-bit format, pixel data can be arranged in any of the following orders in DRAM.

Figure 53: Post processing for Graphic Plane

Table 102: ARGB/AYUV Pixel Format in DRAM

Format Description Address in system Memory


0 ARGB/AVYU B1/U1 G1/Y1 R1/V1 A1 B0/U0 G0/Y0 R0/V0 A0

1 ABGR/AUYV R1/V1 G1/Y1 B1/U1 A1 R0/V0 G0/Y0 B0/U0 A0

2 RGBA/VYUA A1 B1/U1 G1/Y1 R1/V1 A0 B0/U0 G0/Y0 R0/V0

3 BGRA/UYVA A1 R1/V1 G1/Y1 B1/U1 A0 R0/V0 G0/Y0 B0/U0

SWITCH

AXI64-bit


stage


PGScaler

Bank41024x64SRAM

Loader

IG (G0)Scaler

Bank31024x64SRAM

Loader

Bank21024x64SRAM

Loader LUT + CSC

LUT

LUT

Bank11024x64SRAM

Loader LUT + CSC

agDhub (dHub1)

pl-3a (PG)

pl-3(IG/G0)

pl-3b(Cursor/

G1)

pl-3c(MOSD/

G2)

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Video Post Processing (VPP)AUX Channel



15.7 AUX ChannelAUX channel is designed to generate simultaneous SD content of primary output from CPCB0. The progressive output of CPCB0 is fed back to AUX scaler input. The down-scaled picture from AUX scaler is stored to DRAM frame buffer at the CPCB0 TG refresh rate. CPCB2 has a timing generator at SD output rate. CPCB2 loads data directly from DRAM at the required frame rate. The Figure 54 illustrates the AUX channel connections.

Figure 54: AUX Channel Connections

Depending on software setting, the AUX scaler can process fully or partially blended pixel data from the CPCB0 blender. Following options are possible through register programming:

Main video data onlyPIP video data onlyMain & PIP overlayed data before CMU processingMain & PIP overlayed data after CMU processingFinal CPCB0 output data (after blending with BG and graphic planes)

15.8 ScalerScaling the input frame to fit the display resolution or the user-specified resolution.• Interpolation, Reduction, 1:1• Supports video (for Main, PIP and AUX channels) and graphics (for PG & IG channels)

scaling.• Independent horizontal and vertical scaling ratios.Non-linear 3 zones scaling for preserving aspect ratio.• Main video, PIP and AUX scalers support• 12 taps horizontal, 8 taps vertical for SD• 12 taps horizontal, 5 taps vertical for HDPG and IG (G0) scalers can support

AUXScaler

16-bit CPCB2Bank5

1024x641-portSRAM

AXI64-bit

vppDHub (dHub0)


stage


pl-1(AUX)

CPCB0

Loader

Loader

16-bit

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• 12 taps horizontal, 8 taps vertical for SD• 12 taps horizontal, 3 taps vertical for HDMaximum input/output resolution is 1920x1080Implements programmable poly-phase filter of phases 64 and 12 taps in horizontal direction and up to a maximum of 8 taps in vertical direction (the maximum vertical taps supported depend on video/graphic and SD/HD as mentioned above)

In 88DE3010 following planes have scaler support:

Main video planePIP video planeAUX planePG plane (with Alpha channel scaling support)IG (G0) plane (with Alpha channel scaling support)

For Main, PIP and AUX planes, the scalers support both in-line mode and off-line mode; for the rest of the planes, the scalers only support in-line mode.

In in-line mode, the scaler loads the data from Format Conversion stage and outputs the scaled data to Blending stage directly. The data doesn’t go through any DRAM buffering. This mode will be used for bypass (no scaling), up scaling and down-scaling when vertical down-scaling ratio is less than 2x.

In off-line mode, the scaler loads the data from Format Conversion stage and outputs the scaled output to a frame-buffer in DRAM. The data in the DRAM frame buffer is loaded by Blender later for further processing. This mode shall be used for down-scaling when the vertical down-scaling ratio is equal or more than 2x.

Main video, PIP and AUX (for SD output) scalers support both in-line and off-line scaling feature. IG & PG scalers support ONLY the in-line scaling mode. Note that AUX scaler always operates in off-line mode as its only application is down-scaling (for SD path).

Figure 55 describes the internal components of the scaler module.

Figure 55: Internal Components of the scalar module

U2: Chroma Up sampler

D: Chroma Down sampler

Scaler Register Bank

Scaler Coefficient

Bank

H-scale D

V-scale U2

32/24/16

OSD Formatter

data in

valid

request

H-scaleslot1

Circular Line Buffer Memory System

1280x144

32/24/16 144

H-scaleslot2

32/24/16 request

valid

data out

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Video Post Processing (VPP)Scaler



15.8.1 Detail ScalerDetail scaler is part of the Edge-enhancement solution for the Main video plane. The detail scaler scales the luma detail difference signal from the Detail EE module of Format Conversion stage (Main video path). Its functionality is a subset of the generic scaler with the following differences:

The input and output of the detail scaler is 8-bitIts coefficient values, coefficient format or number of taps are not programmable to all possible combinations. They have to be selected from a set of fixed coefficients.

Horizontal coefficients can be selected from the following 2 sets:

Horizontal table 1: Taps 2. Bilinear soft coefficients.

Horizontal table 2: Taps 12. Sharp coefficients. Good for 1:1 and upscaling operations.

Table 103: Coefficient sets for horizontal scaling in Detail scaler

ph Htable 1 Htable 2

0 144'h000000000000000000400000000000000000 144'h000000000000000000400000000000000000

1 144'h0000000000000000103f0000000000000000 144'h00000080100380600f40080f006803001000

2 144'h0000000000000000203e0000000000000000 144'h00000180300680d01f3ff81d00c806003801

3 144'h0000000000000000303d0000000000000000 144'h00000180400981302f3fd82b012809004801

4 144'h0000000000000000403c0000000000000000 144'h00000280600c81a0403fa83801880b005802

5 144'h0000000000000000503b0000000000000000 144'h80100380700f8210523f684401d80e006802

6 144'h0000000000000000603a0000000000000000 144'h8010038080138270633f1850022810007803

7 144'h000000000000000070390000000000000000 144'h80100480a01682e0753ed85c027813008803

8 144'h000000000000000080380000000000000000 144'h80100480b0198350883e686702c815009803

9 144'h000000000000000090370000000000000000 144'h80100580d01d83c09b3dd87103181700a803

10 144'h0000000000000000a0360000000000000000 144'h80100580e0208430ae3d687a03581900b804

11 144'h0000000000000000b0350000000000000000 144'h80100681002384a0c23cd88303981b00c804

12 144'h0000000000000000c0340000000000000000 144'h8020078110268510d63c488c03d81d00d804

13 144'h0000000000000000d0330000000000000000 144'h80200781302a8580ea3bb89404181f00d804

14 144'h0000000000000000e0320000000000000000 144'h80200881502d85f0ff3b089b04482000e805

15 144'h0000000000000000f0310000000000000000 144'h8020088160308661143a48a104782200f805

16 144'h000000000000000100300000000000000000 144'h80200981703386d1293978a704a82300f805

17 144'h0000000000000001102f0000000000000000 144'h80300a81903687313e38a8ad04d824010805

18 144'h0000000000000001202e0000000000000000 144'h80300a81a03987a15437d8b204f825010805

19 144'h0000000000000001302d0000000000000000 144'h80300b81c03c88016936f8b6051826010805

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Vertical coefficients can be selected from the following 2 sets:

Vertical table 1: Taps 2. Bilinear soft coefficients.

Vertical table 2: Taps 8. Sharp coefficients. Good for 1:1 and upscaling operations.

Vertical table 3: Taps 5. Sharp coefficients. Good for 1:1 and upscaling operations.

20 144'h0000000000000001402c0000000000000000 144'h80300b81d03f88617f35f8ba053827011805

21 144'h0000000000000001502b0000000000000000 144'h80300c81e04288c19534e8bd055828011805

22 144'h0000000000000001602a0000000000000000 144'h80300d8200458921ab33e8bf056829011805

23 144'h000000000000000170290000000000000000 144'h80400d8210478981c232f8c1057829011806

24 144'h000000000000000180280000000000000000 144'h80400e82204989d1d831e8c305882a011806

25 144'h000000000000000190270000000000000000 144'h80400e82304c8a21ed30a8c405982a012805

26 144'h0000000000000001a0260000000000000000 144'h80400f82404e8a72022f88c405982a012805

27 144'h0000000000000001b0250000000000000000 144'h80400f8250508ab2172e58c405a82a012805

28 144'h0000000000000001c0240000000000000000 144'h80400f8260528b022e2d38c405a82a011805

29 144'h0000000000000001d0230000000000000000 144'h8050108270538b52462c18c405982a011805

30 144'h0000000000000001e0220000000000000000 144'h8050108280558b72592ac8c105982a011805

31 144'h0000000000000001f0210000000000000000 144'h8050108280568ba26e2978bf058829011805

32 144'h000000000000000200200000000000000000 144'h8050118290578bd2832838bd057829011805

Table 103: Coefficient sets for horizontal scaling in Detail scaler (Continued)

ph Htable 1 Htable 2

Table 104: Coefficient sets for vertical scaling in Detail scaler

ph Vtable 1 Vtable 2 Vtable 3

0 96'h000400000000000000000000 96'h000000000000400000000000 96'h00c87026a26a870000000000

1 96'h0103f0000000000000000000 96'h00000180500e40180e004801 96'h00c87328025486d000000000

2 96'h0203e0000000000000000000 96'h00000380901d3fd81b009802 96'h00d87629623d86a000000000

3 96'h0303d0000000000000000000 96'h80100480e02c3fc82700d803 96'h00e8782aa227867000000000

4 96'h0403c0000000000000000000 96'h80100581303c3fa833010804 96'h00e87a2bf210863000000000

5 96'h0503b0000000000000000000 96'h80100781804c3f583e014805 96'h00f87b2d21f985f000000000

6 96'h0603a0000000000000000000 96'h80100881d05d3f0849018806 96'h00f87d2e71e285b000000000

7 96'h070390000000000000000000 96'h80100a82206e3ea85301b807 96'h01087e2fb1cb858000000000

8 96'h080380000000000000000000 96'h80200c8280803e585d01e808 96'h01087f30e1b5854000000000

9 96'h090370000000000000000000 96'h80200d82d0923de866021809 96'h01187f32019e850000000000

10 96'h0a0360000000000000000000 96'h80200f8330a53d486e024809 96'h01187f33118884b000000000

11 96'h0b0350000000000000000000 96'h8030118380b83cc87602680a 96'h01187e342172847000000000

12 96'h0c0340000000000000000000 96'h80301283e0cb3c387d02880a 96'h01187d35315c843000000000

13 96'h0d0330000000000000000000 96'h8030148430df3b688302b80b 96'h01287c36214783f000000000

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Video Post Processing (VPP)CPCB (Overlay and Timing Generator)



15.9 CPCB (Overlay and Timing Generator)The CPCB modules mix various video and graphics sources into a single image, and output that image according to the timing generator generated timings. Timing Generator generates the video format timing reference signals to request frame data from the processing pipeline and send to the output port. The 88DE3010 includes 3 CPCBs (CPCB0, CPCB1 and CPCB2). The CPCB0 & CPCB1 are similar except that CPCB0 have CMU & Interlacer functions. CPCB2 has no overlay and its only function is to support SD (480i/576i) output.

Each of the CPCB has its own Timing Generator (TG). The Timing Generator module provides all other modules inside that CPCB with timing reference signals. The basic TG registers that control the generated video format timing are:

VTOTAL: Total vertical lines including blank lines (E.g.: 1125 for 1080p60 resolution)HTOTAL: Total horizontal pixels per line including blank pixels (E.g.: 2200 for 1080p60 resolution)HSYNC_START: Position where horizontal sync is activated with in a line in terms of pixel clocksHSYNC_END: Position where horizontal sync is de-activated with in a line in terms of pixel clocks VSYNC_START: Position where vertical sync is activated with in a frame in terms of linesVSYNC_END: Position where vertical sync is de-activated with in a frame in terms of lines

14 96'h0e0320000000000000000000 96'h8040168490f33ac88902c80b 96'h01287a37213183b000000000

15 96'h0f0310000000000000000000 96'h80401884f1083a088f02e80c 96'h01287838111c837000000000

16 96'h100300000000000000000000 96'h80401985411c39389403080c 96'h01187538f108833000000000

17 96'h1102f0000000000000000000 96'h80501b85a13138689803180c 96'h01187239c0f482f000000000

18 96'h1202e0000000000000000000 96'h80501d85f14637789c03280c 96'h01186f3a90e082b000000000

19 96'h1302d0000000000000000000 96'h80501f86515c36789f03380c 96'h01186a3b40cc827000000000

20 96'h1402c0000000000000000000 96'h80602086a1723598a203480d 96'h0108663c00ba824000000000

21 96'h1502b0000000000000000000 96'h8060228701873498a403580d 96'h00f8603ca0a7820000000000

22 96'h1602a0000000000000000000 96'h80702487519d3388a503580d 96'h00f85a3d209581c000000000

23 96'h170290000000000000000000 96'h80702687a1b33258a603680d 96'h00e8543db084819000000000

24 96'h180280000000000000000000 96'h80802787e1c93138a703680c 96'h00d84d3e3073816000000000

25 96'h190270000000000000000000 96'h8080298831de3018a703680c 96'h00c8453e9063813000000000

26 96'h1a0260000000000000000000 96'h80802a8881f42ef8a703680c 96'h00a83d3ef05380f000000000

27 96'h1b0250000000000000000000 96'h80902c88c20a2dc8a603580c 96'h0098353f604380d000000000

28 96'h1c0240000000000000000000 96'h80902d8902202c88a503580c 96'h00882b3f803580a000000000

29 96'h1d0230000000000000000000 96'h80a02e8942362b58a403480b 96'h0068213fb027807000000000

30 96'h1e0220000000000000000000 96'h80a03089724b29f8a203480b 96'h0048173ff019805000000000

31 96'h1f0210000000000000000000 96'h80a03189a26128a8a003380b 96'h00280c40000c802000000000

32 96'h200200000000000000000000 96'h80b03289d27627689d03280b 96'h000000400000000000000000

Table 104: Coefficient sets for vertical scaling in Detail scaler (Continued)

ph Vtable 1 Vtable 2 Vtable 3

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Apart from the output timing, each plane has its own set of registers to specify the position and size with in the total display canvas defined by the PLANE-4 registers:

PLANE_START_X: Horizontal start position of the plane in terms of pixelsPLANE_START_Y: Horizontal end position of the plane in terms of pixelsPLANE_END_X: Vertical start position of the plane in terms of linesPLANE_END_Y: Vertical end position of the plane in terms of lines

15.9.1 CPCB0The main features of CPCB0 overlay engine of 88DE3010 are as follows:

Can overlay up-to 7 input planes (3 video planes and 4 graphic planes): pl-1 (Main video), pl-2 (PIP), pl-3 (IG/G0), pl-4 (PG), pl-5 (Cursor/G1), pl-6 (MOSD/G2) and pl-7 (BG)For graphic planes the input can be AYUV 32-bit or AYC24-bit. For video planes, the input can be YUV 4:2:2 or YUV 4:4:4.For graphic planes, programmable to take alpha from input (per pixel alpha) or from a programmable register (global alpha). For video planes, alpha is programmable from register (global alpha).Pre-overlay of Main & PIP planes to enable sharing of single CMU for both Main & PIP planes. The different features of CMU can be individually turned-off or on for Main video and PIP planes.Supports Luma-key when blending PIP with Main video.Option to invert the usage of alpha.Supports boarder plane for each input plane. Supports different alpha for boarder planes. For example, PG plane (pl-3a) and its boarder plane (pl-7a) can have different alpha. Supports crop planes for pl-1 (Main video), pl-2 (PIP), pl-3 (IG), and pl-3a (PG)Overlay happens in YUV domain.Programmable mapping from plane to overlay layers to facilitate flexible Z-order (order of blending).

Figure 56 shows the detailed block diagram of the CPCB0, it consists of an Edge Enhancement block (EE), Video overlay, Color Management Unit (CMU), Film Grain Generator (FGG), chroma Upsampler (UPS), OSD overlay (OO) and an Interlacer.

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Figure 56: Detailed Block Diagram of CPCB0

The edge enhancer (EE) consists of two independent modules, luma detail enhancement circuit and transient improvement (LTI & CTI) circuit. The Edge enhancer takes the Main video data along with the detail input to form edge enhanced Main video output. UPS indicates chroma up-sampler and is used to convert 422 YUV input to 444 YUV data before blending.

Video overlay block overlays the Main and PIP pictures which includes the Luma-key function on PIP path and feeds the data to the Color Management unit (CMU). When enabled through register programming, the luma-key function will make the PIP pixel transparent (weight=0 for that pixel) if the luma value of that pixel falls into a pre-programmed range.

The following blending equation is used to overlay the Main video and PIP:

VO output = weight * PIP + (1 – weight) * Main

VO_WEIGHT: weight – defines the alpha for PIP pixels

VO_KEY_MIN: min value to compare against PIP pixels

VO_KEY_MAX: max value to compare against PIP pixels

INT0(to Video Output stage)

EE

VideoOverlay

CMU

Interlacer

pl-1(Main)

pl-2(PIP)

pl-3 (IG/G0)

pl-3a(PG)

Detail

FGG

UPS

UPS

UPS

pl-3b(Cursor/

G1)

pl-3c(MOSD/

G2)

pl-3d(BG)

PROG0(to Video Output stage)

to AUX scaler

pl-1

OO

pl-2

pl-3

pl-3a

pl-3b

pl-3c

pl-3d

UPS

Timing Generator (TG)

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The CMU is the main color processing unit of 88DE3010. It has functions such as Adaptive Contrast Enhancement (ACE), Intelligent Color Remapper (ICR), and a 3-channel Gamma correction block. The Film Gain Generator (FGG) module adds a relatively small amount of film grain noise to make the video look more natural and more pleasing to the human viewer. For more detailed descriptions of these processing functions please refer to section 2.8: Color Management Unit of this datasheet.

The final mixing of main video and PIP data along with the other planes are done at OSD overlay block. Figure 57 illustrates the details of basic overlay function (OSD Overlay – OO) used by CPCB0 and CPCB1.

Figure 57: Block Diagram of Overlay Engine which is part of CPCB0/CPCB1

In Figure 57, the multiplexer indicates that there is no alpha-blending involved. Mixing input plane with its border plane is not alpha-blending, it is just a selection based on their sizes – a multiplexer is used to denote this function. Mixing layer0 with layer1 is also not alpha-blending as layer0 is a solid color. The “Alpha Blender” module of OSD Overlay implements the following equation for alpha-blending. FGP is fore-ground plane and BGP is back-ground plane participating in the blending function:

Normal Mode operation:

Alpha Blender Output = alpha * FGP + (1 – alpha) * BGP (normal alpha sense)

alpha * BGP + (1 – alpha) * FGP (inverted alpha sense)

Matte Mode operation: This mode of overlay is used when graphic pixels are pre-multiplied with alpha (in inverted alpha case) and 1-alpha (in normal alpha case).

Alpha Blender Output = alpha * BGP + FGP (normal alpha sense)

(1 – alpha) * BGP + FGP (inverted alpha sense)

pl-0

pl-4layer-0

pl-1

pl-5

pl-2

pl-6

pl-3

pl-7

pl-3a

pl-7a

pl-3b

pl-7b

pl-3c

pl-7c

pl-3d

pl-7d

layer-1 layer-2

AlphaBlender

layer-3

AlphaBlender

layer-4

AlphaBlender

AlphaBlender

layer-5

AlphaBlender

layer-6

AlphaBlender

layer-7

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Table 105 describes the source of different CPCB0 planes:

The order-of-overlay (Z-order) is completely programmable through the layer selection. Layer1 is the bottom-most layer (above layer0 which is the base-plane), and layer7 is the top-most layer. There is a 3-bit select control provided for each of the 7 layers (layer1 to layer7). Any of the input planes can go to any of the layers. For example, the following shows one kind of Z-order:

Layer1: pl-3d (BG)

Layer2: pl-1 (Main)

Layer3: pl-2 (PIP)

Layer4: pl-3a (PG)

Layer5: pl-3 (IG)

Layer6: pl-3b (Cursor)

Layer7: pl-3c (MOSD)

The restrictions of the input layer selections and plane routings for CPCBs are:

When one layer on CPCB is not used, it needs to be disabled by setting the layer control register to 0One input source can not be enabled on more than one CPCB inputsThe AUX scaler output source is directly connected to CPCB2 pl-1; it’s not selectable to other CPCB.

Table 105: Source of different CPCB0 planes

CPCB0 plane Description Source

pl-0 Base plane Solid color from Register

pl-1 Main from video processing pipe

pl-2 PIP from video processing pipe

pl-3 IG (G0) from video processing pipe

pl-3a PG from video processing pipe

pl-3b Cursor (G1) from video processing pipe

pl-3c MOSD (G2) from video processing pipe

pl-3d BG from video processing pipe

pl-4 Boarder for plane0 (overall display canvas)

Solid color from Register

pl-5 Boarder for plane1 Solid color from Register



pl-7a Boarder for plane3a Solid color from Register

pl-7b Boarder for plane3b Solid color from Register

pl-7c Boarder for plane3c Solid color from Register

pl-7d Boarder for plane3d Solid color from Register

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Since there is a pre-overlay between Main video and PIP (before feeding it to the CMU), the Z-order must not be programmed in such a way that some other plane comes in between the Main video & PIP planes.Detail scaler output is always connected to CPCB0. So, Detail function is not available (must be disabled) when Main video plane is routed to CPCB1.

At the output stage of the CPCB, the Interlacer block converts the progressive output from OSD overlay into interlaced output. Output pixel data from different stages of CPCB0 can be selected and sent to the AUX scaler to generate SD output from 88DE3010 as shown in Figure 56.

The video and graphics overlay in 88DE3010 happens in YUV 444 domain. Before the blending can happen, the input source data with various formats must be converted into YUV444 through up-sampler (UPS) module as shown in Figure 56

15.9.2 CPCB1The detailed functional block diagram of the CPCB1 path is as shown in Figure 58. CPCB1 is very similar to CPCB0 except few functional blocks like Edge Enhancer for Main video, CMU, FGG and Interlacer functions are not present in CPCB1. Apart from the edge enhancement and color management the CPCB1 will perform all the video overlay operation along with OSD overlay and gives out only progressive output to the Video Output stage.


UPS

UPS

UPS

pl-1

OO

pl-2

pl-3

pl-3a

pl-3b

pl-3c

pl-3d

VideoOverlay

pl-1(Main)

pl-2(PIP)

pl-3 (IG/G0)

pl-3a(PG)

pl-3b(Cursor/G1)

pl-3c(MOSD/G2)

pl-3d(BG)

UPS

UPS

PROG 1(to Video

Output stage)


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15.9.3 CPCB2The Detailed functional block diagram of the CPCB2 path is as shown below. CPCB2 has no overlay function and is essentially a Timing Generator (TG) to generate SD video output for 88DE3010. The plane input for CPCB2 is directly loaded from DRAM, which could be written by AUX scaler with the down-scaled version of the primary video output content (from CPCB0).


pl-1(AUX) UPS

Interlacer

pl-0

pl-4

pl-5

PROG2(to Video Output

stage)

INT2(to Video Output

stage)


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15.10 Color Management Unit (CMU)Figure 60 depicts all the sub-modules of CMU. Input CSC and Global CSC are generic color-space converters. Other blocks are explained below:

Figure 60: High-level block Diagram of 88DE3010's Color Management Unit (CMU)

15.10.1 Input Color Space ConverterThis is a fully programmable 3 x 3 + 3 x 1 converter that can be used to convert between RGB and YCbCr (601 or 709) or any other linear color-space

15.10.2 Adaptive Contrast Enhancement (ACE)The Adaptive Contrast Enhancement (ACE) block analyzes each frame and adjusts the contrast locally to improve the contrast of the scene. The contrast adjustment is set automatically based on scene content. Darker regions are stretched to improve their contrast without over-enhancing or clipping brighter regions. The brightness control block changes the brightness of the input image to more visually pleasing levels.

All the parameters for ACE and brightness control can be independently controlled for Main and PIP channels

15.10.3 Intelligent Color Remapper (ICR)The Intelligent Color Remapper (ICR) is a highly flexible block that can perform diverse tasks such as flesh tone correction and identification and enhancement of specific colors that can be programmed using software. The ICR block performs enhancements on chroma only and does not modify the luma. The ICR also handles global saturation control that can be tapered in flesh like regions. All the functionality of the ICR can be independently controlled for Main and PIP channels.

The ICR consists of two blocks – a Flesh Tone Detection and Correction (FTDC) block and a Hue-Saturation Calibration block.

InputCSC

YUV8-bit

Intelligent Color Remapper

Flesh Tone Detection & Correction

Hue Saturation & Calibration

Adaptive Contrast Enhancement

UV

Y

YUV11-bit

YUV10-bit

YUV10-bit

Global CSC

Gamut Compression

GammaCorrection

YUV10-bit

CMU out

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Video Post Processing (VPP)Color Management Unit (CMU)



15.10.3.1 Flesh Tone Detection and Correction (FTDC)Fleshtone can be detected and adjusted using 2D correction vectors. The color-space around the most common fleshtone hue and saturation is split into an inner and outer region for multi-bit detection and graded correction. Colors in these regions can be made to conform more closely to true fleshtone, as shown in Figure 61. FTDC can be independently controlled for Main and PIP channels.

Figure 61: Flesh Tone Correction

15.10.3.2 Hue – Saturation CalibrationThis module allows colors to be manipulated independently by dividing the color space into up to 12 programmable regions to process up to 6 colors at a time (For example, the 12 chosen regions could be red, magenta, blue, cyan, green, and yellow, and the six regions between them). All 6 regions are completely programmable. Hue and saturation control can be done in any one or more of these regions in a graded manner. In this way, specific colors, such as grass green or sky blue, can be defined and enhanced without affecting any other color. The pixel values are monitored to make sure the results produced are always valid and no clipping or loss of detail occurs even when the saturation enhancement is set to maximum.

Hue saturation modifications can be independently controlled for Main and PIP channels.

15.10.4 Gamut CompressionThe Gamut Compression block detects invalid RGB pixels and “corrects” them. It is programmed to detect invalid YCbCr pixels that are getting converted to RGB. Most color processing is done in YCbCr space but not every valid 30-bit YCbCr triplet is a valid RGB pixel. Many color processing algorithms can take a valid YCbCr pixel and process them resulting in an invalid output. The usual way to deal with this problem is clamp the RGB values at 0 and 1023 during color conversion but this can lead to artifacts when heavy color processing occurs, for example saturation by a factor of 4. The Gamut Compression block “corrects” these invalid pixels by applying the required amount of

Inner Hue RangeFlesh-tone Weighting = 3

Outer Hue RangeFlesh-tone Weighting varies from 2 to 1

Region of I and Q correction

The arrows show how the various points, falling in different segments of the 2D chroma space, are moved by the programmed fleshtone correction 1550

1400

I(123°)

95°

Cr

Q

Cb

110°

Weighting outsideFlesh-tone region = 3

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de-saturation to bring the input pixel within valid RGB range. This block accepts the 11-bit output from the GCSC and gives 10-bit valid RGB output. The Gamut Compression block can be independently controlled for Main and PIP channels.

15.10.5 Gamma CorrectionThree independent gamma LUTs (lookup tables, 3x2048x12) are provided, one for each of the three channels – R/Cr, G/Y, B/Cb, to map 10-bit input to 12-bit output. These tables can be used independently for gamma correction on the R/Cr, G/Y and B/Cb channels. Main and PIP channels can be enabled/disabled independently. Also the gamma correction can be turned on or off independently for the R/Cr, G/Y and B/Cb channels. Main channel R/Cr, G/Y and B/Cb pixels address the memory directly whereas an offset of 1024 is added to the PIP channel data before it addresses the memories. Outputs of gamma LUTs are fed into the OSD overlay module of the CPCB subsystem.

15.10.6 Film Gain Generator (FGG)The Film Grain Generator adds specially shaped noise to the image to give a film grain look to the image and conceal contouring artifacts. It can be disabled for pass through mode.

15.11 InterlacerThe 88DE3010 VPP interlacer supports two modes of progressive to interlace conversion: scan line decimation and vertical filtering. In the scan line decimation mode every alternative active scan line of the progressive frame is decimated (discarded). In the vertical filtering mode, the interlacer will calculate the average of two adjacent scan lines and output the result as interlaced pixel data.

The weighing factor (WF) register can be programmed to set the Interlacer to scan line decimation or vertical filtering mode. The value of 256 or 0 forces the interlacer to scan line decimation mode and value from 1 to 255 to vertical filtering mode.

There are 2 interlacers in 88DE3010’s VPP: one inside CPCB0 output stage (could be used for showing 1080i on Component while 1080p is shown on HDMI) and another one in CPCB2 output stage (for SD output).

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Video Post Processing (VPP)Video Output Modules



15.12 Video Output ModulesThe 88DE3010's VPP has the following video output Interfaces:

HDMIHD Component (YPbPr)SD – CVBS & S-VideoDigital Video Output (DVO)

Figure 62 describes the selection scheme (from different overlay engines to different video outputs). Each of the VPP's video output interfaces has a dedicated VOP block. VOP selects one output among the different CPCB outputs in YUV444 format and performs color space conversion (CSC) in RGB output case, and chroma down-sample (DNS) in YUV422 output case.

15.12.1 HDMI OutputThe 88DE3010 implements an HDMI output that is fully complaint to HDMI 1.3a specification. The HDMI PHY is integrated into 88DE3010.

15.12.1.1 HDMI VOPHDMI VOP has the following blocks.

Figure 62: Block Diagram of HDMI VOP module

Switch selects which CPCB output is routed to HDMI. PROG0 indicates progressive output of CPCB0, INT0 indicates interlaced output of CPCB0, PROG1 indicates progressive output of CPCB1, PROG2 indicates progressive output of CPCB2, and INT2 indicates interlaced output of CPCB2.CSC (Color Space Converter) is provided so that the YUV data from CPCBs can be converted to RGB before sending it to HDMI Transmitter. If RGB data needs to be sent over HDMI, CSC in HDMI-VOP is programmed. In all other cases, the CSC in HDMI-VOP is in bypass mode.DNS (chroma down sampler) is provided so that YUV 422 data can be sent over HDMI (if there is such a requirement). DNS can be enabled/disabled.

15.12.1.2 HDMI TransmitterThe main features that are supported by the HDMI-Transmitter are:

Fully complaint with HDMI 1.3a specification

HDMI_VOP

DNSCSC

SWITCH

PROG0

INT0

PROG1

0

PROG2

INT2

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Supports 8/10/12-bit color-depths at up to 1080 60p output rateSupports pixel repetition for all video resolutions allowed by the HDMI specificationSupports multi-channel (up to 8) L-PCM audio of up to 192KHz sample-rate through Audio Sample PacketsSupports compressed audio of low-bit rate through Audio Sample Packets and high-bit rate over High Bit Rate (HBR) PacketsSupports DVI modeFully complaint with HDCP Specification Revision 1.2Supports xvYCC – supports Gamut Metadata Packet transmission and full range data pass throughSupports CEC function with EDIDIntegrated HDMI-TX PHY

Figure 63 shows the internal structure of the HDMI Transmitter:

Figure 63: Block Diagram of the HDMI Transmitter along with the HDMI-TX PHY

The HDMI-TX takes digital video inputs with a maximum resolution of 12 bits/channel from the up-stream CPCB block in the Blending stage and Audio data from 88DE3010 device’s Audio Engine.

The video data is first pre-conditioned as per the input data format (YUV/RBG 444 or YUV 422). Then the data is passed through pixel repetition block if pixel repetition is enabled. Otherwise it is bypassed. The input 36/30-bit video data is then packed into 8-bit/channel video data using the deep color FSM described in the HDMI 1.3 standard. The clocks required for Deep color and Pixel Repetition are generated by the AVPLL depending on the resolution of the video data. If the input is 24-bit, then no data packing is required and the deep-color logic is bypassed. After the data

VideoInput

Interface

PixelRepetition

DeepColor

HDCPTMDS/TERC4Encoder

HDMI-TXPHY

clock channel

CH0

CH1

CH2

AudioInput

Interface

AudioFIFO

DIArbiter Packetizer

ACRGenerator

HostPacket

Generator

Registers

Video Data from Blending

stage

Audio Data from Audio

Engine

clocksfrom

AVPLLHPD

RegisterBus

CEC CEC

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conversion, the data is passed through the HDCP block. The Deep-color module also generates GCP packet per every frame/field to indicate the AVMUTE, Color-Depth and Last Packing Phase information to HDMI-RX.

The HDMI-TX can support up-to 8-channel LPCM and high-bit rate compressed audio data. It transmits the LPCM data and low-bit rate compressed data over Audio Sample Packets and high-bit rate audio over HBR Audio packets. The Audio input interface pre-conditions the audio data based on various programmable options. The conditioned data is then stored in the audio FIFO. Once a frame is available in the audio FIFO, audio transmit request is generated to the DI Arbiter block. To facilitate the Audio Clock Recovery at the HDMI-RX side, the ACR/CTS generator module of HDMI-TX generates ACR packets as per the HDMI standard.

HDMI standard describes many other packets which can be transmitted over the HDMI link to convey different information. In 88DE3010 device’s HDMI-TX, all such packets are controlled by the software with the help from HDMI-TX hardware. Six different packet types can be stored at any time each having a 31-byte buffer. Software can decide the type of packets and whether it needs to be transmitted every frame or only on command. Each of this packet type generates its own request and there is an internal arbiter to grant access among the host packets with a simple round-robin scheme. Hence only one host packet request is visible to the Data Island (DI) Arbiter.

The Data Island Arbiter block accepts requests from the various sources and grants access to make sure all the HDMI standard specified rules are complied. The DI arbiter module identifies the valid DI region in the frame. The packetizer block performs the function of packetization and control bit encoding. The packetized data along with the control bits are provided to the HDCP block.

High-bandwidth Digital Content Protection System (HDCP) is designed for protecting audiovisual content over certain high-bandwidth interface from being copied. Audio-visual data from 88DE3010 gets encrypted by HDCP and is sent through TMDS encoder. HDCP also authenticates the receiver as a valid HDCP receiver before allowing the transmission process.

The HDCP encoded data is then TMDS encoded and sent to the HDMI-TX PHY for serialization over the HDMI link.

15.12.1.3 HDCPThe HDCP block performs the HDCP encoding of both video and auxiliary data and also performs the authentication through the DDC channel. The DDC is fully controlled by software through a set of commands. The Key security is managed by the on chip DRMDMX secure processor. During the HDMI initialization, the application software will load the encrypted key information from external Flash device to the DRMDMX secure processor. The DRMDMX secure processor will decrypt this key information using the RKEK and directly program the HDCP keys into the HDMI module. The HDCP key can only be read by HDCP hardware. They are write only and not readable by any processors. Most of the authentication decisions are made by the HDCP driver. The HDCP block provides registers to store the required results computed in the hardware. Also it provides an interrupt to CPU whenever software intervention is required.

In 88DE3010, the DDC channel for HDCP and EDID transactions is implemented through a generic TWSI controller.

15.12.1.4 CECConsumer Electronics Control (CEC), defined by HDMI 1.3 standard, provides high-level control functions between all of the audiovisual products in a user's environment. The CEC module, inside HDMI Transmitter, consists of a set of programmable registers, status registers, Initiator and Follower state-machine logic and two FIFOs of depth 16 for Initiator and Follower. The programmable registers are addressed and data written to or read from through the Register bus. These registers serve to control the CEC Initiator and Follower logic. The status registers indicate status of interrupts and FIFO status and may be read through the Register bus. The Follower and Initiator logic take CEC line as an input to sense the activity on the common CEC line while the Initiator logic drives CEC line to affect the status (low/high impedance) of the CEC line. Software

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writes the CEC packet to Initiator FIFO and command the CEC module to send the packet on CEC line. Once done with the transmission, CEC module raises “Tx Done” interrupt. Similarly, when a CEC packet is received and stored in Follower FIFO, CEC module raises “Rx Done” interrupt. All the packet decoding and other tasks are handled by 88DE3010 software.

15.12.1.5 HDMI-TX PHYHDMI-TX PHY implements 4 identical data channels. HDMI-TX PHY treats clock channel also as another data channel. Channel 3 is used as clock-channel. It gets the HDMI serial clock from the AVPLL, which it divides internally to drive TMDS clock to the HDMI Transmitter. For each channel, the HDMI-TX PHY implements a parallel to serial converter and a serial differential driver.

Table 106 describes the control registers for HDMI-TX PHY.

15.12.2 HD Component and SD CVBS, S-Video OutputsThe 88DE3010 implements 6 on-chip Video DACs – 3 of them are used for HD Component output, 2 of them for SD S-Video output and one of them is for SD CVBS output. Video DAC takes 12-bit input and can work up-to 300M samples/second.

15.12.2.1 HD Component and SD CVBS, S-Video VOPHD Encoder (Component output) and SD Encoder (CVBS/S-Video output) have separate VOPs. Each VOP is identical in terms of functionality. Figure 64 is the block diagram of AHD-VOP (for the HD Encoder).

For each VOP, there’s a switch to select different output formats from CPCB modules as listed below:

PROG0: progressive output of CPCB0INT0: interlaced output of CPCB0PROG1: progressive output of CPCB1PROG2: scaled down progressive output of CPCB1INT2: interlaced output of CPCB2

After the input selection, color space conversion can be applied by the CSC module when RGB data output on video DAC is required. In other cases, the CSC module will be bypassed.

Table 106: Control Registers for HDMI-TX-PHY

Register Control Default Value Descript ion

PD_TX[3:0] 0xF One bit per channel, bit0 is for channel 0.1: Power down the transmitter0: No power-down, normal operation

POLSWAP_TX[3:0] 0x0 Swap the Polarity of TXP/TXN; one bit per channel, bit0 is for channel 0.0: Data-P is driven on TXP and data-N is driven on TXN1: Data-P is driven on TXN and data-N is driven on TXP

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Figure 64: Block Diagram of HD Component VOP module

15.12.2.2 Video EncoderThe function of Video Encoder is to encode digital video data into standard SD and HD analog formats to output for television and monitors. Fig 2.20 illustrates the block diagram of the 88DE3010 video encoder. The 88DE3010 video encoder supports two independent digital video inputs, separate processing path for HD and SD, an output selection and over sampling filter, and 6 high performance video DACs (Digital to Analog Converter).

The Outputs of the two encoders will be further processed by over-sampling filters before used to drive the video DACs. The over sampling rate can be 1x/2x/4x or 8x of the input clock frequency with the constrain of maximum output clock of 300MHz. Poly-phase filters are used for interpolation and filtering. The output of the over-sampling filters is 12bit.

AHD_VOP

CSC

SWITCH

PROG0

INT0

PROG1

0

PROG2

INT2

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Figure 65: Block Diagram of the Video Encoder and Video DACs

SD processing pathThe 88DE3010 video encoder SD process path encodes standard definition digital video into Component, Composite and S-video format for output.

The SD encoder is capable of providing all three types of output simultaneously. For Component output, the SD encoder supports SDTV YPbPr, SDTV RGB or graphics RGB. Video blanking/synchronization signals can be inserted to the Y channel of component, composite and S-video after over sampling.

88DE3010 supports VBI data insertion to all channels of analog RGB output. The data can programmed by SOC CPU to VBI data registers during the video blanking intervals.

88DE3010 also supports teletext insertion. The teletext data is loaded through a dedicated DMA channel in VPP dHub. The VBI data can be inserted into all composite, S-video, and analog RGB output.

88DE3010 supports Macrovision analog copy protection for all SD outputs.

88DE3010 supports digital sync out for all composite, S-video, and component output for SD resolution.

The 88DE3010 SD encoder does not have any scaling capability, the input resolution and output resolution to the SD encoder must be matched.

HD processing pathThe input to 88DE3010 HD processing supports resolutions at 480p, 576p, 720p, 1080i or 1080p. The output of the HD processing path is in YPbPr444 or RGB444 component format.

The output video can be in following formats –:

High Definition Processing(480p/ 576p/ 720p/ 1080i/ 1080p)

Standard Definition Processing(480i/ 576i)

Out

put

Mux

+ O

ver

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mpl

ing

filte

rs

VDAC6P

VDAC5P

VDAC4P

VDAC3P

VDAC2P

VDAC1P

HD refs

SD refs

Teletext Interface

12-bitDACs

SDComponent

SDsyncs

HDComponent

Composite

S-Video36 bitYCbCr/ RGB

SD data

36 bitYCbCr/ RGB

HD data

HDsyncs

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480p / 576p – with Macrovision analog copy protection720p1080p1080i480i and 576i component outputs can also be supported (without Macrovision analog copy protection).

The HD encoder is capable of color conversion and progressive to interlace conversion when enabled, however, the HD encoder does not have any up-scaling or down-scaling capability. The input resolution and output resolution must be matched.

88DE3010 HD video encoder supports to add video synchronization signals to Y channel only or all the 3 channels.

Vertical Blanking (VBI) Data88DE3010 supports VBI data services including closed captioning (CC), wide-screen signaling (WSS), copy generation management system (CGMS) and teletext (TT). <<<please include standard specification version we support in VBI data service>>> WSS and CGMS will never occur together. WSS is applicable mainly to 625 line PAL systems. VBI data is present on only Y channel of an analog video interface or all the RGB channels of analog RGB interface.

Closed captioning and teletext are not available on the HD path. CGMS and WSS are present both on the SD and HD paths. To support high data rate for teletext, one of the vppDHub channel is dedicated to carry teletext data from DRAM to the SD encoder.

15.12.2.3 Video DAC88DE3010 integrates a 6-channel Video DAC. Three of the video DACs are used for Component output, 2 of them are assigned for SD S-Video output and one of them is assigned for SD CVBS output. Video DAC takes 12-bit input and can work up-to 300M samples/second. Each of the DAC is a 12 bit digital to analog converter with current output. The full scale current of each main DAC is independently programmable with 9 bit accuracy using the corresponding gain DAC channel.

The outputs of the encoder output are multiplexed to video DACs. The multiplexing is controlled by software programming.

VDAC1P/2P/3P has three multiplexing modes: SD component, CVBS&S-Video, and CVBS only mode.

VDAC4P/5P/6P has four modes, it supports HD component, SD component, CVBS&S-Video, and CVBS only mode.

Table 107: VBI data support

Mode / Type CGMS WSS CC Teletext Macrovision

480i/60 (NTSC) Y - Y Y Y

576i/50 (PAL) - Y Y Y Y

480p/60 Y - - - Y

576p/50 - Y - - Y

720p/60 Y - - - -

1080i/60 Y - - - -

1080p/60 - - - - -

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Table 108 and Table 109 summarize the supported output combinations.

The video DACs of 88DE3010 has an operating range up to 300 MHz. For improved DAC performance and simpler external filtering requirements, the encoded outputs are over-sampled to operate the DAC at a higher frequency

For standard definition data can be over-sampled up to 216 MHz (16x). 720p, 1080i and 1080p data can be over-sampled up to 297 MHz (4x and 2x). Refer to Table 110 for over-sampling rates for all supported video formats.

Table 108: Supported output format on VDAC1P, VDAC2P and VDAC3P

88DE3010 VDAC PAD NAME

DAC Modes

SD Component

CVBS and S-Video CVBS

VDAC1P SD B/Pb CVBS S-Video C CVBS

VDAC2P SD G/Y S-Video Y S-Video Y CVBS

VDAC3P SD R/Pr S-Video C CVBS CVBS

Table 109: Supported output formats on VDAC4P, VDAC5P and VDAC6P

88DE3010 VDAC PAD

NAME

DAC Modes CVBS

HD Component

SD Component

CVBS and S-Video

VDAC6P HD B/Pb SD B/Pb CVBS S-Video C CVBS

VDAC5P HD G/Y SD G/Y S-Video Y S-Video Y CVBS

VDAC4P HD R/Pr SD R/Pr S-Video C CVBS CVBS

Table 110: Output over-sampling rates

Video Type Video format Pixel Frequency (MHz)

Over-sampling up to

DAC Frequency (MHz)

HD 480p(525p) 27 8x 216

576p(625p) 27 8x 216

720p 74.25 4x 297

1080i 74.25 4x 297

1080p 148.5 2x 297

SD 480i 13.5 16x 216

576i 13.5 16x 216

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15.12.3 Digital Video Output (DVO)In addition to VDAC, 88DE3010 also provides 16-bit bus and necessary synchronization signals for digital video output ports (DVO). The DVO interface of 88DE3010 supports 3 modes:

DDR HD (double data rate) + SD mode Dual DDR HD mode Single HD (single data rate) mode

88DE3010 DVO supports BT656 format (SD), SMPTE274M (1080p/1080i) and SMPTE296M (720p). The DVO of 88DE3010 can be used to send digital video output to external video post processors if needed.

In SD mode, half of the 88DE3010 DVO pins are configured to SDR (single-data-rate) 8-bit interface. The Y and C components are time-multiplexed on the 8-bit data bus according to BT-656 format. The data changes only on the positive edge of the clock. The first data that comes after SAV is C and followed by Y (as defined in BT-656 protocol).

In SDR-HD mode, 88DE3010 DVO uses 8-bit for Y and 8-bit for C, with embedded EVA/SAV symbols, it is compliant to SMPTE274M and SMPTE296M format.

To support 2 simultaneous digital video output on 16bit bus, 88DE3010 supports DDR (double-data-rate) model for HD output. In this mode, the output pads are set to SSTL 1.8v and signal will toggle on both positive and negative edges of the clock. Since each channel is embedded with EAV/SAV, when the SDR output is converted to DDR, each EAV/SAV code will be repeated twice. On the system design, 8 positive edge and 8 negative edge flops maybe required to convert this 8-bit DDR output to 16-bit SDR for some video post processors.

88DE3010 supports the combination of the DDR-HD and SD output modes. However, when only 1 SDR HD output is needed, the data source must be from DV0_VOP as indicated in figure 2-29.

In addition to embedded EVA/SAV signaling, 88DE3010 also provides separate HS (horizontal sync), VS (vertical sync), and FLD (field ID) signals for both video outputs

The DNS module provides YUV444 to YUV422 conversion, and CSC (color space convert) can provide extra flexibility for color space conversion before final output on DVO interface.

Figure 66 explains the DVIO datapath:

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Figure 66: Block Diagram of the 88DE3010 device's Digital Video Output Scheme

16-bit SDR sel

DV1:DVIO[15:8]

DV1_CLK,DV1_HS,DV1_VS,DV1_FID1

0

1

0

DV0:DVIO[7:0]

DV0_CLK,DV0_HS,DV0_VS,DV0_FID

16-bit enc YC

8-bit DDR HD

8-bit BT 656

16-bit YC 422

656encoder

DV0_VOP

Y enc

C enc

clk

DNSCSC

SWITCH

PROG0

INT0

PROG1

0

PROG2

INT2

16-bit enc YC

8-bit DDR HD

8-bit BT 656

16-bit YC 422

656encoder

DV1_VOP

Y enc

C enc

clk

DNSCSC

SWITCH

PROG0

INT0

PROG1

0

PROG2

INT2

Not Used

15:8

7:0

7:0

7:0

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Figure 67 illustrates the timing diagram of the 88DE3010 DVO Interface.

Figure 67: DVO Interface Timing Diagram

FF 00 00 CTRL CB0 Y0 CR1 Y1 CRi Yi

SAV

FF 00 00 CTRL

EAV

DV0_CLK/DV1_CLK

DVO[7:0]/DVO[15:8]

BT-656 output Timing Diagram

FF 00 00 CTRL Y0 Y1 Y2 Y3 Yi-1 Yi

SAV

FF 00 00 CTRL

EAV

DV0_CLK

DVO[7:0]

SDR output Timing Diagram (it is also possible to route C on DVO[7:0] and Y on DVO[15:8])

FF 00 00 CTRL CB0 CR1 CB2 CR3 CBi-1 CRi

SAV

FF 00 00 CTRL

EAV

DVO[15:8]

FF 00 00 CTRL CB0

SAV

FF 00 00 CTRL

EAV

DV0_CLK/DV1_CLK

DVO[7:0]/DVO[15:8]

DDR output Timing Diagram (it is also possible to output Y on rise edge and C on fall edge of the clock)

Y0 CR1 Y1 CB3 Y3 CR4 Y4 CBi-1 Yi-1 CRi Yi

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15.13 Color Space ConverterThe 88DE3010 Qdeo pipe-line have multiple CSC (Color Space Converters) in various stages as listed below:

Format conversion stage in cursor(G1) planeFormat conversion stage in MOSD(G2) planeScaling stage in IG(G0) planeScaling stage in PG(G3) planeColor management/processing stage in main and PIP video planeOutput stage in all VOP modules for each output ports (DV0, DV1, HDMI, HD encoder, SD encoder)

All of them use similar CSC (with few differences in parameter representation explained below). The 88DE3010 Color Space Converter (CSC) is a linear 3x3 matrix transformation with 3x1 offsets. The CSC implements the following equation:

where [x y z] is the input vector and [X Y Z] is the output vector.

The CSC can perform any linear 3x3 color space conversion such as interchange between RGB, YcbCr, etc. The coefficients and offsets of the CSC are fully programmable. For input, output, coefficient and off-set bit width and format, refer the Table 111.

Table 111 illustrates bit width for CSC modules.

Table 111: 88DE3010 VPP and their coefficient/offset formats

CSC Coeff icient (C0-C8) bit width, Sign.Int.Frac format

Offset (A0-A2) bit width, Sign.Int.Frac format

Input Bit with per component

Output bit width per component

CSC in Format Conversion stage (for G1 & G2 planes) and CSC in Scaling stage (for PG & G0 planes)

14, 1.4.9 16, 1.11.4 8 8

VOP CSC (HDMI/AHD/ASD/DV0/DV1)

14, 1.4.9 18, 1.13.4 12 12

ICSC (part of CMU) 14, 1.4.9 18, 1.13.4 8 10

GCSC (part of CMU) 14, 1.4.9 18, 1.13.4 10 11

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Video Post Processing (VPP)VPP Pipeline Control



15.14 VPP Pipeline Control15.14.1 Register Interface

All the VPP registers are accessible from CPU through internal AHB bus on 32bit boundary. It takes up 64KB address space in total.

In some applications frame accurate on-the-fly pipeline re-configuration is required (for example, a smooth scaling effect coupled with synchronized graphics overlay animation). In this case, a large number of VPP register needs to be reprogrammed during the video blank time. In order to achieve this without heavy loading on CPU interrupt routine, 88DE3010 has a DMA channel to program the VPP related registers automatically. It helps to program the registers at the maximum speed. To use this feature, CPU can prepares the register programming data in DRAM (address, data pairs) and then kick off the DMA programming channel during video blanking interval so that VPP registers are programmed in a seamless way without disturbing the output.

15.14.2 DRAM InterfaceVPP loads all frame data from DRAM. Two DMA engines (dHub0/vppDHub and dHub1/agDhub) interface VPP to DRAM controller through 2 independent 64bit AXI bus at 400MHz.

Refer to dHub Chapter for AVIO dHub channel assignment details.

15.14.3 Interrupt schemeAll the VPP related interrupts are segregated and sent to 88DE3010 SoC Interrupt Controller (PIC). The following VPP events can be enabled to generate interrupts:

CPCB0 VBI StartCPCB1 VBI StartCPCB2 VBI StartHDCP Interrupt eventCEC InterruptHDMI HPD plug and unplug eventCPCB0 Start of active video eventCPCB1 Start of active video eventCPCB2 Start of active video event

15.15 VPP Clock GenerationThe 88DE3010 uses AVPLL (Audio-Video PLL) to generate all the audio-video clocks. AVPLL generates following clock sources for VPP:

Over-sampling clock for CPCB0 (VCLK0)Over-sampling clock for CPCB1 (VCLK1)Over-sampling clock for CPCB2 (VCLK2) andHigh speed serial clock for HDMI-TX PHY

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Figure 68 describes the clock-scheme for VPP.

Figure 68: Block Diagram of 88DE3010's VPP Clock-scheme

CD-1

CD-2

CD-3

DV0_CLK

DV1_CLK

HDMIpixel clock

CD-4HDMI

pixel Repetition clock

HD encoderpixel clock

SD encoderpixel clock

CD-5HD Encoder

over-sampling clock

CD-6SD Encoder

over-sampling clock

VCLK0

VCLK1

VCLK2

asd_sel

ahd_sel

dv0_sel

dv1_sel

hdmi_sel

hdmi_sel

ahd_sel

asd_sel

PLL-A

PLL-B

1

2

2

1

5

AVPLL

7HDMI-TX

PHY

high-speed serial clock

HDMITMDS clock

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Video Post Processing (VPP)VPP Clock Generation



Table 112 describes AVPLL frequency settings and the CD (Clock Divider) settings referred by the above diagram for all the standard resolutions supported by the VPP (when HDMI is in 8 or 12-bit color-depths). The settings depend on HDMI color-depth because AVPLL VCO frequency would be different when generating clocks for 10-bit color-depth.

Table 112: AVPLL and Clock Divider settings for 8-bit and 12-bit color-depths of HDMI

Resolution AVPLL Frequency (MHz)

CPCB Clock Divider (CD-1,2,3)

HDMI Pixel Repeti t ion Factor, Divider (CD-4)

HD Encoder Over-sampling Factor, Divider (CD-5)

SD Encoder Over-sampling Factor, Divider (CD-6)

480i/576i 27 x 8 d8 2x (1440x480i), d8 NOT SUPPORTED

16x, d1

4x (2880x480i), d4 8x, d2

4x, d4

2x, d8

480p/576p 27 x 8 d8 none (720x480p), d8 8x, d1 NOT SUPPORTED2x (1440x480p), d4 4x, d2

4x (2880x480p), d2 2x, d4

1x, d8

720p 74.25 x 4 d4 none (1280x720p), d4 4x, d12x, d21x, d4

NOT SUPPORTED

1080i 148.5 x 2 d2 none (1920x1080i), d4 4x, d1 NOT SUPPORTED2x, d2

1x, d4

1080p 148.5 x 2 d2 none (1920x1080p), d2 2x, d1 NOT SUPPORTED1x, d2

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Table 113 indicate the settings when HDMI is in 10-bit deep-color mode:

Table 113: AVPLL and Clock Divider Settings for 10-bit color-depth of HDMI

Sl No

Resolution AVPLL Frequency (MHz)

CPCB Clock Divider (CD-1,2,3)

HDMI Pixel Repetit ion Factor, Divider (CD-4)

HD Encoder Over-sampling Factor, Divider (CD-5)

SD Encoder Over-sampling Factor, Divider (CD-6)

1 480i/576i 27x 4 d4 2x (1440x480i), d4 NOT SUPPORTED

8x, d1

4x (2880x480i), d2 4x, d2

2x, d4

2 480p/576p 27 x 4 d4 none (720x480p), d4

4x, d1 NOT SUPPORTED

2x (1440x480p), d2

2x, d2

4x (2880x480p), d1

1x, d4

3 720p 74.25 x 2 d2 none (1280x720p), d2

2x, d1 NOT SUPPORTED1x, d2

4 1080i 148.5 d1 none (1920x1080i), d2

2x, d1 NOT SUPPORTED1x, d2

5 1080p 148.5 d1 none (1920x1080p), d1

1x, d1 NOT SUPPORTED

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Video Post Processing (VPP)AVPLL



15.16 AVPLLFigure 69 illustrates the functional diagram of the 88DE3010 AVPLL. It is used to generate all the audio-video clocks. It consists of two core PLLs (PLL-A and PLL-B), working on a 25 MHz reference clock, which can generate 1.25875 GHz, 1.35 GHz, 1.5105 GHz, 1.62 GHz, 1.854395604 GHz and 2.225274725 GHz clocks. It provides 14 clock outputs which are derived from the 2 core PLLs. The frequency of each clock output from the AVPLL can be divided independently. On each channels there’s a phase interpolator that will enable a fixed 1000ppm frequency offset. This will enable 88DE3010 support both 60Hz and 59.94Hz systems. In additional, the phase interpolator for each channel also allows a programmable frequency output up to 1.5%. This offset can be used by the software to implementing STC clock tracking in MPEG-2 transport system.

Figure 114 shows all the 14 clock outputs from the AVPLL and their usage in 88DE3010

Figure 69: AVPLL Functional Diagram

Table 114: Clock Outputs from AVPLL

AVPLL Clock Output

Usage Notes

PLL-A[1] CPCB0 (HD primary video) clock (VCLK0)

PLL-A[2] CPCB1 (2nd video output) clock (VCLK1) VCLK1 has 2 sources: PLL-A[2] or PLL-B[2]

PLL-A[3] Primary Audio Clock

PLL-A[4] HDMI Audio Clock

PLL-A[5] CPCB2 (SD auxiliary video) clock (VCLK2) VCLK2 has 2 sources: PLL-A[5] or PLL-B[1]

PLL-A[6] NOT USED

PLL-A[7] HDMI high speed clock, used by HDMI-TX PHY

PLL-B[1] CPCB2 (SD auxiliary video) clock (VCLK2) VCLK2 has 2 sources: PLL-A[5] or PLL-B[1]

PLL-B[2] CPCB1 (2nd video output) clock (VCLK1) VCLK1 has 2 sources: PLL-A[2] or PLL-B[2]

PLL-B[3] Secondary Audio Clock

25MHzReference

Clock

Phase Interpolator

Pre & Feedback

Divider

PLL-A(VCOA)

Post DividerChannel 0

Phase Interpolator Post DividerChannel 1

Phase InterpolatorPLL-B

(VCOB) Post DividerChannel 12

Phase Interpolator Post DividerChannel 13

Pre & Feedback

Divider

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In the 88DE3010 device, the VCO frequency of AVPLL should be determined by the video resolution requirements. Each of the 14 clock outputs from AVPLL has its own Phase Interpolator and post-divider to control the frequency output. The post-divider supports division of 1, 1.5, 3, 7.5, 12.5, 15, 25 or any even number (up to 256). Video clocks are derived using post-divider, the phase interpolator is not used by default to generate video clocks unless STC clock tracking is needed. The audio clocks are generated in similar way, except the phase interpolator is enabled by default to achieve the exact frequency required by different audio system.

Using the combination of AVPLL Pre&Feedback divider, channel interpolator, and channel post divider, the 88DE3010 AVPLL is capable of providing clocks to support for all defined combination of following audio and video user scenarios:

Video resolution: 720x576, 720x480, 1280x720, 1920x1080Interlaced and progressive video8-bit,10-bit, and 12-bit pixel depth in HDMIOversampling clocks for video DAC (up to 297 MHz)50 Hz, 60 Hz, and 59.95 Hz system32 KHz,4.1 KHz and 48 KHz audio system192, 256, 384,512,768 FS audio bit clock

A 16-bit register Freq_Offset is used to control phase interpolator to generate frequency offsets of up to ±1.5% as in following formula:

Offset (%) = 100* Freq_Offset/(219)

PLL-B[4] Can be used by SoC modules




Table 114: Clock Outputs from AVPLL

AVPLL Clock Output

Usage Notes

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Audio DSP



16 Audio DSPThe audio DSP in 88DE3010 device is a high performance, general purpose DSP with enhancements addressing for high profile audio processing. It supports the following features:

Superscalar architecture, with up to 4 instructions executed per cycleHardware scheduling logic to determine the number of instructions to issue every cycleStatic branch prediction to minimize branching penaltiesHigh throughput load/store architecture allowing up to four 64-bit concurrent accesses to local memory (DTCM) per cycleSimple, orthogonal RISC instruction set16 16-bit general purpose registers Dual Multiplier Accumulator Unit (MAU) supporting total 4 16-bit Multiplication Accumulation calculation (MAC) operations per cycleSupporting four nested zero overhead loops16 low latency interrupts with programmable priorities128 KB ITCM and 128 KB DTCMUnified 32-bit address for TCM, external memories and memory-mapped I/OSupport JTAG based debuggerRunning at 500 MHz

The Audio DSP can handle all kinds of popular audio application on the market. Table 115 lists the number of clock cycles per second required for the typical audio codec

The Audio DSP is capable of handling multiple tasks of different codec as along as the total clock cycles required does not exceed 500M cycles (running at 500 MHz). In multi-task mode, it will switch between tasks by saving and restoring ITCM/DTCM context to/from external DRAM. There are some performance penalties for context switch. For each additional task, the extra clock cycles per second required for context switch is about 10M cycles.

Table 115: Audio DSP Performance

Audio codec Clock Cycles

Dolby Digital AC3 Encode (5.1ch 48 KHz) 45M

Dolby Digital Plus Decode (7.1ch 48 KHz) 44M

Dolby Digital TrueHD Decode (5.1ch 192 KHz) 76M

DTS Encode (5.1ch 48 KHz) 41M

DTS-HD MA Decode (5.1ch 192 KHz) 208M

DTS LBR Decode (5.1ch 48 KHz) 49M

MPEG 1/2/2.5 L1-3 Decode (2ch 48 KHz) 8M

MPEG2/4 HE-AAC V1/V2 Decode (5.1ch 48 KHz) 43M

WMA9 Decode (2ch 48 KHz) 16M

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16.1 Function Description16.1.1 Audio DSP Block Diagram

Figure 70: Audio DSP Block Diagram

16.1.2 InterfacesAudio DSP provides four major interfaces to communicate with rest of the 88DE3010 SoC.

A memory access interface. The audio DSP uses this interface as a master to accesses data in the external DRAM. A register access interface. The SoC CPU uses this interface to access the audio DSP ITCM, DTCM, control/status registers. Interrupt mechanism for communication between Audio DSP and SoC CPU.JTAG interface for Audio DSP firmware debug

16.1.2.1 Register Access InterfaceThe Audio DSP uses 512 KB of the system address space. Only 32-bit reads and writes are permitted. SoC CPU can access the ITCM, DTCM and control registers through this interface.

RegisterProgramming

Interface

Slave

JTAG

128KBITCM

128KBDTCM

DMAAudio DSP Core

Master

Interrupt tohost CPU

Master

Memory Access

Interface

ControlRegister

Master Slave Slave

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Audio DSPFunction Description



Table 116 shows the address mapping of Audio DSP register space on this interface.

16.1.2.2 Memory Access InterfaceThe Audio DSP access the external DRAM through the memory access interface. Two agents can issue requests, the DSP core and the DMA. The Audio DSP core uses this interface to access instruction/data in the external DRAM. The DMA uses this interface to transfer instruction/data between TCM and external DRAM.

The latency on the memory access could affect the Audio DSP firmware performance. It is recommended that if a large amount of code/data need to be loaded from DRAM, Audio DSP firmware needs to program DMA engine to preload those code/data into ITCM/DTCM before they are used.

16.1.3 ITCM/DTCM and DMA128 KB ITCM and 128 KB DTCM are included in the Audio DSP. The Audio DSP core accesses them through two independent high throughput internal data buses. Audio DSP core can fetch 4 instructions (128 bits) from ITCM in every cycle, which matches the throughput of the execution logic. The DTCM provides two 64-bit load ports and two 64-bit store ports. The Audio DSP core can issue two 64-bit load requests and two 64-bit store requests to DTCM in every cycle.

The Audio DSP core can also directly fetch instructions and load/store data from external DRAM without DMA engine, but the latency will be much higher than DTCM access and throughput will be much smaller. It’s recommended the Audio DSP core uses this type of access very occasionally.

The Audio DSP core can access the full 1GB physical external DRAM address space supported by 88DE3010, except for the lowest 512 KB (0x0 – 0x0007_FFFF). The lowest 512 KB address space is reserved for internal access to ITCM/DTCM and registers. Table 117 illustrates Audio DSP memory address map.

Table 116: Audio DSP Register Address Mapping

Offset address (Byte) Target

0x0_0000~0x1_ffff ITCM

0x2_0000~ 0x3_ffff DTCM

0x4_0000~ 0x6_3fff Reserved

0x6_4000~ 0x6_43ff Audio DSP Core Control/Status registers

0x6_4400~ 0x6_47ff Interrupt Register

0x6_4800~ 0x6_4bff DMA Register

0x6_4c00~0x7_ffff Reserved

NoteRefer to the SoC Connectivity section for Audio DSP base address.

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A DMA is used to transfer data between ITCM/DTCM and external DRAM. DMA transfers can be initiated either by Audio DSP core or by SoC CPU through the register programming bus. During a transfer, the DMA will access one of the ITCM/DTCM but it won’t stall the Audio DSP core.

The Audio DSP DMA engine supports only one DMA command at a time. After DMA transfer is finished, DMA engine will generate an interrupt to either Audio DSP or SoC CPU based on register programming. There is no restriction on byte alignment of DMA starting address on both DRAM and ITCM/DTCM access and no byte alignment restriction on DMA buffer size. The maximum DMA buffer size is 64K bytes.

16.1.4 InterruptThe Audio DSP core can communicate with SoC CPU through the interrupt registers. There are two sets of the interrupt registers. One used for interrupts to Audio DSP core and the other one used for interrupt to SoC CPU.

16.1.4.1 Interrupt to audio DSPThe Audio DSP supports 16 interrupts. Three of them are reserved for internal interrupt sources. Two are used for DMA. The other 11 are all from configuration registers. The SoC CPU can trigger interrupt to audio DSP by program one the 11 interrupt register bits.

All interrupts have programmable priority levels that can be programmed on the fly. In Audio DSP lower priority interrupts can be nested within higher priority interrupt service routines. Audio DSP supports vectorized interrupt handler. Once interrupt is received, Audio DSP will jump to the associate interrupt vector table offset in ITCM according to received interrupt. Table 118 lists the interrupts to Audio DSP.

Table 117: Audio DSP Memory Address Map

Address (Byte) Target

0x0_0000~0x1_ffff ITCM

0x2_0000~ 0x3_ffff DTCM

0x4_0000~ 0x6_3fff reserved

0x6_4000~ 0x6_43ff Audio DSP Core Control/Status registers

0x6_4400~ 0x6_47ff Interrupt Register

0x6_4800~ 0x6_4bff DMA Register

0x6_4c00~0x7_ffff reserved

0x8_0000~0x3fff_ffff External DRAM

0x4000_0000~ 0xffff_ffff reserved

Table 118: Interrupts to Audio DSP

Interrupt vector table offset in ITCM

Name Source

0x10 nmi_irq Interrupt to audio DSP register 0

0x20 dec_icu_irq reserved

0x30 dma_done_irq DMA done interrupt

0x40 dma_error_irq DMA error interrupt

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Audio DSPFunction Description



16.1.4.2 Interrupt to SoC CPUIn 88DE3010 Audio DSP, a set of configuration registers are used to control the interrupts to SoC CPU. The Audio DSP sends interrupt to SoC CPU by setting these interrupt control bits, which will trigger the interrupt line connected to the SoC PIC. There are totally 16 interrupt sources. Two are directly controlled by DMA. The other 14 are all from configuration registers. When any of the interrupt sources is active, an SoC CPU interrupt will be asserted. Table 119 lists Audio DSP generated interrupt sources to SoC CPU.

0x50 cpu-irq11 Interrupt to audio DSP register 1





0xa0 timer_irq_1 Internal timer 1 interrupt

0xb0 timer_irq_0 Internal timer 0 interrupt

0xc0 cpu-irq4 Interrupt to audio DSP register 6

0xd0 cpu-irq3 Interrupt to audio DSP register 7

0xe0 cpu-irq2 Interrupt to audio DSP register 8

0xf0 cpu-irq1 Interrupt to audio DSP register 9


Table 118: Interrupts to Audio DSP (Continued)

Interrupt vector table offset in ITCM

Name Source

Table 119: Audio DSP Generated Interrupt Sources

ID Name source

0 soft_int_0 Interrupt to SoC CPU register 0














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16.1.5 Audio DSP Initialization

After reset, Audio DSP will stay in idle mode. SoC CPU needs to prepare the initial ITCM/DTCM content in external DRAM and use the DMA to transfer them into ITCM/DTCM. After that, the SoC CPU needs to program the first instruction address into boot-up address register and then enable Audio DSP by setting the core enable register to 1. After enabled, Audio DSP will start to execute the firmware code from the boot-up address.

During the run time, Audio DSP and SoC CPU will keep communicating with each other by using the interrupt registers and exchange data through the external DRAM.

14 dma_done_irq DMA done interrupt

15 dma_error_irq DMA error interrupt

Table 119: Audio DSP Generated Interrupt Sources (Continued)

ID Name source

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Audio Post Processor (APP)Operation Model



17 Audio Post Processor (APP)In the 88DE3010 device, the Audio Post Processor (APP) is used to post process the decoded audio samples before they are sent out to the audio formatter (AIO module) through DRAM buffer.

APP is a command driven data processing engine with hardware support of the following audio signal processing functions:

FilterSampling rate converterFaderMixerSoft limiterDown mixerEqualizer

Each function is mapped to a single APP command. Some sophisticated tasks, such as bass management, can be implemented with a combination of the above basic functions.

17.1 Operation ModelAPP accesses the system memory through an external DMA engine (agDHub) in the AVIO module. Refer to the dHub Chapter for further details about dHub based DMA engine. It uses two DMA read channels and one DMA write channel. One of the read channels is used for loading APP commands. Firmware needs to set up DMA transfers for this channel and APP will read the APP commands through it. The other read channel is used for audio samples and coefficients loading. APP will setup DMA transfers for this channel. The write channel is used for saving audio samples to DRAM. APP will setup DMA transfers for this channel.

The behavior of APP is totally controlled by APP commands. Each APP command consists of

The source address of the input data buffer The destination address of the output data bufferThe size of the data to be processedType of data processingParameters of the data processing

Firmware prepares the APP commands in DRAM and then sets up the APP command DMA channel to load them. APP will read these commands through the DMA channel and execute them one by one in order. APP commands are classified into two categories: data loading/saving commands and data processing commands. Upon receiving a data loading/saving command, APP will issue these commands to the APP Data DMA channel to load data from DRAM into local SRAM or to save data to DRAM from local SRAM. Upon receiving a data processing command, APP will read data from SRAM, process the data as defined by the command and then write the data back to SRAM. With the combination of these two types of command, firmware can instruct APP to perform any of the pre-defined audio processing functions in a DRAM to DRAM manner.

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There are two Multiply-Accumulate Units (MAC) in APP and the whole block runs up to 600 MHz. This will provide a nominal computing power of 1200 million MAC instructions per second. Due to the data coherency conflicts and APP’s internal SRAM loading/saving congestion, the overall performance of APP will be between 900 million to 1200 million MAC instructions per second.

APP consists of three major functional blocks, command parser, local SRAM array, and execution logic.

Command parser analyzes the APP commands from DMA and splits them into atomic instructions for the execution logic. The SRAM array is a local storage to hold the input/output and intermediate data. Logically it is one big linear addressed memory. To provide parallel access, it is physically split into five pieces based on two LSB bits of the logic address. The splitting is transparent to APP command, where only linear address is used.The execution logic executes the atomic instructions, loads data from the SRAM array or DMA input FIFO interface and saves the results back to the SRAM array or DMA output FIFO interface.

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Audio Post Processor (APP)APP Functional Diagram



17.2 APP Functional DiagramFigure 71: Functional Diagram

17.2.1 APP DMA channelsAPP accesses the external DRAM through the dHub based DMA. There are a total of three DMA channels used by the APP module:

Loading APP commandsLoading input data / audio samples Saving output data / audio samples

All the three channels are included in agDHub engine in the AVIO sub-system. Refer to the dHub Chapter for further details about dHub based DMA engine.

Firmware will initiate the APP command-loading channel by setting registers in the DMA engine. For the data loading/saving channels, the DMA command and data transaction is initiated by APP. When APP initiates the DMA command, it can optionally enable the DMA interrupt. If the interrupt is enabled, DMA will issue an interrupt to the SoC CPUs after it finishes the DMA transaction.

CommandParser

Instruction Parser

SRAM Controller

Singal-Port

SRAM 0

Singal-Port

SRAM 3

Singal-Port

SRAM 2

Singal-Port

SRAM 1

CoherenceChecker

MACEngine

MACInput Data

FIFO

MACOutput Data

FIFO

SRAMSave Adr

FIFO

SRAMLoad Adr

FIFO

InstructionFIFO

MACControlFIFO

DMAFIFOFIFO FIFO FIFO

DMAWRITECMD

FIFO

DMAREADCMD

DMA Adaptor

DMAREADDATA

DMAWRITEDATA

INOUTSRAM

APPCMD

CmdInst InFIFO

CmdData InFIFO

CmdData Out

FIFO

Singal-Port

SRAM 4

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17.2.2 DMA AdaptorThis block converts the internal FIFO interface into the DMA protocol. There are three major functions in the block: synchronization, padding, and buffering.

The DMA adaptor isolates the clock between the rest of 88DE3010 SoC and the APP module. This will enable the APP module clock to be adjusted independently (up to 600 MHz) of the system clock, including the DMA engine (runs up to 400 MHz).

The DMA adaptor handles all the byte alignments so the APP DMA buffers do not have any byte alignment restrictions.

The DMA adaptor also provides the data buffering between the APP engine and the DMA for both read and write, so the APP engine performance will not be affected by the availability of the DMA channel.

17.2.3 Command ParserThe APP Command Parser reads and parses APP commands from DRAM. If the command is an AppDmaCmd, it will forward the DMA command to DMA adaptor. Otherwise, based on the type of the command, it will split the command into a group of instructions and send them into the instruction FIFO. The command parser is able to generate two instructions every cycle to match the APP execution unit performance.

17.2.4 Instruction ParserThe APP Instruction Parser loads instructions from the instruction FIFO. It split each instruction into three different parts, the SRAM loading address, the SRAM saving address, and the MAC control information. The instruction parser is capable to parse two instructions every cycle to match the performance of the APP execution unit performance. Instruction parser will be stalled when coherence checker detects a coherence conflict,

17.2.5 Coherence CheckerThe function of APP instruction coherence checker is to stall the Instruction Parser when data is loaded from an internal SRAM address that has a pending write operation by an earlier dispatched APP instruction.

17.2.6 SRAM controllerThe SRAM controller handles all the data routing between data storage, data source and destination DMA, and execution unit (the MAC engine).

17.2.7 MAC EngineMAC engine consists of two cascaded MAC units and one local register storing the sum of all the previous MAC operations. It reads four items from the MAC input data FIFO and uses them as the four inputs of the two MAC units. It also reads the MAC control command FIFO, decodes the commands and generates some control signals of the data path. It may write one or two or none of the two MAC outputs into the MAC output FIFO, depends on the value of decoded control signals.

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Audio Post Processor (APP)APP commands



Figure 72: MAC Engine Block Diagram

17.3 APP commandsAPP reads the APP commands from the external DRAM through its DMA channel. Each APP command can be variable length of 64 bits, 128 bits, or 192 bits depending on the command type.

Command parser will split all the APP commands into atomic instructions and the MAC engine will execute these instructions.

Table 120 summarizes all the APP commands

MAC 0Data In 0

MACCommand

* *

+

0SUM

+

MAC 1Data Out

0

Mac0Ctrl

CommandDecoding

MAC 1Data In 1

MAC 0Data In 1

MAC 1Data In 0

MAC 0Data Out

Limiter

Shifter

Limiter

Shifter

Mac1Ctrl

SUM

USUM 0

ASUM 0

ASUM 1USUM 1

Clipper Clipper

Table 120: APP Commands

Command Name Function

AppDmaCmd APP command parser will translate it into a DMA command and forward it to the APP DMA engine for data loading, data storing

AppDmaDat Transfer data between DMA engine and internal APP SRAMs

AppCopy Copy data from one APP SRAM location to another

AppFilter IIR filter with 1~256 forward taps and 0~15 backward taps

AppSrc N/M sampling rate conversion, where N and M both range from 1 to 255 (inclusive). 1~256 tap FIR is used for sampling rate conversion.

AppFader Apply increasing or decreasing gain to the input audio samples.

AppMixer Mix two multi-channel audio inputs into one.

AppDownMix Convert an N channel audio input into M channel with a gain matrix.

AppEqualizer Support up to 32 bands. Each band is defined by an IIR with up to 31 taps.

AppInterleave Interleave audio samples from two channels together for audio output.

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17.3.1 Atomic InstructionAll the APP commands listed Table 120 will be split into a sequence of atomic instructions by command parser. There are totally four types of atomic instructions:

AppMovAppMac AppMax AppLmt

17.3.1.1 AppMovAppMov saves the data from source address into destination address.

Table 121 lists AppMov instruction parameters:

Table 122 illustrates the function of AppMov instruction

17.3.1.2 AppMacAppMac calculates the product of input data, adds it to a 72-bit local accumulation register and saves the summary back to memory.

Table 123 lists AppMac instruction parameters.

Table 121: AppMov Instruction Parameters

Parameter Name Description

SRCADR[15:0] SRAM address of the data source

DESADR[15:0] SRAM address of the data destination

Table 122: AppMov Instruction

AppMove(SRCADR,DESADR){

*DESADR=*SRCADR;

}

Table 123: AppMac Instruction Parameters


CSUM[0:0] 1: Clear the sum register before the MAC;0: Do not clear the sum.

SSUM[0:0] 1: Save new sum to SRAM after the MAC;0: Do not save new sum to SRAM.

SHIFT[2:0] Right shift sum (28+SHIFT) before save back to memory.Valid only if SSUM is 1.

SRCADR1[15:0] SRAM address of the input data 1 for MAC.

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Table 124 illustrates the function of AppMac instruction

17.3.1.3 AppMaxAppMax compares the value of two inputs and saves the larger one into the memory.

Table 125 lists AppMax instruction parameters:

SRCADR0[15:0] SRAM address of the input data 0 for MAC.

DESADR[15:0] SRAM address of output data; Valid only if SSUM is 1.

Table 124: AppMac Instruction

AppMac(){

static [71:0] sum; //local variable in MAC engine

if(CSUM) {

sum = 0;

}

sum=sum+(*SRCADR0)*(*SRCADR1);

if(SSUM) {

*DESADR= clipper(sum>>(28+SHIFT));

}

}

clipper(sample) {

if(sample>231-1)

sample=231-1;

else if(sample<-231)

sample=-231;

return sample;

}

Table 123: AppMac Instruction Parameters


Table 125: AppMax instruction parameters


SRCADR1[15:0] SRAM address of the input data 1 for MAC

SRCADR0[15:0] SRAM address of the input data 0 for MAC

DESADR[15:0] SRAM address of output data;

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Table 126 illustrates the function of AppMax instruction.

17.3.1.4 AppLmtAppLmt reduces the dynamic range of the input data and save the result into memory.

Table 127 lists AppLmt instruction parameters.

Table 128illustrates the function of AppLmt instruction.

17.3.1.5 AppDmaCmdAPP command parser will translate it into a DMA command and forward it to the APP DMA engine for data loading, data storing.

Table 126: AppMax instruction

AppMax(){

*DESADR=(*SRCADR0>*SRCADR1)?*SRCADR0:*SRCADR1;

}

Table 127: AppLmt Instruction Parameters


SRCADR[15:0] SRAM address of the data source

DESADR[15:0] SRAM address of the data destination

Table 128: AppLMT Instruction Parameters

AppLmt(SRCADR,DESADR){

*DESADDR = soft_limiter(*SRCADR);

}

soft_limiter(sample) {

dynamic range compressor implemented with 16 step table look up

}

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17.3.1.6 AppDmaDatTable 129 lists AppDmaCmd parameters.

APPDmaDat transfers data between DMA engine and internal APP SRAMs.

Table 130 lists AppDmaDat parameters.

Table 131 illustrates the function of AppDmaDat.

Table 129: AppDmaCmd Parameters

Parameter Name Descript ion

WRITE[0:0] Direction of the DMA transfer 0 = DDR to DMA;1 = DMA to DDR;

INTERRUPT[0:0] 1= Upon finishing the execution of this command, DMA will issue an interrupt;0 = No interrupt

LENGTH[15:0] Size of the DMA transfer minus 1, in byte

DDRADR[31:0] DDR address of the DMA transfer, in byte

Table 130: AppDmaDat Parameters


WRITE[0:0] Direction of the DMA transfer 0 = DMA to work SRAM;1 = Work SRAM to DMA;

LENGTH[11:0] Size of the DMA transfer minus 1, in byte

OFFSET[11:0] Offset address of the transfer in the source/destination buffer, in DW

BUFSIZE[11:0] Size of the source/destination buffer in APP SRAM minus 1, in DW

BUFBASE[15:0] Base address of the source/destination buffer in APP SRAM, in DW

Table 131: AppDmaDat Functions

for(i=0;i<=LENGTH;i++) {

addr=BUFBASE+(OFFSET+i)%(BUFSIZE+1);

if(WRITE)

AppMov(SRCADR=addr,DESADR=DMA output FIFO);

else

AppMov(SRCADR=DMA input FIFO,DESADR=addr);

}

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17.3.2 AppCopyAPPCopy copies data from one APP SRAM location to another

Table 132 lists AppCopy parameters:

Table 133 illustrates the function of AppCopy

17.3.2.1 AppFilterAPPFilter implements an IIR filter with 1~256 forward taps and 0~15 backward taps

Table 134 lists AppFilter parameters:

Table 132: AppCopy Parameters


CHANNEL[3:0] Number of channels to process minus 1

LENGTH[8:0] Number of audio samples in each channel minus 1

SOFFSET[11:0] Offset address of the first sample in the source buffer, in DW

SBUFSIZE[11:0] Size of the source buffer in APP SRAM minus 1, in DW

SBUFBASE[15:0] Base address of the source buffer in APP SRAM, in DW

DOFFSET[11:0] Offset address of the first sample in the destination buffer, in DW

DBUFSIZE[11:0] Size of the destination buffer in APP SRAM minus 1, in DW

DBUFBASE[15:0] Base address of the destination buffer in APP SRAM, in DW

Table 133: AppCopy functions

for(channel=0;channel<=CHANNEL;channel++){

for(i=0;i<=LENGTH;i++){

AppMov(SRCADR=SBUFBASE+(channel*(SBUFSIZE+1))+

(SOFFSET+i)%(SBUFSIZE+1),

DESADR=DSUFBASE+(channel*(DBUFSIZE+1))+

(DOFFSET+i)%(DBUFSIZE+1));

}

}

Table 134: AppFilter parameters


CHANNEL[3:0] number of channels to process minus 1





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Table 135 illustrates the function of AppFilter


SHIFT[2:0] SHIFT for filter sum

TAPB[3:0] Number of backward filter taps

TAPF[7:0] Number of forward filter taps minus 1

COADR[15:0] Absolute address of the filter coefficients in APP SRAM, in DW

HISTADRB[15:0] Absolute address of the backward history data in APP SRAM, in DW

HISTADRF[15:0] Absolute address of the forward history data in APP SRAM, in DW

Table 135: AppFilter Functions

for(sample=0;sample<=LENGTH;sample++){


for(tap=0;tap<=TAPF;tap++){

if(sample+tap<TAPF){

srcAdr=HISTADR+channel*TAPF+sample+tap

}else{

srcAdr=SBUFADR+channel*(SBUFSIZE+1)+sample+tap

}

AppMac(SRCADR0=srcAdr,

SRCADR1=COADR+tap,

DESADR=DBUFADR+channel*(DBUFSIZE+1)+sample,

CSUM=(tap==0),

SSUM=(tap==TAPF-1)&(TAPB==0),

SHIFT=SHIFT);

}

for(tap=0;tap<TAPB;tap++){

if(sample+tap<TAPB){

srcAdr=HISTADR+HISTADRB+channel*TAPB+sample+tap

}else{

srcAdr=DBUFADR+channel*(DBUFSIZE+1)+sample+tap

}

AppMac(SRCADR0=srcAdr,

SRCADR1=COADR+TAPF+tap,


Table 134: AppFilter parameters (Continued)


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17.3.2.2 AppSrcAppSrc provides a N/M sampling rate conversion, where N and M both range from 1 to 255 (inclusive). 1~256 tap FIR is used for sampling rate conversion.

Table 136 lists AppSrc parameters:

Table 137 illustrates the function of AppSrc.

CSUM=(TAPF==0)&(tap==0),

SSUM=(tap==TAPB-1),

SHIFT=SHIFT);

}

SSUM=(tap==TAPB

}

Table 135: AppFilter Functions

Table 136: AppSrc Parameters




SOFFSET[11:0] Offset address of the first sample in the source buffer, in DW



DOFFSET[11:0] Offset address of the first sample in the destination buffer, in DW




TAP[7:0] Number of FIR filter taps minus 1

COADR[15:0] Absolute address of the filter coefficients in APP SRAM, in DW

N[7:0] Up sampling rate

M[7:0] Down sampling rate

INIT_PHASE[7:0] Initial output phase. Value of INIT_PHASE should range from 1 to M, inclusive.

Table 137: AppSrc function


sample_out=0;

phase_num=INIT_PHASE;

for(sample=0;sample<=LENGTH;sampe++) {

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17.3.2.3 AppFaderAppFader applies increasing or decreasing gain to the input audio samples.

Table 138 lists AppFader parameters:

for (phase = N-1; phase >=0; phase--) {

if ((phase_num% M) == 0) {

for(tap=0;tap<=TAP;tap++) {

AppMac(SRCADR0= SBUFBASE+(channel*(SBUFSIZE+1))+

(SOFFSET+sample)%(SBUFSIZE+1),

SRCADR1=COADR+phase*(TAP+1)+tap,

DESADR=DBUFADR+channel*(DBUFSIZE+1)+

(DOFFSET+sample_out)%(DBUFSIZE+1),

CSUM=(tap==0),

SSUM=(tap==TAP),

SHIFT=SHIFT);

}

sample_out++;

phase_num=0;

}

phase_num++;

}

}

}

Table 137: AppSrc function

Table 138: AppFader Parameter









COADR[15:0] Absolute address of the gain coefficients in APP SRAM, in DW

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Table 139 illustrates the function of AppFader.

17.3.2.4 AppMixerAppMixer mixes two multi-channel audio inputs into one.

Table 140 lists AppMixer parameters:

Table 139: AppFader Functions

AppMov(SRCADR=COADR,DESADR=MAC to command parser FIFO);

AppMov(SRCADR=COADR+1,DESADR=MAC to command parser FIFO);

AppMov(SRCADR=COADR+2,DESADR=MAC to command parser FIFO);

gain_begin=read MAC to command parser FIFO;

gain_delta= read MAC to command parser FIFO;

gain_target= read MAC to command parser FIFO;


gain=gain_begin;


write gain into command parser to MAC FIFO;

AppMac(SRCADR0=SBUFADR+channel*(SBUFSIZE+1)+sample,

SRCADR1=command parser to MAC FIFO,

DESADR=DSUFADR+channel*(DBUFSIZE+1)+sample,

CSUM=1,

SSUM=1,

SHIFT=SHIFT);

gain=gain+gain_delta;

if(gain>gain_target)

gain=gain_target;

}

}

Table 140: AppMixer Parameters




SBUFSIZE0[11:0] Size of the source buffer 0 in APP SRAM minus 1, in DW

SBUFBASE0[15:0] Base address of the source buffer 0 in APP SRAM, in DW

SBUFSIZE1[11:0] Size of the source buffer 1 in APP SRAM minus 1, in DW



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Table 141 illustrates the function of AppMixer.



COADR[15:0] Absolute address of the gain coefficients in APP SRAM, in DW

MONO[0:0] 0:Multi channel mix with multi channel1:Multi channel mix with mono

LIMIT[0:0] 0: Not apply softer limiter to output samples.1: Apply softer limiter to output samples.

Table 141: AppMixer Functions


AppMove(SRCADR=COADR+channel,DESADR=MAC to command parser FIFO);

AppMove(SRCADR=COADR+(CHANNEL+1)+channel,DESADR= MAC to command parser FIFO);

AppMove(SRCADR=COADR+2*(CHANNEL+1)+channel,DESADR= MAC to command parser FIFO);

AppMove(SRCADR=COADR+3*(CHANNEL+1)+channel,DESADR= MAC to command parser FIFO);

gain_0 = read MAC to command parser FIFO;

gain_delta_0 = read MAC to command parser FIFO;

gain_1 = read MAC to command parser FIFO;

gain_delta_1 = read MAC to command parser FIFO;


write gain_0 into command parser to MAC FIFO

write gain_1 into command parser to MAC FIFO

AppMac(SRCADR0=SBUFADR0+channel*(SBUFSIZE0+1)+sample,


DESADR=0,

CSUM=1,

SSUM=0,

SHIFT=SHIFT);

AppMac(SRCADR0=SBUFADR1+(MONO?0:(channel*(SBUFSIZE1+1)))+sample,



CSUM=0,

SSUM=1,

SHIFT=SHIFT);

Table 140: AppMixer Parameters (Continued)


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17.3.2.5 AppDownMixAppDownMix converts an N channel audio input into M channel with a gain matrix.

Table 142 lists AppDownMix parameters:

Table 143 illustrates the function of AppDownMix.

if(LIMIT) {

AppLmt(SRCADR=DBUFADR+channel*(DBUFSIZE+1)+sample,

DESADR=DBUFADR+channel*(DBUFSIZE+1)+sample);

}

gain_0=gain_0+gain_delta_0;

gain_1=gain_1+gain_delta_1;

}

}

Table 141: AppMixer Functions (Continued)

Table 142: AppDownMix Parameters


CHANNELI[4:0] number of input channels minus 1

CHANNELO[3:0] number of output channels minus 1







COADR[15:0] Absolute address of the gain matrix in APP SRAM, in DW

Table 143: AppDownMix functions


for(channelo=0;channelo<=CHANNELO;channelo++){

for(channeli=0;channeli<=CHANNELI;channeli++){

AppMac(SRCADR0=SBUFADR+channeli*(SBUFSIZE+1)+sample,

SRCADR1=COADR+channelo*(CHANNELI+1)+channeli,

DESADR=DBUFADR+channelo*(DBUFSIZE+1)+sample,

CSUM=(channeli==0),

SSUM=(channeli==CHANNELI),

SHIFT=SHIFT);

}

}

}

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17.3.2.6 AppEqualizerAppEqualizer supports up to 32 bands. Each band is defined by an IIR with up to 31 taps.

Table 144 lists AppEqualizer parameters:

Table 145 illustrates the function of AppEqualizer

Table 144: AppEqualizer Parameters




SBUFADR[15:0] Base address of the source buffer in APP SRAM, in DW

DBUFADR[15:0] Base address of the destination buffer in APP SRAM, in DW

BAND[5:0] Number of band minus 1

GAINADR[15:0] Absolute address of the gain coefficients in APP SRAM, in DW

SHIFG[2:0] SHIFT for gain sum

TAP[3:0] Number of IIR filter tap minus 1

FLTRADR[15:0] Absolute address of the filter coefficients in APP SRAM, in DW

SHIFF[2:0] SHIFT for filter sum

HISTADR[15:0] Absolute address of the history data in APP SRAM, in DW

MAXADR[15:0] Absolute address of the maximum value of each band in APP SRAM, in DW

Table 145: AppEqualizer Functions


for(band=0;band<=BAND;band++){

AppFilter(CHANNEL=CHANNEL,

LENGTH=0,

SBUFSIZE=LENGTH,

SBUFBASE=SBUFADR+sample,

DBUFSIZE=TAP+1,

DBUFBASE=HISTADR+(band+1)*(CHANNEL+1)*(TAP+1),

SHIFT=SHIFTF,

TAPB=TAP+1,

TAPF=TAP+1,

COADR=FLTRADR+band*(TAP*2+3),

HISTADRB=HISTADR+(band+1)*(CHANNEL+1)*(TAP+1);

HISTADRF=HISTADR);

}


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AppMov(SRCADR=HISTADR+((band+1)*(CHANNEL+1)+channel)*(TAP+1),

DESADR=HISTADR+channel*(TAP+1);

for(tap = 0;tap<TAP;tap++){

AppMov(SRCADR=HISTADR+((band+1)*(CHANNEL+1)+channel)*(TAP+1)+tap+1,

DESADR=HISTADR+((band+1)*(CHANNEL+1)+channel)*(TAP+1)+tap);

}

AppMov(SRCADR=HISTADR+channel*(TAP+1),

DESADR=HISTADR+((band+1)*(CHANNEL+1)+channel)*(TAP+1)+TAP);

}

}


for(tap = 0;tap<TAP;tap++){

AppMov(SRCADR=HISTADR+channel*(TAP+1)+tap+1,

DESADR=HISTADR+channel)*(TAP+1)+tap);

}

AppMov(SRCADR=SRCADR+channel*(LENGTH+1)+sample,

DESADR=HISTADR+channel*(TAP+1)+TAP);

}



AppMac(SRCADR0=HISTADR+((band+1)*(CHANNEL+1)+channel)*(TAP+1)+TAP,

SRCADR1=GAINADR+band,

DESADR=DBUFADR+channel*(LENGTH+1)+sample,

CSUM=(band==0),

SSUM=(band==BAND),

SHIFT=SHIFTG);

AppMax(SRCADR0=DBUFADR+channel*(LENGTH+1)+sample,

SRCADR1=MAXADR+band*(CHANNEL+1)+channel,

DESADR=MAXADR+band*(CHANNEL+1)+channel);

}

}

}

Table 145: AppEqualizer Functions (Continued)

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17.3.2.7 AppInterleaveAppInterleave interleaves audio samples from two channels together for audio output.

Table 146 lists AppInterleave parameters:

Table 147 illustrates the function of AppInterleave.

Table 146: AppInterleave Parameters


LENGTH[8:0] Number of audio samples from each input source minus 1




Table 147: AppInterleave functions


AppMov(SRCADR=SBUFADR0+sample,DESADR=DBUFADR+2*sample);

AppMov(SRCADR=SBUFADR1+sample,DESADR=DBUFADR+2*sample+1);

}

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18 Audio Input OutputThe main function of Audio input-output (AIO) module is to transmit the audio stream prepared in DRAM by firmware in supported audio formats. The 88DE3010 AIO also has digital stereo audio input port to de-serialize the input audio stream and store it to DRAM.

The 88DE3010 AIO module supports simultaneous data transmission and reception on all the following ports:

7.1 channel audio Primary port: This audio transmitter generates the 7.1 channel audio output. Firmware can configure this port as 2/4/6/8 channels by programming the port configuration registers.Stereo audio Secondary port: This stereo audio transmitter generates the stereo audio output (2 channels). HDMI audio HD port: The HD audio transmitter is capable of generating High Bit Rate audio (HBR) and pass the output data to the HDMI module in Video Post Processing (VPP) unit. Firmware has the option of sending data either from the 7.1 channel audio transmitter or from HD audio transmitter to the HDMI module. S/P-DIF port: The S/P-DIF transmitter generates the S/P-DIF stream from the input data. Digital audio input port: The digital audio receive module receives the input audio stream, decodes and stores it in DRAM.

The 88DE3010 support I2S, Left-Justified and Right-Justified modes on all audio I/O ports except S/P-DIF output port.

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Audio Input Output



Figure 73 illustrates the functional diagram of the AIO module.

Figure 73: Functional diagram of AIO module

7.1 Audio PortFiFo

HD Audio PortFiFo

7.1 Audio Transmitter(primary)

HD AudioTransmitter

(HBR)

Stereo AudioTransmitter (Secondary)

S/PDIF AudioTransmitter

RX AudioReceiver

bClkSec

bClkHD

bClkS/PDIF

1

0

AIO Configuration Registers

Flush

TX underFlow/RX OverFlow

Interrupt32-bit Register Configuration interface

bClkRX

Port Configuration values

LRCK Primary

Data Primary [3:0]

LRCK HD

Data Secondary

LRCK RX

DATA RX

MCLK Primary

MCLK HD

MCLK Secondary

MCLK S/P-DIF

bClkPri 01

invBclk

bClkPriOut

0

1invBclk

bClkHD

0

1bClkSecOut

bClkSec

bClkHDOut

Bit Clock Sync

sysClk

10

hdPortTxSel

Clock Divider(divide by 1/2/4/8/

16/32/64/128)

BCLK RX

MCLK S/P-DIF

bClkPri

invBclk

1

0Data HD [3:0]

64-bitDMA

Interface

Read channel

4 Read channels

LRCK Secondary

S/P-DIF Out

StereoAudio

Port FiFo

S/P-DIF Audio

Port FiFo

RXAudio

Port FiFo

Read channel

Read channel

Write Channel

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The 88DE3010 AIO module utilizes eight DMA channels in agDHUB DMA engine in the AVIO subsystem. Refer to 88DE3010 datasheet part2, dHub chapter for further details on DMA channel assignments.

For output audio ports, 88DE3010 firmware is responsible to prepare audio samples in the DRAM buffers. Each DRAM buffer contains data for a pair of channels in the same port. For primary port, there are four channel pairs – channel 0/1, 2/3, 4/5, and 6/7. For secondary port, HDMI audio HD port, S/P-DIF port, and digital audio input port, there is only one channel pair – channel 0/1.

The 88DE3010 firmware will setup the DMA channels for data loading, and initializes the transmitters to start sending the data out. Each audio port can be started and stopped independently.

For each input/output ports, there are audio FIFOs between the DMA channel and the Transmitter/Receiver block. In unexpected or error cases when underflow or overflow happens an interrupt will be generated. All the FIFO’s can be flushed by firmware.

The 88DE3010 AIO module also has audio clock logic to generate the various sampling clocks (Bit-Clocks or BCLK) required for each port by dividing from Master Clock (MCLK). The source of MCLK is driven by the AVPLL or external source. Refer to the AVPLL section in the VPP Chapter for all supported audio clock source frequencies by the AVPLL.

18.1 Audio Clock GenerationThe audio clock module generates the data BCLK for AIO module by dividing the input Master Clock (MCLK) by 1/2/4/8/16/32/64/128. The desired BCLK clock frequency and polarity can be selected by programming the AIO registers.

18.1.1 Audio Clock Scheme The AIO uses the following clock sources from the AVPLL:

1. AVPLL-A3: Provide master clocks (MCLK) for Primary, S/P-DIF and digital audio input ports.2. AVPLL-A4: Provide HD master clock for HDMI audio 3. AVPLL-B3/A3: Provide master clock for secondary port

By using three independent AVPLL outputs, each of the audio clocks can be fine adjusted to track the audio source rate if the source stream is from broadcast or network.

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Audio Input OutputSampling rate and Bit Clock



Figure 74 shows the audio clock generation scheme:

Figure 74: Audio Clock Generation Scheme

18.2 Sampling rate and Bit Clock The bit clock toggles once for each discrete bit of data on the data lines. The bit clock frequency is derived by the number of bits per channel, the number of channels, and the sampling rate. For example, stereo audio (2 channels) with a sample frequency of 192 KHz and 16-bits per sample will have a bit clock frequency of 6.144 MHz (192x2x16). The word select clock (LRCK) indicates whether Left Channel or Right Channel data is currently being sent to the device. Transitions on the LRCK also serve as a start-of-word indicator. The LRCK frequency is always the same as the audio sampling rate. The sampling size and sampling rate must be same within the same channel pair and the same port.

audioHdExtClksel

audioFastExtClkSel

External Audio 0 Clock :: DV1_VS (ACLKI[0])

External Audio 1 Clock :: DV1_FID ACLKI[1])

Clock Divider (1/2/3/4/6/8/12)

S/P-DIF Audio Master Clock

RX Audio Master Clock Out

audio1ClkPllSel

audio1ExtClkSel

0

1audio1SrcClkSel

A

3

B

4

3

0

1

audioHdClksel

1

0

HD Audio Master Clock HD MCLK

Divider(1/2/4/8/16/32/64/128)

0

11

0

audioFastClkSel

Primary Audio Master Clock

Secondary Bit-Clock

AVPLL

Primary MCLKDivider

(1/2/4/8/16/32/64/128)

Primary Bit-Clock

Clock Divider (1/2/3/4/6/8/12)

S/P-DIF MCLKDivider

(1/2/4/8/16/32/64/128)

S/P-DIF Bit-Clock

SecondaryAudio Master

Clock Secondary MCLKDivider

(1/2/4/8/16/32/64/128)

1

0

0

1

DividerClkSel

DividerClkSel

DividerClkSel

DividerClkSel

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Table 148 shows the required BCLK frequency for supported audio sampling rates at 32FS/48FS/64FS.

To generate desired frequencies for audio clocks, AVPLL must be first configured to generate required MCLKs. AIO clock dividers must be programmed to generate correct BCLKs and LRCKs from MCLKs. Refer to the AVPLL section in the VPP Chapter for details of generating MCLKs.

18.3 AIO Transmitters and ReceiverAIO has four digital audio transmitters and one receiver. Table 149 lists the capabilities of each of these.

Table 148: Sampling Rate and Bit Clock Relationship

Sampling rate(FS)

Bit- clock frequency (MHz)

32FS 48FS 64FS

32KHz 1.02 1.536 2.048

44.1KHz 1.4112 2.1168 2.8224

48KHz 1.536 2.304 3.072

96KHz 3.072 4.608 6.144

192KHz 6.144 9.216 12.288

Table 149: AIO Transmitter and Receiver Capabilities

Transmitter/Receiver

# Channels Data resolution FS (LRCK width in terms of data bits)

Data modes Master/Slave mode

7.1 channel audio primary transmitter

8 channel 16/18/20/24/32-bit 32/48/64FS I2S, Left- Justified, and Right-Justified

Master

Stereo audio secondary transmitter

2 channel 16/18/20/24/32-bit 32/48/64FS I2S, Left- Justified, and Right-Justified

Master

HD audio transmitter

2/8 channel 16/18/20/24/32-bit 32/48/64FS I2S, Left- Justified, and Right-Justified

Master

S/P-DIF transmitter

2 channel 24-bit - S/P-DIF Master

Audio receiver 2 channel 16-bit 32/48/64FS I2S, Left- Justified, and Right-Justified

Slave

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Audio Input OutputData formats



18.4 Data formatsThe 88DE3010 AIO supports I2S mode, Left-Justified mode, Right-Justified mode and S/P-DIF mode.

The following sections provide brief description about each of the supported data formats.

18.4.1 I2S modeIn I2S mode, data is sent out “one” BCLK after the LRCK transition. In this mode left channel data is transmitted during the low period of LRCK and right channel data is transmitted during the high period of LRCK. Figure 75 shows the I2S mode.

Figure 75: I2S mode

18.4.2 Left-Justified mode In Left-Justified mode, there is no BCLK delay between the first data transmission and the LRCK transition and data is aligned with the leading transitions on LRCK. In this mode left channel data is transmitted during the high period of LRCK and right channel data is transmitted during the low period of LRCK. Figure 76 shows the Left-Justified mode.

Figure 76: Left-Justified mode

18.4.3 Right-Justified modeReferring to Figure 77, its relatively apparent that the Right-Justified format is very similar to the Left-Justified format, with the exception that the placement of channel data within the LRCK. In this mode the data lines up with the right edge of LRCK transition and last bit of the data is transmitted one BCLK before the LRCK transition.

As with the Left-Justified mode, left channel data is transmitted during the high period of LRCK and right channel data is transmitted during the low period of LRCK. Figure 77 shows the Right-Justified mode.

BCLK

FSYNC/LRCK

1 2 3 ------ n-1 n

Left Channel

TSD 0/1/2/3MSB LSB

Right Channel

MSB LSB

1 BCLK 1 BCLK1 2 3 ------ n-1 n

1/fs

BCLK

FSYNC/LRCK

1 2 3 ------ n-1 n

Left Channel

TSD 0/1/2/3MSB LSB

Right Channel

MSB LSB1 2 3 ------ n-1 n

1/fs

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Figure 77: Right-Justified mode

18.4.4 S/P-DIF S/P-DIF transmitter generates the S/P-DIF stream up to 192 KHz from the input data. This block operates on S/P-DIF Master Clock (MCLK) generated from the AVPLL or from external source.

S/P-DIF module reads the input audio stream from DRAM using a dedicated DMA Channel and generates the serial S/P-DIF output. S/P-DIF functionality is divided among firmware and hardware. AIO hardware performs the following functions:

Sync preamble codingParity bit generationOutput channel coding in bi-phase-mark-code (BMC)

The functions performed by firmware are:

Block and frame formatsValidity flag, user data format and channel status

Figure 78 shows the S/P-DIF frame format:

Figure 78: S/P-DIF Frame Format

BCLK

FSYNC/LRCK

1 2 3 ------ n-1 n

Left Channel

TSD 0/1/2/3MSB LSB

Right Channel

MSB LSB1 2 3 ------ n-1 n

1/fs

M Channel 1 BW Channel 2 Channel 1 Channel 1W Channel 2 W Channel 2M M

Frame 191 Frame 0 Frame 1

Sub-frame Sub-frame

X Y Z Y X Y X

Start of block

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Audio Input OutputData formats



18.4.4.1 S/P-DIF internal Sub-Frame format AIO receives the S/P-DIF data from firmware in the following sub-frame format. Each sub frame is 32-bit's long as shown in Figure 79.

Figure 79: S/P-DIF internal frame format

Bits 0 to 3 carry one of the three permitted preambles. AIO directly encode the received 4-bit data into the corresponding preamble sync words as shown in Table 150.

Bits 8 to 31 carry the audio sample word in linear 2's complement representation.

Bit 4 carries the validity flag associated with the audio sample word, this flag is set to logical 0 if the audio sample is reliable, and it is set to logical 1 if unreliable. Firmware maintains this bit.

Bit 5 carries one bit of the user data channel associated with the audio channel transmitted in the same sub frame. Firmware maintains this bit.

Bit 6 carries one bit of the channel status word associated with the audio channel transmitted in the same sub frame. Firmware maintains this bit.

Bit 7 is meant of parity AIO hardware calculates the parity for the sub-frame.

SYNCVUCPAuxData

bits

Validity FlagUser DataChannel Status

Parity Bit

Audio SampleWord

31 ----- 12 11 - 8 7 6 5 4 3 - 0MSB

LSB

Table 150: Encoding for Preambles

Preamble Word Encoding [3:0]

B “0000”

M “0010”

W “0011” –“1111”

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19 Peripheral Sub SystemThe Peripheral Subsystem integrates various standard interface controllers to provide connectivity between the 88DE3010 device’s SoC and the variety of peripheral devices that can be attached to the 88DE3010 device.

The SATA host controller provides connectivity to an external optical drive and/or hard drive. The Ethernet controller provides support for IEEE 802.3 at 10/100 Mbps. The PCIe controller provides the capability for an external host to talk to the 88DE3010. The two USB host controllers provide connections to external USB 2.0 compliant devices. The SDIO host controller supports SD memory card and other applications based on SDIO interface. The NAND flash controller supports various data flashes. The Local Bus Controller (LBC) provides an 8-bit asynchronous parallel interface to connect to an external device. The TWSI and SPI controllers provide an interface for 88DE3010 to access various low speed devices.

19.1 DescriptionThere are dedicated controllers to handle the communication protocol for each of the standard interfaces of the 88DE3010. All of the controllers have connection to an internal slave bus interface for register programming. Most of the high speed interface controllers such as SATA, PCIe and USB, also include a built-in DMA, which enable them to access the 88DE3010 device’s system memory as a master. To improve the performance of those low speed controllers without built-in DMAs, a common DMA module (pBridge) is integrated to transfer data between low speed devices and the system memory on behalf of the CPU. For the details of pBridge, refer to the pBridge chapter.

Besides the interface controllers, there are also some functional blocks in the peripheral sub-system. These blocks include the Digital Rights Management (DRM) engine that supports various DRM schemes used in consumer electronic applications. There are also 8 timers, 3 watch dog timers and local PIC (programmable interrupt controllers) for the low speed interface controllers.

Figure 80 is the diagram of the peripheral sub-system:

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Peripheral Sub SystemDescription



Figure 80: 88DE3010 Peripheral Block Diagram

PERIFData Bus

Crossbar

PCIe

Ethernet MAC

SATAHost 0

USBHost 0

32-bit @200Mhz

NANDFlash

DRM

64-bit@200Mhz

64-bit Data Bus Master @400Mhz

64-bit Data Bus Slave @400Mhz

32-bit Configuration BusSlave @100Mhz

TWSI

4-bit MII @25Mhz

pBridge

x4 TSI

8-bit ASync

SATAHost1

Arb

x2 TWSI

x1 SPI

x32 GPIO

PHY

64-bit @200Mhz

USBHost 1

8-bit UTMI @60Mhz

DMX

LBC

SDIO

PWM

PTP

PHY

PHY

PHY

PHY

x4 PWM

8-bit PIPE @250Mhz

20-bit @150Mhz

20-bit @150Mhz

8-bit UTMI @60Mhz

PIC

4-bit @50Mhz

interrupt

NAND/LBC

ConfigBus

Crossbar

Low speed perif

ConfigBus

CrossbarSPIHandler GPIO

SPI

WatchDog

Timer

2.5Gbps

3.0Gbps

3.0Gbps

480Mbps

480Mbps

64-bit@200Mhz

32-bit @200Mhz

64-bit @200Mhz

32-bit @200Mhz

64-bit @200Mhz

64-bit @200Mhz

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The integrated peripheral sub-system communicates with the 88DE3010’s SoC through four interfaces as listed below:

32-bit slave interface on the configuration bus running @100 MHz for system CPUs to access PERIF registers64-bit master interface on the data bus @400 MHz for PERIF DMAs to access system memories64-bit slave interface on the data bus @400 MHz for system CPUs to access the external device/host memory map through PCIeInterrupts to system CPUs

The peripheral sub-system supports the following external interfaces:

1 PCI Express 1.0a x1 RootComplex or EndPoint with integrated PHY2 SATA Gen2 host interface with integrated PHYs2 USB 2.0 host interface with integrated PHYs1 10/100 Ethernet with MII interface1 SDIO controller interface, 1 bit or 4 bit mode1 8-bit NAND flash controller interface1 8-bit parallel Local Bus Controller interface (dynamically shares pins with NAND flash controller)2 TWSI interfaces. Can be programmed to be master or slave individually.1 SPI master interface.32 GPIO pins, the GPIOs are pin shared with other interfaces, refer to the 88DE3010 datasheet part 1 for pin multiplex details.4 PWM pinsTransport stream input interfaces support up to 4 serial ports or (1 parallel port and 2 serial ports)

19.2 External interface controllers19.2.1 PCIe controller with integrated PHY

The PCI Express interface in 88DE3010 has the following features.

PCI Express Base 1.0a compatibleConfigurable as RootComplex or Endpointx1 link width and 2.5 GHz signalingLane polarity reversal supportMaximum payload size of 128bytesSingle virtual channel (VC-0) supportIngress and egress flow controlExtended Tag supportInterrupt Emulation Message supportPower Management: L0s-RX and SW L1 supportAdvanced Error Reporting (AER) capability supportSingle function device configuration headerMessage Signaled Interrupts (MSI) capability support, as an Endpoint.Power Management (PM) capability support, as an Endpoint.Expansion ROM support

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Peripheral Sub SystemExternal interface controllers



Programmable address map.Supports 3 BARs (BAR0,BAR1, and BAR2)No ECRC support

19.2.2 Ethernet MAC Controller InterfaceThe 10/100 Ethernet MAC Controller in 88DE3010 has the following features:

IEEE 802.3 compliant MAC layer functionIEEE 802.3u compliant MII interface10/100 Mbps operation – half and full-duplexFlow Control features• IEEE 802.3x flow-control for full-duplex operation mode• Backpressure for half-duplex operation modeInternal and External loopback modes1/2k or 8k address filtering capability – Hash table is fetched from external memoryIntegrated Transmit & Receive FIFOsIntegrated Transmit & Receive DMA – DMA supports scatter & gather linked-list buffer descriptor schemePer packet interrupt generation

19.2.3 SATA Host Controller with integrated PHYThe SATA host Controllers in 88DE3010 has the following features:

Serial ATA 2.5 compliant • Gen2 Serial ATA PHY (3Gb/s) with speed negotiation to Gen1• Supports Gen1i, Gen1m, Gen1x, Gen2i, Gen2m, and Gen2x Supports the following protocols over SATA ports• ATA and ATAPI commands • Native Command Queuing (NCQ)

• In-order data delivery • 32 outstanding commands per port

Vendor Unique commands Port Multiplier • FIS-based Switching on NCQ, and legacy commands Supports Port Selector Supports Interrupt Coalescing

88DE3010 device integrates two SATA Host Controllers.

19.2.4 USB Host Controller with integrated PHYThe USB host Controllers in 88DE3010 has the following features:

USB 2.0 compliant Intel™ EHCI host controller. The USB host controller registers and data structures are compliant to Intel ™ EHCI

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Dedicated transmit and receive buffers to isolate memory latency on the system bus from the timing requirements of the USB

88DE3010 integrates two USB Host Controllers.

19.2.5 NAND Flash Controller The NAND flash controller in 88DE3010 has the following features:

Supports two chip selects and 8-bit interface to the data-flash device.Supports ganging of 8-bit devices into a logical 16-bit device.Supports 32/64/128/256 page block sizes.Supports 512 byte, 2 KB, 4 KB and larger pages.Uses the system DMA for data-flash data transfers.Computes ECC and corrects single-bit errors and detects 2-bit errors per page using Hamming code.Computes ECC and corrects up to 16 errors per page (including spare, if enabled and parity bits themselves) using BCH code.Programmable interface timings.Interrupts can be enabled to indicate page and command completion, bad blocks, bit errors, flash-ready status and command, and data-write/read requests

For further details, refer to the NAND Flash Controller chapter.

19.2.6 Local Bus Controller (LBC)LBC provides a host bus interface to enable CPUs to access different external I/O devices.

8-bit asynchronous parallel interfaceThree dedicated address bits to access the external device’s registersProgrammable data/address setup time and hold time to control signalsProgrammable width for control signals

LBC shares data and control pads with NAND Flash Controller (NFC). The arbitration of the pads between LBC and NAND is carried out in hardware and transparent in software. For further details, refer to the LBC chapter.

19.2.7 SDIO host Controller The SDIO host Controllers in 88DE3010 has the following features:

Meets SD Host Controller Standard Specification Version 2.0Meets SDIO card specification version 2.0Meets SD Memory Card Specification Draft version 2.0Meets SD Memory Card Security Specification version 1.01Meets MMC Specification version 3.31, 4.2, and 4.3Meets CE-ATA Digital Protocol revision 1.1Supports both DMA and Non-DMA mode of operationSupports CE-ATA Digital Protocol commands (CMD60 / CMD61)Supports MMC Plus and MMC MobileCard Detection (Insertion / Removal)Password protection of Cards

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Peripheral Sub SystemExternal interface controllers



Host clock rate variable between 0 and 50 MHzSupports 1 bit and 4 bit SD modes and SPI modeSupports Multi Media Card Interrupt modeAllows card to interrupt host in 1bit and 4 bit SD modes and SPI mode.Up to 100Mbits per second data rate using 4 parallel data lines (sd4 bit mode)Cyclic Redundancy Check CRC7 for command and CRC16 for data integrityDesigned to work with I/O cards, Read-only cards and Read/Write cardsError Correction Code (ECC) support for MMC4.3 cardsSupports Read wait Control, Suspend/Resume operationSupports FIFO Overrun and Underrun condition by stopping SD clock

19.2.8 Transport stream input interfaceThe transport stream interface has the following features:

Accept MPEG2 TS stream (188 bytes) and Cable card 2.0 packet (200 bytes)Can be configured to support either 4 serial ports or 1 8-bit parallel port and 2 serial ports simultaneouslySupport up to 80 Mbps per stream

The output of the Transport stream interface are directly send to the DRMDMX sub-system for further processing. Refer to the Transport Stream processor and digital right management (DRMDMX) sub-system for more details about the transport stream input and processing.

19.2.9 TWSI interface88DE3010 integrates two TWSI interfaces in the SoC power domain, and two TWSI interfaces in the SM power domain.

Each TWSI interface has the following features:

Can be programmed to be either a master or a slave.Can operate in standard mode (data rates up to 100 kbps) and fast mode (data rates up to 400 kbps).Programmable baud-rate and SCL duty-cycles using HCNT and LCNT (high and low count) counter registers with a source clock of 100 MHz for the SoC power domain, and 10-30 MHz for the SM power domain.Supports of 7-bit and 10-bit addressing modes.Programmable SAR (slave address register).Ability to dynamically update the TAR (target address register) in master mode without the need to disable the TWSI interface.• Available for both SoC TWSI interfaces, and SM TWSI0.Supports re-start conditions. This allows a master to send multiple bytes per transfer, change direction within a transfer, send a start byte, perform combined format transfers in 7 and 10-bit addressing modes and perform a read operation with a 10-bit address.• Some older slaves may not support re-start conditions.Controllable via pBridge DMA engine.Operation status registers to indicate FIFO, and TWSI master and slave FSM activity status.Error status registers for debugging the reasons behind transfer aborts such as lost of arbitration, ACK time-out, etc.…Maskable interrupt support for the following events:• Receive FIFO underflow, overflow, full (programmable threshold).

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• 64-byte RX FIFO for SoC, 8-byte for SM.• Transmit FIFO overflow, empty (programmable threshold)

• 64-byte TX FIFO for SoC, 8-byte for SM.• Read request (receives read when acting as a slave)• Transmit abort (unable to completely transmit FIFO contents)• Receive done (when acting as slave-transmitter, master acknowledged last byte)• Activity (asserted whenever there is TWSI activity)• Stop (STOP condition occurred)• Start (START or RESTART condition occurred)• General Call (upon receiving a general call address)

19.2.10 SPI interface88DE3010 integrates two SPI interfaces, one in the SoC power domain, and the other in the SM power domain.

Each SPI interface has the following features:

Supports full-duplex master mode only.4 slave-select lines.Programmable baud rates using the BAUDR clock divider register with a source clock of 100 MHz in the SoC power domain, and 10-30 MHz in the SM power domain.Programmable clock phase and polarity.Programmable data frame size (# of bits) and length (# of bytes per transaction).Supports various transfer modes: transmit only, receive only, transmit & receive, and EEPROM read.Controllable via pBridge DMA engine.Operation status registers to indicate FIFO, and SPI FSM activity status.Maskable interrupt support:• Receive FIFO underflow, overflow, full (programmable threshold).

• 64-byte RX FIFO for SoC, 8-byte for SM.• Transmit FIFO overflow, empty (programmable threshold).

• 64-byte TX FIFO for SoC, 8-byte for SM.The SoC domain SPI interface also has an AHB to SPI bridge that provides direct memory-mapped access from CPU to an off-chip SPI Flash device. This is done via an SPI handler module. CPU just needs to issue an AHB read transaction from the SPI Flash address range, the SPI handler will then initiate all the necessary SPI controller setup transactions to read the external device, and return the data through the AHB bus. This feature allows the SoC CPUs on the 88DE3010 to directly boot from an external SPI Flash device. The SPI handler is used at the boot-up stage, functioning as a hardware driver. During normal operation, software access to the SPI controller is used.

19.2.11 GPIOPERIF supports 32 General Purpose I/O Ports. All of them can be programmed to accept external signals as interrupt sources.

19.2.12 PWM88DE3010 has 4 programmable Pulse-width-modulated ports.

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Peripheral Sub SystemFunctional blocks



19.3 Functional blocks19.3.1 DRMDMX engine

The DRM system is designed to support multiple DRM schemes. It provides:

A dedicated security system CPU, inaccessible to external interfaces, for managing authentication, key generation and content access functions.Protection for the distribution and consumption of multimedia content for IPTV/Blu-ray DVD players/recorders and HDTV.Hardware cryptography engines for high speed payload decryptionA single framework supporting multiple schemesOptical Disk DRM Schemes: AACS, DVD-CSS, CPPM-CPRMBroadcasting DRM Schemes: Multi-2, ATSCOn-line DRM Schemes: Microsoft Windows Media DRM

Refer to the Transport Stream processor and digital right management (DRMDMX) sub-system for further details about the DRM scheme support.

19.3.2 TimersPERIF has 8 32-bit-wide programmable timers with interrupt support.

19.3.3 Watch dogPERIF has 3 Watch dogs. They are 32-bit count down counters that can be used to generate interrupt or reset the system in the event of unpredictable software behavior. Each watch dog timer will send an interrupt to CPU when the first time out occurs. When the second time out occurs before CPU taking action on the first time out interrupt, watch dog timer will fire a chip reset request to Global unit.

19.3.4 Embedded Interrupt controller88DE3010 peripheral sub-system has 3 sub-system level programmable interrupt controllers, one for each of the CPUs and external PCIe master in 88DE3010. These PICs are only used to manage the interrupts from TWSI, SPI, Timer and Watch dog. The interrupt signals are sent to top level PIC before sending to their destination. For further details of top level PIC, refer to the PIC Chapter. Interrupts from other blocks will be handled by the upper level PIC directly.

19.3.5 pBridgeTo off load CPU from monitoring the data transfers for peripheral devices, Perif Bridge provide a light weight shared DMA for the low bandwidth HW devices inside perif (LBC, NFC, TWSI and SPI). Here is the feature list for the Perif Bridge.

DMA function for data transfer between DDR and devices.Can be used to configure all the registers and memories for devices Semaphore operation for the flow control and synchronization between DDR devices.

For details for pBridge, refer to the pBridge Chapter.

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20 pBridgeIn the 88DE3010 device peripheral subsystem, there are some slow devices which do not have the built-in DMA functionality, such as the NAND flash controller (NFC), local bus controller (LBC), TWSI, and SPI etc. It is inefficient for the SoC CPUs to access those devices through AHB bus when significant amount of data transfer is needed. The Peripheral DMA bridge (pBridge) is a flexible DMA engine to off load the CPU for data transfer between DRAM and these devices. The Figure 81 shows the interconnection between pBridge and other component inside the 88DE3010 device’s Peripheral subsystem.

Figure 81: Peripheral Subsystem

In the 88DE3010 Peripheral subsystem, high speed blocks such as USB controllers, Fast Ethernet controller, DRMDMX engine, SATA controllers, PCIe controller and SDIO controller all have built-in DMA engines. These bus masters are multiplexed with the pBridge bus master for direct access to DRAM through AXI bridge.

The AHB fabric allows CPU to access any register space in the peripheral subsystem. For the low speed devices such as NFC, LBC, TWSI, SPI etc., both the pBridge and CPU can access their register space. In this way, it’s flexible for software to utilize pBridge for the DMA operations for some of these devices while keep others under direct access from CPU.

AXI bridge

LBCNFC TWSI SPI

AHB bridge

To memory controller From CPU

pBridge

AHB/APB bus fabric

DRMDMX 2x SATA2x USB PCIe SDIO Fast

Ethernet

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pBridgepBridge Block Diagram



20.1 pBridge Block Diagram

Figure 82 illustrates all the major components involved in pBridge operation.

Figure 82: Major Components in pBridge operation

pBridge Descriptors: The DMA engine operates based on pBridge descriptors. The descriptors are data structures in DRAM to instruct pBridge for DMA setup, register access for target device initialization and data related operation. Each peripheral device controlled through the pBridge will have its own dedicated descriptor buffer. Refer to next section, pBridge Descriptor Format, for more detailed information for pBridge descriptors.

dHub: The dHub module within pBridge provides the DMA functionality for 7 concurrent channels: - one data read channel, one data write channel and 5 descriptor read channels supporting up to 5 active devices for concurrent operations. These 5 descriptor read channels are used for loading the pBridge descriptors from DRAM. While all the active devices will share the DATA read and write channels, each of them will require their own descriptor channel.

BCM: The BCM module parses pBridge descriptors. According to descriptors, it will generate all the necessary control or data transactions to all the involved modules.

The BCM module handles one descriptor a time. Each descriptor may specify a semaphore check condition. Those descriptors will not join the arbitration until the associated semaphore condition is met. The semaphore condition is normally used to indicate the data/buffer availability for the active devices.

For DMA read operation, BCM will read the data from DRAM via the dHub read data channel and generate 8/16/32-bit data peripheral register access. For DMA write operation, BCM will collect the data read from devices and write to DRAM through dHub write channel. To finish a DMA operation for a device, multiple descriptors from the same channel may need to be processed by BCM. In this case, BCM will lock the arbitration until the whole DMA operation for current device finishes.

Semaphore: The semaphore module is used for the handshake and synchronization between BCM module and the active devices. In semaphore module, each active device has a dedicated one semaphore bit. It can be updated (set to one) by the device and acquired (clear to zero if semaphore is one) by BCM. The device will update semaphore when it has enough data/buffer for DMA transfer. BCM will try to acquire semaphore when a SEMA descriptor is parsed. If a semaphore cannot be acquired successfully, the BCM will keep trying to acquire the same semaphore and will not load the next descriptor from the same channel.

pBridge Peripheral ControllersDRAM

Read Data Channel

BCM

Write Data Channel

Descriptor channel 0Descriptor channel 1Descriptor channel 2Descriptor channel 3Descriptor channel 4

AHB Master

Sem

apho

re

pBridge & Device Register access

Device DMA request &

Acknowlege A

XI B

us M

aste

rDescriptorBuffers

DescriptorBuffers

DescriptorBuffers

Data BufferData Buffer

Data Buffer

dHub

AXI

Brid

geOther Peripheral Masters

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In order to better utilize the shared DMA data channels, the BCM should only start to process descriptors when the active device is ready for the data transfer. This is achieved by synchronization through the semaphore. For example, when NFC and TWSI controller DMA transfer are concurrent, both of them are arbitrating for the DMA write channel, a SEMA descriptor (for semaphore acquiring) need to be inserted before the WCMD descriptor (for DMA write operation). The BCM will block DMA operations from arbitration until the semaphore condition is met.

20.2 pBridge descriptor formatTo enable the DMA transactions for slow devices through pBridge, CPU needs to preload the pBridge descriptors and DMA data to DRAM, and then enable pBridge as a master to operate the peripheral devices for register configuration and data read/write. The pBridge descriptor provides register configurations, DMA operations, and synchronization mechanisms between pBridge and active devices. The synchronization mechanism is achieved through semaphore operation for data/buffer availability. Table 151 lists all supported pBridge descriptor types.

Each pBridge descriptor is defined as 64-bit word. Bit [63:60] is the 4-bit header, which defines the descriptor type, and bit [59:0] includes all the information needed for the operation. The descriptors are written into the DRAM by CPU and read by pBridge from the DRAM.

20.2.1 CFGW

Table 151: pBridge Descriptor Type

pBridge descriptor Type Description

CFGW Single configuration register write. This is used to program registers in the device controllers.

RCMD Descriptor used to set up pBridge DMA channel to load a block of data from DRAM to dHub read data buffer. This descriptor must be followed by a RDAT descriptor.

RDAT Descriptor used to generate the bus write operation from dHub read data buffer to device using the data loaded by RCMD

WCMD Descriptor to set up pBridge DMA write channel to write a block of data to DRAM.

WDAT Descriptor used to generate bus read transaction from data buffer/register in the active device and send to DMA channel. This descriptor must be followed by a WCMD descriptor.

LDFN Descriptor used to set up a pBridge DMA channel to load descriptors, LDFN can be used to link scattered descriptor buffers in DRAM for different peripheral functions

SEMA Descriptor used to instruct pBridge BCM state machine to acquire/update semaphore.

NULL No operation

Table 152: CFGW

Msb Lsb

Header=0x0(CFGW) devAdr[27:0] dat[31:0]

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pBridgepBridge descriptor format



This descriptor defines a 28-bit device address and 32-bit data pair. BCM will parse this descriptor and generate an AHB transaction by writing 32-bit data to the target address. There is one base_addr register defined in the pBridge module, the target address is the summation of base_addr and devAddr[27:0].

20.2.2 RCMD and RDAT

The RCMD and RDAT together define a DMA data transfer from a DRAM buffer to a device. Descriptor RCMD defines the data transfer from DRAM to dHub, and RDAT defines the data transfer from dHub to device.

The ddrAdr and Size fields in RCMD descriptor specify the location and size of the DRAM data buffer. The ddrAdr must be 8-byte aligned and the unit of size is byte.

In the RDAT descriptor, the devAdr field specifies register address of data buffer/FIFO in the target device. The size field in RDAT descriptor specifies the number of bytes to be transferred. The target device register/bus size (8/16/32-bit) and endianess (little or big endian) are specified by the mode and endian fields. For mode description, refer to the Table 155. Table 156 and Table 157 illustrate the data access sequence when endian equals to 0 (little endian) and 1 (big endian).

In RDAT descriptor, cUpdID is reserved. Only the pUpdID needs to be programmed. The pUpdID is used to specify the semaphore producer update after the completion of the data copy from dHub local buffer to the target device. The associated semaphore will be updated only if the ID is a non-zero value.

Table 153: RCMD

Msb Lsb

Header=0x1(RCMD) RSVD[11:0] size[15:0] ddrAdr[31:0]

Table 154: RDAT

Msb Lsb

Header=0x2(RDAT) devAdr[27:0] pUpdID[4:0] cUpdID[4:0] endian mode[1:0] size[15:0]

Table 155: RDAT and WDAT Mode Definition

Mode Register/Bus Width of target Device

00 8-bit

01 16-bit

10 32-bit

11 Reserved

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Table 156: Device Data Access Sequence When endian = 0 (Little Endian)

Program Sequence

First Programmed

Last Programmed

8-bit Device B0 B1 B2 B3 B4 B5 B6 B7

16-bit Device Bit[15:8] = B1;Bit[7:0] = B0;

Bit[15:8] = B3;Bit[7:0] = B2;

Bit[15:8] = B5;Bit[7:0] = B4;

Bit[15:8] = B7;Bit[7:0] = B6;

32-bit Device Bit[31:24] = B3; Bit[23:16] = B2; Bit[15:8] = B1; Bit[7:0] = B0;

Bit[31:24] = B7; Bit[23:16] = B6;Bit[15:8] = B5; Bit[7:0] = B4;

Table 157: Device Data Access Sequence When endian = 1 (Big Endian)

Program Sequence

First Programmed

Last Programmed

8-bit Device B0 B1 B2 B3 B4 B5 B6 B7

16-bit Device Bit[15:8] = B0;Bit[7:0] = B1;

Bit[15:8] = B2;Bit[7:0] = B3;

Bit[15:8] = B4;Bit[7:0] = B5;

Bit[15:8] = B6;Bit[7:0] = B7;

32-bit Device Bit[31:24] = B0; Bit[23:16] = B1; Bit[15:8] = B2; Bit[7:0] = B3;

Bit[31:24] = B4; Bit[23:16] = B5; Bit[15:8] = B6; Bit[7:0] = B7;

NoteB0, B1, …, B7 are continuous bytes in DRAM data buffer with sequential increasing address.

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pBridgepBridge descriptor format



20.2.3 WCMD and WDAT

Similar to RCMD and RDAT, the WCMD and WDAT together define the DMA data transfer from device to DRAM. The WDAT descriptor defines data transfer from device to dHub, and WCMD descriptor defines the data transfer from dHub to DRAM.

The ddrAdr and Size fields in WCMD descriptor specify the location and size of the DRAM data buffer. The ddrAdr must be 8-byte aligned and the unit of size is byte.

In the WDAT descriptor, the size and devAdr fields specify the DMA transfer size and source device address. The bus size (8/16/32-bit) and endianess (little or big endian) are specified by the mode and endian fields. Refer to Table 155, Table 156, and Table 157 for the definitions. In WDAT descriptor, both pUpdID and cUpdID are reserved.

20.2.4 SEMA

The SEMA descriptor defines 4 semaphore ID fields, which are used for the 4 kinds of semaphore operations, producer update/check, and consumer update/acquire. For each field, if the semaphore ID is 0, no semaphore operation will be done for that field. The semaphore acquire is a blocking operation, which means before the semaphore is successfully acquired, the subsequent descriptor from the same channel will not be processed by the BCM. This descriptor is typically used for event synchronization between pBridge and target devices to share common DMA resources of the read/write data channel and AHB bus for devices register access.

20.2.5 LDFN

The LDFN descriptor can be used to link the scattered descriptor buffers inside DRAM. The ddrAdr and size define the descriptor buffer location and size inside the DRAM. When intr field is set to 1,

Table 158: WCMD

Msb lsb

Header=0x3(WCMD) RSVD[11:0] size[15:0] ddrAdr[31:0]

Table 159: WDAT

Msb lsb

Header=0x5(WDAT) devAdr[27:0] pUpdID[4:0] cUpdID[4:0] endian mode[1:0] size[15:0]

Table 160: SEMA

msb lsb

Header=0x6(SEMA) RSVD[37:0] cChkID[4:0] cUpdID[4:0] pChkID[4:0] pUpdID[4:0]

Table 161: LDFN

msb lsb

Header=0x1 (LDFN) RSVD[6:0] intr chID[3:0] size[15:0] ddrAdr[31:0]

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pBridge will generate an interrupt when the descriptor buffer loading is finished. The following diagram shows descriptor buffers scattered inside DRAM, and the last descriptor of “Des Buf0” is a LDFN descriptor which point to the “Des Buf1”, and same idea applied between “Des Buf1” and “Des Buf2”.

Figure 83: Using the LDFN to link the scattered descriptor buffers

20.2.6 NULL

The NULL descriptor means no operation, the BCM module will ignore this descriptor for execution.

DRAM

Des Buf 0 CFGW

…..

LDFN

Des Buf 1 SEMA

…..

LDFN

Des Buf 2 CFGW

…..

CFGW

Table 162: Null

msb lsb

Header=0xf(Null) RSVD[59:0]

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NAND Flash ControllerFeatures



21 NAND Flash Controller

21.1 Features Supports two chip Selects and 8-bit interface to the data-flash device Separate Ready (Ready/Busy) pins for each chip selectSupports stacking of 8-bit devices into a logical 16-bit deviceSupports 32/64/128/256 page block sizesSupports page sizes up to 8KBSupports two ECC algorithms:• Hamming ECC for 2-bit detection and 1-bit correction per page • BCH ECC to correct up to 16-bit errors per page (including spare, if enabled and parity bits

themselves) Supports up to 7-address cyclesProgrammable interface timing Interrupts can be enabled to indicate page and command completion, bad blocks, bit errors, flash-ready status and command, and data-write/read requests.Supports hardware-locking mechanism to blocks address ranges within the NAND device from being erased or programmed. ONFI 1.0 compliant

21.2 NAND Interface ConfigurationNAND Flash Controller (NFC) allows following combinations of chip select and Ready/Busy signals to allow different system configurations.

21.2.1 Stacked configurationFigure 84 shows two 8-bit NAND devices connected to separate chip selects with a single “ND_RnB” (Ready/Busy) signal. In this configuration both NAND devices can toggle the “ND_RnB” signal to show when the NAND device is busy and when it is ready. The busy performance is the worst case of the two devices and the logical page size doubles.

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Figure 84: Stacked configuration example using 2 Chip Selects and 1 Ready/Busy signal

Figure 85 shows two 8-bit NAND devices connected to separate chip selects with separate “ND_RnB” (Ready/Busy) signals. With a separate “ND_RnB” signal for each device, software has the option of having concurrent accesses on both NAND devices. NFC will overlap the command execution to improve the bandwidth of the system, if the currently executed command and the next command meet the following requirement:

Command1 is an erase or program command for device interfaced using a particular chip select and Command2 is a command for device interfaced using other chip select.

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NAND Flash ControllerNAND Interface Configuration



Figure 85: Stacked configuration example using 2 Chip Selects and 2 Ready/Busy signal

21.2.2 LBC/NAND Pad Shared configurationIn this configuration, another I/O device can be connected to the 88DE3010 NAND interface with dedicated “ND_RnB1” and “ND_nCS1”. The rest of the pads (control and data) are shared between the I/O device and NAND device. The pad sharing is achieved through an arbiter and it is transparent to software. The I/O device is independently controlled by 88DE3010 LBC module. Refer to the LBC Chapter for details.

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21.3 NAND Timing Diagrams NFC provides programmable NAND Interface Timing using register NDTR0CS0/1 to configure:

The setup and hold times of outputs driven by the NAND flash controller (ND_ALE, ND_CLE, ND_nCS1 and ND_nCS0) Pulse widths and cycle times of “ND_nRE” and “ND_nWE”.

All timing parameters in NDTR0CS0/1 are set in terms of NAND controller clock period. Refer to the 88DE3010 register manual for details.

21.3.1 NAND Flash Program Timing Data-flash program operation writes data to the Flash.Figure 86 illustrates the programming sequence for a flash device with a page size of 512 bytes, and a spare area of 16 bytes. The Flash device is addressed in four cycles. Refer to Table 163 for the detailed descriptions of the timing parameters. If the Auto-read Status bit (AUTO_RS) is set in the command, the NAND Flash Controller performs a status check (command 0x70) to determine whether the program operation was successful.

Figure 86: NAND Flash Program Timing Diagram

0x80 ADDR2 ADDR3 ADDR4 DIN0 DIN527 0x10

Tdh

TdhTdh

ND_nCSx

ND_nWE

ND_CLE

ND_ALE

DF_IO<x:0>

ND_RnB

Tds

Tds

TwlTwh

ADDR1

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NAND Flash ControllerNAND Timing Diagrams



21.3.2 NAND Flash Erase Timing Figure 87 illustrates the erase sequence for a Flash device. The block to be erased in the Flash device is addressed in three cycles. Refer to Table 163 for the detailed descriptions of the timing parameters. If the Auto-read Status bit (AUTO_RS) is set in the command, the Data Flash Controller performs a status check (Command 0x70) to determine whether the Erase operation was successful.

Figure 87: NAND Flash Erase Timing Diagram

21.3.3 NAND Flash Read Timing Figure 88 illustrates the Read sequence for a Small-block Flash device. The Flash device is addressed in four cycles. Refer to Table 163 for detailed descriptions of the timing parameters.

Figure 88: NAND Flash Read Timing Diagram

0x60 ADDR2 0xD0

Tdh

ND_nCSx

ND_nWE

ND_CLE

ND_ALE

DF_IO<x:0>

ND_RnB

Tds

TwlTwh

ADDR3ADDR1

0x00 ADDR1 ADDR2 ADDR3 DOUT0 DOUT1

TdwrTrl

Trh

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

ND_RnB

Tdh

Tds

TwlTwh

DF_IO<x:0> ADDR4 0x30

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21.3.4 NAND Flash Status Read Timing Figure 89 illustrates the Status-read sequence for a Flash device. Refer to Table 163 for detailed description of the timing parameters.

Figure 89: NAND Flash Status Read Timing Diagram

21.3.5 NAND Flash Read ID Timing Figure 90 illustrates the ID read sequence for a Flash device. Refer to Table 163 for detailed description of the timing parameters.

Figure 90: NAND Flash Read ID Timing Diagram

0x70 Status

Tdwsr

Tdh

ND_nCSx

ND_CLE

ND_nWE

ND_nRE

DF_IO<x:0>

TdsTwl

Trl

0x90 0x00 Byte1 Byte2 Byte3 Byte4

Tdar

TdhTds

TdhTds

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

DF_IO<x:0>

TrlTrh

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NAND Flash ControllerNAND Timing Diagrams



21.3.6 NAND Flash Reset Timing Figure 91 illustrates the reset sequence for a Flash device. Refer to Table 163 for detailed

description of the timing parameters.

Figure 91: NAND Flash Reset Timing Diagram

21.3.7 NAND Flash Timing ParametersTable 163 provides the values for the programmable timing parameters.

0XFF

TdhTds

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

DF_IO<x:0>

ND_RnB

Table 163: NAND Flash Timing Parameters

Symbol Description Min Typical Max Units

TDH1 Hold time from ND_nWE rising to

ND_CLE falling1 NDTR0CS0[tCH] + 1 8 NFC Clock

TDS1 Setup time of ND_CLE, ND_ALE,

ND_nCS to ND_nWE falling1 NDTR0CS0[tCS] + 1 8 NFC Clock

TWL1 ND_nWE low pulse width 3 NDTR0CS0[tWP] + 1 8 NFC Clock

TWH1 ND_nWE high pulse width 2 NDTR0CS0[tWH] + 1 8 NFC Clock

TRL1 ND_nRE low pulse width 2 NDTR0CS0[tRP] + 1 16 NFC Clock

TRH1 ND_nRE high pulse width 2 NDTR0CS0[tRH] + 1 8 NFC Clock

TDWR1 ND_nWE rising to ND_nRE falling

delay for Read3 (NDTR1CS0[tR] + 2)

+ (NDTR0CS0[tCH] + 1)

65536 NFC Clock

TDWSR1 ND_nWE rising to ND_nRE falling

delay for Status Read1 NDTR1CS0[tWHR] 32 NFC Clock

TDAR1 ND_ALE falling to ND_nRE falling

delay for ID read1 NDTR1CS0[tAR] 16 NFC Clock

1. NFCLK is 5 ns clock period.

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21.4 NFC Host Interface NFC is part of 88DE3010 peripheral sub-system. Figure 92 shows the block diagram of NFC. 88DE3010 SoC CPU can access NFC through AHB interface. A DMA interface is also provided for command and data transfer through the pBridge module. Refer to the pBridge chapter for more details.

Figure 92: NAND Flash Controller Block Diagram

21.4.1 NFC Host Features Provides 2176-byte data buffer Provides 16-byte command buffer Programmable option to enable spare area in a page Programmable ECC enable or disable optionProgrammable PIO and DMA mode select Programmable Page size and pages per Block Programmable option to do sequential multiple page reads with single host command Programmable option to stop the next host command on uncorrectable error Programmable option to generate Interrupt in the following events:• Flash device is ready • Chip select based page done interrupt• Chip select based host command done interrupt per command basis• Chip select based bad block detect interrupt• ECC uncorrectable bit error is detected • ECC correctable bit error is detected • Write Data Request interrupt • Read Data Request interrupt

BCHNANDFlash

Interface

Host Interface

FIFOControl

Data Buffer(2K+128 byte)

Sequencing Control and

Status

Command Buffer

(16 Bytes)

NAND InterfaceController

Command Semantic State

Machine

NAND FlashHost System Bus

DMA interface

Hamming ECC

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NAND Flash ControllerNFC Host Interface



• Write Command Request interrupt Provides Status register for indicating Block Error Count, NAND Flash ready CS0/1, page done, Command done, bad block detect, correctable/uncorrectable detected, write/read data request, write command requestProvides a register to measure the length of a read, program and erase timing to determine the overall health of a particular block and to predict the failure. Provide Auto Read Status option for automatic checking of the program/erase status by issuing a read status command. Provides option to interleave commands when 2 NAND devices are connected to increase the performance Allows option to issue non-standard status commands using register bits NDCB2[ST_CMD] Provides CPU direct control option to issue custom command and address cycles

21.4.2 Command Interface Host commands to the NFC are stored in the command buffer (16-bytes). This buffer can be programmed by 88DE3010 SoC CPU using register configuration bus or by using DMA mode through pBridge module.

The command-semantics state machine will read command from command buffer and generate corresponding NAND interface commands according to register settings.

For performance consideration, NFC will request a new command as soon as the current command is accepted by NAND device.

21.4.3 Data Interface The write/read data will be stored in the 2176-bytes data buffer. The 88DE3010 SoC CPU using register configuration bus or using DMA mode through pBridge module can access this buffer.

During the program operation, the ECC data will be computed by ECC module and written into the NAND device. During the read operation, ECC module will check/correct the incoming data.

21.4.4 PIO and DMA operating ModesThe NFC supports two operating modes: Programmed I/O (PIO) or DMA mode.

21.4.4.1 PIO operating ModeIn PIO operating mode, software is responsible for all command and data movement to and from NFC, as well as status checking. In this mode, software needs to poll NAND status (NDSR) register bits to know when NFC is able to accept a new command or ready for data transfer. Alternatively, instead of polling status register, the following interrupts can be enabled by clearing the appropriate masks bits in NAND control (NDCR) register:

Write-command request interruptWrite-data request interruptRead-data request interrupt

The following is the brief description of steps in program/read operation in PIO mode:

NFC registers should be programmed based on device timing and configurations.Start NAND controller by setting NDCR[ND_RUN] register bit.Software will receive a write-command request interrupt from NFC, it should respond by writing the command to the command buffer register (NDCBx).

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If the command is a write (single page or multi-page), software will further receive the write-data request interrupt. Software should respond by writing data to the data buffer register (NDDB). Multiple interrupts should be responded for multi-page operation.Similarly, for read operations, the read-data request interrupt will be received after NFC finished reading a page of data from the flash device, and software should read the data buffer with correct page size.After every write/read operation, software should read the NDSR register for ECC checking result and/or bad block status, and handle the error cases accordingly.

21.4.4.2 DMA operating ModeIn DMA operating mode, the NFC utilizes the Peripheral DMA bridge (pBridge) for command and data transfers. Refer to the pBridge chapter for details. NFC asserts command and data service requests based on command and data buffer status.

The following is the brief description of steps in program/read operation in DMA mode:

Software setup the pBridge, read/write DMA buffer, and a descriptor buffer in DRAM. The DMA buffer is for the NAND data to be transferred. The descriptor buffer includes sequence of register programming, NFC commands, and NFC data read/write.pBridge loads the NFC descriptors, programs the NFC registers for the device timing and configurations.pBridge starts NAND controller by setting NDCR[ND_RUN] register bit.pBridge will receive a command request from NFC, it will respond by writing the command to the command buffer register (NDCBx). If the command is a write (single page or multi-page), pBridge will further receive the data request per page. It will respond by writing data from DMA buffer to the NFC data buffer register (NDDB). Similarly, for read operations, the data request will be received after NFC finished reading a page of data from the flash device, and pBridge will write the data from this buffer to DMA buffer in DRAM.pBridge will generate interrupts based on descriptors setting for the DMA operation status.After every write/read operation, NFC will generate interrupt if detecting a bad block or uncorrectable ECC error. In this case, software needs to stop and flush the pBridge, and handle the error case accordingly.

21.4.5 Error Handling

21.4.5.1 Error Checking and Correction (ECC)Error-detection code/error-correction code (EDC/ECC) is used in the NFC to detect and correct errors occurring in the flash device due to bit flipping. The 88DE3010 NFC supports 2 ECC modes:

Hamming ECC mode: Corrects 1-bit errors and detects 2-bit errors in a page.BCH ECC mode: Corrects up to 16-bit errors across 2Kbyte page.

Software can be informed by interrupts if any ECC error has been detected.

21.4.5.2 Bad Block Management SupportThe NFC has an option for performing automatic bad block checking after each program/erase operation. If the status check returns an error, a bad-block-detect interrupt (if enabled) is sent out and Bad Block registers can be read to determine the address of the bad block.

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Local Bus Controller (LBC)Features



22 Local Bus Controller (LBC)Local Bus Controller (LBC) is part of Peripheral sub-system in the 88DE3010 device. LBC provides 8-bit asynchronous parallel interface to connect to external device. LBC shares data and control pads with NAND Flash Controller (NFC). The arbitration of the pads between LBC and NAND is done in hardware and transparent to software.

Software can access LBC through pBridge (Peripheral Bridge) module or through register configuration bus. LBC decodes the transactions address to determine whether the transaction is for accessing internal LBC registers or for accessing external device. The transactions for external device will be arbitrated with NFC for pad access. The following block diagram shows the interconnection among LBC and other modules in Peripheral sub-system in the 88DE3010 device.

Figure 93: Interconnection between LBC and other components

22.1 FeaturesLBC Supports the following features:

3 dedicated address bits to access external device’s registers.8-bit wide bi-directional data bus. 1 dedicated read/write control signal.1 acknowledge signal for external device to hold the transaction.Support 8 accessible registers through LBC directly mapped to internal AHB bus. The LBC waiting cycles will be directly reflected on AHB bus.Programmable polarity of acknowledge signal.Programmable data/address setup time and hold time regarding to control signals.Programmable width for control signals.

pBridge

Nand Flash Controller

Local Bus Controller

Arbitrator enable GrantReq

ExternalNandFlash

External Device

Slave

Slave

External 8-bit Async

interface

Chip SelectReady

Chip SelectReady/Busy

MUX

LBC Data/Control

NFC Data/Control

Internal AHB Bus

64-bit AXI Data Bus

32-bit Register Configuration Bus

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22.2 PAD arbitration between LBC and NFCThe LBC and the NFC share the 88DE3010 PADs for the data and control signals. The NAND Flash controller must also be configured properly before any LBC operations can be performed.

Table 164 illustrates the pin mapping of LBC signals to 88DE3010 PADS.

Arbitration logic inside the NFC takes care of data and control pads sharing between LBC and NFC. When LBC needs to access the pads, LBC issues a request to NFC and waits for the grant to start driving the pads. Once the access is done, request signal from LBC will go low.

Table 164: Mapping of LBC signals to 88DE3010 Pads

Internal LBC port 88DE3010 Pads I /O External device pin

Remarks

lbc_io [7:0] NAND_IO[7:0] Input/Output HD [7:0] Host data bus

lbc_wen NAND_WEN Output HRW Indicates the direction of data: Read (High)Write (Low)

lbc_cs_n[0] NAND_CS[1] Output HCS Chip select

lbc_addr[2] NAND_CLE Output HA[0] Register Address

lbc_addr[3] NAND_ALE Output HA[1] Register Address

lbc_addr[4] NAND_REN Output HA[2] Register Address

lbc_rdy NAND_RDY[1] Input HACK Data transfer Acknowledge

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Local Bus Controller (LBC)Programming Local Bus Controller Registers



22.3 Programming Local Bus Controller RegistersAt reset de-assertion, all LBC registers reset to their default values. They must be configured appropriately before any accesses can be performed. In order for LBC to function correctly, follow these steps to configure the LBC. For details of register definitions, refer to 88DE3010 register manual:

Configure the interface properties: • Configure the CSDFICFG0 [ADDMODE] register bit as non-muxed address mode. • Configure the CSDFICFG0 [RDSYNC] and CSDFICFG0 [WRSYNC] register bits as

asynchronous mode.• Configure CSDFICFG0 [RDY_SPEC] register bits to be asynchronous for both Read and

Write. Configure proper address: • Configure CSDFICFG0 [ADDRBASE] register bits as byte-address<0>. • Configure CSDFICFG0 [LOWADD] register bit to not enable, for Non-Muxed modeConfigure the proper timing for signals based on the external device timing. • Configure register MSC0 [WE_D_HO/WE_D_SU/WE_LEN/WE_GEN] bits for proper write

timing access (refer to the Figure 4)• Configure register MSC0 [OE_D_SU/OE_D_HO/OE_SU/OE_HO/OE_GEN] bits for proper

read access timing (refer to Figure 5).

22.4 External Device InterfaceFigure 94 shows an example of a typical external device interface.

Figure 94: An Example of External Device Interface

NoteCSDFICFG0 [ADDMODE] means ADDMODE bit field in CSDFICFG0 register.

ExternalDevice

HD [7:0]

HRW

HCS

HA[2:0]

HACK

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22.4.1 LBC Write ProtocolLBC write transaction has the following 5 states:

1. Write address-data setup state: In this state, operation is initiated by LBC by driving Chip Select (HCS) to low. In the mean time, the address (HA [2:0]) and data (HD [7:0]) are ready on the respective buses. LBC stays in this state for “WE_D_SU” LBC clock cycles (this indicates data setup before HRW latching the data) and after that enters the Write Ready Wait state. The “WE_D_SU” can be programmed through MSC0 Control register.

2. Write Ready Wait state: In this state, LBC will pull down the Write Enable (HRW) signal to indicate a write operation to external device. LBC waits for the external device to assert acknowledge (HACK). HACK can be programmed to be either active high or active low through CSDFICFG0 [RDY_SPEC].

3. Write Enable state: LBC stays in this state for “WE_LEN” LBC clock cycles (this indicates the length of the HRW latch). “WE_LEN” can be programmed through MSC0 Control register.

4. Write Data Hold state: In this state, LBC pulls up Write Enable (HRW) and holds the data for additional LBC clock cycles defined by “WE_HO” and “WE_GEN”. “WE_HO” and “WE_GEN” can be programmed through MSC0 Control register.

5. Write completion state: In this state LBC pulls up HCS and return HD to its hi-Z state. This completes the write transaction.

Figure 95: LBC Write Protocol

WE_D_SU WE_LEN WE_D_HO WE_GENMSC0 Control Register

Chip Select (HCS)

Write Enable (HRW)

HACK

HA[2:0] Addr[1:0]

Data [7:0]HD[7:0]

WE_SU

RDY Time unknown

WE_LEN

WE_HO

WE_GEN

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Local Bus Controller (LBC)External Device Interface



22.4.2 LBC Read Protocol LBC read transaction has the following 4 states:

1. Read address setup state: In this state, operation is initiated by LBC by driving Chip Select (HCS) to low and setting up the address on HA [2:0] bus. In the mean time, data bus (HD[7:0]) remains in tri-state. The Write Enable (HRW) signal is kept high for the whole read operation. LBC stays in this state for “OE_SU” LBC clock cycles and after that enters the Read Ready Wait state. The “OE_SU” can be programmed through MSC0 Control register.

2. Read Ready Wait state: In this state, LBC waits for the external device to assert acknowledge (HACK). LBC will latch data on HD [7:0] bus when it received the acknowledge signal. HACK can be programmed to be either active high or active low through CSDFICFG0 [RDY_SPEC]. External device should keep data valid till HCS is de-asserted.

3. Read data latch state: LBC stays in this state for “OE_D_SU”, “OE_D_H”, and “OE_HO” LBC clock cycles before pulling up HCS. “OE_D_SU”, “OE_D_H”, and “OE_HO” can be programmed through MSC0 Control register.

4. Read completion state: In this state LBC pulls up HCS. This completes the read transaction.

Figure 96: LBC Read Protocol

OE_SU OE_D_SU OE_D_HO OE_HOMSC0 Control Register

Chip Select (HCS)

Write Enable (HRW)

HACK

HA[1:0] Addr[1:0]

Data [7:0]HD[7:0]

OE_SU

RDY Time unknown

OE_D_SU

OE_D_HO

OE_HO

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23 SD2.0/SDIO 2.0 Host ControllerThe SD2.0/SDIO2.0 Host Controller in 88DE3010 is a Host Controller with an AHB bus interface and DMA engine. It conforms to SD Host Controller Standard Specification Version 2.0.

The SD2.0/SDIO2.0 Host Controller handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), start/end bit, and checking for transaction format correctness.

The SD2.0/SDIO2.0 Host Controller provides Programmed IO method (through AHB bus) and DMA data transfer method (through DMA engine). In programmed IO method, the SoC CPU transfers data using the Buffer Data Port Register in the host controller. SoC CPU can enable DMA mode by programming Host controller registers. DMA allows the Host controller to read or write system memory without the intervention from the SoC CPU. The Host controller system address register points to the starting address of the data buffer in the system memory, and data is then accessed sequentially from that address.

23.1 Key featuresMeets SD Host Controller Standard Specification Version 2.0Meets SDIO card specification version 2.0Meets SD Memory Card Specification Draft version 2.0Meets SD Memory Card Security Specification version 1.01Supports both DMA and Non-DMA mode of operationCard Detection (Insertion / Removal)Password protection of CardsHost clock rate variable between 0 and 50 MHzSupports 1 bit and 4 bit SD modes and SPI modeAllows card to interrupt host in 1bit and 4 bit SD modes and SPI mode.Up to 100Mbits per second data rate using 4 parallel data lines (sd4 bit mode)Cyclic Redundancy Check CRC7 for command and CRC16 for data integrityDesigned to work with I/O cards, Read-only cards and Read/Write cardsSupports Read wait Control, Suspend/Resume operationSupports FIFO Overrun and Underrun condition by stopping SD clockImplements the standard interface to the card stack including standard command, response, and data transactionsProvides DMA operation for data transfers between system memory and data transfer FIFOs.

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SD2.0/SDIO 2.0 Host ControllerKey features



Figure 97 is a block diagram of the SD2.0/SDIO2.0 controller

Figure 97: SD2.0/SDIO2.0 Controller

The SD2.0/SDIO2.0 controller interfaces the SoC CPU through the AHB bus. The SD2.0/SDIO2.0 controller contains an AHB interface block, which provides system access to the internal registers and data FIFOs of the controller. Two 2 KByte data FIFOs provide data buffering for both transmit and receive data. The data FIFOs can also be accessible by DMA engine. Synchronization is provided within the controller to interface logic signals between the AHB and SDIO clock domains. The SD2.0/SDIO2.0 controller has an internal clock control unit which is responsible for generating the SDIO clock based on frequency divider settings within the controller. The internal bus monitor is responsible for monitoring the SD2.0/SDIO2.0 bus for timeout conditions and protocol violations. The controller also contains all of the logic necessary to generate the SD and SDIO protocols.

The SD2.0/SDIO2.0 controller can operate in DMA mode or non-DMA (PIO) mode. The controller consists of command and control registers and data FIFOs. The software has access to these registers and FIFOs, and generates commands, interprets responses, and controls subsequent actions. Either the software or the internal DMA can be used to transfer data from system memory to the data FIFOs or from the data FIFOs to system memory.

Figure 98 shows a block diagram of the interaction of a typical system that is using the SD/SDIO communications protocol.

Figure 98: SD2.0/SDIO2.0 Block Diagram of Interactions of a Typical System

The SD/SDIO bus connects the card/storage device to the SD2.0/SDIO2.0 controller. Software or the controller can turn the SDIO clock on or off. The card and the controller communicate serially

AHB Interface

SD Registers

DMA EngineData FIFO2 x 2KB

Read/Write

Synchronizers

Bus Monitor

Clock Control

Command Control Unit

Data Control Unit

SD Protocol Unit

SD/SDIOStorage Device

AHB Bus

AXI Bus

DMA interface

SD2.0/SDIO2.0 controller

SD2.0/SDIO2.0 Device

Register programming interface

CLK

CMD

DAT

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through the command and data lines and implement a message-based protocol. The messages consist of the following tokens:

Command: A command is a six-byte token that starts an operation. The command set includes card initialization, card register reads and writes, and data transfers. The SD2.0/SDIO2.0 controller sends the command serially on the CMD pin. Response: A response is a token that is an answer to a command token. Each command has either a specific response type or no response type. The format for a response varies according to the command sent and the card mode.Data: Data may be transmitted in serial or 4-bit wide fashion, depending on the negotiated bus width for data tokens between the host and card or storage device. Data is transferred between the SD2.0/SDIO2.0 controller and the card or storage device in eight-bit blocks and at rates up to 50 MHz. The format for the data depends on the card mode.

For SD2.0/SDIO2.0, all operations contain a command and most commands have an associated response. Read and write commands also have an associated data transfer. Command and response are sent and received on the bidirectional CMD pin and data is sent and received on the bidirectional DATx pin(s). Refer to the SD Memory Card Specification Version 2.0 and the SDIO Card Specification Version 2.0 for timing diagrams commands and responses, with and without data transfer.

All protocols are serial command interfaces and either serial or parallel data interfaces to the cards or storage devices as shown in table below. The SD/SDIO protocol supports block and multiple-block data transfers. The SD/SDIO protocol does not support stream-data transfers. The following table shows the supported protocol types.

Table 165: Supported Protocol Types

DATA TRANSFER TYPES SD and SDIO PROTOCOL

Single block Supported

Multiple block - open-ended Supported

Multiple block - predefined Supported

Stream Not supported

RW_IO Direct, CMD52 Supported for SDIO only

RW_IO Extended, CMD53 Supported for SDIO only

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APB Components of Peripheral InterfaceGPIO



24 APB Components of Peripheral Interface

24.1 GPIO24.1.1 GPIO as I/O pins

In I/O mode, the 88DE3010 can control the output data and direction of I/O pads. There 32 GPIO’s in SoC power domain and 16 GPIOs in SM power domain. Some of the GPIO pins have dedicated I/O PADs, rest of them are pin shared with other interfaces. Refer to the 88DE3010 Data sheet part 1 for more pin sharing information. The output and input GPIO status can be accessed directly through memory mapped registers. Each of the GPIO pins can be controlled independently as described further in this chapter.

Figure 99: 88DE3010 GPIO Block Diagram

Figure 99 illustrates 1 of 32 GPIO pins. For each of the GPIO pin (N from 0 to 31) are mapped to registers as following:

GPIO0-7 maps to apb_gpio_0 in the register manual;GPIO8-15 maps to apb_gpio_1; GPIO16-23 maps to apb_gpio_2;GPIO24-31 maps to apb_gpio_3;

D Q

D Q

gpio_swporta_ddrN

gpio_ext_portaNMetastability

Registers D Q

Gpio_swport0_drNGPIO I/O PAD

GPIO_P0_SYNC_EXT_DATA

N=0...31 for all 32 bit GPIOs

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24.1.1.1 Controlling the GPIOThe data and direction control for the signal are sourced from the data register (gpio_swporta_dr) and direction control register.

Under software control, the direction of the external I/O pad is controlled by a write to the data direction register (gpio_swporta_ddr) to control the direction of the GPIO pad.

The data written to the data register (gpio_swporta_dr) drives the output buffer of the I/O pad.

External data are input on the external data signal, gpio_ext_porta. Reading the external signal register (gpio_ext_porta) shows the value on the signal, regardless of the direction. This register is read-only.

24.1.1.2 Reading External Signals The GPIO PAD data on the gpio_ext_porta external signal can always be read through the memory-mapped register, gpio_ext_porta.

A read to the gpio_ext_porta register yields a value equal to that which is on the gpio_ext_porta signal, regardless of direction.

24.1.2 GPIO as Interrupt88DE3010 GPIO can be programmed to accept external signals as interrupt sources on any of the bits of the signal. The type of interrupt is programmable with one of the following settings:

Active-high and level Active-low and level Rising edge Falling edge

The interrupts can be masked by programming the gpio_intmask register. The interrupt status can be read before masking (called raw status) and after masking.

The interrupts are also combined into a single interrupt output signal, which has the same polarity as the individual interrupts. In order to mask the combined interrupts, all individual interrupts have to be masked. The single combined interrupt does not have its own mask bit.

Whenever GPIO is configured for interrupts, the data direction must be set to Input for interrupts to be latched. If the data direction register is reprogrammed to Output, then any pending interrupts are not lost. However, no new interrupts are generated.

Figure 100 illustrates how the interrupts are generated and how the data flows. The signal names in the diagram correspond to either I/O signals or memory-mapped registers.

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APB Components of Peripheral InterfaceUART



Figure 100:GPIO Interrupt Block Diagram

The gpio_status register must be read in the interrupt service routine (ISR) to find the source of the interrupt.

For edge-detected interrupts, the ISR can clear the interrupt by writing a 1 to the gpio_porta_eoi register for the corresponding bit to disable the interrupt. This write also clears the interrupt status and raw status registers. Writing to the gpio_porta_eoi register has no effect on level-sensitive interrupts. If level-sensitive interrupts cause the processor to interrupt, then the ISR can poll the gpio_rawint status register until the interrupt source disappears, or it can write to the gpio_intmask register to mask the interrupt before exiting the ISR. If the ISR exits without masking or disabling the interrupt prior to exiting, then the level-sensitive interrupt repeatedly requests an interrupt until the interrupt is cleared at the source.

If the interrupt service routine reads the gpio_intr_status register to find multiple pending interrupt requests, then it is up to the processor to prioritize these pending interrupt requests. There are no restrictions on the number of edge-detected interrupts that can be cleared simultaneously by writing multiple 1’s to the gpio_porta_eoi register.

Interrupt signals are internally synchronized to a system clock. Synchronization must occur for edge-detect signals. Edge-detected interrupts to the processor are always synchronous to the system bus clock. With level-sensitive interrupts, synchronization is optional and under software control.

24.2 UARTThe 88DE3010 supports three Universal Asynchronous Receiver/Transmitter (UART) controllers. They are used for data input/output operations for peripheral devices connected through a standard UART interface.

The first UART port (UART0) have flow control, the second UART(UART1) does not have flow control, and the third UART port (UART2) is pin shared with the flow control signals of UART0.

All of the UART ports in 88DE3010 are in system manager power domain, e.g. they are in always-on power domain. Both the SM CPU and SoC CPUs can access these UART ports. The assignment of the three UART ports to CPU’s are determined solely by software. The interrupts generated by the UART ports will be routed to all the CPUs.

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24.3 Two-Wire Serial interface (TWSI)24.3.1 Overview

The TWSI bus is a two-wire serial interface. The TWSI module can operate in both standard mode (with data rates up to 100 Kbps), and fast mode (with data rates up to 400 Kbps). The TWSI can communicate with devices only of these modes as long as they are attached to the bus. The TWSI serial clock determines the transfer rate. The TWSI interface protocol is setup with a master and slave. The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible for either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the device that is receiving data, which can be either the master or the slave. The protocol also allows multiple masters to reside on the TWSI bus, which requires the masters to arbitrate for ownership.

The slaves each have a unique address that is determined by the system designer. When the master wants to communicate with a slave, the master transmits a start condition that is then followed by the slave’s address and a control bit (R/W) to determine if the master wants to transmit data or receive data from the slave. The slave then sends an acknowledge (ACK) pulse after the address and the R/W bit is received to notify the master that the slave has received the request. If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver receives a byte of data. This transaction continues until the master terminates the transmission with a stop condition. If the master is reading from a slave, the slave transmits a byte of data to the master, and the master then acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates the transmission by not acknowledging the transaction after the last byte is received, and then the master issues a stop condition or addresses another slave after issuing a restart condition. This is illustrated in Figure 101.

Figure 101:TWSI Start and Stop Condition

The TWSI is a synchronous serial interface. The data signal (SDA) is a bidirectional signal and changes only while the serial clock signal (SCL) is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain or open-collector to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400 pF. Data is transmitted in byte packages.

24.3.2 TWSI Protocols The TWSI has the following protocols:

START and STOP Condition ProtocolAddressing Slave ProtocolTransmitting and Receiving Protocol START BYTE Transfer Protocol

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APB Components of Peripheral InterfaceTwo-Wire Serial interface (TWSI)



24.3.2.1 START and STOP Condition Protocol When the bus is IDLE both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When the master wants to start a transmission on the bus, the master issues a START condition. This is defined to be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate the transmission, the master issues a STOP condition. This is defined to be a low-to-high transition of the SDA line while SCL is 1. Figure 102 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA line must be stable when SCL is 1.

Figure 102:Start and Stop Condition

24.3.2.2 Addressing Slave Protocol There are two address formats: the 7-bit address format and the 10-bit address format. During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the LSB bit (bit 0) is the R/W bit as shown in Figure 103. When Bit 8 is set to 0, the master writes to the slave. When Bit 8 (R/W) is set to 1, the master reads from the slave. Data is transmitted most significant bit (MSB) first. During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte contains the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (Bit 8) is the R/W bit. The second byte transferred sets bits 7:0 of the slave address. Figure 104 shows the 10-bit address format, and Table 166 defines the special purpose and reserved first byte addresses.

Figure 103:7-bit Address Format

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Figure 104:10-bit Address Format

24.3.2.3 Transmitting and Receiving Protocol All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the master sends the address and R/W bit or the master transmits a byte of data to the slave, the slave-receiver must respond with the acknowledge signal. When a slave-receiver does not respond with an acknowledge pulse, the master aborts the transfer by issuing a STOP condition. The slave shall leave the SDA line high so the master can abort the transfer. If the master-transmitter is transmitting data as shown in Figure 105, then the slave-receiver responds to the master-transmitter with an acknowledge pulse after every byte of data is received.

Figure 105:Master-Transmitter Protocol

Table 166: TWSI Definition of Bits in the First ByteSlave Address R/W Bit Description

0000 000 0 General Call Address. The TWSI module places the data in the receive buffer and issues a general call interrupt.

0000 000 1 START byte. Refer to the “Section 24.3.2.4, START BYTE Transfer Protocol, on page 311 for more information.

0000 001 X CBUS address. The TWSI module ignores these accesses.

0000 010 X Reserved.

0000 011 X Reserved.

0000 1XX X High-speed master code (refer to Section 24.3.3.1, Master Arbitration, on page 312 for more information).

1111 1XX X Reserved.

1111 0XX X 10-bit slave addressing.

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APB Components of Peripheral InterfaceTwo-Wire Serial interface (TWSI)



If the master is receiving data as shown in Figure 106, then the master responds to the slave-transmitter with an acknowledge pulse after a byte of data has been received, except for the last byte. This is the way the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No Acknowledge so that the master can issue a STOP condition.

Figure 106:Master-Receiver Protocol

When a master does not want to relinquish the bus with a STOP condition, the master can issue a repeated start condition. This is identical to a START condition except it occurs after the ACK pulse. The master can then communicate with the same slave or a different slave.

24.3.2.4 START BYTE Transfer Protocol The START BYTE transfer protocol is set up for systems that do not have an on board dedicated TWSI hardware module. When the TWSI is addressed as a slave, it always samples the TWSI bus at the highest speed supported so that it never requires a START BYTE transfer. However, when the TWSI is a master, it supports the generation of START BYTE transfers at the beginning of every transfer in case a slave device requires it. The START BYTE protocol consists of seven zeros being transmitted followed by a 1, as illustrated in Figure 107. This allows the processor that is polling the bus to under-sample the address phase until 0 is detected. Once the micro-controller detects a 0, it switches from the under sampling rate to the correct rate of the master. The START BYTE procedure is as follows:

1. Master generates a START condition. 2. Master transmits the START byte (0000 0001)3. Master transmits the ACK clock pulse4. No slave sets the ACK signal to 05. Master generates a repeated START (Sr) condition

Figure 107:Start Byte Transfer

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A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the Sr (restart condition) is generated.

24.3.3 Multiple Master Arbitration and Clock Synchronization The TWSI bus protocol allows multiple masters to reside on the same bus. When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize the SCL clock. This section explains the following topics:

Master ArbitrationClock Synchronization

24.3.3.1 Master ArbitrationArbitration takes place on the SDA line, while the SCL line is 1. The master, which transmits a 1 while the other master transmits 0, loses arbitration and turns off its data output stage. The master that lost arbitration can continue to generate clocks until the end of the byte transfer. If both masters are addressing the same slave device, the arbitration could go into the data phase.

For high-speed mode, the arbitration cannot go into the data phase because each master is programmed with a different high-speed master code. Because the codes are unique, only one master can win arbitration, which occurs by the end of the transmission of the high-speed master code.

24.3.3.2 Clock Synchronization All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL clock. Clock synchronization is performed using the wired-AND connection to the SCL signal. When the master transitions the SCL clock to 0, the master starts counting the low time of the SCL clock and transition the SCL clock signal to 1 at the beginning of the next clock period. However, if another master is holding the SCL line to 0, then the master goes into a HIGH wait state until the SCL clock line transitions to 1. All masters then count off their high time, and the master with the shortest high time transitions the SCL line to 0. The masters then counts out their low time and the one with the longest low time forces the other master into a HIGH wait state. Therefore, a synchronized SCL clock is generated. Optionally, slaves may hold the SCL line low to slow down the timing on the TWSI bus.

24.3.4 Operation Model The TWSI interface operates under the following model:

1. Disable the interface by writing 0 to the IC_ENABLE register.2. Program speed (standard or fast), addressing (7 or 10-bit) and master/slave modes by writing

to the IC_CON register.3. If acting as a master, program the target address into IC_TAR. If acting as a slave, program the

slave address into IC_SAR.4. Program the SCL high and low duty cycles by using the IC_SS_SCL_HCNT and

IC_SS_SCL_LCNT registers for standard-speed mode, and IC_FS_SCL_HCNT and IC_FS_SCL_LCNT for fast-speed mode.

5. Program all required interrupt masks by using the IC_INTR_MASK register.6. Enable the interface by writing 1 to the IC_ENABLE register.7. To transmit onto the TWSI bus, write to the IC_DATA_CMD register.

Bit[7:0]= DataBit[8]= Command (0 = write, 1 = read)

8. To read data received on the TWSI bus, read from the IC_DATA_CMD register.Bit[7:0]= Data

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APB Components of Peripheral InterfaceLow Speed Peripheral Interrupt Controller (ICTL)



24.4 Low Speed Peripheral Interrupt Controller (ICTL)This chapter describes the functional operation of the 88DE3010 low speed device interrupt control-ler referred to as ICTL. The ICTL is used to congregate interrupts from low speed peripheral devices into one single interrupt source to SoC Programmable Interrupt Controller (PIC). There are 3 sepa-rate ICTLs for low speed peripheral devices for the SM power domain. They are connected to PIC input 13, 15, 16. The SoC ICTL is connected to PIC input 3. Refer to the “Programmable Interrupt Controller” chapter of this document for ICTL to PIC source assignments for SM.

The features and block diagram of these ICTL are identical and share the descriptions in this section. The actual connection of the ICTL interrupt sources are different for SoC and SM, refer to Section 3.2.4, System Manager Hardware Devices, on page 40 for ICTL source assignment, and this section for SoC low speed devices interrupt source assignments.

24.4.1 Overview The ICTL component is a configurable, interrupt controller. It supports from multiple interrupt (IRQ) sources that are processed to produce a single IRQ interrupt to the processor. All interrupt processing is combinational so that interrupts are propagated appropriately. This means that reading any of the interrupt status registers (raw, status, or final_status) is simply returning the status of the combinational logic, since there are no flip-flops associated with these registers. It is the user’s responsibility to make sure that the interrupts stay asserted until they are serviced.

IRQ interrupts support software interrupts. They have configurable input and output polarity.

24.4.2 IRQ Interrupt Processing The ICTL in 88DE3010 SoC power domain supports 29 IRQ interrupt sources. The ICTL processes these interrupt sources to produce a single IRQ interrupt to the SoC CPUs and PCIe Host when enabled. The processing of the interrupt sources is shown in Figure 108 and described in the following sections.

Figure 108:Normal Interrupt Generation – Interrupt 1 Example

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24.4.3 IRQ Interrupt Polarity The input polarity of each IRQinterrupt source is configured individually to support the polarity of the device interrupt connected to it. The output polarity of the interrupt signal is active low.

All interrupt status registers are always active-high, regardless of the polarity configured for the interrupt sources and outputs.

24.4.4 IRQ Software-Programmable Interrupts The ICTL supports forcing interrupts from software. To force an interrupt to be active, write to the corresponding bit in the irq_intforce registers (irq_intforce_l or irq_intforce_h). The polarity of each bit in these registers is the same as the polarity of the corresponding interrupt source signal.

Regardless of the polarity configured, the reset state of each bit in the irq_intforce registers is always inactive.

24.4.5 IRQ Enable and Masking To enable each interrupt source independently, write a 1 to the corresponding bit of the irq_inten registers (irq_inten_l or irq_inten_h).

To independently mask each interrupt source, write a 1 to the corresponding bit of the interrupt mask register (irq_maskstatus_l/irq_maskstatus_h). The reset value for each mask bit is 0 (unmasked).

24.4.6 IRQ Interrupt Status Registers The ICTL includes up to four status registers used for querying the current status of any interrupt at various stages of the processing. Refer to Figure 108 for an illustration of the register values. All of the following status registers have the same polarity; a 1 indicates that an interrupt is active, a 0 indicates it is inactive.

irq_rawstatus (irq_rawstatus_l/irq_rawstatus_h) – Contains the state of the interrupt sources after being adjusted for input polarity. Each bit of this register is set to 1 if the corresponding interrupt source bit is active, and is set to 0 if it is inactive. irq_status (irq_status_l/irq_status_h) – Contains the state of all interrupts after the enabling stage; that is, an active-high bit indicates that a particular interrupt source is active and enabled. irq_maskstatus (irq_maskstatus_l/irq_maskstatus_h) – Contains the state of all interrupts after the masking stage; that is, an active-high bit indicates that a particular interrupt source is active, enabled, and not masked. irq_finalstatus (irq_finalstatus_l/irq_finalstatus_h) – this register contains the same value as the irq_maskstatus register (the final stage of processing).

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APB Components of Peripheral InterfaceLow Speed Peripheral Interrupt Controller (ICTL)



24.4.7 SoC ICTL source assignmentTable 167 illustrates the ICTL interrupt source mapping for SoC power domain.

Table 167: ICTL interrupt source mapping

IRQ Source

0 GPIO instance (GPIO 0-7)

1 GPIO instance 1 (GPIO 8-15)



4 SSI instance 0

5 WDT instance 0

6 WDT instance 1

7 WDT instance 2

8 Timer (sub timer 0)








16 TWSI instance 0

17 TWSI instance 1 (GEN_CALL_INTR)

18 TWSI instance 1 (RX_UNDER_INTR)

19 TWSI instance 1 (RX_OVER_INTR)

20 TWSI instance 1 (RX_FULL_INTR)

21 TWSI instance 1 (TX_OVER_INTR)

22 TWSI instance 1 (TX_EMPTY_INTR)

23 TWSI instance 1 (RD_REQ_INTR)

24 TWSI instance 1 (TX_ABRT_INTR)

25 TWSI instance 1 (RX_DONE_INTR)

26 TWSI instance 1 (ACTIVITY_INTR)

27 TWSI instance 1 (STOP_DET_INTR)

28 TWSI instance 1 (START_DET_INTR)

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24.5 TimersThere's one timer in 88DE3010 SM power domain, and one time in 88DE3010 SoC power domain.Each of the timer has 8 separate programmable counters. All these counters can be programmed separately. Each counter counts down from a programmed value and generate an interrupt when the count reaches zero.

The counters in SoC is driven by a 100 MHz clock. The counters in SM is driven by a 10-30 MHz clock. The width of these counters is 32-bits.

The initial value for each counter – that is, the value from which it counts down – is loaded into the counter using the appropriate load count register (TimerNLoadCount). Two events can cause a counter to load the initial count from its TimerNLoadCount register:

The counter is enabled after being reset or disabled The counter counts down to 0

All interrupt status registers and end-of-interrupt registers of the counters can be accessed at any time. When a counter counts down to 0, it loads one of two values, depending on the timer operating mode:

User-defined count mode – Counter loads the current value of the TimerNLoadCount register. Use this mode if you want a fixed, timed interrupt. Designate this mode by writing a “1” to bit 1 of TimerNControlReg.Free-running mode – Counter loads the maximum value, which is dependent on the counter width; that is, the TimerNLoadCount register is comprised of 32 bits, all of which are loaded with 1s. The timer counter wrapping to its maximum value allows time to reprogram or disable the counter before another interrupt occurs.

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APB Components of Peripheral InterfaceWatchdog Timers (WDT)



24.6 Watchdog Timers (WDT)The 88DE3010 integrates 3 watch dog timers (WDT) in SoC power domain and 3 WDT in SM power domain. The WDT is used to prevent system lockup that may be caused by conflicting parts or programs in an SoC.

The WDT in SoC power domain is driven by the Register Configuration Clock at 100 MHz. The WDT in SM power domain is driven by the System Manager Clock at 10-30 MHz.

This chapter describes the functional operation of the WDT and contains the following sections:

CounterInterruptsSystem ResetsReset Pulse LengthTimeout Period Values

Figure 109:Example of a watchdog timer

The generated interrupt is passed to an interrupt controller. The generated reset is passed to the 88DE3010 global module, which in turn generates a reset for the components in the system. The WDT may be reset independently to the other components.

24.6.1 Counter The WDT counts from a preset (timeout) value in descending order to zero. When the counter reaches zero, depending on the output response mode selected, either a system reset or an interrupt occurs. When the counter reaches zero, it wraps to the selected timeout value and continues decrementing. The user can restart the counter to its initial value. This is programmed by writing to the restart register at any time. The process of restarting the watchdog counter is sometimes referred to as kicking the dog. As a safety feature to prevent accidental restarts, the value 0x76 must be written to the Current Counter Value Register (WDT_CRR).

24.6.2 Interrupts The WDT can be programmed to generate an interrupt (and then a system reset) when a timeout occurs. When a 1 is written to the response mode field (RMOD, bit 1) of the Watchdog Timer Control Register (WDT_CR), the WDT generates an interrupt when the first timeout occurs. If it is not cleared by the time a second timeout occurs, then it generates a system reset. If a restart occurs at the same time the watchdog counter reaches zero, an interrupt is not generated.

Figure 110 shows the timing diagram of the interrupt being generated and cleared. The interrupt is cleared by reading the Watchdog Timer Interrupt Clear register (WDT_EOI) in which no kick is required. The interrupt can also be cleared by a “kick” (watchdog counter restart).

Interrupt Controller

ICTL

Watchdog Timer

Global module

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Figure 110:Interrupt Generation

24.6.3 System Resets When a 0 is written to the output response mode field (RMOD, bit 1) of the Watchdog Timer Control Register (WDT_CR), the WDT generates a system reset when a timeout occurs.

Figure 111 shows the timing diagram of a counter restart and the generation of a system reset.

Figure 111:Counter Restart and System Reset

If a restart occurs at the same time the watchdog counter reaches zero, a system reset is not generated.

The length of the reset pulse is the number of clock cycles for which a system reset is asserted. When a system reset is generated, it remains asserted for the number of cycles specified by the reset pulse length or until the system is reset. A counter restart has no effect on the system reset once it has been asserted.

The Timeout period of WDT is not fully programmable. However, the software can chose to select from a set of supported timeout periods. Refer to register WDT_TORR register in the register manual for details.

SM CLK/Register Config CLK

WDT_COUNTER[31:0]

WDT_INTR

Clear_interrupt

3 2 1 0 255 120 119 118 117 116

SM CLK/Register Config CLK

WDT_COUNTER[31:0]

WDT_INTR

WDT_SYS_RST

10 9 8 255 254 2 1 0 255 254

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APB Components of Peripheral InterfaceSerial Peripheral Interface (SPI)



24.7 Serial Peripheral Interface (SPI)This chapter describes the functional operation of the SPI and contains the following sections:

SPI OverviewTransfer ModesOperation Modes

24.7.1 OverviewSPI is a four-wire, full-duplex serial protocol. There are four possible combinations for the serial clock phase and polarity. The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of the slave select signal or the first edge of the serial clock. The slave select line is held high when the SPI is idle or disabled.

The protocol allows for serial slaves to be selected or addressed using either hardware or software. When implemented in hardware, serial slaves are selected under the control of dedicated hardware select lines. The number of select lines generated from the serial master is equal to the number of serial slaves present on the bus. The serial-master device asserts the select line of the target serial slave before data transfer begins. This architecture is illustrated in Figure 112.

Figure 112:Hardware Slave Selection

24.7.2 Clock Ratios The frequency of the SPI serial input clock (SPI_CLK) is 100 MHz.

The maximum frequency of the bit-rate clock (SCLK_OUT) is one-half the frequency of SPI_CLK. This allows the shift control logic to capture data on one clock edge of SCLK_OUT and propagate data on the opposite edge; this is illustrated in Figure 113. The SCLK_OUT line toggles only when an active transfer is in progress. At all other times it is held in an inactive state, as defined by the serial protocol under which it operates.

The frequency of SCLK_OUT can be derived from the following equation:

Fsclkout FspiclkSCkDV-------------------=

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The SCKDV is a bit field in the programmable register BAUDR, holding any even value in the range 0 to 65,534. If SCKDV is 0, then SCLK_OUT is disabled.

Figure 113:Maximum SCLK_OUT/SPI_CLK Ratio

A summary of the frequency ratio restrictions between the bit-rate clock (SCLK_OUT/SCLK_IN) and the SPI peripheral clock (spi_clk) are described as:

Master: Fspi_clk >= 2 × (maximum Fsclk_out)

24.7.3 Transmit and Receive FIFO Buffers The FIFO buffers used by the SPI are internal D-type flip-flops that has a depth of 64. The width of both transmit and receive FIFO buffers is fixed at 16 bits due to the serial specifications, which state that a serial transfer (data frame) can be 4 to 16 bits in length. Data frames that are less than 16 bits in size must be right-justified when written into the transmit FIFO buffer. The shift control logic automatically right-justifies receive data in the receive FIFO buffer.

Each data entry in the FIFO buffers contains a single data frame. It is impossible to store multiple data frames in a single FIFO location; for example, you may not store two 8-bit data frames in a single FIFO location. If an 8-bit data frame is required, the upper 8-bits of the FIFO entry are ignored or unused when the serial shifter transmits the data.

The transmit FIFO is loaded by write commands to the SPI data register (DR). Data are popped (removed) from the transmit FIFO by the shift control logic into the transmit shift register. The transmit FIFO generates a FIFO empty interrupt request (SPI_TXE_INTR) when the number of entries in the FIFO is less than or equal to the FIFO threshold value. The threshold value, set through the programmable register TXFTLR, determines the level of FIFO entries at which an interrupt is generated. The threshold value allows you to provide early indication to the processor that the transmit FIFO is nearly empty. A transmit FIFO overflow interrupt (spi_txo_intr) is generated if you attempt to write data into an already full transmit FIFO. Data are popped from the receive FIFO by read commands to the SPI data register (DR). The receive FIFO is loaded from the receive shift register by the shift control logic. The receive FIFO generates a FIFO-full interrupt request (SPI_RXF_INTR) when the number of entries in the FIFO is greater than or equal to the FIFO threshold value plus 1. The threshold value, set through

SPI_CLK

Note

The transmit and receive FIFO buffers are cleared when the SPI is disabled (SPI_EN = 0) or when it is reset (PRESETN).

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programmable register RXFTLR, determines the level of FIFO entries at which an interrupt is generated.

The threshold value allows you to provide early indication to the processor that the receive FIFO is nearly full. A receive FIFO overrun interrupt (SPI_RXO_INTR) is generated when the receive shift logic attempts to load data into a completely full receive FIFO. However, this newly received data are lost. A receive FIFO underflow interrupt (SPI_RXU_INTR) is generated if you attempt to read from an empty receive FIFO. This alerts the processor that the read data are invalid.

24.7.4 SPI InterruptsThe SPI supports combined interrupt requests, which can be masked. The combined interrupt request is the ORed result of all other SPI interrupts after masking. SPI interrupts are active-high. The SPI interrupts are described as follows:

Transmit FIFO Empty Interrupt (SPI_TXE_INTR) – Set when the transmit FIFO is equal to or below its threshold value and requires service to prevent an under-run. The threshold value, set through a software-programmable register, determines the level of transmit FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data are written into the transmit FIFO buffer, bringing it over the threshold level. Transmit FIFO Overflow Interrupt (SPI_TXO_INTR) – Set when an access attempts to write into the transmit FIFO after it has been completely filled. When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt clear register (TXOICR). Receive FIFO Full Interrupt (SPI_RXF_INTR) – Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow. The threshold value, set through a software-programmable register, determines the level of receive FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data are read from the receive FIFO buffer, bringing it below the threshold level. Receive FIFO Overflow Interrupt (SPI_RXO_INTR) – Set when the receive logic attempts to place data into the receive FIFO after it has been completely filled. When set, newly received data are discarded. This interrupt remains set until you read the receive FIFO overflow interrupt clear register (RXOICR). Receive FIFO Underflow Interrupt (SPI_RXU_INTR) – Set when an access attempts to read from the receive FIFO when it is empty. When set, zeros are read back from the receive FIFO. This interrupt remains set until you read the receive FIFO underflow interrupt clear register (RXUICR). Multi-Master Contention Interrupt (SPI_MST_INTR). The interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring data. This informs the processor of possible contention on the serial bus. This interrupt remains set until you read the multi-master interrupt clear register (MSTICR). Combined Interrupt Request (SPI_INTR) – OR'ed result of all the above interrupt requests after masking. To mask this interrupt signal, you must mask all other SPI interrupt requests.

24.7.5 Transfer Modes The SPI operates in the following four modes when transferring data on the serial bus:

Transmit and ReceiveTransmit onlyReceive onlyEEPROM Read

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The transfer mode (TMOD) is set by writing to control register 0 (CTRLR0).

24.7.5.1 Transmit and Receive When TMOD = 2‘b00, both transmit and receive logic are valid. The data transfer occurs as normal according to the selected frame format (serial protocol). Transmit data are popped from the transmit FIFO and sent through the txd line to the target device, which replies with data on the rxd line. The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame.

24.7.5.2 Transmit Only When TMOD = 2‘b01, the receive data are invalid and should not be stored in the receive FIFO. The data transfer occurs as normal, according to the selected frame format (serial protocol). Transmit data are popped from the transmit FIFO and sent through the txd line to the target device, which replies with data on the RXD line. At the end of the data frame, the receive shift register does not load its newly received data into the receive FIFO. The data in the receive shift register is overwritten by the next transfer. You should mask interrupts originating from the receive logic when this mode is entered.

24.7.5.3 Receive Only When TMOD = 2‘b10, the transmit data are invalid. When configured as a slave, the transmit FIFO is never popped in Receive Only mode. Data from a previous transfer is retransmitted from the shift register. The data transfer occurs as normal according to the selected frame format (serial protocol). The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame. You should mask interrupts originating from the transmit logic when this mode is entered.

24.7.5.4 EEPROM Read When TMOD = 2‘b11, the transmit data is used to transmit an opcode and/or an address to the EEPROM device. Typically this takes three data frames (8-bit opcode followed by 8-bit upper address and 8-bit lower address). During the transmission of the opcode and address, no data is captured by the receive logic (as long as the SPI master is transmitting data on its txd line, data on the rxd line is ignored). The SPI master continues to transmit data until the transmit FIFO is empty. Therefore, you should ONLY have enough data frames in the transmit FIFO to supply the opcode and address to the EEPROM. If more data frames are in the transmit FIFO than are needed, then read data is lost. When the transmit FIFO becomes empty (all control information has been sent), data on the receive line (rxd) is valid and is stored in the receive FIFO. The serial transfer continues until the number of data frames received by the SPI master matches the value of the NDF field in the CTRLR1 register + 1.

24.7.6 Operation Modes Operation ModeSerial-Master Mode

Note

The transfer mode setting does not affect the duplex of the serial transfer. TMOD is ignored for Microwire transfers, which are controlled by the MWCR register.

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24.7.6.1 Operation Mode The SPI interface operates under the following model:

1. Disable the interface by writing 0 to the SPIENR register.2. Program the baud rate setting into the BAUDR register3. Set the transfer modes, clock phase and polarity, data frame size, and number of data frames

by writing to the CTRLR0 and CTRLR1 registers.4. Program all required interrupt masks by using the IMR register.5. Enable the interface by writing 1 to the SPIENR register.6. Enable the desired slave select line by writing to the SER register.7. To transmit onto the SPI bus, write to the DR register8. To read data received from the SPI bus, read from the DR register.

24.7.6.2 Serial-Master Mode This mode enables serial communication with serial-slave peripheral devices. The SPI initiates and controls all serial transfers. Figure 114 shows an example of the SPI configured as a serial master with all other devices on the serial bus configured as serial slaves.

Figure 114:SPI Master Device

The serial bit-rate clock, generated and controlled by the SPI, is driven out on the sclk_out line. When the SPI is disabled (SPI_EN = 0), no serial transfers can occur and sclk_out is held in “inactive” state, as defined by the serial protocol under which it operates.

txd

ssi_oe_n

rxd

sclk_out

ss_n[0]

ss_n[3]ss_n[2]

ss_n[1]

SPI Controller

DIDO

SCLKSSn

Slave Peripheral 0

DIDO

SCLKSSn

Slave Peripheral 1

DIDO

SCLKSSn

Slave Peripheral 2

DIDO

SCLKSSn

Slave Peripheral 3

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24.7.7 Data TransfersData transfers are started by the serial-master device. When the SPI is enabled (SPI_EN=1), at least one valid data entry is present in the transmit FIFO and a serial-slave device is selected. When actively transferring data, the busy flag (BUSY) in the status register (SR) is set. You must wait until the busy flag is cleared before attempting a new serial transfer.

24.7.8 Serial Peripheral Interface (SPI) ProtocolWith the SPI, the clock polarity (SCPOL) configuration parameter determines whether the inactive state of the serial clock is high or low. To transmit data, both SPI peripherals must have identical serial clock phase (SCPH) and clock polarity (SCPOL) values. The data frame can be 4 to 16 bits in length.

When the configuration parameter SCPH = 0, data transmission begins on the falling edge of the slave select signal. The first data bit is captured by the master and slave peripherals on the first edge of the serial clock; therefore, valid data must be present on the txd and rxd lines prior to the first serial clock edge. Figure 115 shows a timing diagram for a single SPI data transfer with SCPH = 0. The serial clock is shown for configuration parameters SCPOL = 0 and SCPOL = 1.

The following signals are illustrated in the timing diagrams in this section:

sclk_out serial clock from SPI master (master configuration only) sclk_in serial clock from SPI slave (slave configuration only) ss_0_n slave select signal from SPI master (master configuration only) ss_in_n slave select input to the SPI slave ss_oe_n output enable for the SPI master/slave txd transmit data line for the SPI master/slave rxd receive data line for the SPI master/slave

Figure 115:SPI Serial Format (SCPH = 0)

Note

The BUSY status is not set when the data are written into the transmit FIFO. This bit gets set only when the target slave has been selected and the transfer is underway. After writing data into the transmit FIFO, the shift logic does not begin the serial transfer until a positive edge of the sclk_out signal is present. The delay in waiting for this positive edge depends on the baud rate of the serial transfer. Before polling the BUSY status, you should first poll the TXE status (waiting for 1) or wait for BAUDR * spi_clk clock cycles.

spi_oe_n

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As data transmission starts on the falling edge of the slave select signal when SCPH = 0, continuous data transfers require the slave select signal to toggle before beginning the next data frame. This is illustrated in Figure 116.

Figure 116:SPI Serial Format Continuous Transfers (SCPH = 0)

When the configuration parameter SCPH = 1, both master and slave peripherals begin transmitting data on the first serial clock edge after the slave select line is activated. The first data bit is captured on the second (trailing) serial clock edge. Data are propagated by the master and slave peripherals on the leading edge of the serial clock. During continuous data frame transfers, the slave select line may be held active-low until the last bit of the last frame has been captured. Figure 117 shows the timing diagram for the SPI format when the configuration parameter SCPH = 1.

Figure 117:SPI Serial Format (SCPH = 1)

Continuous data frames are transferred in the same way as single frames, with the MSB of the next frame following directly after the LSB of the current frame. The slave select signal is held active for the duration of the transfer. Figure 118 shows the timing diagram for continuous SPI transfers when the configuration parameter SCPH = 1.

spi_oe_n

ss_o_n/ss_in_n

spi_oe_n

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Figure 118:SPI Serial Format Continuous Transfer (SCPH = 1)

There are four possible transfer modes on the SPI for performing SPI serial transactions; see “Transfer Modes” on page 321. For transmit and receive transfers (transfer mode field (9:8) of the Control Register 0 = 2'b00), data transmitted from the SPI to the external serial device is written into the transmit FIFO. Data received from the external serial device into the SPI is pushed into the receive FIFO.

spi_oe_n

sp_0_n/sp_in_n

sp1_oe_n

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SATA Host ControllerPHY features



25 SATA Host ControllerThe 88DE3010 device provides two independent SATA host interfaces that allow 88DE3010 to interface with hard drives and/or optical drives simultaneously.

25.1 PHY featuresIntegrated SATA2.0 PHYSupport both 1.5 Gbps and 3.0 Gbps data rateOutput signal level: 400 mv ~ 1600 mv peak-to-peak differentialTX driver pre-emphasis: 5% ~ 50% 10 steps, register programmableTermination: 50 ohm. Can be fine tuned by registers or auto calibration. Resolution: 5% each stepSpread Spectrum clock (TXCLK): up to 0.5% of clock frequency, register programmableReceiver can tolerate up to 2% frequency offset including Spread Spectrum Clock (SSC).Gen2 Serial ATA PHY (3 Gbps) with speed negotiation to Gen1

25.2 Host controller featuresSerial ATA 2.6 compliant• Supports Gen1i, Gen1m, Gen1x, Gen2i, Gen2m, and Gen2xSupported protocols over SATA ports• ATA and ATAPI commands• Native Command Queuing (NCQ)

• In-order data delivery• 32 outstanding commands per port

• Vendor Unique commands• Port Multiplier

• FIS-based Switching on NCQ, and legacy commandsSupports Port SelectorSupports Interrupt CoalescingSupport for eSATASupport for Hot PlugSupport AHCI

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26 Pulse Width Modulator (PWM)

26.1 OverviewThe Pulse Width Modulator (PWM) provides the capability to generate a high resolution periodic digital signal with programmable duty-cycles to control off-chip devices. It has 4 separate channels that are independently configurable.

Figure 119:PWM Block Diagram

pwmClk runs @ 100 MHz.

The PreScaler module pre-divides the input clock if a longer periodic signal is needed.

Read-only counter registers are provided via pwmCh01Ctr and pwmCh23Ctr registers for debug. The counters reside within the Modulator block, meaning that they are clocked by divClk, not the original input pwmClk.

Figure 120:Waveform

Duty cycle is programmed via the pwmCh*Duty registers.Terminal count is programmed via the pwmCh*TCnt registers.If duty cycle is 0, modOut will always be low.If duty cycle is >= terminal count, modOut will always be highmodOut can be inverted by setting the polarity inversion register, pwmCh*PolMaximum divider factor supports 4096Maximum terminal count supports 65535

PreScaler (divider) Modulator PolaritypwmClk pwmOutdivClk modOut

terminal count = 7

duty cycle = 3

divClk

modOut

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USB Host ControllerPHY Features



27 USB Host ControllerThe 88DE3010 provides two independent USB2.0 compliant interfaces that allow the 88DE3010 to interface with peripherals such as mass storage devices, wireless card, keyboard, and USB hubs. The 88DE3010’s USB interface can act as a host controller only.

27.1 PHY FeaturesSupports transfers up to 480 Mbps when operating in High Speed (HS) modeSYNC/EOP generation and checkingData and clock recovery from serial stream on the USBNRZ encoding/decoding with bit stuffing/unstuffingBit stuff error detectionsBit stuffing/unstuffing; bit stuff error detectionHolding registers to stage transmit and receive dataSupport suspend and resumeSupports USB 2.0 Test modesAbility to switch between FS and HS terminations/signalingSupport power off mode to completely shut off USB PHY power independently

27.2 Host Controller FeaturesTwo USB 2.0 compliant ports that operate in host-controller mode Integrated USB 2.0 PHYIntel™ EHCI host controller compliant. Supports direct connection to all peripheral device types – Low Speed (LS), Full Speed (FS), High Speed (HS)Each controller contains 512B TX buffer and 512B RX bufferSupport all types of data transfer modes: Bulk, Control, Interrupt, and Isochronous

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28 PCI ExpressThe 88DE3010 PCI Express interface is a single lane port, allowing 250 Mbyte/s of bandwidth in ingress and egress directions simultaneously, with a total bandwidth of 500 Mbyte/s. This interface has the following features:

PCI Express Base 1.0a compatibleCan be configured to be either RootComplex or EndPoint portEmbedded PCI Express PHY based on proven Marvell® SERDES technologyx1 link width2.5 GHz Gen1 signaling Lane polarity inversion supportMaximum payload size of 128 bytesSingle Virtual Channel (VC-0)Ingress and egress flow controlExtended Tag supportInterrupt emulation message supportPower management: L0s-Rx and SW L1 supportAdvanced Error Reporting (AER) capability supportSingle function device configuration header.Message Signaled Interrupts (MSI) capability supportPower Management (PM) capability support, as an EndPoint.Programmable address map.

28.1 Master Memory TransactionsMaster memory transactions are memory space read and write requests (MRd and MWr TLPs) that are generated and sent over the PCI Express link and the respective completion TLPs that are received in return. These are termed as up-stream transactions when 88DE3010 is an EndPoint and as down-stream transactions when 88DE3010 is a RootComplex.

The following features are supported as a master memory requester:

Single outstanding NP (Non-Posted) request. Either memory read, or Configuration requests.In EndPoint mode, up to two outstanding NP (Non-Posted) requestsMaximum memory read request of 128 bytesMaximum memory write request of 128 bytes64-bit addressing

28.2 Master I/O TransactionsMaster I/O transactions are I/O space read and write requests (IORd and IOWr TLPs) that are generated and sent over the PCI Express link and the respective completion TLPs that are received in return.

Master I/O transactions are not supported in 88DE3010.

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PCI ExpressMaster Configuration Transactions



28.3 Master Configuration TransactionsMaster Configuration Transactions are only for RootComplex mode. Master Configuration transactions are Configuration space read and write requests (CfgRd0, CfgWr0, CfgRd1 and CfgWr1 TLPs) that are generated and sent over the PCI Express link and the respective completion TLPs that are received in return.

The following features are supported as a master Configuration requester:

Single outstanding NP (Non-Posted) request. Either memory read, or Configuration requests.Maximum Configuration read request of 4 bytesMaximum Configuration write request of 4 bytesExtended register number support (4KB extended PCI Express configuration header space)

28.3.1 Configuration Requests GenerationConfiguration requests are generated by using Configuration Address Register and Configuration Data Register. The Configuration address register includes the Target Bus, Device, Function, Register and Extended Register Numbers information. The MSB of Configuration address register, bit [31], is the enable bit to enable the configuration requests. Read or write to the Configuration data register will trigger the read or write configuration request respectively.

There are two types of configuration requests:

Type1 request: generated if Target Bus Number Is different from the internal Bus Number.Type0 request: generated if Target Bus Number is same as the internal Bus Number, and the Target Device Number is different from the internal Device Number.

The transmitted Configuration TLP includes the Target Bus, Device, Function, and Register Numbers as written to the Configuration Address Register.

28.4 Target Memory TransactionsTarget Memory transactions are Memory space read and write requests (MRd, MWr TLPs) that are received over the PCI Express link, and the respective completion TLPs that are generated and transmitted in return. These are termed as up-stream transactions when 88DE3010 is an EndPoint and as down-stream transactions when 88DE3010 is RootComplex.

The following features are supported as a target Memory completer:

Reception of up to eight Memory read requests.Maximum received read request size of 4 KBytes.Maximum received write request of 128 BytesSupport PCI Express access to all of the device’s internal registers.64-bit addressingThree Memory BARs (64-bit), BAR0 is dedicated to internal register access.In EndPoint mode: Expansion ROM support

Note

• Both Configuration read requests and Configuration write requests are Non-Posted requests.

• In EndPoint mode, only memory request generation is allowed by the PCI Express Base 1.0a Specification. User must not initiate Configuration requests when working in EndPoint mode.

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28.4.1 Special CasesAccess attempts that fail address decoding (e.g., do no hit a memory BAR) are completed as Unsupported Requests. The transaction data will be ignored.MemWr accesses to reserved or not implemented registers are completed normally on the PCI Express port, and the data is discarded.MemRd accesses to reserved or not implemented registers are completed normally on the PCI Express port, and a CplD TLP with data value of 0 and SC (Successful Completion status) is returned.

28.5 Target I/O TransactionsTarget I/O transactions are I/O space read and write requests (IORd, IOWr TLPs) that are received over the PCI Express link, and the respective completion TLPs that are generated and transmitted in return.

Target I/O transactions are not supported and should not be generated by downstream device.

28.6 Target Configuration TransactionsTarget Configuration transaction is only supported in EndPoint mode, e.g. the downstream device should not generate target configuration transaction. Target Configuration transactions are Configuration space read and write requests (CfgRd0, CfgWr0, CfgRd1 and CfgWr1 TLPs) that are received over the PCI Express link, and the respective completion TLPs that are generated and transmitted in return.

In EndPoint mode, Target Type0 Configuration transactions are supported. The following features are supported as a target Configuration completer:

Reception of up to eight NP (Non-Posted) requests. Either memory read or Configuration requests.Maximum received Configuration read request size of 4 bytes.Maximum received Configuration write request of 4 bytes

28.6.1 Messages in RootComplex ModePCI Express defines a new message space. Messages are used to replace legacy PCI side-band signals such as interrupts, error signals, hot-plug signals etc. Messages are also used to enable new capabilities such as active power management, Slot Power Limit and others.

88DE3010 Supported Message Groups:

Interrupt signalingError Signaling

88DE3010 doesn't support the following Message Groups:

Power managementHot Plug signalingLocked transaction supportSlot power limit supportVendor specific messages

28.6.2 Messages in EndPoint Mode88DE3010 Supported EndPoint Message Groups:

Interrupt signaling

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PCI ExpressLocked Transactions



Power managementError signalingSlot power limit support

88DE3010 doesn't support the following message groups:

Hot plug signalingLocked transaction supportVendor specific messages

28.7 Locked TransactionsLocked transaction semantics are not supported. That includes MRdLk, CplLk and Unlock message.

28.8 Arbitration and OrderingThe arbitration scheme on both Tx and Rx directions follow the PCI Express ordering rules. On each direction there are separate queues for posted, non-posted and completion TLPs. A simple round-robin arbitration is performed on TLPs that can then be forwarded according the ordering rules.

28.9 Hot ResetHot Reset is an in-band reset indication that can be sent from the root-complex downstream and reset the PCI Express hierarchy. Use the following procedure to generate a hot reset:

1. Write to the <ConfMstr HotReset> bit[24] in the “PCI Express Control Register”.2. To check that Hot Reset has been completed, poll <DL_Down> bit[0] in the “PCI Express Status

Register”. When this bit is set, DL is down and Hot Reset has been completed.3. Clear the <conf_mstr_hot_reset> bit[24] in the PCI Express Control Register.

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28.10 Error Handling28.10.1 Physical Layer Errors

The following Receiver errors will be handled by PHY layer:

PHY overflowPHY underrunPHY 8b/10b decode errorPHY display error

28.10.2 Data Link Layer ErrorsThe following errors will be handled by Data Link layer:

LCRC error detected in received TLPSequence number error detected in received TLPCRC error detected in received DLLPReplay timer expiredREPLAY_NUM rolled-over. Four consecutive replays were transmittedReception of an acknowledge with out of range ackNac_Seq_Num

28.10.3 Transaction Layer ErrorsThe following errors will be handled by Transaction layer:

DLLP receive timer expirationReceived TLP with data payload size larger than the maximum payload sizeReceived TLP with undefined Type and Fmt fields valueReceived TLP with length different than expected according to the length, type, and TD (TLP Digest) fieldReceived request with address/length combination crossing the 4KB boundaryReceived power management set_slot_power, unlock, INTx, and error message with TC field not equal to 0 (TC0)Received a poisoned TLPReceived TLP has ECRC error detectedReceived unsupported TLP type (CfgWr1, CfgRd1, MrdLk)Received unsupported message codes.Failed address decoding on received TLPReceived CfgWr0 or CfgRd0 with function number not equal to 0Received poisoned write request to internal register spaceReceive Cpl TLP with UR completion statusReceived CplLk or CplD with UR completion statusOutstanding non posted request to PCI Express timeout has expiredReceived read requests to the internal address space, with the length field different than 1 DWORD.Received a Cpl with CA completion statusReceived unexpected completion TLP (Cpl or CplD). Completion does not correspond to one of the outstanding NP requestsReceived CplLk or CplDLk TLPs

An error interrupt is raised to CPU and then CPU can read the error log registers of the PCI Express Configuration space to know more details of the error.

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PCI ExpressAddress Translation



28.11 Address Translation28.11.1 Target Address Translation

The following explains the address translation for Target transactions. The following address translation will be performed before forwarding the transaction address to internal bus. The target address translation helps the external initiator device to map 88DE3010 at two non-contiguous address spaces using one BAR (for example, using one BAR, the external device can access 88DE3010's DRAM space and the configuration space which are at different locations of the 88DE3010's memory map).

Terminology:AddrFromPex: Address from PCIe CoreAddrToBus: Address over 88DE3010 Internal BusgPcieBarSize: One bit signal to distinguish if down-stream size is 256MB or 512MB (software programmable register)

The followings are base address of DRAM in 88DE3010 address map that can be addressable by Host.

tPcieBase0: The target PCIe Base0 address; (software programmable register)tPcieBase1: The target PCIe Base1 address; (software programmable register)tPcieBase2: The target PCIe Base2 address; (software programmable register)

Target Address Translation:aIn[28:0] = {AddrFromPex[28:3],3'b0}; // 29-bits are required to address 512 MB (max BAR size)

28.11.2 Initiator Address TranslationThe following explains the address translation for Initiator transactions. The following address translation will be performed before forwarding the transaction address from internal bus to the PCIe Core.

Terminology:AddrToPex: Address to PCIe Core; AddrFromBus: Address over Internal Bus;iPcieBase: The PCIe base address of initiator; (software programmable register)hPcieBase: hPcieBase Register holds the upper 48-bits (i.e., [63:16]) of Host PCIe base for 88DE3010. 48-bit base address allows to map 88DE3010 in 64-bit Host space (if Host can support 64-bit addressing). If Host can only support 32-bit addressing, or only need to map 88DE3010 in 32-bit address range, hPcieBase[47:16] should be programmed to 0. (software programmable register)

Table 168: Target Address Translation

256MB (gPcieBarSize = 1) 512MB (gPcieBarSize = 0)

AddrToBus = {tPcieBase0[15:0], 16'h0} + {4'h0, aIn[27:0]

aIn < 128MB aIn > 128MB

AddrToBus = {5'h0, aIn[26:0]} + {tPcieBase2[15:0], 1'h0}

AddrToBus = {3'h0, aIn[28:0]} + {tPcieBase1[15:0], 1'h0}

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Initiator Address Translation:aIn[31:0] = AddrFromBus[31:0];

ta1[15:0] = aIn[31:16] - iPcieBase[15:0];

ta2[15:0] = ta1[15:0] + hPcieBase[15:0];

AddrToPex[63:0] = {hPcieBase[47:16],ta2[15:0],aIn[15:0]};

28.12 Internal PHY AccessRegisters of the internal PCIe PHY can be accessed either through Marvell defined PCIe register space (BAR0) over PCIe link or through local CPU's configuration bus interface (address offset: 0x1B00). Please refer to 88DE3010 register document for details.

28.13 InterruptsThe 88DE3010 PCIe Controller supports 64-bit MSI (Message Signaling Interrupt) interrupt. One of the target interrupt output from the SoC PIC is connected to the 88DE3010 PCIe Controller when it is operating in EndPoint mode. The PCIe controller transmits an MSI packet, on to the PCIe link, in response to the interrupt from the SoC PIC.

While in RootComplex mode, the received interrupt from the PCIe hierarchy is sent to the SoC PIC, from there it can be routed to the 88DE3010 CPUs.

Other than these, all the PCIe error cases are combined as an interrupt and sent to the SoC PIC. The error interrupt is valid in both EndPoint and RootComplex modes.

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10/100MB ETHERNET ControllerFunctional Overview



29 10/100MB ETHERNET Controller

29.1 Functional Overview

The 10/100Mb Ethernet controller in 88DE3010 handles all functionality associated with moving packet data between local memory and an Ethernet port. It integrates the MAC function and a dual speed MII interface. It is fully compliant with the IEEE 802.3 and 802.3u standards.

The controller’s speed and duplex mode is auto-negotiated through the signaling with external PHY and does not require software intervention. The port also features 802.3x flow-control mode for full-duplex and backpressure mode for half-duplex.

Integrated address filtering logic provides support for up to 8K MAC addresses. The address table resides in DRAM with proprietary hash functions for address table management. The address table functionality supports Multicast as well as Unicast address entries.

The Ethernet controller integrates powerful DMA engines, which automatically manage data movement between buffer memory and the controller, and guarantee the wire-speed operation on the port. There are two DMA for 88DE3010 Ethernet controller - one dedicated for receive and the other for transmit.

29.2 FeaturesThe 10/100 Mb Ethernet port provides the following features:

IEEE 802.3 compliant MAC Layer function.IEEE 802.3u compliant MII interface.10/100Mb operation - half and full-duplex.Flow control features:• IEEE 802.3x flow-control for full-duplex operation mode.• Backpressure for half-duplex operation mode.Internal and external loopback modes.Transmit functions:• Short frame (less than 64 bytes) zero padding.• Long frames transmission (limited only by external memory size).• Programmable values for IPG and Blinder timers.• CRC generation (programmable per packet).• Automatic frame retransmission upon collision (with programmable retransmit limit).• Backoff algorithm execution.• Error report.Receive functions:• 1/2k or 8k address filtering capability.• Address filtering modes:• Perfect filtering.• Reverse filtering.• Promiscuous mode.

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• Broadcast reject mode.• IGMP packet trapping (Layer 3 analysis in hardware).• Automatic discard of errored frames, short (less than 64 bytes) or collided.• Reception of long frames (programmable up to 64 KB).• CRC checking.• Pass bad frames mode.• Error report.

29.3 Operational DescriptionIn 88DE3010, the Ethernet packet data is stored in memory buffers, with any single packet spanning multiple buffers if necessary. Upon completion of packet transmission or reception, a status report, which includes error indications, is written by the Ethernet controller to the first or last descriptor associated with this packet.

The buffers are allocated by the CPU and are managed through chained descriptor lists. Each descriptor points to a single memory buffer and contains all the relevant information relating to that buffer (i.e. buffer size, buffer pointer, etc.) and a pointer to the next descriptor. Data is read from buffer or written to the buffer according to information contained in the descriptor. Whenever a new buffer is needed (end of buffer or end of packet), a new descriptor is automatically fetched and the data movement operation is continued using the new buffer.

Figure 121 shows an example of memory arrangement for a single packet using three buffers.

Figure 121:Ethernet Descriptors and Buffers

Descriptor 1 031Commands/status

Buffer size/byte count

Buffer pointer

Next descriptor pointer

Descriptor2 031Commands/status


Buffer pointer


Descriptor3 031Commands/status


Buffer pointer


Packet1 – buffer 1



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10/100MB ETHERNET ControllerOperational Description



29.3.1 Transmit OperationIn order to initialize a transmit operation, the CPU must do the following:

1. Prepare a chained list of descriptors and packet buffers. The TxDMA supports two priority transmit queues - high and low. If the user wants to take advantage of this capability, a separate list of descriptors and buffers must be prepared for each of the priority queues.

2. Write the pointer to the first descriptor to the DMA’s current descriptor registers (TxCDP) associated with the priority queue to be started. If both priority queues are needed, initialize TxCDP for each queue.

3. Initialize and enable the Ethernet controller by writing to the controller’s configuration and command registers.

4. Initialize and enable the DMA by writing to the DMA’s configuration and command registers.

After completing these steps, The DMA start to fetch the first descriptor from the specific queue it decided to serve after arbitration, and starts transferring data from memory buffer to the TX-FIFO. When either 384 bytes of packet data are in the FIFO or when the entire packet is in the FIFO (for packets shorter than 384 bytes), the controller initiates transmission of the packet across the MII. While data is read from the FIFO, new data is written into the FIFO by the DMA.

For packets that span more than one buffer in memory, the DMA will fetch new descriptors and buffers as necessary.

When transmission is completed, status is written to the first double word of the last descriptor. The Next Descriptor’s address, which belongs to the next packet in the queue, is written to the current descriptor pointer register.

This process (starting with DMA arbitration) is repeated as long as there are packets pending in the transmit queues.

Ownership of any descriptor other than the last is returned to CPU upon completion of data transfer from the buffer pointed by that descriptor. The Last descriptor, however, is returned to CPU ownership only after the actual transmission of the packet is completed. This is achieved by DMA engine to change the ownership bit of the last descriptor upon the packet transmission is done. The DMA engine also writes status information into the descriptor, which indicates any errors that might have happened during transmission of this packet.

Refer to Table 169 to Table 172 for TX DMA descriptor details.

29.3.1.1 Retransmission (Collision)Full collision support is integrated into the Ethernet controller for half-duplex operation mode by re-transmit the data already stored in local FIFO.

29.3.1.2 Zero Padding for short packetsZero Padding is a term used to denote the operation of adding zero bytes to a packet. 88DE3010 Ethernet controller offer this feature to offload CPU when the packet padding request bit in the TX descriptor is set. The controller logic will enlarge packets shorter than 64 bytes by appending zero bytes. The packets equal or larger than 64 bytes are not affected.

29.3.1.3 CRC GenerationEthernet CRC denotes four bytes of Frame-Check-Sequence appended to each packet.

CRC logic is integrated into the controller and can be used to automatically generate and append CRC to a transmitted packet. One bit in the TX descriptor is used for specifying if CRC generation is required for a specific packet.

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29.3.1.4 TX DMA DescriptorsFigure 122 depicts the format of TX DMA descriptors.

The following set of restrictions apply to TX descriptors:

Descriptor length is must be 4 Double Word, and the descriptor starting address must be 4 Double Word alignedDescriptors may reside anywhere is CPU address space except for NULL address (0x00000000), which is used to indicate end of descriptor chainLast descriptor in the linked chain must have a NULL value in its NextDescriptorPointer field.TX buffers associated with TX descriptors are limited to 64K bytes and can reside anywhere in memory. However, buffers with a payload smaller than 8 bytes must be aligned to 8 byte boundary.

Figure 122:Ethernet TX Descriptor Structure

416 031Commands/status

Byte Count

Buffer pointer


Reserved

4'b0

Table 169: Ethernet TX Descriptor Format

Bits Name Description

31 O Ownership bit.When set to ‘1’, the buffer is “owned” by the device.When set to ‘0’, the buffer is owned by the CPU. Buffers owned by the CPU are not processed by the DMA.

30 AM Auto ModeWhen set, the DMA does not clear the Ownership bit at the end of buffer processing.

29:24 Reserved.

23 EI Enable Interrupt.The device generates a maskable TxBuffer interrupt upon closing the descriptor.NOTE: In order to limit the number of interrupts and prevent an

interrupt per buffer situation, the user should set this bit only in descriptors associated with LAST buffers.

If this is done, TxBuffer interrupt will be set only when transmission of a frame is completed.

22 GC Generate CRCWhen set, CRC is generated and appended to this packet.NOTE: All frame descriptors must be set to the same value.

21:19 Reserved.

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18 P PaddingWhen this bit is set, zero bytes are appended to the packet if the packet is smaller than 60 bytes. Use this feature to prevent transmission of fragments.NOTE: All frame descriptors should be set to same value.

17 F First. Indicates first buffer of a packet.

16 L Last. Indicates last buffer of a packet

15 ES Error Summary. ES = LC or UR or RLSet by the device to indicate an error event that occurred during transmission of the packet. NOTE: Valid only if L (bit 16) is set.

14 Reserved.

13:10 RC[3:0] Retransmit Count. Indicates actual number of retransmits for this packet RC is valid only if L (bit 16) is set

9 COL Collision. When set, indicates that at least one collision event occurred during transmission of the packet NOTE: Valid only if L (bit 16) is set.

8 RL Retransmit Limit (Excessive Collision) error. Indicates that retransmit count reached the limit specified in the DMA configuration register NOTE: Valid only if L (bit 16) is set.

7 Reserved.

6 UR Under-Run error. Indicates that part of the packet’s data was not available while transmission was in progress, probably due to memory access delays). NOTE: Valid only if L (bit 16) is set.

5 LC Late Collision error. Collision occurred outside the collision window (i.e. more than 512 bits were transmitted before collision assertion).NOTE: Valid only if L (bit 16) is set

4:0 Reserved.

Table 169: Ethernet TX Descriptor Format (Continued)


Table 170: Ethernet TX Descriptor - Byte Count


31:16 Byte Count Number of bytes to be transmitted from associated buffer. This is the payload size in bytes.

15:0 Reserved

Table 171: Ethernet TX Descriptor - Buffer Pointer


31:0 Buffer Pointer

32-bit pointer to the beginning of the buffer associated with this descriptor.NOTE: The alignment restrictions for buffers that have Byte-Count

smaller than 8 bytes

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29.3.2 Receive OperationIn order to initialize a receive operation, the CPU must do the following:

1. Prepare a chained list of descriptors and packet buffers.The RxDMA supports four priority queues. If the user wants to take advantage of this capability, a separate list of descriptors and buffers should be prepared for each of the priority queues.

2. Write the pointer to the first descriptor to the DMA’s first and current descriptor registers (RxFDP, RxCDP) associated with the priority queue to be started. If multiple priority queues are needed, the user has to initialize TxFDP and TxCDP for each queue.

3. Initialize and enable the Ethernet controller by writing to the controller’s configuration and command registers.

4. Initialize and enable the DMA channel by writing to the DMA’s configuration and command registers.

After completing these steps, the controller starts waiting for a receive frame to arrive at the MII interface. When this occurs, receive data is packed and transferred to the RxFIFO. At the same time, address filtering test is done in order to decide if the packet is destined to the 88DE3010 device. If the packet passes address filtering check, a decision is made regarding the destination queue to which this packet should be transferred. When this is done, actual data transfer to memory takes place. Packets which fail address filtering are dropped and not transferred to memory.

For packets that span more than one buffer in memory, the DMA will fetch new descriptors as necessary. However, the first descriptor pointer will not be changed until packet reception is done. When reception is completed, status is written to the first longword of the first descriptor, and the Next Descriptor’s address is written to both first and current descriptor pointer registers. This process is repeated for each received packet.

The RxCDP and RxFDP point to the same descriptor whenever the DMA is ready for receiving a new packet. RxFDP is not modified during packet reception and points to the first descriptor. Only after the packet had been fully received and status information was written to the first LW of the first descriptor, will the ownership bit be reset (i.e. descriptor returned to CPU ownership).

Ownership of any descriptor other than the first is returned to CPU upon completion of data transfer to the buffer pointed by that descriptor. This means that the first descriptor of a packet is the last descriptor to return to CPU ownership (per packet).

29.3.2.1 RX DMA DescriptorsFigure 123 shows the format of RX DMA descriptors.

The following set of restrictions apply to RX descriptors:

Descriptor length is 4 Double Word and it must be 4 Double Word aligned (i.e. Descriptor_Address[3:0]=0000).

Table 172: Ethernet TX Descriptor - Next Descriptor Pointer


31:0 Next Descriptor Pointer

32-bit pointer that points to the beginning of next descriptor. Bits [3:0] must be set to 0.DMA operation is stopped when a NULL (all zero) value in the Next Descriptor Pointer field is encountered.

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Descriptors reside anywhere in the CPU address space except NULL address, which is used to indicate end of descriptor chain.RX buffers associated with RX descriptors are limited to 64K bytes and must be 64-bit aligned. Minimum size for RX buffers is 8 bytes.

Figure 123:Ethernet RX DMA Descriptor

3'b0

3'b0

416 031Commands/status

Byte Count

Buffer pointer


Byte Count

4'b0

Table 173: Ethernet RX Descriptor - Command/Status word


0 CE CRC ErrorReceived CRC does not match calculated CRC for the received packet.Valid only if F (bit 17) is set.

3:1 Reserved.

4 COL CollisionCollision was sensed during packet reception.In normal operation mode collided packets are automatically discarded by the controller (being shorter than 64 bytes). Collided packets are accepted only when PBF is set in the Configuration register.

Valid only if F (bit 17) is set.

5 LC Reserved.

6 OR Overrun ErrorIndicates that the RX DMA was unable to transfer data from RxFiFO to memory fast enough, causing data overrun in the FIFO.Valid only if F (bit 17) is set.

7 MFL Max Frame Length ErrorIndicates that a frame longer than MAX_FRAME_LEN was received. The maximum frame length is programmable.Valid only if F (bit 17) is set.

8 SF Short Frame ErrorIndicates that a frame shorter than 64 bytes was received.In normal operation mode, packets that are shorter then 61 bytes are discarded. Packets which are 15 words long, and shorter then 64 bytes, will be accepted.In Pass Bad Frames mode (PBF bit in the Configuration register is set), packets are received regardless of their length.Valid only if F (bit 17) is set.

10:9 Reserved.

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11 FT Frame Type1 - 802.30 - EthernetSet to ‘1’ when the Type/Length field in the received packet has a value not bigger than 1500 (decimal).Valid only if F (bit 17) is set.

12 M Missed Frame0 - Match1 - MissSet to indicate that this packet’s destination address is not found in the address table. This bit may be set if HDM or PM are set in the Configuration register.Also, set to indicate that this is a broadcast packet. Broadcast packets are received regardless of the HDM or PM setting in the Configuration register.This bit is valid only if F (bit 17) is set.

13 HE Hash Table ExpiredSet to indicate that hash process completed 12 searches, but could not find the address. This means that the address is not in 12 adjacent entries starting from the Hash index. This can be the result of an unwritten address or an address that is written in a wrong Hash index, or if all 12 adjacent entries starting from the Hash index are full.Valid only if F (bit 17) is set.

14 IGMP Set to indicate that this packet has been identified as an IGMP packet. Valid only if F (bit 17) is set.

15 ES Error SummaryES = CE or COL or LC or OR or MFL or SFValid only if F (bit 17) is set.

16 L LastIndicates last buffer of a packet.

17 F FirstIndicates first buffer of a packet.

22:18 Reserved.

23 EI Enable InterruptThe device generates a maskable interrupt upon closing the descriptor.In order to limit the number of interrupts and prevent an interrupt per buffer situation, the user should set the EI bits in all the Rx descriptors and set RIFB bit in the DMA Configuration register. The RxBuffer interrupt is set only on frame (rather than buffer) boundaries.

29:24 Reserved.

30 AM Auto ModeWhen set, the DMA does not clear the Ownership bit at the end of buffer processing.

31 O Ownership bit. When set to ‘1’, the buffer is “owned” by the device. When set to ‘0’, the buffer is owned by CPU.

Table 173: Ethernet RX Descriptor - Command/Status word (Continued)


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29.3.3 Ethernet Address Recognition88DE3010 Ethernet controller supports address recognition through Hash table.

The 88DE3010 Ethernet receive address hash table is a data structure prepared by the CPU and resides in the system DRAM. Its location is identified by a register in the controller. 88DE3010 supports two sizes for the Hash table, selectable by the Ethernet Configuration Register.

8K address table. 256 KB of DRAM required (4 x 64-KB banks)1/2K address table. 16 KB of DRAM required (4 x 4-KB banks)

A Four bank Hash table is used in order to reduce the number of addresses that are mapped to the same table entry.

There are two Hash algorithm’s used in the 88DE3010 Ethernet Controller.

Table 177 describes each Hash table entry.

Table 174: Ethernet RX Descriptor - Buffer Size / Byte Count


15:0 Byte Count

When the descriptor is closed this field is written by the device with a value indicating number of bytes actually written by the DMA into the buffer.

31:16 Buffer Size

Buffer Size in BytesWhen number of bytes written to this buffer is equal to Buffer Size value, the DMA closes the descriptor and moves to the next descriptor.Bits [18:16] must be set to 0.

Table 175: Ethernet RX Descriptor - Buffer Pointer


31:0 Buffer Pointer

32-bit Pointer to The Beginning of the Buffer Associated with The DescriptorRX buffers have to be 64-bit aligned, so bits [2:0] must be set to 0.

Table 176: Ethernet RX Descriptor - Next Descriptor Pointer


31:0 NextDescriptorPointer

32-bit Next Descriptor Pointer to the Beginning of Next DescriptorBits [3:0] must be set to 0. DMA operation is stopped when a NULL value in the Next Descriptor Pointer field is encountered.

Table 177: Description of Hash Table EntryBits Name Description

0 Valid Indicates Valid Entry

1 Skip Skip empty entry in a chain

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29.3.3.1 Hash Mode 0In Hash mode 0, the Hash entry address is calculated in the following manner:

hashResult[14:0] = hashFunc0(ethernetADD[47:0])

hashResult is the 15 bits Hash entry address.ethernetADD is a 48 bit number, which is derived from the Ethernet MAC address, by nibble swapping in every byte; i.e. MAC address of 0x123456789abc translates to ethernetADD of 0x21436587a9cb.Inverse every nibble; i.e. ethernetADD of 0x21436587a9cb translates to 0x482c6a1e593d hashFunc0 calculates the hashResult in the following manner:hashResult[14:9] = ethernetADD[7:2]hashResult[8:0]= ethernetADD[14:8,1,0] XOR ethernetADD[23:15] XOR ethernetADD[32:24]

29.3.3.2 Hash Mode 1In Hash mode 1, the Hash entry address is calculated in the following manner:

hashResult[14:0] = hashFunc1(ethernetADD[47:0])

hashResult is the 15 bits Hash entry address.ethernetADD is a 48 bit number, which is derived from the Ethernet MAC address, by nibble swapping in every byte (i.e MAC address of 0x123456789abc translates to ethernetADD of 0x21436587a9cb).Inverse every nibble; i.e. ethernetADD of 0x21436587a9cb translates to 0x482c6a1e593d hashFunc1 calculates the hashResult in the following manner:hashResult[14:9] = ethernetADD[0:5]hashResult[8:0]= ethernetADD[6:14] XOR ethernetADD[15:23] XOR ethernetADD[24:32]

2 Receive/Discard (RD) 0 - Discard packet upon match1 - Receive packet upon match

50:3 Ethernet address[47:0] Mapped to Ethernet MAC address[47:0]

52:51 Priority The priority queue of a packet sent to this Ethernet address, in case there are no other priority signals (i.e. ToS or VLAN)

63:53 Reserved Reserved

Table 177: Description of Hash Table EntryBits Name Description

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10/100MB ETHERNET ControllerMII interface support



29.3.3.3 Creating and using the Hash TableFor each Ethernet address, the Hash table entry address is the lower 13 bits of the hashResult for the 8-KB address table, or the lower 9 bits for the 0.5-KB address table.The entry is an offset from the address base and is octet-byte aligned. The address of the entry is therefore:

8K Address Table: {tblID,tblEntry} = hashResult[14:0]1/2K Address Table: {tableID,tblEntry} =hashResult[10:0]

When preparing the Hash table data structure, the CPU must first (typically at boot time) initialize the Hash table memory to ‘0’.

The table filling algorithm is described below. The hopNumber (maximum Hash number) is 12 in 88DE3010. After 12 tries to identify an address, the Ethernet controller will pass the address to the CPU and sets the HE (Hash Expired) bit in the descriptor status field.

Calculate tblEntryAdd according to mode of operation (Hash Mode 1 or Hash Mode 0).Check that tblEntry is empty (Valid Bit is “0”).If the tblEntry is empty, Write the hashEntry (Valid, Skip and RD bits and Ethernet Address).If the tblEntry is occupied (i.e. Valid bit is 1 and Skip bit is 0), move to tblEntry+1.If less than hopNumber tries, Repeat to Step c.

If after hopNumber failed tries, the CPU has been unable to located a free table entry. The CPU can then:

• Defragment the table.• Create a new Hash table using the alternate Hash Mode, which may redistribute the

addresses more evenly in the table.

In cases where more than one address is mapped to the same table entry, an address chain is created. In this case, when the CPU needs to erase an address that is part of an address chain, it cannot clear its Valid bit since this would cut the chain. Instead, the Skip bit is used by the CPU to maintain the address chain for the Hash chain. Its recommended software defragment the Hash table from time to time (to eliminate skipped entries).

29.4 MII interface support The 88DE3010 Ethernet controller interfaces directly to a MII (Media Independent Interface) PHY compliant with the IEEE standard (please refer to IEEE 802.3u Fast Ethernet standard for detailed interface and timing information).

The interface is clocked by the 25 MHz transmit and receive clocks in 100 Mbps operation, or by 2.5 MHz transmit and receive clocks in 10 Mbps operation. It supports following features:

Capable of supporting both 10 Mbps and 100 Mbps data rates in half or full-duplex modes.Data and delimiters are synchronous to clock references.Provides independent 4-bit wide transmit and receive paths.Uses TTL signal levels.Provides a simple management interface through MDIOCapable of driving a limited length of shielded cable.The controller incorporates all the required digital circuitry to interface with a 100BASE-TX, 100BASE-T4, and 100BASE-FX MII PHYs.

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Doc. No. MV-S104738-02 Rev. A CONFIDENTIAL Copyright © 2010 MarvellPage 348 Document Classification: Proprietary Information March 31, 2010, Advance


A Acronyms and Abbreviations

Table 178: Acronyms and Abbreviations

Acronym Definit ion

ARM Advanced RISC machine

AV Audio and Video

B-Frame Bi-directionally predicted frame/picture

DMA Direct memory access

EC Error concealment engine

ES Elementary stream

IDCT Inverse discrete cosine transform

IEEE Institute of Electrical and Electronics Engineers

ITU International Telecommunication Union (formerly CCITT)

I-Frame Intra coded/predicted frame/picture

JPEG Joint Photographic Experts Group

LCD Liquid crystal display

MB Macro-block

ME Motion estimation engine/Motion estimator

MIPS Million instructions per second

MPEG Moving Picture Experts Group

MSB Most significant bit

MV Motion vector

NRZ Non return to zero

PSNR Peak signal-to-noise ratio

P-Frame Predicted (uni-directionally) frame/picture

PID Packet identifier

PCR Program Clock Reference

PES Packetized Elementary stream

PTS Presentation time-stamp

pCube Pixel processor for Marvell® VMeta™ Technology

RAM Random access memory

RGB Red, green and blue

RLC Run-Length Compression

RLE Run-Length Expansion

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Copyright © 2010 Marvell CONFIDENTIAL Doc. No. MV-S104738-02 Rev. AMarch 31, 2010, Advance Document Classification: Proprietary Information Page 349


ROM Read only memory

SDK Software development kit

TS Transport stream

UP Up-Sampler

VLC Variable Length Coding

VLD Variable Length Decoding

VMeta™ Marvell® video CODEC technology

vScope Video stream parser in VMeta Technology

YCbCr Luminance and 2 chrominance color components

YCrCb Luminance and 2 chrominance color components

YUV Luminance and 2 chrominance color components

Table 178: Acronyms and Abbreviations (Continued)

Acronym Definit ion

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Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500Fax: 1.408.988.8279

www.marvell.com

www.marvell.com

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