9232686 Multitasking and Task Switching in Real Mode

8/8/2019 9232686 Multitasking and Task Switching in Real Mode

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Multitasking and TaskMultitasking and TaskSwitching in RealSwitching in Real

ModeMode

Prepared ByPrepared ByDipan A ParikhDipan A Parikh

Roll No. 200Roll No. 200


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ContentsContents

oo IntroductionIntroduction

oo DefinitionDefinition MultitaskingMultitasking

oo How Multitasking worksHow Multitasking worksoo Types of MultitaskingTypes of Multitasking

oo Task structureTask structure

oo Introduction to task and TaskIntroduction to task and TaskSwitchSwitch

oo Task SwitchingTask Switching


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IntroductionIntroduction

In multitasking, theIn multitasking, the CPUCPU switches back andswitches back and

forth quickly between programs, giving theforth quickly between programs, giving the

appearance that all programs areappearance that all programs are runningrunning

simultaneously. In task switching, the CPUsimultaneously. In task switching, the CPU

does not switch back and forth, butdoes not switch back and forth, butexecutesexecutes

only one program at a time. Task switchingonly one program at a time. Task switching

does allow you to switch smoothly from onedoes allow you to switch smoothly from oneprogram to another.program to another.

Task switching is sometimes calledTask switching is sometimes called contextcontext

switchingswitching


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MultitaskingMultitasking

The 386, as mentioned earlier, has support forThe 386, as mentioned earlier, has support for

multitaskingmultitasking, i.e. running several processes, i.e. running several processes

concurrently. In reality, however, they do notconcurrently. In reality, however, they do not

run concurrently. It only appears to the user asrun concurrently. It only appears to the user as

though they were all running at the same time.though they were all running at the same time.

The 386 uses the Task State Segments (TSSs)The 386 uses the Task State Segments (TSSs)

to support multitasking. The TSS descriptorto support multitasking. The TSS descriptor

points to a buffer which must be at least 104points to a buffer which must be at least 104

bytes long. In addition to multitasking, TSSsbytes long. In addition to multitasking, TSSs

can also be used for hardware interruptcan also be used for hardware interrupt

handling (using task gates in the IDT).handling (using task gates in the IDT).


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The TSS selector is neither readable norThe TSS selector is neither readable nor

writeable. Generally, a TSS alias iswriteable. Generally, a TSS alias is

created, which is nothing but a "data typecreated, which is nothing but a "data type

segment pointing to the TSS buffer. TSSsegment pointing to the TSS buffer. TSS

selectorsselectors alwaysalways appear in the GDT, neverappear in the GDT, never

in LDT or IDT. However, as mentionedin LDT or IDT. However, as mentioned

above, task gates may appear in the IDT.above, task gates may appear in the IDT.

The processor uses the TSS selectorThe processor uses the TSS selector

internally.internally.


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Since a multitasking switch requires theSince a multitasking switch requires the

processor state to be saved, the bufferprocessor state to be saved, the buffer

mostly contains the contents of themostly contains the contents of the

hardware registers. When a task switchhardware registers. When a task switch

occurs, the processor saves various detailsoccurs, the processor saves various detailsin the TSS buffer automatically. This processin the TSS buffer automatically. This process

is very quick and hence not many CPUis very quick and hence not many CPU

cycles are wasted in switching to a newcycles are wasted in switching to a newtask. Before a task is initially started, thetask. Before a task is initially started, the

operating system has to fill in certain entriesoperating system has to fill in certain entries

in the TSS buffer.in the TSS buffer.


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A task switch may occur during a "far jump" orA task switch may occur during a "far jump" or

a "far call". The offset of the call or jump isa "far call". The offset of the call or jump is

simply ignored. The values in the TSS aresimply ignored. The values in the TSS are

loaded into the registers and the new taskloaded into the registers and the new task

beings to execute. The selector referred by thebeings to execute. The selector referred by the

jump or call must be a TSS selector or a taskjump or call must be a TSS selector or a task

gate. The task gate contains the TSS selector.gate. The task gate contains the TSS selector.

But unlike the TSS selector, the task gate mayBut unlike the TSS selector, the task gate may

occur in the GDT, IDT or LDT.occur in the GDT, IDT or LDT.


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The 386 also supports nested tasks. It handlesThe 386 also supports nested tasks. It handles

nested tasks using the NT bit in the EFLAGSnested tasks using the NT bit in the EFLAGS

register. Whenever a task "calls" another task,register. Whenever a task "calls" another task,

the 386 stores the old task's TSS selector in thethe 386 stores the old task's TSS selector in the

"back"back--link" field of the new TSS. Also, the NT bitlink" field of the new TSS. Also, the NT bit

in the EFLAGS register is set. When the new taskin the EFLAGS register is set. When the new task

wishes to return to the old one, it issues an IRETwishes to return to the old one, it issues an IRET

instruction.instruction.

The TSS aren't reentrant. Whenever a task isThe TSS aren't reentrant. Whenever a task is

running, the 386 sets the BUSY bit in the TSSrunning, the 386 sets the BUSY bit in the TSS

selector to indicate this. This is done to preventselector to indicate this. This is done to prevent

recurive calling of tasks.recurive calling of tasks.


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It is incorrect to say that a multitasking OS runsIt is incorrect to say that a multitasking OS runs

multiple programs (i.e., tasks) simultaneously. Inmultiple programs (i.e., tasks) simultaneously. In

reality, it loads a task into memory, permits it toreality, it loads a task into memory, permits it to

run for a while and then suspends it. It suspendsrun for a while and then suspends it. It suspends

the program by creating a snapshot, or image, ofthe program by creating a snapshot, or image, of

all or many of the processor's registers inall or many of the processor's registers inmemory. In the IA32 architecture, the image ismemory. In the IA32 architecture, the image is

stored in a special data structure in memorystored in a special data structure in memory

referred to as a Task State Segment (TSS) and isreferred to as a Task State Segment (TSS) and is

accomplished by performing an automatic seriesaccomplished by performing an automatic series

of memory write transactions. In other words, theof memory write transactions. In other words, the

exact state of the processor at the point ofexact state of the processor at the point of

suspension is saved in memorysuspension is saved in memory..


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Having effectively saved a snapshot thatHaving effectively saved a snapshot that

indicates the point of suspension and theindicates the point of suspension and the

processor's complete state at the time, theprocessor's complete state at the time, the

processor then initiates another task by loadingprocessor then initiates another task by loading

it into memory and jumping to its entry point.it into memory and jumping to its entry point.

Based on some OSBased on some OS--specific criteria, the OS atspecific criteria, the OS at

some point makes the decision to suspend thissome point makes the decision to suspend this

task as well. As before, the state of thetask as well. As before, the state of theprocessor is saved in memory (in this task'sprocessor is saved in memory (in this task's

TSS) as a snapshot of the task's state at its pointTSS) as a snapshot of the task's state at its point

of suspension.of suspension.


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At some point, the OS makes the decision toAt some point, the OS makes the decision to

resume a previouslyresume a previously--suspended task. This issuspended task. This isaccomplished by reloading the processor'saccomplished by reloading the processor's

registers from the previouslyregisters from the previously--saved registersaved register

image (i.e., its TSS) by performing a seriesimage (i.e., its TSS) by performing a seriesof memory read transactions. The processorof memory read transactions. The processor

then uses the address pointer stored in thethen uses the address pointer stored in the

CS:EIP register pair to fetch the nextCS:EIP register pair to fetch the next

instruction, thereby resuming programinstruction, thereby resuming program

execution at the point where it had beenexecution at the point where it had been

suspended earlier.suspended earlier.


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The criteria that an OS uses in making theThe criteria that an OS uses in making the

decision to suspend a program is specific to thatdecision to suspend a program is specific to thatOS. It may simply use timeslicingOS. It may simply use timeslicingeach programeach program

is permitted to execute for a fixed amount of timeis permitted to execute for a fixed amount of time

(e.g., 10ms). At the end of that period of time, the(e.g., 10ms). At the end of that period of time, thecurrently executing task is suspended and thecurrently executing task is suspended and the

next task in the queue is started or resumed. Thenext task in the queue is started or resumed. The

OS may assign priority levels to programs,OS may assign priority levels to programs,

thereby permitting a higher priority program tothereby permitting a higher priority program to

"preempt" a lower priority program that may"preempt" a lower priority program that may

currently be running.currently be running.


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This is referred to asThis is referred to as preemptivepreemptive

multitaskingmultitasking. The OS would also choose to. The OS would also choose to

suspend the currently executing program ifsuspend the currently executing program if

the program needs something that is notthe program needs something that is not

immediately available (e.g., when it attemptsimmediately available (e.g., when it attempts

an access to a page of information that isan access to a page of information that is

currently not in memory, but resides on acurrently not in memory, but resides on amass storage device).mass storage device).


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The following items define the state of thecurrently executing task:

The tasks curent execution space, defined by the

segment selectors in the segment registers (CS, DS, SS, ES, FS, and GS).

The state of the general-purpose registers.

The state of the EFLAGS register.

The state of the EIP register. The state of control registerCR3.

The state of the task register.

The state of the LDTR register.

The I/O map base address and I/O map (containedin the TSS).

Stack pointers to the privilege 0, 1, and 2 stacks(contained in the TSS).

Link to previously executed task (contained in theTSS).


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Prior to dispatching a task, all of these items arecontained in the tasks TSS, except the state of

the task register. Also, the complete contents ofthe LDTR register are not contained in the TSS,only the segment selector for the LDT.

Software or the processor can dispatch a task forexecution in one of the following ways:

A explicit call to a task with the CALL instruction.

A explicit jump to a task with the JMP instruction.

An implicit call (by the processor) to an interrupt-handler task.

An implicit call to an exception-handler task.

A return (initiated with an IRET instruction) whenthe NT flag in the EFLAGS register is set.


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When a task is dispatched for execution, a taskswitch automatically occurs between thecurrently running task and the dispatched task.

During a task switch, the execution environmentof the currently executing task (called the tasksstate or context) is saved in its TSS and execution

of the task is suspended. The context for the

dispatched task is then loaded into the processorand execution of that task begins with theinstruction pointed to by the newly loaded EIP

register. If the task has not been run since the

system was last initialized, the EIP will point to

the first instruction of the tasks code; otherwise,it will point to the next instruction after the last

instruction that the task executed when it was lastactive.


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Task Switching

The processor transfers execution to anothertask in any of four cases:

The current program, task, or procedure

executes a JMP or CALL instruction to a TSSdescriptor in the GDT.

The current program, task, or procedure

executes a JMP or CALL instruction to a task-gate descriptor in the GDT or the current LDT.

An interrupt or exception vector points to a task-

gate descriptor in the IDT.


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The current task executes an IRET when the NTflag in the EFLAGS register is set.

The JMP,C

ALL, and IRET instructions, as well asinterrupts and exceptions, are all generalized

mechanisms for redirecting a program. The

referencing of a TSS descriptor or a task gate

(when calling or jumping to a task) or the state of

the NT flag (when executing an IRET instruction)

determines whether a task switch occurs.


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The processor performs the following operations

when switching to a new task:1. Obtains the TSS segment selector for the new

task as the operand of the JMP or CALL

instruction, from a task gate, or from theprevious task link field (for a task switch initiated

with an IRET instruction).

2. Checks that the current (old) task is allowedto switch to the new task. Data-access

privilege rules apply to JMP and CALL

instructions.


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The CPL of the current (old) task and the RPL of

the segment selector for the new task must beless than or equal to the DPL of the TSS

descriptor or task gate being referenced.

Exceptions, interrupts (except for interruptsgenerated by the INT n instruction), and the

IRET instruction are permitted to switch tasks

regardless of the DPL of the destination task-gate or TSS descriptor. For interrupts

generated by the INT n instruction, the DPL is

checked.


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3. Checks that the TSS descriptor of the new task is

marked present and has a valid limit (greater

than or equal to 67H).

4. Checks that the new task is available (call, jump,

exception, or interrupt) or busy (IRET return).

5. Checks that the current (old) TSS, new TSS, and

all segment descriptors used in the task switch

are paged into system memory.

6. If the task switch was initiated with a JMP or IRET

instruction, the processor clears the busy (B) flag

in the current (old) tasks TSS descriptor; if


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initiated with a CALL instruction, an exception,

or an interrupt, the busy (B) flag is left set.

7. If the task switch was initiated with an IRET

instruction, the processor clears the NT flag in

a temporarily saved image of the EFLAGS

register; if initiated with a CALL or JMP

instruction, an exception, or an interrupt, the

NT flag is left unchanged in the saved EFLAGS

image.


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8. Saves the state of the current (old) task in thecurrent tasks TSS. The processor finds the

base address of the current TSS in the task

register and then copies the states of thefollowing registers into the current TSS: all the

general-purpose registers, segment selectors

from the segment registers, the temporarily

saved image of the EFLAGS register, and the

instruction pointer register (EIP).


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9. If the task switch was initiated with a CALL

instruction, an exception, or an interrupt, the

processor will set the NT flag in the EFLAGSloaded from the new task. If initiated with an IRET

instruction or JMP instruction, the NT flag will

reflect the state of NT in the EFLAGS loaded fromthe new task.

10. If the task switch was initiated with a CALL

instruction, JMP instruction, an exception, or aninterrupt, the processor sets the busy (B) flag in

the new tasks TSS descriptor; if initiated with an

IRET instruction, the busy (B) flag is left set.


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11. Loads the task register with the segment

selector and descriptor for the new task's TSS.

12. The TSS state is loaded into the processor. This

includes the LDTR register, the PDBR (control

registerCR3), the EFLAGS registers, the EIP

register, the general-purpose registers, and the

segment selectors. Note that a fault during the

load of this state may corrupt architectural state.

13. The descriptors associated with the segment

selectors are loaded and qualified. Any errors

associated with this loading and qualification

occur in the context of the new task.


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At this point, if all checks and saves have been

carried out successfully, the processor commitsto the task switch. If an unrecoverable error

occurs in steps 1 through 11, the processor does

not complete the task switch and insures that the

processor is returned to its state prior to the

execution of the instruction that initiated the task

switch. If an unrecoverable error occurs in step

12, architectural state may be corrupted, but an

attempt will be made to handle the error in the

prior execution environment.


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If an unrecoverable error occurs after the commit

point (in step 13), the processor completes the

task switch (without performing additional accessand segment availability checks) and generates

the appropriate exception prior to beginning

execution of the new task. If exceptions occurafter the commit point, the exception handler

must finish the task switch itself before allowing

the processor to begin executing the new task.14. Begins executing the new task. (To an exception

handler, the first instruction of the new task

appears not to have been executed.)


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The state of the currently executing task is always

saved when a successful task switch occurs.

If the task is resumed, execution starts with the

instruction pointed to by the saved EIP value, and

the registers are restored to the values they held

when the task was suspended.

When switching tasks, the privilege level of the

new task does not inherit its privilege level from

the suspended task. The new task begins

executing at the privilege level specified in the CP

field of the CS register, which is loaded from the

TSS.


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THANK YOUTHANK YOU

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9232686 Multitasking and Task Switching in Real Mode