REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aAD9752*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 © Analog Devices, Inc., 1999

12-Bit, 125 MSPS High Performance TxDAC® D/A Converter

FUNCTIONAL BLOCK DIAGRAM

150pF+1.20V REF

AVDD ACOMREFLO

ICOMPCURRENTSOURCEARRAY

+5V

SEGMENTEDSWITCHES

LSBSWITCHES

REFIOFS ADJ

DVDD

DCOM

CLOCK

+5VRSET

0.1mF

CLOCK

IOUTA

IOUTB

0.1mF

LATCHES

AD9752

SLEEP

DIGITAL DATA INPUTS (DB11–DB0)

FEATURESHigh Performance Member of Pin-Compatible

TxDAC Product Family125 MSPS Update Rate12-Bit ResolutionExcellent Spurious Free Dynamic Range PerformanceSFDR to Nyquist @ 5 MHz Output: 79 dBcDifferential Current Outputs: 2 mA to 20 mAPower Dissipation: 185 mW @ 5 VPower-Down Mode: 20 mW @ 5 VOn-Chip 1.20 V ReferenceCMOS-Compatible +2.7 V to +5.5 V Digital InterfacePackage: 28-Lead SOIC and TSSOPEdge-Triggered Latches

APPLICATIONSWideband Communication Transmit Channel:

Direct IFBasestationsWireless Local LoopDigital Radio Link

Direct Digital Synthesis (DDS)Instrumentation

PRODUCT DESCRIPTIONThe AD9752 is a 12-bit resolution, wideband, second generationmember of the TxDAC series of high performance, low powerCMOS digital-to-analog-converters (DACs). The TxDAC family,which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, isspecifically optimized for the transmit signal path of communica-tion systems. All of the devices share the same interface options,small outline package and pinout, thus providing an upward ordownward component selection path based on performance,resolution and cost. The AD9752 offers exceptional ac and dcperformance while supporting update rates up to 125 MSPS.

The AD9752’s flexible single-supply operating range of 4.5 V to5.5 V and low power dissipation are well suited for portable andlow power applications. Its power dissipation can be furtherreduced to a mere 65 mW, without a significant degradation inperformance, by lowering the full-scale current output. Also, apower-down mode reduces the standby power dissipation toapproximately 20 mW.

The AD9752 is manufactured on an advanced CMOS process.A segmented current source architecture is combined with aproprietary switching technique to reduce spurious componentsand enhance dynamic performance. Edge-triggered input latchesand a 1.2 V temperature compensated bandgap reference havebeen integrated to provide a complete monolithic DAC solution.The digital inputs support +2.7 V to +5 V CMOS logic families.

The AD9752 is a current-output DAC with a nominal full-scaleoutput current of 20 mA and > 100 kΩ output impedance.

Differential current outputs are provided to support single-ended or differential applications. Matching between the twocurrent outputs ensures enhanced dynamic performance in adifferential output configuration. The current outputs may betied directly to an output resistor to provide two complemen-tary, single-ended voltage outputs or fed directly into a trans-former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured formaximum accuracy and flexibility. The AD9752 can be drivenby the on-chip reference or by a variety of external referencevoltages. The internal control amplifier, which provides a wide(>10:1) adjustment span, allows the AD9752 full-scale currentto be adjusted over a 2 mA to 20 mA range while maintainingexcellent dynamic performance. Thus, the AD9752 may oper-ate at reduced power levels or be adjusted over a 20 dB range toprovide additional gain ranging capabilities.

The AD9752 is available in 28-lead SOIC and TSSOP packages.It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS1. The AD9752 is a member of the wideband TxDAC product

family that provides an upward or downward component selec-tion path based on resolution (8 to 14 bits), performance andcost. The entire family of TxDACs is available in industrystandard pinouts.

2. Manufactured on a CMOS process, the AD9752 uses aproprietary switching technique that enhances dynamicperformance beyond that previously attainable by higherpower/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches interface readilyto +2.7 V to +5 V CMOS logic families. The AD9752 cansupport update rates up to 125 MSPS.

4. A flexible single-supply operating range of 4.5 V to 5.5 V anda wide full-scale current adjustment span of 2 mA to 20 mAallow the AD9752 to operate at reduced power levels.

5. The current output(s) of the AD9752 can be easily config-ured for various single-ended or differential circuit topologies.

TxDAC is a registered trademark of Analog Devices, Inc.*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and5703519.

–2–

AD9752–SPECIFICATIONS

REV. 0

(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)DC SPECIFICATIONSParameter Min Typ Max Units

RESOLUTION 12 Bits

DC ACCURACY1

Integral Linearity Error (INL)TA = +25°C –1.5 ±0.5 +1.5 LSBTMIN to TMAX –2.0 +2.0 LSB

Differential Nonlinearity (DNL)TA = +25°C –0.75 ±0.25 +0.75 LSBTMIN to TMAX –1.0 +1.0 LSB

ANALOG OUTPUTOffset Error –0.02 +0.02 % of FSRGain Error (Without Internal Reference) –2 ±0.5 +2 % of FSRGain Error (With Internal Reference) –5 ±1.5 +5 % of FSRFull-Scale Output Current2 2.0 20.0 mAOutput Compliance Range –1.0 1.25 VOutput Resistance 100 kΩOutput Capacitance 5 pF

REFERENCE OUTPUTReference Voltage 1.14 1.20 1.26 VReference Output Current3 100 nA

REFERENCE INPUTInput Compliance Range 0.1 1.25 VReference Input Resistance 1 MΩSmall Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTSOffset Drift 0 ppm of FSR/°CGain Drift (Without Internal Reference) ±50 ppm of FSR/°CGain Drift (With Internal Reference) ±100 ppm of FSR/°CReference Voltage Drift ±50 ppm/°C

POWER SUPPLYSupply Voltages

AVDD 4.5 5.0 5.5 VDVDD 2.7 5.0 5.5 V

Analog Supply Current (IAVDD)4 34 39 mADigital Supply Current (IDVDD)5 3 5 mASupply Current Sleep Mode (IAVDD)6 4 8 mAPower Dissipation5 (5 V, IOUTFS = 20 mA) 185 220 mWPower Supply Rejection Ratio7—AVDD –0.4 +0.4 % of FSR/VPower Supply Rejection Ratio7—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °CNOTES1Measured at IOUTA, driving a virtual ground.2Nominal full-scale current, IOUTFS, is 32 × the IREF current.3Use an external buffer amplifier to drive any external load.4Requires +5 V supply.5Measured at fCLOCK = 25 MSPS and IOUT = static full scale (20 mA).6Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.7±5% Power supply variation.

Specifications subject to change without notice.

REV. 0 –3–

AD9752

DYNAMIC SPECIFICATIONSParameter Min Typ Max Units

DYNAMIC PERFORMANCEMaximum Output Update Rate (fCLOCK) 125 MSPSOutput Settling Time (tST) (to 0.1%)1 35 nsOutput Propagation Delay (tPD) 1 nsGlitch Impulse 5 pV-sOutput Rise Time (10% to 90%)1 2.5 nsOutput Fall Time (10% to 90%)1 2.5 nsOutput Noise (IOUTFS = 20 mA) 50 pA/√HzOutput Noise (IOUTFS = 2 mA) 30 pA/√Hz

AC LINEARITYSpurious-Free Dynamic Range to Nyquist

fCLOCK = 25 MSPS; fOUT = 1.00 MHz0 dBFS Output

TA = +25°C 75 84 dBc–6 dBFS Output 76 dBc–12 dBFS Output 81 dBc

fCLOCK = 50 MSPS; fOUT = 1.00 MHz 81 dBcfCLOCK = 50 MSPS; fOUT = 2.51 MHz 81 dBcfCLOCK = 50 MSPS; fOUT = 5.02 MHz 76 dBcfCLOCK = 50 MSPS; fOUT = 14.02 MHz 62 dBcfCLOCK = 50 MSPS; fOUT = 20.2 MHz 60 dBcfCLOCK = 100 MSPS; fOUT = 2.5 MHz 78 dBcfCLOCK = 100 MSPS; fOUT = 5 MHz 76 dBcfCLOCK = 100 MSPS; fOUT = 20 MHz 63 dBcfCLOCK = 100 MSPS; fOUT = 40 MHz 55 dBc

Spurious-Free Dynamic Range within a WindowfCLOCK = 25 MSPS; fOUT = 1.00 MHz 84 93 dBcfCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span 86 dBcfCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span 86 dBc

Total Harmonic DistortionfCLOCK = 25 MSPS; fOUT = 1.00 MHz

TA = +25°C –82 –74 dBcfCLOCK = 50 MHz; fOUT = 2.00 MHz –76 dBcfCLOCK = 100 MHz; fOUT = 2.00 MHz –76 dBc

Multitone Power Ratio (8 Tones at 110 kHz Spacing)fCLOCK = 20 MSPS; fOUT = 2.00 MHz to 2.99 MHz

0 dBFS Output 81 dBc–6 dBFS Output 81 dBc–12 dBFS Output 85 dBc–18 dBFS Output 86 dBc

NOTES1Measured single ended into 50 Ω load.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,50 V Doubly Terminated, unless otherwise noted)

REV. 0

AD9752

–4–

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD9752 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

WithParameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 VDVDD DCOM –0.3 +6.5 VACOM DCOM –0.3 +0.3 VAVDD DVDD –6.5 +6.5 VCLOCK, SLEEP DCOM –0.3 DVDD + 0.3 VDigital Inputs DCOM –0.3 DVDD + 0.3 VIOUTA, IOUTB ACOM –1.0 AVDD + 0.3 VICOMP ACOM –0.3 AVDD + 0.3 VREFIO, FSADJ ACOM –0.3 AVDD + 0.3 VREFLO ACOM –0.3 +0.3 VJunction Temperature +150 °CStorage Temperature –65 +150 °CLead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximumratings for extended periods may effect device reliability.

DIGITAL SPECIFICATIONSParameter Min Typ Max Units

DIGITAL INPUTSLogic “1” Voltage @ DVDD = +5 V1 3.5 5 VLogic “1” Voltage @ DVDD = +3 V 2.1 3 VLogic “0” Voltage @ DVDD = +5 V1 0 1.3 VLogic “0” Voltage @ DVDD = +3 V 0 0.9 VLogic “1” Current –10 +10 µALogic “0” Current –10 +10 µAInput Capacitance 5 pFInput Setup Time (tS) 2.0 nsInput Hold Time (tH) 1.5 nsLatch Pulsewidth (tLPW) 3.5 ns

NOTES1When DVDD = +5 V and Logic 1 voltage ≈3.5 V and Logic 0 voltage ≈1.3 V. IVDD can increase by up to 10 mA, depending on fCLOCK.Specifications subject to change without notice.

0.1%

0.1%

tS tH

tLPW

tPD tST

DB0–DB11

CLOCK

IOUTAOR

IOUTB

Figure 1. Timing Diagram

(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)

ORDERING GUIDE

Temperature Package PackageModel Range Description Options*

AD9752AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28AD9752ARU –40°C to +85°C 28-Lead TSSOP RU-28AD9752-EB Evaluation Board

*R = Small Outline IC; RU = Thin Shrink Small Outline Package.

THERMAL CHARACTERISTICSThermal Resistance28-Lead 300 Mil SOIC

θJA = 71.4°C/WθJC = 23°C/W

28-Lead TSSOPθJA = 97.9°C/WθJC = 14.0°C/W

REV. 0

AD9752

–5–

PIN CONFIGURATION

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

TOP VIEW(Not to Scale)

28

27

26

25

24

23

22

21

AD9752

NC = NO CONNECT

(MSB) DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

NC

NC

CLOCK

DVDD

DCOM

NC

AVDD

ICOMP

IOUTA

IOUTB

ACOM

NC

FS ADJ

REFIO

REFLO

SLEEP

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB11 Most Significant Data Bit (MSB).2–11 DB10–DB1 Data Bits 1–10.12 DB0 Least Significant Data Bit (LSB).13, 14,19, 25 NC No Internal Connection.15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated

if not used.16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).Requires 0.1 µF capacitor to ACOM when internal reference activated.

18 FS ADJ Full-Scale Current Output Adjust.19 NC No Connect.20 ACOM Analog Common.21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V).26 DCOM Digital Common.27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).28 CLOCK Clock Input. Data latched on positive edge of clock.

REV. 0

AD9752

–6–

DEFINITIONS OF SPECIFICATIONSLinearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of theactual analog output from the ideal output, determined by astraight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)DNL is the measure of the variation in analog value, normalizedto full scale, associated with a 1 LSB change in digital input code.

MonotonicityA D/A converter is monotonic if the output either increases orremains constant as the digital input increases.

Offset ErrorThe deviation of the output current from the ideal of zero iscalled offset error. For IOUTA, 0 mA output is expected whenthe inputs are all 0s. For IOUTB, 0 mA output is expectedwhen all inputs are set to 1s.

Gain ErrorThe difference between the actual and ideal output span. Theactual span is determined by the output when all inputs are setto 1s minus the output when all inputs are set to 0s.

Output Compliance RangeThe range of allowable voltage at the output of a current-outputDAC. Operation beyond the maximum compliance limits maycause either output stage saturation or breakdown resulting innonlinear performance.

Temperature DriftTemperature drift is specified as the maximum change from theambient (+25°C) value to the value at either TMIN or TMAX. Foroffset and gain drift, the drift is reported in ppm of full-scalerange (FSR) per °C. For reference drift, the drift is reportedin ppm per °C.

Power Supply RejectionThe maximum change in the full-scale output as the suppliesare varied from nominal to minimum and maximum specifiedvoltages.

Settling TimeThe time required for the output to reach and remain within aspecified error band about its final value, measured from thestart of the output transition.

Glitch ImpulseAsymmetrical switching times in a DAC give rise to undesiredoutput transients that are quantified by a glitch impulse. It isspecified as the net area of the glitch in pV-s.

Spurious-Free Dynamic RangeThe difference, in dB, between the rms amplitude of the outputsignal and the peak spurious signal over the specified bandwidth.

Total Harmonic DistortionTHD is the ratio of the rms sum of the first six harmoniccomponents to the rms value of the measured input signal. It isexpressed as a percentage or in decibels (dB).

Multitone Power RatioThe spurious-free dynamic range for an output containing mul-tiple carrier tones of equal amplitude. It is measured as thedifference between the rms amplitude of a carrier tone to thepeak spurious signal in the region of a removed tone.

+1.20V REF

AVDD ACOMREFLO

ICOMPPMOSCURRENT SOURCE

ARRAY

+5V

SEGMENTED SWITCHESFOR DB11–DB3

LSBSWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

RSET2kV

0.1mF

DVDDDCOM

IOUTA

IOUTB

0.1mF

AD9752

SLEEP50V

RETIMEDCLOCK

OUTPUT*

LATCHES

DIGITALDATA

TEKTRONIXAWG-2021

W/OPTION 4

LECROY 9210PULSE GENERATOR

CLOCKOUTPUT

50V 20pF

50V 20pF

100V

TO HP3589ASPECTRUM/NETWORKANALYZER50V INPUT

MINI-CIRCUITST1-1T

* AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.

150pF

Figure 2. Basic AC Characterization Test Setup

REV. 0

AD9752

–7–

Typical AC Characterization Curves @ +5 V Supplies(AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50 V Doubly Terminated Load, Differential Output, TA = +258C, SFDR up to Nyquist, unless otherwise noted)

fOUT – MHz

SF

DR

– d

B

90

80

400 1 10010

70

60

50

25MSPS 50MSPS

125MSPS65MSPS

Figure 3. SFDR vs. fOUT @ 0 dBFS

fOUT – MHz

SF

DR

– d

Bc

90

80

400 5 3020

70

60

50

10 15 25

–12dBFS

–6dBFS

0dBFS

Figure 6. SFDR vs. fOUT @ 65 MSPS

AOUT – dBFS

SF

DR

– d

B

90

70

–30 –25 0–10

80

–20 –15 –540

60

50

2.27MHz@25MSPS

4.55MHz@50MSPS

5.91MHz@65MSPS

11.36MHz@125MSPS

Figure 9. Single-Tone SFDR vs. AOUT

@ fOUT = fCLOCK/11

SF

DR

– d

B

90

80

400 2 1412

70

60

50

4 6 8 10

–12dBFS

0dBFS

–6dBFS

fOUT – MHz

Figure 4. SFDR vs. fOUT @ 25 MSPS

SF

DR

– d

B

90

80

400 10 6040

70

60

50

20 30 50

–6dBFS

0dBFS

–12dBFS

fOUT – MHz

Figure 7. SFDR vs. fOUT @ 125 MSPS

AOUT – dBFS

SF

DR

– d

B

90

70

–30 –25 0–10

80

–20 –15 –540

60

50

5MHz@25MSPS

10MHz@50MSPS

13MHz@65MSPS

25MHz@125MSPS

Figure 10. Single-Tone SFDR vs.AOUT @ fOUT = fCLOCK/5

fOUT – MHz

SF

DR

– d

Bc

90

80

400 5 2510

70

60

50

15 20

–12dBFS

–6dBFS

0dBFS

Figure 5. SFDR vs. fOUT @ 50 MSPS

fOUT – MHz

SF

DR

– d

Bc

90

0 2 128

80

70

4 6 1050

60

10mA FS

20mA FS

5mA FS

Figure 8. SFDR vs. fOUT and IOUTFS

@ 25 MSPS and 0 dBFS

fCLOCK – MSPS

SN

R –

dB

0 20 12080

80

40 60 100

60

70

50

20mA FS

10mA FS5mA FS

Figure 11. SNR vs. fCLOCK and IOUTFS

@ fOUT = 2 MHz and 0 dBFS

REV. 0

AD9752

–8–

CODE

ER

RO

R –

LS

B

0 40001000 2000 3000

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

Figure 12. Typical INL

fOUT – MHz

SIG

NA

L A

MP

LIT

UD

E –

dB

m

0 6010 20 30

0

–10

–20

–30

–40

–100

–50

–60

–70

–80

–90

40 50

fCLK = 125MSPSfOUT1 = 13.5MHzfOUT2 = 14.5MHzAOUT = 0dBFSSFDR = 68.4dBc

Figure 15. Dual-Tone SFDR

CODEE

RR

OR

– L

SB

0 40001000 2000 3000

0.1

0.0

–0.1

–0.2

–0.3

–0.5

–0.4

Figure 13. Typical DNL

SIG

NA

L A

MP

LIT

UD

E –

dB

m

0 30.05.0 10.0 15.0

0

–10

–20

–30

–40

–100

–50

–60

–70

–80

–90

20.0 25.0

fCLK = 65MSPSfOUT1 = 6.25MHzfOUT2 = 6.75MHzfOUT3 = 7.25MHzfOUT4 = 7.75MHzSFDR = 69dBcAMPLITUDE = 0dBFS

fOUT – MHz

Figure 16. Four-Tone SFDR

TEMPERATURE – 8C

SF

DR

– d

Bc

–55 95–30 –5 20

90

70

80

50

60

45 70

fOUT = 4MHz

fOUT = 10MHz

fOUT = 29MHz

fOUT = 40MHz

Figure 14. SFDR vs. Temperature @125 MSPS, 0 dBFS

REV. 0

AD9752

–9–

FUNCTIONAL DESCRIPTIONFigure 17 shows a simplified block diagram of the AD9752.The AD9752 consists of a large PMOS current source array thatis capable of providing up to 20 mA of total current. The arrayis divided into 31 equal currents that make up the five mostsignificant bits (MSBs). The next four bits or middle bits consistof 15 equal current sources whose value is 1/16th of an MSBcurrent source. The remaining LSBs are binary weighted frac-tions of the middle-bits current sources. Implementing themiddle and lower bits with current sources, instead of an R-2Rladder, enhances its dynamic performance for multitone or lowamplitude signals and helps maintain the DAC’s high outputimpedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other ofthe two output nodes (i.e., IOUTA or IOUTB) via PMOSdifferential current switches. The switches are based on a newarchitecture that drastically improves distortion performance.This new switch architecture reduces various timing errors andprovides matching complementary drive signals to the inputs ofthe differential current switches.

The analog and digital sections of the AD9752 have separatepower supply inputs (i.e., AVDD and DVDD). The digitalsection, which is capable of operating up to a 125 MSPS clockrate and over a +2.7 V to +5.5 V operating range, consists ofedge-triggered latches and segment decoding logic circuitry.The analog section, which can operate over a +4.5 V to +5.5 Vrange, includes the PMOS current sources, the associated differ-ential switches, a 1.20 V bandgap voltage reference and a refer-ence control amplifier.

The full-scale output current is regulated by the reference con-trol amplifier and can be set from 2 mA to 20 mA via an exter-nal resistor, RSET. The external resistor, in combination withboth the reference control amplifier and voltage reference VREFIO,sets the reference current IREF, which is mirrored over to thesegmented current sources with the proper scaling factor. Thefull-scale current, IOUTFS, is thirty-two times the value of IREF.

DAC TRANSFER FUNCTIONThe AD9752 provides complementary current outputs, IOUTAand IOUTB. IOUTA will provide a near full-scale current output,IOUTFS, when all bits are high (i.e., DAC CODE = 4095) whileIOUTB, the complementary output, provides no current. Thecurrent output appearing at IOUTA and IOUTB is a functionof both the input code and IOUTFS and can be expressed as:

IOUTA = (DAC CODE/4096) × IOUTFS (1)

IOUTB = (4095 – DAC CODE)/4096 × IOUTFS (2)

where DAC CODE = 0 to 4095 (i.e., Decimal Representation).

As mentioned previously, IOUTFS is a function of the referencecurrent IREF, which is nominally set by a reference voltageVREFIO and external resistor RSET. It can be expressed as:

IOUTFS = 32 × IREF (3)

where IREF = VREFIO/RSET (4)

The two current outputs will typically drive a resistive loaddirectly or via a transformer. If dc coupling is required, IOUTAand IOUTB should be directly connected to matching resistiveloads, RLOAD, which are tied to analog common, ACOM. Note,RLOAD may represent the equivalent load resistance seen byIOUTA or IOUTB as would be the case in a doubly terminated50 Ω or 75 Ω cable. The single-ended voltage output appearingat the IOUTA and IOUTB nodes is simply :

VOUTA = IOUTA × RLOAD (5)

VOUTB = IOUTB × RLOAD (6)

Note the full-scale value of VOUTA and VOUTB should not exceedthe specified output compliance range to maintain specifieddistortion and linearity performance.

The differential voltage, VDIFF, appearing across IOUTA andIOUTB is:

VDIFF = (IOUTA – IOUTB) × RLOAD (7)

Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can beexpressed as:

VDIFF = (2 DAC CODE – 4095)/4096 ×(32 RLOAD/RSET) × VREFIO (8)

These last two equations highlight some of the advantages ofoperating the AD9752 differentially. First, the differential op-eration will help cancel common-mode error sources associatedwith IOUTA and IOUTB such as noise, distortion and dc offsets.Second, the differential code dependent current and subsequentvoltage, VDIFF, is twice the value of the single-ended voltageoutput (i.e., VOUTA or VOUTB), thus providing twice the signalpower to the load.

Note, the gain drift temperature performance for a single-ended(VOUTA and VOUTB) or differential output (VDIFF) of the AD9752can be enhanced by selecting temperature tracking resistors forRLOAD and RSET due to their ratiometric relationship as shownin Equation 8.

DIGITAL DATA INPUTS (DB11–DB0)

150pF

+1.20V REF

AVDD ACOMREFLO

ICOMPPMOSCURRENT SOURCE

ARRAY

+5V

SEGMENTED SWITCHESFOR DB11–DB3

LSBSWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

RSET2kV

0.1mF

IOUTA

IOUTB

0.1mF

AD9752

SLEEPLATCHES

IREF

VREFIO

CLOCK

IOUTB

IOUTA

RLOAD50V

VOUTB

VOUTA

RLOAD50V

VDIFF = VOUTA – VOUTB

Figure 17. Functional Block Diagram

REV. 0

AD9752

–10–

REFERENCE OPERATIONThe AD9752 contains an internal 1.20 V bandgap referencethat can easily be disabled and overridden by an external refer-ence. REFIO serves as either an input or output depending onwhether the internal or an external reference is selected. IfREFLO is tied to ACOM, as shown in Figure 18, the internalreference is activated and REFIO provides a 1.20 V output. Inthis case, the internal reference must be compensated externallywith a ceramic chip capacitor of 0.1 µF or greater from REFIOto REFLO. Also, REFIO should be buffered with an externalamplifier having an input bias current less than 100 nA if anyadditional loading is required.

150pF

+1.2V REF

AVDDREFLO

CURRENTSOURCEARRAY

+5V

REFIO

FS ADJ

2kV

0.1mF

AD9752

ADDITIONALLOAD

OPTIONALEXTERNAL

REF BUFFER

Figure 18. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO toAVDD. In this case, an external reference may then be appliedto REFIO as shown in Figure 19. The external reference mayprovide either a fixed reference voltage to enhance accuracy anddrift performance or a varying reference voltage for gain control.Note that the 0.1 µF compensation capacitor is not requiredsince the internal reference is disabled, and the high input im-pedance (i.e., 1 MΩ) of REFIO minimizes any loading of theexternal reference.

150pF

+1.2V REF

AVDDREFLO

CURRENTSOURCEARRAY

AVDD

REFIO

FS ADJ

RSET

AD9752

EXTERNALREF

IREF =VREFIO/RSET

AVDD

REFERENCECONTROLAMPLIFIER

VREFIO

Figure 19. External Reference Configuration

REFERENCE CONTROL AMPLIFIERThe AD9752 also contains an internal control amplifier that isused to regulate the DAC’s full-scale output current, IOUTFS.The control amplifier is configured as a V-I converter as shownin Figure 19, such that its current output, IREF, is determined bythe ratio of the VREFIO and an external resistor, RSET, as statedin Equation 4. IREF is copied over to the segmented currentsources with the proper scaling factor to set IOUTFS as stated inEquation 3.

The control amplifier allows a wide (10:1) adjustment span ofIOUTFS over a 2 mA to 20 mA range by setting IREF between62.5 µA and 625 µA. The wide adjustment span of IOUTFS

provides several application benefits. The first benefit relatesdirectly to the power dissipation of the AD9752, which isproportional to IOUTFS (refer to the Power Dissipation section).The second benefit relates to the 20 dB adjustment, which isuseful for system gain control purposes.

The small signal bandwidth of the reference control amplifier isapproximately 0.5 MHz. The output of the control amplifier isinternally compensated via a 150 pF capacitor that limits thecontrol amplifier small-signal bandwidth and reduces itsoutput impedance. Since the –3 dB bandwidth corresponds tothe dominant pole, and hence the time constant, the settlingtime of the control amplifier to a stepped reference input re-sponse can be approximated. In this case, the time constant canbe approximated to be 320 ns.

There are two methods in which IREF can be varied for a fixedRSET. The first method is suitable for a single-supply system inwhich the internal reference is disabled, and the common-modevoltage of REFIO is varied over its compliance range of 1.25 Vto 0.10 V. REFIO can be driven by a single-supply amplifier orDAC, thus allowing IREF to be varied for a fixed RSET. Since theinput impedance of REFIO is approximately 1 MΩ, a simple,low cost R-2R ladder DAC configured in the voltage modetopology may be used to control the gain. This circuit is shownin Figure 20 using the AD7524 and an external 1.2 V reference,the AD1580.

1.2V

150pF

+1.2V REF

AVDDREFLO

CURRENTSOURCEARRAY

AVDD

REFIO

FS ADJ

RSET AD9752IREF =VREF/RSET

AVDD

VREF

VDDRFB

OUT1

OUT2

AGND

DB7–DB0

AD7524AD1580

0.1V TO 1.2V

Figure 20. Single-Supply Gain Control Circuit

REV. 0

AD9752

–11–

The second method may be used in a dual-supply system inwhich the common-mode voltage of REFIO is fixed and IREF isvaried by an external voltage, VGC, applied to RSET via an ampli-fier. An example of this method is shown in Figure 21, in whichthe internal reference is used to set the common-mode voltageof the control amplifier to 1.20 V. The external voltage, VGC, isreferenced to ACOM and should not exceed 1.2 V. The valueof RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µAand 625 µA, respectively. The associated equations in Figure 21can be used to determine the value of RSET.

150pF

+1.2V REF

AVDDREFLO

CURRENTSOURCEARRAY

AVDD

REFIO

FS ADJ

RSET AD9752IREF

VGC

1mF

IREF = (1.2–VGC)/RSETWITH VGC < VREFIO AND 62.5mA # IREF # 625A

Figure 21. Dual-Supply Gain Control Circuit

ANALOG OUTPUTSThe AD9752 produces two complementary current outputs,IOUTA and IOUTB, which may be configured for single-endor differential operation. IOUTA and IOUTB can be convertedinto complementary single-ended voltage outputs, VOUTA andVOUTB, via a load resistor, RLOAD, as described in the DACTransfer Function section by Equations 5 through 8. Thedifferential voltage, VDIFF, existing between VOUTA and VOUTB

can also be converted to a single-ended voltage via a transformeror differential amplifier configuration.

Figure 22 shows the equivalent analog output circuit of theAD9752 consisting of a parallel combination of PMOS differen-tial current switches associated with each segmented currentsource. The output impedance of IOUTA and IOUTB is deter-mined by the equivalent parallel combination of the PMOSswitches and is typically 100 kΩ in parallel with 5 pF. Due tothe nature of a PMOS device, the output impedance is alsoslightly dependent on the output voltage (i.e., VOUTA and VOUTB)and, to a lesser extent, the analog supply voltage, AVDD, andfull-scale current, IOUTFS. Although the output impedance’ssignal dependency can be a source of dc nonlinearity and ac linear-ity (i.e., distortion), its effects can be limited if certain precau-tions are noted.

AVDD

IOUTBIOUTA

RLOAD RLOAD

Figure 22. Equivalent Analog Output

IOUTA and IOUTB also have a negative and positive voltagecompliance range. The negative output compliance range of–1.0 V is set by the breakdown limits of the CMOS process.Operation beyond this maximum limit may result in a break-down of the output stage and affect the reliability of the AD9752.The positive output compliance range is slightly dependent onthe full-scale output current, IOUTFS. It degrades slightly from itsnominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS =2 mA. Operation beyond the positive compliance range willinduce clipping of the output signal which severely degradesthe AD9752’s linearity and distortion performance.

For applications requiring the optimum dc linearity, IOUTAand/or IOUTB should be maintained at a virtual ground via anI-V op amp configuration. Maintaining IOUTA and/or IOUTBat a virtual ground keeps the output impedance of the AD9752fixed, significantly reducing its effect on linearity. However,it does not necessarily lead to the optimum distortion perfor-mance due to limitations of the I-V op amp. Note that theINL/DNL specifications for the AD9752 are measured inthis manner using IOUTA. In addition, these dc linearityspecifications remain virtually unaffected over the specifiedpower supply range of 4.5 V to 5.5 V.

Operating the AD9752 with reduced voltage output swings atIOUTA and IOUTB in a differential or single-ended outputconfiguration reduces the signal dependency of its outputimpedance thus enhancing distortion performance. Althoughthe voltage compliance range of IOUTA and IOUTB extendsfrom –1.0 V to +1.25 V, optimum distortion performance isachieved when the maximum full-scale signal at IOUTA andIOUTB does not exceed approximately 0.5 V. A properly se-lected transformer with a grounded center-tap will allow theAD9752 to provide the required power and voltage levels todifferent loads while maintaining reduced voltage swings atIOUTA and IOUTB. DC-coupled applications requiring adifferential or single-ended output configuration should sizeRLOAD accordingly. Refer to Applying the AD9752 section forexamples of various output configurations.

The most significant improvement in the AD9752’s distortionand noise performance is realized using a differential outputconfiguration. The common-mode error sources of bothIOUTA and IOUTB can be substantially reduced by thecommon-mode rejection of a transformer or differential am-plifier. These common-mode error sources include even-order distortion products and noise. The enhancement indistortion performance becomes more significant as the recon-structed waveform’s frequency content increases and/or itsamplitude decreases.

The distortion and noise performance of the AD9752 is alsoslightly dependent on the analog and digital supply as well as thefull-scale current setting, IOUTFS. Operating the analog supply at5.0 V ensures maximum headroom for its internal PMOS currentsources and differential switches leading to improved distortionperformance. Although IOUTFS can be set between 2 mA and20 mA, selecting an IOUTFS of 20 mA will provide the best dis-tortion and noise performance also shown in Figure 8. Thenoise performance of the AD9752 is affected by the digital sup-ply (DVDD), output frequency, and increases with increasingclock rate as shown in Figure 11. Operating the AD9752 withlow voltage logic levels between 3 V and 3.3 V will slightly re-duce the amount of on-chip digital noise.

REV. 0

AD9752

–12–

In summary, the AD9752 achieves the optimum distortion andnoise performance under the following conditions:

(1) Differential Operation.

(2) Positive voltage swing at IOUTA and IOUTB limited to+0.5 V.

(3) IOUTFS set to 20 mA.

(4) Analog Supply (AVDD) set at 5.0 V.

(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-priate logic levels.

Note that the ac performance of the AD9752 is characterizedunder the above mentioned operating conditions.

DIGITAL INPUTSThe AD9752’s digital input consists of 12 data input pins and aclock input pin. The 12-bit parallel data inputs follow standardpositive binary coding where DB11 is the most significant bit(MSB) and DB0 is the least significant bit (LSB). IOUTAproduces a full-scale output current when all data bits are atLogic 1. IOUTB produces a complementary output with thefull-scale current split between the two outputs as a function ofthe input code.

The digital interface is implemented using an edge-triggeredmaster slave latch. The DAC output is updated following therising edge of the clock as shown in Figure 1 and is designed tosupport a clock rate as high as 125 MSPS. The clock can beoperated at any duty cycle that meets the specified latch pulse-width. The setup and hold times can also be varied within theclock cycle as long as the specified minimum times are met;although the location of these transition edges may affect digitalfeedthrough and distortion performance. Best performance istypically achieved when the input data transitions on the falling edgeof a 50% duty cycle clock.

The digital inputs are CMOS compatible with logic thresholds,VTHRESHOLD set to approximately half the digital positive supply(DVDD) or

VTHRESHOLD = DVDD/2 (±20%)

The internal digital circuitry of the AD9752 is capable of operatingover a digital supply range of 2.7 V to 5.5 V. As a result, thedigital inputs can also accommodate TTL levels when DVDD isset to accommodate the maximum high level voltage of the TTLdrivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensureproper compatibility with most TTL logic families. Figure 23shows the equivalent digital input circuit for the data and clockinputs. The sleep mode input is similar with the exception thatit contains an active pull-down circuit, thus ensuring that theAD9752 remains enabled if this input is left disconnected.

DVDD

DIGITALINPUT

Figure 23. Equivalent Digital Input

Since the AD9752 is capable of being updated up to 125 MSPS,the quality of the clock and data input signals are important inachieving the optimum performance. The drivers of the digital

data interface circuitry should be specified to meet the mini-mum setup and hold times of the AD9752 as well as its re-quired min/max input logic level thresholds. Typically, theselection of the slowest logic family that satisfies the above con-ditions will result in the lowest data feedthrough and noise.

Digital signal paths should be kept short and run lengthsmatched to avoid propagation delay mismatch. The insertion ofa low value resistor network (i.e., 20 Ω to 100 Ω) between theAD9752 digital inputs and driver outputs may be helpful in reduc-ing any overshooting and ringing at the digital inputs that con-tribute to data feedthrough. For longer run lengths and high dataupdate rates, strip line techniques with proper termination resis-tors should be considered to maintain “clean” digital inputs. Also,operating the AD9752 with reduced logic swings and a corre-sponding digital supply (DVDD) will also reduce data feedthrough.

The external clock driver circuitry should provide the AD9752with a low jitter clock input meeting the min/max logic levelswhile providing fast edges. Fast clock edges will help minimizeany jitter that will manifest itself as phase noise on a recon-structed waveform. Thus, the clock input should be driven bythe fastest logic family suitable for the application.

Note, the clock input could also be driven via a sine wave, which iscentered around the digital threshold (i.e., DVDD/2), and meetsthe min/max logic threshold. This will typically result in a slightdegradation in the phase noise, which becomes more noticeableat higher sampling rates and output frequencies. Also, at highersampling rates, the 20% tolerance of the digital logic thresholdshould be considered since it will affect the effective clock dutycycle and subsequently cut into the required data setup andhold times.

INPUT CLOCK/DATA TIMING RELATIONSHIPSNR in a DAC is dependent on the relationship between theposition of the clock edges and the point in time at which theinput data changes. The AD9752 is positive edge triggered, andso exhibits SNR sensitivity when the data transition is close tothis edge. In general, the goal when applying the AD9752 is tomake the data transitions shortly after the positive clock edge.This becomes more important as the sample rate increases. Figure24 shows the relationship of SNR to clock placement with dif-ferent sample rates and different frequencies out. Note that atthe lower sample rates, much more tolerance is allowed in clockplacement, while at higher rates, much more care must be taken.

TIME OF DATA CHANGE RELATIVE TORISING CLOCK EDGE – ns

68

40–8 10–6 –4 –2 0 2 4 6 8

64

60

56

52

48

SN

R –

dB

44

FS = 65MSPS

FS = 125MSPS

Figure 24. SNR vs. Clock Placement @ fOUT = 10 MHz

REV. 0

AD9752

–13–

SLEEP MODE OPERATIONThe AD9752 has a power-down function which turns off theoutput current and reduces the supply current to less than8.5 mA over the specified supply range of 2.7 V to 5.5 V andtemperature range. This mode can be activated by applying alogic level “1” to the SLEEP pin. This digital input also con-tains an active pull-down circuit that ensures the AD9752 re-mains enabled if this input is left disconnected. The AD9752takes less than 50 ns to power down and approximately 5 µs topower back up.

POWER DISSIPATIONThe power dissipation, PD, of the AD9752 is dependent onseveral factors which include: (1) AVDD and DVDD, thepower supply voltages; (2) IOUTFS, the full-scale current output;(3) fCLOCK, the update rate; (4) and the reconstructed digitalinput waveform. The power dissipation is directly proportionalto the analog supply current, IAVDD, and the digital supply cur-rent, IDVDD. IAVDD is directly proportional to IOUTFS as shown inFigure 25 and is insensitive to fCLOCK.

Conversely, IDVDD is dependent on both the digital input wave-form, fCLOCK, and digital supply DVDD. Figures 26 and 27show IDVDD as a function of full-scale sine wave output ratios(fOUT/fCLOCK) for various update rates with DVDD = 5 V andDVDD = 3 V, respectively. Note, how IDVDD is reduced by morethan a factor of 2 when DVDD is reduced from 5 V to 3 V.

IOUTFS – mA

35

52 204 6 8 10 12 14 16 18

30

25

20

15

10

I AV

DD

– m

A

Figure 25. IAVDD vs. IOUTFS

RATIO (fCLOCK/fOUT)

18

16

00.01 10.1

I DV

DD

– m

A

8

6

4

2

12

10

14

125MSPS

100MSPS

50MSPS

25MSPS

5MSPS

Figure 26. IDVDD vs. Ratio @ DVDD = 5 V

RATIO (fCLOCK/fOUT)

8

00.01 10.1

I DV

DD

– m

A

6

4

2

125MSPS

100MSPS

50MSPS

25MSPS

5MSPS

Figure 27. IDVDD vs. Ratio @ DVDD = 3 V

APPLYING THE AD9752OUTPUT CONFIGURATIONSThe following sections illustrate some typical output configura-tions for the AD9752. Unless otherwise noted, it is assumedthat IOUTFS is set to a nominal 20 mA. For applications requir-ing the optimum dynamic performance, a differential outputconfiguration is suggested. A differential output configurationmay consist of either an RF transformer or a differential op ampconfiguration. The transformer configuration provides the opti-mum high frequency performance and is recommended for anyapplication allowing for ac coupling. The differential op ampconfiguration is suitable for applications requiring dc coupling, abipolar output, signal gain and/or level shifting.

A single-ended output is suitable for applications requiring aunipolar voltage output. A positive unipolar output voltage willresult if IOUTA and/or IOUTB is connected to an appropri-ately sized load resistor, RLOAD, referred to ACOM. This con-figuration may be more suitable for a single-supply systemrequiring a dc coupled, ground referred output voltage. Alterna-tively, an amplifier could be configured as an I-V converter thusconverting IOUTA or IOUTB into a negative unipolar voltage.This configuration provides the best dc linearity since IOUTAor IOUTB is maintained at a virtual ground. Note, IOUTAprovides slightly better performance than IOUTB.

DIFFERENTIAL COUPLING USING A TRANSFORMERAn RF transformer can be used to perform a differential-to-single-ended signal conversion as shown in Figure 28. Adifferentially coupled transformer output provides the optimumdistortion performance for output signals whose spectral contentlies within the transformer’s passband. An RF transformer suchas the Mini-Circuits T1-1T provides excellent rejection ofcommon-mode distortion (i.e., even-order harmonics) and noiseover a wide frequency range. It also provides electrical isolationand the ability to deliver twice the power to the load. Trans-formers with different impedance ratios may also be used forimpedance matching purposes. Note that the transformerprovides ac coupling only.

REV. 0

AD9752

–14–

RLOADAD9752

MINI-CIRCUITST1-1T

OPTIONAL RDIFF

IOUTA

IOUTB

Figure 28. Differential Output Using a Transformer

The center tap on the primary side of the transformer must beconnected to ACOM to provide the necessary dc current pathfor both IOUTA and IOUTB. The complementary voltagesappearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB)swing symmetrically around ACOM and should be maintainedwith the specified output compliance range of the AD9752. Adifferential resistor, RDIFF, may be inserted in applications inwhich the output of the transformer is connected to the load,RLOAD, via a passive reconstruction filter or cable. RDIFF is deter-mined by the transformer’s impedance ratio and provides theproper source termination which results in a low VSWR. Notethat approximately half the signal power will be dissipated acrossRDIFF.

DIFFERENTIAL USING AN OP AMPAn op amp can also be used to perform a differential to single-ended conversion as shown in Figure 29. The AD9752 is con-figured with two equal load resistors, RLOAD, of 25 Ω. Thedifferential voltage developed across IOUTA and IOUTB isconverted to a single-ended signal via the differential op ampconfiguration. An optional capacitor can be installed acrossIOUTA and IOUTB forming a real pole in a low-pass filter.The addition of this capacitor also enhances the op amps distor-tion performance by preventing the DACs high slewing outputfrom overloading the op amp’s input.

AD9752

IOUTA

IOUTBCOPT

500V

225V

225V

500V

25V25V

AD8055

Figure 29. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typicallydetermined by the resistor matching. In this circuit, the differ-ential op amp circuit is configured to provide some additionalsignal gain. The op amp must operate off of a dual supply sinceits output is approximately ±1.0 V. A high speed amplifier suchas the AD8055 or AD9632 capable of preserving the differentialperformance of the AD9752 while meeting other system levelobjectives (i.e., cost, power) should be selected. The op ampsdifferential gain, its gain setting resistor values, and full-scaleoutput swing capabilities should all be considered when opti-mizing this circuit.

The differential circuit shown in Figure 30 provides the neces-sary level-shifting required in a single supply system. In thiscase, AVDD which is the positive analog supply for both theAD9752 and the op amp is also used to level-shift the differ-ential output of the AD9752 to midsupply (i.e., AVDD/2). TheAD8041 is a suitable op amp for this application.

AD9752

IOUTA

IOUTBCOPT

500V

225V

225V

1kV25V25V

AD8041

1kVAVDD

Figure 30. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUTFigure 31 shows the AD9752 configured to provide a unipolaroutput range of approximately 0 V to +0.5 V for a doubly termi-nated 50 Ω cable since the nominal full-scale current, IOUTFS, of20 mA flows through the equivalent RLOAD of 25 Ω. In thiscase, RLOAD represents the equivalent load resistance seen byIOUTA or IOUTB. The unused output (IOUTA or IOUTB)can be connected to ACOM directly or via a matching RLOAD.Different values of IOUTFS and RLOAD can be selected as long asthe positive compliance range is adhered to. One additionalconsideration in this mode is the integral nonlinearity (INL) asdiscussed in the ANALOG OUTPUT section of this data sheet.For optimum INL performance, the single-ended, bufferedvoltage output configuration is suggested.

AD9752IOUTA

IOUTB

50V

25V

50V

VOUTA = 0 TO +0.5VIOUTFS = 20mA

Figure 31. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUTCONFIGURATIONFigure 32 shows a buffered single-ended output configuration inwhich the op amp U1 performs an I-V conversion on the AD9752output current. U1 maintains IOUTA (or IOUTB) at a virtualground, thus minimizing the nonlinear output impedance effecton the DAC’s INL performance as discussed in the ANALOGOUTPUT section. Although this single-ended configurationtypically provides the best dc linearity performance, its ac distor-tion performance at higher DAC update rates may be limited byU1’s slewing capabilities. U1 provides a negative unipolar out-put voltage and its full-scale output voltage is simply theproduct of RFB and IOUTFS. The full-scale output should be setwithin U1’s voltage output swing capabilities by scaling IOUTFS

and/or RFB. An improvement in ac distortion performance mayresult with a reduced IOUTFS since the signal current U1 will berequired to sink will be subsequently reduced.

REV. 0

AD9752

–15–

AD9752IOUTA

IOUTB

COPT

200V

U1 VOUT = IOUTFS 3 RFB

IOUTFS = 10mA

RFB200V

Figure 32. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWERSUPPLY REJECTIONMany applications seek high speed and high performance underless than ideal operating conditions. In these circuits, the imple-mentation and construction of the printed circuit board designis as important as the circuit design. Proper RF techniques mustbe used for device selection, placement and routing as well aspower supply bypassing and grounding to ensure optimumperformance. Figures 42-47 illustrate the recommended printedcircuit board ground, power and signal plane layouts which areimplemented on the AD9752 evaluation board.

One factor that can measurably affect system performance is theability of the DAC output to reject dc variations or ac noisesuperimposed on the analog or digital dc power distribution(i.e., AVDD, DVDD). This is referred to as Power SupplyRejection Ratio (PSRR). For dc variations of the power supply,the resulting performance of the DAC directly corresponds to again error associated with the DAC’s full-scale current, IOUTFS.AC noise on the dc supplies is common in applications wherethe power distribution is generated by a switching power supply.Typically, switching power supply noise will occur over thespectrum from tens of kHz to several MHz. PSRR vs. frequencyof the AD9752 AVDD supply, over this frequency range, isgiven in Figure 33.

FREQUENCY – MHz

90

80

601.00.26

PS

RR

– d

B

0.5 0.75

70

Figure 33. Power Supply Rejection Ratio of AD9752

Note that the units in Figure 33 are given in units of (amps out)/(volts in). Noise on the analog power supply has the effect ofmodulating the internal switches, and therefore the outputcurrent. The voltage noise on the dc power, therefore, will beadded in a nonlinear manner to the desired IOUT. Due to therelative different sizes of these switches, PSRR is very code depen-dent. This can produce a mixing effect which can modulate low

frequency power supply noise to higher frequencies. Worst casePSRR for either one of the differential DAC outputs will occurwhen the full-scale current is directed towards that output. As aresult, the PSRR measurement in Figure 33 represents a worstcase condition in which the digital inputs remain static and thefull scale output current of 20 mA is directed to the DAC out-put being measured.

An example serves to illustrate the effect of supply noise on theanalog supply. Suppose a switching regulator with a switchingfrequency of 250 kHz produces 10 mV rms of noise and forsimplicity sake (i.e., ignore harmonics), all of this noise is con-centrated at 250 kHz. To calculate how much of this undesirednoise will appear as current noise super imposed on the DAC’sfull-scale current, IOUTFS, one must determine the PSRR in dBusing Figure 33 at 250 kHz. To calculate the PSRR for a givenRLOAD, such that the units of PSRR are converted from A/V toV/V, adjust the curve in Figure 33 by the scaling factor 20 × Log(RLOAD). For instance, if RLOAD is 50 Ω, the PSRR is reducedby 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB inFigure 33 becomes 40 dB VOUT/VIN).

Proper grounding and decoupling should be a primary objectivein any high speed, high resolution system. The AD9752 featuresseparate analog and digital supply and ground pins to optimizethe management of analog and digital ground currents in asystem. In general, AVDD, the analog supply, should be de-coupled to ACOM, the analog common, as close to the chip asphysically possible. Similarly, DVDD, the digital supply, shouldbe decoupled to DCOM as close as physically as possible.

For those applications that require a single +5 V or +3 V supplyfor both the analog and digital supply, a clean analog supplymay be generated using the circuit shown in Figure 34. Thecircuit consists of a differential LC filter with separate powersupply and return lines. Lower noise can be attained using lowESR type electrolytic and tantalum capacitors.

100mFELECT.

10-22mFTANT.

0.1mFCER.

TTL/CMOSLOGIC

CIRCUITS

+5V OR +3VPOWER SUPPLY

FERRITEBEADS

AVDD

ACOM

Figure 34. Differential LC Filter for Single +5 V or +3 V Applications

Maintaining low noise on power supplies and ground is criticalto obtaining optimum results from the AD9752. If properlyimplemented, ground planes can perform a host of functions onhigh speed circuit boards: bypassing, shielding, current trans-port, etc. In mixed signal design, the analog and digital portionsof the board should be distinct from each other, with the analogground plane confined to the areas covering the analog signaltraces, and the digital ground plane confined to areas coveringthe digital interconnects.

All analog ground pins of the DAC, reference and other analogcomponents should be tied directly to the analog ground plane.The two ground planes should be connected by a path 1/8to 1/4 inch wide underneath or within 1/2 inch of the DAC to

REV. 0

AD9752

–16–

maintain optimum performance. Care should be taken to ensurethat the ground plane is uninterrupted over crucial signal paths.On the digital side, this includes the digital input lines runningto the DAC as well as any clock signals. On the analog side, thisincludes the DAC output signal, reference signal and the supplyfeeders.

The use of wide runs or planes in the routing of power lines isalso recommended. This serves the dual role of providing a lowseries impedance power supply to the part, as well as providingsome “free” capacitive decoupling to the appropriate groundplane. It is essential that care be taken in the layout of signal andpower ground interconnects to avoid inducing extraneous volt-age drops in the signal ground paths. It is recommended that allconnections be short, direct and as physically close to the pack-age as possible in order to minimize the sharing of conductionpaths between different currents. When runs exceed an inch inlength, strip line techniques with proper termination resistorshould be considered. The necessity and value of this resistorwill be dependent upon the logic family used.

For a more detailed discussion of the implementation andconstruction of high speed, mixed signal printed circuit boards,refer to Analog Devices’ application notes AN-280 andAN-333.

FREQUENCY – Hz

–30

–40

–1001M600k

AM

PLI

TU

DE

– d

Bm

800k

–50

–60

–70

–80

–90

Figure 35a. Notch in Missing Bin at 750 kHz is Down >60 dB. (Peak Amplitude + 0 dBm).

FREQUENCY – MHz

–30

–40

–100

5.154.85

AM

PLI

TU

DE

– d

Bm

5

–50

–60

–70

–80

–90

–110

Figure 35b. Notch in Missing Bin at 5 MHz is Down >60 dB. (Peak Amplitude + 0 dBm).

APPLICATIONSVDSL Applications Using the AD9752Very High Frequency Digital Subscriber Line (VDSL) technol-ogy is growing rapidly in applications requiring data transferover relatively short distances. By using QAM modulation andtransmitting the data in multiple discrete tones, high data ratescan be achieved.

As with other multitone applications, each VDSL tone is ca-pable of transmitting a given number of bits, depending on thesignal-to-noise ratio (SNR) in a narrow band around that tone.The tones are evenly spaced over the range of several kHz to10 MHz. At the high frequency end of this range, performanceis generally limited by cable characteristics and environmentalfactors, such as external interferers. Performance at the lowerfrequencies is much more dependent on the performance of thecomponents in the signal chain. In addition to in-band noise,intermodulation from other tones can also potentially interferewith the recovery of data for a given tone. The two graphs inFigure 35 represent a 500 tone missing bin test vector, withfrequencies evenly spaced from 400 Hz to 10 MHz. This test isvery commonly done to determine if distortion will limit thenumber of bits which can be transmitted in a tone. The testvector has a series of missing tones around 750 kHz, which isrepresented in Figure 35a and a series of missing tones around5 MHz which is represented in Figure 35b. In both cases, thespurious free range between the transmitted tones and the emptybins is greater than 60 dB.

Using the AD9752 for Quadrature Amplitude Modulation(QAM)QAM is one of the most widely used digital modulationschemes in digital communication systems. This modulationtechnique can be found in FDM as well as spreadspectrum (i.e.,CDMA) based systems. A QAM signal is a carrier frequencythat is modulated in both amplitude (i.e., AM modulation) andphase (i.e., PM modulation). It can be generated by indepen-dently modulating two carriers of identical frequency but with a90° phase difference. This results in an in-phase (I) carrier com-ponent and a quadrature (Q) carrier component at a 90° phaseshift with respect to the I component. The I and Q componentsare then summed to provide a QAM signal at the specified car-rier frequency.

A common and traditional implementation of a QAM modu-lator is shown in Figure 36. The modulation is performed in theanalog domain in which two DACs are used to generate thebaseband I and Q components, respectively. Each component isthen typically applied to a Nyquist filter before being applied toa quadrature mixer. The matching Nyquist filters shape andlimit each component’s spectral envelope while minimizingintersymbol interference. The DAC is typically updated at theQAM symbol rate or possibly a multiple of it if an interpolatingfilter precedes the DAC. The use of an interpolating filter typi-cally eases the implementation and complexity of the analogfilter, which can be a significant contributor to mismatches ingain and phase between the two baseband channels. A quadra-ture mixer modulates the I and Q components with in-phaseand quadrature phase carrier frequency and then sums the twooutputs to provide the QAM signal.

REV. 0

AD9752

–17–

AD9752(“I DAC”)

AD9752(“Q DAC”)

IOUTA

IOUTB

QOUTA

QOUTB

DCOM

FSADJREFIO SLEEP

RSET21.9kV0.1mF

CLK

Q DATAINPUT

I DATAINPUT

DVDD

AVDD

100W

500V

100V

CFILTER

100V

CFILTER

100V

500V

500V

500V500V

500V 500V

634V

0.1mF

+5V

VPBFBBIP

BBIN

BBQP

BBQNAD8346

PHASESPLITTER

LOIP

LOIN

VOUT

500mV p-p WITHVCM=1.2V

NOTE: 500V RESISTOR NETWORK - OHMTEK ORN5000D100V RESISTOR NETWORK - TOMC1603-100D

REFLO

ACOM

REFLOAVDD

REFIO

FSADJRSET12kV

RCAL220V

U1

U2

AVDD

1.82V

LATCHES500V

DAC

DAC

+

LATCHES

Figure 37. Baseband QAM Implementation Using Two AD9752s

AD9752

0

90

AD9752

CARRIERFREQUENCY

12

12

TOMIXER

DSPOR

ASIC

NYQUISTFILTERS

QUADRATUREMODULATOR

S

Figure 36. Typical Analog QAM Architecture

In this implementation, it is much more difficult to maintainproper gain and phase matching between the I and Q channels.The circuit implementation shown in Figure 37 helps improveupon the matching and temperature stability characteristicsbetween the I and Q channels, as well as showing a path for up-conversion using the AD8346 quadrature modulator. Using asingle voltage reference derived from U1 to set the gain for boththe I and Q channels will improve the gain matching and stabil-ity. RCAL can be used to compensate for any mismatch in gainbetween the two channels. This mismatch may be attributed tothe mismatch between RSET1 and RSET2, effective load resistanceof each channel, and/or the voltage offset of the control ampli-fier in each DAC. The differential voltage outputs of U1 and U2are fed into the respective differential inputs of the AD8346 viamatching networks.

Using the same matching techniques described above, Figure 38shows an example of the AD9752 used in a W-CDMA transmit-ter application using the AD6122 CDMA 3 V transmitter IF

subsystem. The AD6122 has functions, such as external gaincontrol and low distortion characteristics, needed for the supe-rior Adjacent Channel Power (ACP) requirements of W-CDMA.

CDMACarrier Division Multiple Access, or CDMA, is an air transmit/receive scheme where the signal in the transmit path is modu-lated with a pseudorandom digital code (sometimes referred toas the spreading code). The effect of this is to spread the trans-mitted signal across a wide spectrum. Similar to a DMT wave-form, a CDMA waveform containing multiple subscribers canbe characterized as having a high peak to average ratio (i.e.,crest factor), thus demanding highly linear components in thetransmit signal path. The bandwidth of the spectrum is definedby the CDMA standard being used, and in operation is imple-mented by using a spreading code with particular characteristics.

Distortion in the transmit path can lead to power being trans-mitted out of the defined band. The ratio of power transmittedin-band to out-of-band is often referred to as Adjacent ChannelPower (ACP). This is a regulatory issue due to the possibility ofinterference with other signals being transmitted by air. Regula-tory bodies define a spectral mask outside of the transmit band,and the ACP must fall under this mask. If distortion in thetransmit path cause the ACP to be above the spectral mask,then filtering, or different component selection is needed tomeet the mask requirements.

REV. 0

AD9752

–18–

AD9752(“I DAC”)

AD9752(“Q DAC”)

IOUTA

IOUTB

QOUTA

QOUTB

DCOM

FSADJREFIO SLEEP

RSET21.9kV0.1mF

CLK

Q DATAINPUT

I DATAINPUT

DVDD

AVDD

100W

500V

100V

CFILTER

100V 500V

500V

500V500V

500V

500V

634V

+3V

IIPP

IIPN

IIQP

IIQN

AD6122

REFLO

ACOM

REFLOAVDD

REFIO

FSADJRSET12kV

RCAL220V

U1

U2

AVDD

LATCHES500V

DAC

DAC

LATCHES

100V

PHASESPLITTER42

TEMPERATURECOMPENSATION

GAINCONTROL

SCALEFACTOR

REFIN

VGAINGAINCONTROL

LOIPPLOIPN

TXOPPTXOPN

VCC VCC

Figure 38. CDMA Transmit Application Using AD9752

Figure 39 shows the AD9752 reconstructing a wideband, orW-CDMA test vector with a bandwidth of 5 MHz, centered at15.625 MHz and being sampled at 62.5 MSPS. ACP for the giventest vector is measured at 70 dB.

–20

–80

–120CENTER 16.384MHz SPAN 14.096MHz1.4096MHz

–30

–70

–90

–110

–50

–60

–100

–40

CO COCL1 CU1

Figure 39. CDMA Signal, Sampled at 65 MSPS, AdjacentChannel Power >70 dBm

It is also possible to generate a QAM signal completely in thedigital domain via a DSP or ASIC, in which case only a singleDAC of sufficient resolution and performance is required toreconstruct the QAM signal. Also available from several vendorsare Digital ASICs which implement other digital modulationschemes such as PSK and FSK. This digital implementation hasthe benefit of generating perfectly matched I and Q componentsin terms of gain and phase, which is essential in maintainingoptimum performance in a communication system. In this imple-mentation, the reconstruction DAC must be operating at asufficiently high clock rate to accommodate the highest specified

QAM carrier frequency. Figure 40 shows a block diagram ofsuch an implementation using the AD9752.

50VAD9752LPF

50V

TOMIXER

STEL-1130QAM

12COS

12SIN

12

12I DATA

Q DATA

12CARRIERFREQUENCY

12

STEL-1177NCO

CLOCK

Figure 40. Digital QAM Architecture

AD9752 EVALUATION BOARDGeneral DescriptionThe AD9752-EB is an evaluation board for the AD9752 12-bitD/A converter. Careful attention to layout and circuit designcombined with a prototyping area allow the user to easily andeffectively evaluate the AD9752 in any application where highresolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9752in various configurations. Possible output configurations includetransformer coupled, resistor terminated, inverting/noninvertingand differential amplifier outputs. The digital inputs are designedto be driven directly from various word generators, with theon-board option to add a resistor network for proper loadtermination. Provisions are also made to operate the AD9752with either the internal or external reference, or to exercise thepower-down feature.

Refer to the application note AN-420 for a thorough descriptionand operating instructions for the AD9752 evaluation board.

REV. 0

AD9752

–19–

109

87

65

43

2

1

R4

109

87

65

43

2

1

R7

DV

DD

109

87

65

43

2

1

R3

109

87

65

43

2

1 DV

DD

R6

2 4 6 810 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

P1

109

87

65

43

2

1

R5

DV

DD

109

87

65

43

2

1

R1

16 15 14 13 12 11 109

1 2 3 4 5 6 7 8

C19

C1

C2

C25

C26

C27

C28

C29

16 P

IND

IPR

ES

PK 16 15 14 13 12 11 10

1 2 3 4 5 6 7

C30

C31

C32

C33

C34

C35

C36

16 P

IND

IPR

ES

PK

1 2 3 4 5 6 7 8 910 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

DB

13D

B12

DB

11D

B10

DB

9D

B8

DB

7D

B6

DB

5D

B4

DB

3D

B2

DB

1D

B0

CLO

CK

DV

DD

DC

OM

NC

AV

DD

CO

MP

2IO

UT

AIO

UT

BA

CO

MC

OM

P1

FS

AD

JR

EF

IOR

EF

LOS

LEE

P

U1

AD

975x

AV

DD

CT

1

A1

A

R15

49.9

V

CLK

JP1

AB 3

21

J1T

P1

EX

TC

LK

C7

1mF

C8

0.1m

F

AV

DD

A

C9

0.1m

F

TP

8

2

AV

DD

TP

11

C11

0.1m

F

TP

10T

P9

R16

2kV TP

14

JP4

C10

0.1m

F

OU

T 1

OU

T 2

TP

13

R17

49.9

V

PD

INJ2

AA

AA

VD

D

3JP

2

TP

12

TP

7

AC

610

mF

AV

CC

B6

TP

6

AC

510

mF

AV

EE

B5

TP

19

A

AG

ND

B4 TP

18

TP

5C

410

mF

TP

4

AV

DD

B3

TP

2

DG

ND

B2

C3

10m

F

TP

3

DV

DD

B1

R20

49.9

V

J3

C12

22pF

AA

R14 0

A

4 5 6

13

T1

J7

R38

49.9

V

J4 AA

JP6A

JP6B

A

R13

OP

EN

C13

22pF

C20 0

R12

OP

EN

A

B A

JP7B

B A

JP7A

R10

1kV

B A

JP8

R9

1kV

A B

A

R35

1kV

JP9

R18

1kV

A

37

6

24

AD

8047

C21

0.1m

F

A

C22

1mF

R36

1kV C

230.

1mF

A

C24

1mF

AV

EE

AV

CC

R37

49.9

V

J6 A

37

6

24

12

3

JP5

C15

0.1m

F

A

AV

EE

R46

1kV

C17

0.1m

F

A123

JP3

AB

AV

CC

A

CW

R43

5kV

R45

1kV

C14

1mF

A

R44

50V

EX

TR

EF

INJ5 A

R42

1kV

C16

1mF

A

AV

CC

C18

0.1m

F

U7

62

4A

VIN

VO

UT

GN

D

RE

F43

98

76

54

32

1

R2

10

A

109

87

65

43

2

1 DV

DD

R8

U6

A

AD

8047

OU

T2

OU

T1

U4

Figure 41. Evaluation Board Schematic

REV. 0

AD9752

–20–

Figure 42. Silkscreen Layer—Top

Figure 43. Component Side PCB Layout (Layer 1)

REV. 0

AD9752

–21–

Figure 44. Ground Plane PCB Layout (Layer 2)

Figure 45. Power Plane PCB Layout (Layer 3)

REV. 0

AD9752

–22–

Figure 46. Solder Side PCB Layout (Layer 4)

Figure 47. Silkscreen Layer—Bottom

REV. 0

AD9752

–23–

28-Lead, 300 Mil SOIC(R-28)

SEATINGPLANE

0.0118 (0.30)0.0040 (0.10)

0.0192 (0.49)0.0138 (0.35)

0.1043 (2.65)0.0926 (2.35)

0.0500(1.27)BSC

0.0125 (0.32)0.0091 (0.23)

0.0500 (1.27)0.0157 (0.40)

8808

0.0291 (0.74)0.0098 (0.25) 3 458

0.7125 (18.10)0.6969 (17.70)

0.4193 (10.65)0.3937 (10.00)

0.2992 (7.60)0.2914 (7.40)

PIN 1

28 15

141

28-Lead TSSOP(RU-28)

28 15

141

0.386 (9.80)0.378 (9.60)

0.25

6 (6

.50)

0.24

6 (6

.25)

0.17

7 (4

.50)

0.16

9 (4

.30)

PIN 1

SEATINGPLANE

0.006 (0.15)0.002 (0.05)

0.0118 (0.30)0.0075 (0.19)

0.0256 (0.65)BSC

0.0433(1.10)MAX

0.0079 (0.20)0.0035 (0.090)

0.028 (0.70)0.020 (0.50)

8808

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

C33

32–8

–1/9

9P

RIN

TE

D IN

U.S

.A.