A 1.248 Gb/s – 2.918 Gb/s Low-Power Receiver for MIPI ...jsts.org/html/journal/journal_files/2015/08/Year2015Volume15_04_10.pdf · 508 SANG-YUN KIM et al : A 1.248 GB/S – 2.918

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.4, AUGUST, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2015.15.4.506 ISSN(Online) 2233-4866

Manuscript received May. 29, 2015; accepted Aug. 4, 2015 College of Information and Communication Engineering, Sungkyunkwan University E-mail : [email protected]

A 1.248 Gb/s – 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital

Frequency Detection Loop in 0.11 μm CMOS

Sang-Yun Kim, Juri Lee, Hyung-Gu Park, Young Gun Pu, Jae Yong Lee, and Kang-Yoon Lee†

Abstract—This paper presents a 1.248 Gb/s – 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is 0.01 μs the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 600 μm x 250 μm. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are 35.24 psp-p and 4.25 psrms respectively for HS-G2 mode. Index Terms—MIPI-DigRF M-PHY, low-power, clock and data recovery (CDR), fully digital frequency detection loop, fast phase tracking loop, bandwidth switching

I. INTRODUCTION

As the demand for next generation mobile devices and

their design complexity increases, many mobile applications are adopting the common physical layer (PHY). This makes it possible to meet the requirements of complicated next generation mobile systems. Since various high-speed interfaces [1-3] are required for camera and video applications, the design requirements can be relaxed and the use of the common high-speed interface can reduce the development time for complicated mobile systems. MIPI-DigRF M-PHY is the one of the most popular common high-speed interface standards for many applications in the mobile area.

M-PHY serial links have been developed for a broad range of applications such as in displays, cameras and mobiles. In this case, the system to be introduced is targeted at mobile applications. The data rate of M-PHY for mobile is up to 5.80 Gb/s (1.45/2.90/5.80 Gb/s). The MIPI-DigRF M-PHY can provide high bandwidth with low power consumption using only a small number of pins making it ideal for many mobile applications. Common high-speed interfaces, such as MIPI-DigRF M-PHY need to provide interoperability at the interface level between different integrated circuits. Also, it can support many variables at the system design level and can be expanded to other systems efficiently. MIPI-DigRF M-PHY is composed of a digital controller block and analog block. The digital controller controls the overall operation of the M-PHY communicating with the protocol layer. At the analog receiver side, serial data from the other M-PHYs is deserialized to be transferred to the protocol layer. Low power consumption is one of the key features of MIPI-DigRF M-PHY since it operates using battery power.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.4, AUGUST, 2015 507

Table 1 summarizes the specification of MIPI-DigRF M-PHY. The MIPI-DigRF M-PHY supports three different interface modes: low speed mode and high speed mode. It should support different interface data rates according to the interface mode and clocks of 26 MHz, 38.4 MHz and 52 MHz.

The MIPI-DigRF M-PHY should be operated in 3 symbol interval (SI) training time which is very short compared with other interfaces such as display port [4-7]. The length of the SYNC pattern is 3 SI (= 30 UI (unit intervals)), which is 0.01 μs in HS-G2B mode. Due to this short SYNC pattern, clock and data recovery (CDR) in the receiver should have an extremely fast locking time [8, 9].

This paper presents, a low-power receiver for MIPI-DigRF M-PHY with a wide data rate of 1.248 Gb/s – 2.918 Gb/s.

Section II describes the receiver architecture. Section III discusses the building blocks of the receiver. Section IV shows the experimental results while Section V summarizes the paper.

II. MIPI-DIGRF M-PHY RECEIVER

ARCHITECTURE

Fig. 1 shows the block diagram of the low-power receiver for MIPI-DigRF M-PHY. The receiver transfer the data between the protocol side and line side. The MIPI-DigRF M-PHY communicates 8-bit data with the protocol layer in different gears and rates based on the control signals (HSGEAR<1:0> and HSRATE<1:0>) from the protocol layer. The MIPI-DigRF M-PHY has two gear modes, G1/G2 and two rate modes, A/B, leading to four operating modes.

The receiver is composed of the Rx control & data interface, comma detector, HS deserializer, LS deserializer, CDR, and input buffer. It recovers the clock and data based on serial data from the line side. The recovered data from the CDR is deserialized into 10-bit parallel data. A comma detector should detect comma data, or SYNC patterns, from the data which is the output from the deserializer [10, 11]. The first real data from the transmitter cannot be identified from the output of the

Table 1. Specification of MIPI-DigRF M-PHY

Interface Mode Mnemonic Reference Frequency (MHz) Interface Data Rate (Mbps) Low Speed LS Mode (SYS-BURST) 26 / 38.4 / 52 26 / 38.4 / 52

HS-G1A 26 / 38.4 / 52 1248 26 / 52 1456 High Speed 1x HS-G1x

(HS-BURST1) HS-G1B 38.4 1459.2

HS-G2A 26 / 38.4 / 52 2496 26 / 52 2912 High Speed 2x HS-G2x

(HS-BURST2) HS-G2B 38.4 2918.4

Length of SYNC Pattern 0 to 5 SI (default length of 3 SI) (1 SI (Symbol Interval) = 10 UI (Unit Interval))

Time for Gear/Rate Change 10 μs

CDR

RxFSM

RxControl & Data

Interface

INPUTBUFFER Rx_DN

Rx_DPHS

DeserializerCommaDetector

LSDeserializer

HSDataP

HSDataN

LS_DataP

LS_DataN

Data10

FSMState

RX_Symbol

Rx_SymbolClk

Line

Sid

e

Prot

ocol

Sid

e

Data10

REF_CLK

8

Receiver

Data_ST

Fig. 1. Top block diagram of the receiver for MIPI-DigRF M-PHY.

508 SANG-YUN KIM et al : A 1.248 GB/S – 2.918 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING …

deserializer. Therefore, it is necessary to detect the SYNC patterns at the comma detector, in this way 10-bit real data can be recovered correctly according to the detected SYNC pattern. 10-bit parallel data is decoded to 8-bit parallel data by the Rx control and data interface and transferred to the protocol layer.

Fig. 2 is the timing diagram of the receiver for MIPI-DigRF M-PHY. The data from the protocol layer includes real data and control bits as well as control information for states of the finite state machine (FSM). The DIF_N signal is the initial value of RX_DP/DN. PREPARE and SYNC are transferred before the control bits and real data, these are used to initialize the analog blocks of MIPI-DigRF M-PHY. The SYNC pattern is used for clock recovery before data transmission. After the SYNC pattern, the start (ST) signal of the symbols from the transmitter is received. Then, control bits and real data are transferred.

On the receiver side, control signals and real data sent from the transmitter are received through the transmission line. The internal symbol clock (Rx_SymbolClk) is generated and the Rx_Burst signal becomes high when the SYNC patterns are sent from the transmitter. Control signals and real data are sent from the transmitter and are recovered by the CDR. The recovered control signals and real data are used by the RX_FSM in the receiver to provide 8-bit data, Rx_Symbol<7:0>, to the protocol side.

III. BUILDING BLOCKS

1. Clock and Data Recovery The CDR circuit is an important block for optical and

electrical communications [12]. It is used to recover and retime the required clock from data. However, it is still a very challenging task to design high speed and low power CDRs.

The phase detector (PD) is a critical block in the unit as it limits the performance of the CDR’s speed. The speed performance of the CMOS is limited when compared to other high-speed technologies such as SiGe. Lowering the clock frequency relaxes the speed limit imposed by the CMOS. In this work, a quarter-rate PD is used to mitigate the operating speed of the PD in the CDR circuit. The main disadvantage of a lower-rate linear PD is that its complexity increases when the rate decreases. This will involve additional circuits such as a clock tree to compensate for the delay time and result in higher power consumption. Also, a large number of outputs would require more charge pump (CP) blocks, which may lead to severe current mismatches in the CP circuits. As the circuit structure of the quarter-rate PD is still very complex, this paper focuses on minimizing the complexity and output signals of the linear PD in the quarter-rate design without compromising good performance and low power consumption.

Fig. 3 shows the block diagram of the proposed CDR circuit. It employs a dual-loop CDR architecture with a frequency detection loop and a phase tracking loop which help to prevent false locking. The phase tracking loop is composed of a quarter-rate PD, four CPs, a second order loop filter, bandwidth (BW) switching control block, a quadrature voltage controlled oscillator (VCO) and data recovery circuit.

The SYNC pattern time of the MIPI-DigRF M-PHY is 3 SI, which is very short compared with other interfaces. Therefore, CDR has to lock the frequency and phase very quickly in a 3 SI SYNC pattern. When the loop bandwidth of the CDR is increased, the locking time is reduced. Unfortunately, the wide bandwidth allows noise sources to be translated into output jitter. It is important that the CDR has good output jitter performance after locking.

To meet the jitter specification and locking time of the CDR, a CDR using a bandwidth switching method is

PREPARE SYNC TOBDIF_NRX_DP/DN

Rx_Burst

Rx_SymbolClk

Rx_Symbol<7:0> ST Control Bits Control BitsDATA

Control Bits Control BitsDATA

Fig. 2. Timing diagram of receiver for MIPI-DigRF M-PHY.


proposed. The bandwidth switching method is to widen the loop bandwidth during the locking operation of the CDR, and to narrow the loop bandwidth after the locking operation.

Initially, the bandwidth of CDR circuit is set to be wide for the fast phase locking time. After the SYNC pattern, the bandwidth is switched to have a narrow value for the stable phase locking operation by changing the charge pump current, capacitor values and resistor values in the loop filter.

The bandwidth of the CDR with a second order loop filter can be written as follows:

2CP VCO z z

cz p

I K R CN C Cp

× ×w = ×

+ (1)

The ωC, KVCO, N, and ICP are bandwidth of CDR, VCO

gain, division ratio, and CP current, respectively. Also, RZ, CZ and CP are the resistors and capacitors of the second order loop filter. In Eq. (1), the bandwidth is determined by the parameters of the second order loop filter.

In Fig. 3, SW1, SW2, and SW3 are turned on when the control signal (BW_SW or BW_SWB) is VDD, which is high. On the other hand, they are turned off when the control signal (BW_SW or BW_SWB) is GND, which is low. The BW_SWB signal has an inverse relationship with the BW_SW signal. When the BW_SW is low, SW1 and SW2 are turned off. Simultaneously, SW3 is turned on because BW_SWB is high. Then, CP, CZ and RZ of the second order loop filter become C1, C3 and R1, respectively. This is the high bandwidth mode. On the

other hand, when the BW_SW signal is high, SW1 and SW2 are turned on and SW3 is turned off. Therefore, the values of CP, CZ and RZ are changed to C1+C2, C3+C4, and R1 + R2. This is the low bandwidth mode. Initially the BW_SW signal is low, and it becomes high after a 3 SI training pattern.

If only the capacitor and the resistor are changed for the bandwidth switching, there will be a stability problem. In this paper, the CP current, ICP, is also controlled when the bandwidth is switched. As a result, size variation of the capacitor and resistor can be reduced.

In this paper, the CDR locks the frequency and phase at a bandwidth of 50 MHz in the high bandwidth mode. Subsequently, the bandwidth is switched to 10 MHz, which is the low bandwidth mode. The loop parameters of each bandwidth mode are summarized in Table 2.

Fig. 4 shows the timing diagram of the frequency detection loop and phase tracking loop. Firstly, in the frequency detection loop, the CDR detects the target frequency that needs to be recovered before the SYNC pattern data is applied. The frequency detection loop is a digital block. It detects the target frequency by controlling FCONT<M:0> and CAP_CON<K:0>.

The FREQ_LOCK signal becomes high when the frequency detection loop process is finished. Subsequently, the phase tracking loop detects the phase using the SYNC pattern input. The phase tracking loop is composed of the PD, CP and loop filter. In order to

FrequencyDetection

Block

1/4 rate PD

CPUP0

DN0

BW Switching Control Block

2nd orderLoop Filter

~

Deserializer

R_Data<3:0>

4-Phase Recovered

clockData

Data

REF_CLK

BW_SW,BW_SWBUP1

DN1UP2

DN2UP3

DN3

CP

CP

CP

4-Phase Recovered clock

(CK0 - CK3)FCONT<M:0>,

CAP_CON<K:0>

CP

DATA_ST

VCTRL

CZ

C1

R1

C2R2

C4C3

BW_ SW

BW_ SWB

BW_SW RZ

SW1

SW2

SW3

Fig. 3. Quarter-Rate CDR architecture with full digital frequency detection.

Table 2. Loop Parameters of the CDR

Parameters BW =50 MHz

BW =10 MHz Units

ICP 1 0.1 mA CP 1.25 3.13 pF RZ 654 1308 ohm CZ 19.13 45.33 pF

VCO_DIVK

REF_CLK

RST_CNT

COM_CLK

CAP_CON<K:0> 10…

DEN_CLK

EN_CNT

FREQ_LOCK

DATA PREPARE SYNC(3SI)

BW_SW

11...

Frequency Detection Loop Phase Tracking Loop

Data_ST

...01FCONT<M:0>

Data

BW_SWB

Fig. 4. Timing diagram of the frequency detection loop and phase tracking loop.


overcome the disadvantages of a conventional linear PD, a quarter-rate PD is adopted. The operating speed of each PD can be reduced by a factor of four.

After the SYNC pattern is applied, the Rx controller creates a Data_ST signal which starts the real data being transmitted. When the Data_ST signal becomes high, the CDR bandwidth is switched and BW_SW becomes high

Fig. 5(a) shows the block diagram of the frequency detection loop. The frequency detection loop works with the reference clock signal (REF_CLK) to generate RST_CNT, EN_CNT, DEN_CLK, and COM_CLK signals.

In the fully digital frequency detection loop, the N-bit counter is used to estimate the period of the VCO frequency which results in VCO_CNT<N:0>. Then VCO_CNT<N:0> is compared to the reference counting value, COMP_REF<N:0> which is generated from the mapping table. At each stage, the frequency control signal (FCONT<M:0>, CAP_CON<K:0>) is determined digitally based on the comparison result. After frequency calibration, the control voltage of VCO is adjusted to fine-tune the phase of the VCO.

Fig. 5(b) shows the timing diagram of the frequency detection loop. The N-bit counter is periodically reset by the RST_CNT signal. This counting operation is masked by the EN_CNT signal. The N-bit counter is enabled only when EN_CNT is high. When the output of the counter is smaller than the reference counting value, COMP_REF<N:0>, the UP signal is asserted at the rising edge of COM_CLK to increase the frequency of the VCO. The UP/DOWN signals are used to decide the frequency control signals in the frequency detection loop.

The tuning controller in the frequency detection loop determines the current FCONT<M:0>, and the capacitances, CAP_CON<K:0>. FCONT<M:0> is the MSB control bits of VCO and is the VCO frequency coarse control signal. After FCONT<M:0> controls the VCO frequency coarsely, the VCO frequency is controlled finely by CAP_CONT<K:0> signals.

Fig. 6(a) shows the block diagram of a quarter-rate phase detector. It consists of four latches, two AND gates and two exclusive-OR (XOR) gates. The data is latched by four phase clocks (CK0-CK3) and each latch output D0, D1, Q0 and Q1, respectively. D0/D1 and Q0/Q1 pass through the XOR gate and AND gate and give UP0 and DN0, respectively. At this time, UP0 and DN0 are

generated with CK2 and CK1. To compensate for the demerits of conventional linear and nonlinear phase

VCO

/2 N-bit Counter

Reference Divider

DigitalComparator

UP/DN

MSK

_CNT

VCO-CNT<N:0>

~REF_CLK

TuningController

FCONT<M:0>, CAP_CONT<K:0>

COM_CLK

RST

_CNT

VCO/2VCO_OUT

DEN_CLKCOMP_REF<N:0>

VCTRL

VoltageGenerator

Coarse_Lock

EXT_REF<N:0>

MappingTable

MUX

REF_DIV<N:0>

EXT_COMP_EN

INT_REF<N:0>

Freq_Sel

VCO_OUTB

REF_SEL<1:0>

(a)

REF_CLK

COM_CLK

EN_CNT

VCO_DIVK

DEN_CLK

RST_CNT

FCONT<M:0> ...10 ...11

CAP_CON<K:0> 10... 10... 11...

(b)

Fig. 5. (a) Block diagram of fully digital frequency detection,(b) Timing diagram of frequency detection loop.

D LatchD

CLK

Q

QB

D LatchD

CLK

Q

QB

D LatchD

CLK

Q

QB

D LatchD

CLK

Q

QB

Data

CK3

CK0

CK1

CK0

CK2UP0

Q0

Q1

D0

D1

Data

CK2

DN0

(a)

0 1 2 43 5 6 7Data

CK0

CK1

CK2

CK3

8 9 10

Q0 -1 1 2 3 5 6 7 9 10

0 3 4 8 10Q1 2 6 7

UP0

D0 3 7

D1 4 8

DN0

(b)

Fig. 6. (a) Block diagram of quarter-rate phase detector, (b) timing diagram of the phase tracking loop.


detectors, a quarter-rate phase detector is used for linear output and a wide output signal width at high frequency.

Since this can also reduce the burden of designing a phase tracking loop, the quarter-rate phase detector offers highly reliable operation at high frequencies. Fig. 6(b) shows the timing diagram of the phase tracking loop. UP0 and DN0 signals are generated based on the four phase clocks, CK0 – CK3. Q0 and Q1 are outputs of the latches which are latched by CK2 and CK3, respectively. These two signals pass through the XOR gate and AND gate with CK0. Therefore, the UP0 signal becomes high when Q0 and Q1 are different from each other while CK0 is high. As shown in Fig. 6(b), when the phase is locked, the UP0 signal becomes high for three quarters of the pulse width of CK0. If the VCO frequency is faster than the data rate, the time when Q0 and Q1 are different decreases while CK0 is high which leads the duration where UP0 is high is decreased. On the other hand, when the VCO frequency is slower than the data rate, the time when Q0 and Q1 are different increases while CK0 is high, so the time when UP0 is high increases.

D0 and D1 signals pass through an XOR gate and the outputs of the XOR gate and CK2 pass through an AND gate which leads to the output DN0. Therefore, the DN0 signal is high when the D0 signal is different from D1 while CK2 is high. D0 and D1 are the latch outputs latched by CK0, CK1, respectively, using Q0 and Q1 that are latched by CK2, CK3, respectively. As a result, D0 and D1 signals are always different from the other. Consequently, when CK2 is high, the DN0 signal is always high regardless of the phase difference between the VCO clock and the input data.

As mentioned above, the time when UP0 is high can be changed according to the phase difference between the data rate and the VCO frequency, while the DN0 signal is fixed. The PD is operated by the variation of the high duration of the UP0 signal. For example, when the VCO frequency is faster than the data rate, the high time of the UP0 signal decreases. Then, the UP current, which is generated by the charge pump is decreased and VCTRL is also decreased through the loop filter. As a result, the VCO frequency decreases. On the other hand, the VCO frequency is increased when the high time of UP0 increases.

When the phase locking process of the CDR is complete, the pulse width ratio of the UP0 and DN0 is

determined to be 1.5:2. If the charging and discharging current ratio of the charge pump is 2:1.5, the net charge from the charge pump will be zero.

2. Voltage Controlled Oscillator

Generally, the VCO gain of ring-type VCOs [13, 14] is

designed to be large since its frequency is very sensitive to process, voltage and, temperature (PVT) variations. However, if the VCO gain is too large, the jitter specification cannot be satisfied. As shown in Fig. 7(a), if the VCO gain is large, it is possible to cover the overall frequency range using the K+1 capacitors. However, As shown in Fig. 7(b), if the VCO gain is small to reduce jitter performance, it is impossible to cover the overall frequency range using the same K+1 capacitors. Therefore, to cover the overall frequency range with a small VCO gain, a great number of VCO curves should be implemented using current arrays and capacitor arrays. Also, the resolution of the frequency detection loop

Frequency

V_CTRL0 VDD

CAP_CONT<N:0>=All 0

CAP_CONT<N:0>=All 1

Slope=KVCO=2*A MHz/V

VDD/2

Fmin

Fmax

Overall Frequency Range

(a)

V_CTRL0 VDD

Fmin

Fmax

CAP_CONT<N:0>=All 0

CAP_CONT<N:0>=All 1

Overall Frequency Range

Slope=KVCO=A MHz/V

VDD/2

Frequency

FCONT<M:0>=All 0

FCONT<M:0>=All 1

K+1 Cap Frequency Range

(b)

Fig. 7. The tuning curve of (a) high gain VCO, (b) low gain VCO.


needs to be as small as possible since the nominal duration of the SYNC pattern during the phase tracking is 3 SI. As the accuracy of the frequency detection loop is increased, the time for phase tracking will be reduced.

In this paper, the VCO frequency is controlled by the current control signal (FCONT<M:0>) and capacitor control signal (CAP_CON<N:0>). In this way, the VCO can compensate for PVT variation even if the VCO has low gain. The jitter performance of the VCO is also improved due to the low VCO gain.

The ring-type VCO shown in Fig. 8(a) is composed of four differential delay cells with dual inputs. Fig. 8(b) shows the delay cell of the VCO. The frequency control

signals, FCONT<N:0> and CAP_CON<N:0>, are used to calibrate the frequency. The tuning controller in the frequency detection loop determines a current according to the FCONT<N:0>, and a capacitance according to the CAP_CON<N:0>.

FCONT<N:0> and CAP_CON<N:0> are controlled by the frequency detection loop. FCONT<N:0> as the MSB controls the frequency coarsely. When using the capacitor to control frequency coarsely, its size becomes extremely large due to the large capacitor size. To prevent this problem, a current control technique is proposed to control the frequency. By controlling current with the control signal FCONT<N:0> to change the frequency, the size due to the large capacitors can be reduced. After detecting the frequency coarsely with FCONT<N:0>, fine tuning with CAP_CON<N:0> can be performed to detect the frequency accurately.

Dual mode VCO is implemented to support the HS-G1 and HS-G2 mode by just controlling the tail current tuning bit, MODE_SEL, as shown in Fig. 8(b). When MODE_SEL is ‘0’, the output frequency of the VCO corresponds to the HS-G1 mode. On the other hand, the output frequency of the VCO corresponds to the HS-G2 mode with a larger tail current compared to the HS-G1 mode. The area and power consumption can be minimized with the dual mode VCO.

Fig. 8(c) shows the tuning curve of the VCO. Capacitor arrays are used to implement the dual mode wide tuning range which makes the overall frequency tuning range 2.61 GHz. The VCO gain (KVCO) is 100 MHz/V.

3. Deserializer

Fig. 9(a) shows the block diagram of the deserializer.

Since the MIPI-DigRF LINK layer takes parallel data from the MIPI-DigRF M-PHY in 10-bit unit, the 4-bit recovered data (R_DATA<3:0>) from the quarter-rate CDR need to be converted to 10-bits by the deserializer.

The D flip-flop arrays in the deserializer synchronize the R_DATA<3:0> by the phase detectors in the quarter-rate CDR with the recovered clock (R_CLK). The 10-bit deserialized data is transferred to the Rx control and Data Interface.

Fig. 9(b) shows the timing diagram of the deserializer. The serial data from the phase detectors are stored in the

VIN2VIN1

VIN1BVIN2B

OUTBOUT

VCTRLCAP_CON

<K:0>FCONT<M:0>

2nd orderLoop Filter

Frequency DetectionBlock

VIN2VIN1

VIN1BVIN2B

OUTBOUT

VIN2VIN1

VIN1BVIN2B

OUTBOUT

VIN2VIN1

VIN1BVIN2B

OUTBOUT

CK0

CK2

CK1

CK3

(a)

FCONT<M:0>

VIN2B

OUTOUTB

VIN1 VIN1B

VIN2

VDD

VCTRL

M1 M2

M3 M4

M5 M6

M7 M8

CAP_CON<K:0>CAP_CON<K:0>

MODE_SEL

(b)

1st Coarse Tuning (Wide-Frequency Range Tuning)

FCONT is determined.

2nd Coarse Tuning(Fine-Frequency Range Tuning)

CAP_CON<K:0> is determined.

FCONT

“0”

“1”

Wide-TuningRange

CAP_CON<N:0>Fine-TuningRange

Center Frequency

FCONT<M:0>

Frequency

Frequency

(c)

Fig. 8. (a) Voltage controlled oscillator, (b) delay cell, (c) the tuning curve of the VCO.


12 D flip-flops (Q0 – Q11) as 12-bit parallel data, which is converted into final 10-bit parallel data at the following MUX and D flip-flops by sampling them with CLK_M.

4. Comma Detector

Fig. 10(a) shows the block diagram of the comma

detector. It is composed of two 10-bit registers, 10 comma detect blocks (CDBs), a 10-register and 10-input OR gate. As mentioned above, the comma detector is used to recover 10-bit real data correctly according to the detected SYNC pattern. The comma detector detects word boundaries from the 10-bit parallel data converted by the deserializer. Aligned data from this word boundary is connected to the 10B/8B decoder input.

Fig. 10(b) shows the detailed block diagram of the CDB. The 10-bit parallel data from the deserializer is

saved in two 10-bit registers and that saved 20-bit piece of data becomes the input to the comma detection block. The CDB searches the 10-bit data that includes comma signals, then determines the word boundary, and sends the information about any word boundaries to the word align block (WAB).

The WAB generates the final 10 parallel pieces of data based on the information from the CDB.

IV. EXPERIMENTAL RESULTS

This chip was made with in a 0.11 mm CMOS process. Fig. 11 shows the chip layout of the analog front end of the receiver. The die area is 0.15 mm2.

Fig. 12 shows the simulation results when the CDR

D Q D Q D Q

D Q D Q D Q

D Q D Q D Q

D Q D Q D Q

Q0 Q4

Q8

Q1 Q5 Q9

Q2 Q6 Q10

Q3 Q17 Q11

MUX D QQ10

MODE

DOUT<0>

Q9

MUX D QQ11

MODE

DOUT<1>

Q10

MUX D QQ4

MODE

DOUT<2>

Q1MUX D QQ3

MODE

DOUT<9>

CLK_MQ8

Save Recovered Data

R_DATA<0>

R_DATA<1>

R_DATA<2>

R_DATA<3>

R_CLK

Deserializing

(a)

0

0 1 2 43 5 6 7DATA

R_DATA<0>

8 9 10

R_CLK

11 12 13 1514 16 17 18 19 20 21

4 8 12 16 20 24

1 5 9 13 17 21

2 6 10 14 18 22

3 7 11 15 19 23

R_DATA<1>

R_DATA<2>

R_DATA<3>

0 4 8 12 16 20

1 5 9 13 17 21

2 6 10 14 18 22

3 7 11 15 19 23

Q0

Q1

Q2

Q3

0 4 8 12 16

1 5 9 13 17

2 6 10 14 18

3 7 11 15 19

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

0 4 8 12

1 5 9 13

2 6 10 14

3 7 11 15

22 23 24 25 26

CLK_M

MODE

(b)

Fig. 9. (a) Block diagram, (b) timing diagram of deserializer.

CDB9

CDB1CDB0

[9:0]19

OR

Reg

RegReg

[18:9]

sel[9:0]

Trigger

(a)

010111

Comma Detecting

sel[9:0]10

1100

[19:0]

d[19:0]

sel[5]

d15 d6

OUT d[15:6]

OUT sel

WordAllign Block

d11d10

d6

d1d0

10

(b)

Fig. 10. (a) Comma detector circuit, (b) comma detection block.

250 µm

600 µm

Receiver

Rx Control & Data

Interface

Rx FSM

CDR

CommaDetector

HSDeserializer

LSDeserializer

INPUTBUFFER

Fig. 11. The chip layout.


using a switched loop bandwidth for the HS-G2A modes. Before the SYNC pattern is applied, a full digital frequency detection loop detects the clock frequency to recover the data rate which is faster than 10 ms. After frequency detection, when the SYNC pattern is applied, a phase tracking loop locks the phase using 50 MHz high bandwidth, then lowers the BW to 10 MHz which enhances the stability of the CDR phase tracking loop.

The data rate is 2.496 Gb/s using a 4-phase clock of 624 MHz. When the 3 SI SYNC pattern is applied, the wide BW allows a fast locking time with BW switching, and the BW becomes narrower for high stability.

Rx full operation is determined by the FSM state of the Rx controller. Before the data is applied, all blocks in the Rx are in a STALL state that is the standby status for the HS mode, and then when the prepare signal is applied from transmitter, the blocks are changed to the HS-burst state for the transmission of the control signal and data. By using serial data from the transmitter, the CDR recovers the clock and data. The recovered data is converted to parallel data by the deserializer, and then transmitted to the protocol side through the digital controller. Fig. 13 shows the simulation results of the recovering process as mentioned above.

Fig. 14 shows the test board for the MIPI-DigRF M-PHY receiver chip measurement. The test board was made to apply control signals from external ports to verify the performance of the digital controller and analog block.

Fig. 15 shows the measured frequency settling transients of the CDR for the HS-G2A mode. When the FD loop is completed, the frequency of the VCO will be within the range of the specified frequency. The CDR

starts from the tuned frequency set by the FD Loop and locks to the target frequency when the SYNC pattern is applied. After the FD loop and 3 SI of SYNC pattern is applied, the frequency locks to 624 MHz. The lock time of the CDR is less than 20 ns.

Fig. 16 shows the measured data eye diagram of the

1.1

0

1.1

0

0.40.5

0.6

20n0

0000000000 1010101011 0101010101

DOUT<9:0>

DATA

VCTRL

Volta

ge (V

)

Time (s)30n 40n 50n

D10.5 Sync Pattern(3SI)

BW_SW

Bandwidth Switching

2.496 Gbps

Fig. 12. Simulation result of clock and data recovery for HS-G2A mode.

Volta

ge (V

)

Time (s)

1.1

0

0

1.1

50n 100n 150n 200n

0.30.60.9 VCTRL

1.1

0

10b COMMA DETECTOR OUT

8b_RX_Symbol

SERIALIZER OUT

CDR_CLK

/10 PLL_CLK

SYNC

SYNCPREPARE

PREPARE

MK0 B3 FF C4

01 FF E2 5E DATA

DATA

CDR BW Switching

Fig. 13. Simulation result of RX Top for HS-G2A mode.

HSSI Receiver

RX_DP RX_DN

Fig. 14. MIPI-DigRF M-PHY test board.

fout [MHz]

time[㎲]

625

620

615

610

605

600

595

630

635

1 2 3 4 5 6 7 8 9 10

Frequency Detection Loop

3SISYNC

624 MHz

Lock Time= 20ns (3SI)

Fig. 15. The measured frequency settling transients of the CDR for HS-G2A mode.


recovered data for the HS-G2A mode. Eye opening is 78 ps (0.96 UI), the peak-to peak jitter is 35.24 ps, and RMS jitter is 4.25 ps.

Fig. 17 shows the loopback measurement results. The transmitted data of the receiver is “10101010” while applying a “10101010” pattern to Tx_symbol<7:0>. In Rx, the input data is recovered by the CDR and converted to parallel data by the deserializer and transmitted as 8-bit data using the Rx_symbol<7:0> to the protocol side through the decoder from the Rx digital controller. As shown in Fig. 17, it shows the output recovered data of Rx_symbol<7:0> as “10101010”.

Table 3 shows the circuit performance summary of the proposed receiver. The data rate of this work is 1.248 Gb/s – 2.918 Gb/s. The power consumption of the receiver is 16 mW. The performance reported for similar chips in references [4-6] does not include the power consumption of the transmitter. If the power consumption of the transmitter is included, the total power consumption of the references will be much higher than that of this research. Moreover, the Rx power consumption is much lower compared to previous research even though the data rate is much higher and the CDR lock time is much shorter. The proposed CDR is a

dual-loop type with a fully digital frequency detection loop and it adopts a quarter-rate linear phase detector.

The table shows that the HS-G1 and HS-G2 CDR locking time of this work is 0.048 ms and 0.020 ms, respectively. This performance is the fastest compared to other. In this work, to satisfy the 3 SI locking time of the CDR, a bandwidth switching method was proposed. The results show that, the CDR can be operated in such a short time, such as a 3 SI of SYNC pattern.

The data rate of this work is 1.248 Gb/s – 2.918 Gb/s. The measured peak-to-peak jitter and rms jitter in HS-G1A mode are 38.06 psp-p and 2.97 psrms, respectively. Also, the peak-to-peak jitter in HS-G2A mode is 35.24 psp-p, and RMS jitter is 4.25 ps .

V. CONCLUSIONS

This paper presents a 1.248 Gb/s – 2.915 Gb/s low-power receiver for MIPI-DigRF M-PHY with a fully digital frequency detection loop. In the receiver, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement the fast phase tracking loop. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 600 μm x 250 μm. The power consumption of the receiver is 16 mW from 1.1V supply for the HS-G2A mode. The measured rms and peak jitter are 35.24 psp-p and 4.25 psrms respectively for the HS-G2 mode

Eye Opening= 0.96 UI

Fig. 16. The measured data eye diagram of recovered data for HS-G2A mode.

RX_Symbol<7> = '1'

RX_Symbol<6> = '0'

RX_Symbol<5> = '1'

RX_Symbol<4> = '0'

RX_Symbol<3> = '1'

RX_Symbol<2> = '0'

RX_Symbol<1> = '1'

RX_Symbol<0> = '0'

RX_Symbol<7:0> = "10101010"

Fig. 17. The measured output of receiver transmitted data.

Table 3. Performance comparison with previous research

[4] [5] [6] This work Data rate

2.7 Gb/s – 1.62 Gb/s

2.7 Gb/s – 1.62 Gb/s

2.7 Gb/s – 1.62 Gb/s

2.918 Gb/s – 1.248 Gb/s

Process CMOS 0.18 mm

CMOS 0.13 mm

CMOS 0.13 mm

CMOS 0.11 mm

PD type Half-rate Linear-PD

1/5-rate Linear-PD Weighted Quarter-rate

Linear-PD Supply Voltage 1.8V 1.2 V 1.2 V 1.1 V

Power 81 mW

@ 2.7 Gb/s (Rx)

87 mW @ 2.7 Gb/s

(Rx)

23 mW @ 2.7 Gb/s

(Rx)

Rx 12 mW

(HS-G1A) 16 mW

(HS-G2A)

CDR Lock Time

0.4 ms N.A. 0.96 ms

0.048ms (HS-G1A) 0.020 ms

(HS-G2A)

Jitter 37 psp-p 154 psp-p 29 psrms

23 psp-p 3.28 psrms

35.24 psp-p 4.25 psrms

Chip Area N.A. 0.4- mm2 (Rx)

0.07 mm2 (Rx)

0.32 mm2 (Rx)


ACKNOWLEDGMENTS

This work was supported by the ICT R&D program of MSIP/IITP. [10045451, Development of tracking the location of continuous moving objects in wide-area].

REFERENCES

[1] K. Hu et al., “A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-locked Ring Oscillators in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899–908, Apr. 2010.

[2] J.-K. Kim, J. Kim, G. Kim, and D.-K. Jeong, “A Fully Integrated 0.13-mm CMOS 40-Gb/s Serial Link Transceiver,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1510–1521, May. 2009.

[3] K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, “A 27-mW 3.6-Gb/s I/O Transceiver,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 602–612, Apr. 2004.

[4] S. Lee et al., “A 2.7 Gbps & 1.62 Gbps Dual-mode Clock and Data Recovery for DisplayPort in 0.18 CMOS,” in Proc. IEEE Int. SOC Conf., 2009, pp. 179–182.

[5] K. Min, and C. Yoo, “A 1.62/2.7Gbps Clock and Data Recovery with Pattern Based Frequency Detector for DisplayPort,” IEEE Transaction on Consumer Electronics, vol. 56, no. 4, pp. 2032–2036, Nov. 2010.

[6] J. Song, I. Jung, M. Song, Y.-H. Kwak, S. Hwang, and C. Kim, “A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiverfor DisplayPort v1.1a With Weighted Phase and Frequency Detection,” IEEE Transactions on Circuits and Systems, vol. 60, no. 2, pp. 268–278, Feb. 2013.

[7] M. Hossain et al., “A 7.4 Gb/s 6.8 mW source synchronous receiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899–908, Apr. 2010.

[8] M. Hwang et al., “A 180-Mb/s to 3.2 Gb/s, Continuous-rate, Fast-locking CDR without Using External Reference Clock,” in Proc. IEEE Asian Solid-State Circuits Conf., 2007, pp. 144–147.

[9] J.-K. Woo, H. Lee, W.-Y Shin, H. Song, D.-K Jeong, and S. Kim, “A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge

Pump and Loop Filter,” IEEE ASSCC 2006, pp. 411–414, Nov. 2006.

[10] W.-H Zhao, Z.-G. Wang, and E. Zhu, “A 3.125-Gb/s CMOS Word Alignment Demultiplexer for Serial Data Communications,” in Proc. IEEE European Solid-State Circuits Conf., 2003, pp. 389-392.

[11] Y. Zhen, and H. Qing-sheng, “A Comma Detection and Word Alignment Circuit for High-speed SerDes,” IEEE WiCOM 2011, pp. 1-4.

[12] R. Inti et al., “A 0.5-to-2.5 Gb/s Reference-less Half-rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Dutycycle Error Tolerance,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150–3162, Dec. 2011.

[13] L. Hai Qi et al., “A Low-noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and Fine Frequency Tuning,” IEEE Trans. Very Large Scale Integr. Syst. , vol. 17, pp. 571–577, 2009.

[14] S. Zhinian et al., “A 2.4-GHz Ring-oscillator-based CMOS Frequency Synthesizer with a Fractional Divider Dual-PLL Architecture,” IEEE J. Solid-State Circuits, vol. 39, pp. 452–462, 2004.

Sang-Yun Kim received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013. He is currently working towards a combined Ph.D. & M.S. at the School of Information and Communication

Engineering at, Sungkyunkwan University. His research interests include high-speed interface ICs and CMOS RF transceivers.

Juri Lee received her B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013, where she is currently working toward a combined Ph.D. & M.S degree at the School of Information and Communication

Engineering, Sungkyunkwan University. Her research interests include VCSEL drivers and CMOS RF transceivers.


Hyung-Gu Park was born in Seoul, Korea. He received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2010, where he is currently working toward a Ph.D. degree through the School of

Information and Communication Engineering, Sungkyun- kwan University. His research interests include high-speed interface IC and CMOS RF transceiver.

Young Gun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively. His research interest is focused on CMOS fully integrated frequency

synthesizers and oscillators and on transceivers for low-power mobile communication.

Jae Yong Lee was born in Seoul, Korea. He received the Bachelor of Industrial Engineering from the Hankuk University of Foreign Studies, Seoul, Korea, in 1998. He carried out Telematics and LBS

service business at SK networks, RealTelecom and Hubilon for more than a decade. He is currently CEO at Hubilon CO.,LTD which is a leading company in the field of indoor positioning service in Korea. His research interests cover the design and analysis of RTLS and indoor location services with over 10 patents.

Kang-Yoon Lee received his B.S., M.S. and Ph.D. degrees from the School of Electrical Engineering at Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc.,

San Jose, CA, where he was a Manager of the Analog Division and worked on the design of the CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was an Associate Professor at the Department of Electronics Engineering, Konkuk University. Since 2012, he has been an Associate Professor at the College of Information and Communi- cation Engineering, Sungkyunkwan University. His research interests include the implementation of power integrated circuits, CMOS RF transceivers, analog integrated circuits, and analog/digital mixed-mode VLSI system design.

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