A 1.7mW All Digital Phase-Locked Loop withNew Gain Generator and Low Power DCO

Tzu-Chiang Chao and Wei HwangDepartment of Electronics Engineering & Institute of electronics, and

Microelectronics and Information Systems Research Center,National Chiao-Tung University, HsinChu 300, Taiwan

ctc.ee9 1 g(n du.tw, Hwangmai .nctu .edu.twAbstract-In this paper, a new architecture and algorithm for Inrual Targetall digital phase-locked loop (ADPLL) is proposed. By usingthe new search algorithm, it can accomplish phase lock processwithin 18 input clock cycles. By using the new architecture, wecan combine the functions of the frequency comparator, phasedetector and gain generator in one hard block. Also, a new MJodified BiEary Searchdigitally controlled oscillator (DCO) structure for low power,small area is presented and its frequency range is from 200 nleal YargeetMHz to 750 MHz with a supply voltage 1.2v. The total power fnqencyconsumption of ADPLL is 1.7mW. This ADPLL hascharacteristics of fast frequency locking, small hard cost and l . llower power consumption. This ADPLL is designed and Propose Searchimplemented by TSMC's 0.13um CMOS technology. Figure 1. Modified Binary Search VS. Dynamic Control

Gain SearchI. INTRODUCTION

A phase-locked loop (PLL) is a widely used circuit for II. THE ALGORITHM ANDARCHITECTURE OF ADPLLclocking digital IP-blocks. Traditionally, a PLL is made asan analog building block. However, integrating an analog A. AlgorithmPLL in a digital noisy systems-on-a-chip (SoC) environment In this section, we will discuss the algorithm of theis challenging. In addition, the analog PLL is sensitive to ADPLL. The conventional ADPLL [3] uses four modes ofprocess parameters and must therefore be redesigned for operation: frequency acquisition, phase acquisition,each new technology. frequency maintenance and phase maintenance. Each mode

Digitally controlled clock generators cannot compete is like a "search" algorithm with different adaptive scheme.with analog implementations in terms of high clock rate Phase lock begins with frequency acquisition. Whencombined with low phase noise, but are much easier to frequency acquisition is complete, the ADPLL enters phaseimplement without targeting at a specific technology. acquisition mode. After phase lock completes, the ADPLLAssuming that all digital phase-locked loop (ADPLL) is enters both frequency maintenance and phase maintenance.implemented with only active components such as transistors, In frequency acquisition mode, in order to find the targetit will scale with technology. Capacitors and resistors, which frequency, the conventional ADPLL uses a modified binary-are used in analog circuits will not scale with technology to search algorithm. The modified binary-search algorithm [3]the same extent [1,2]. Also, integrating an analog circuit was shown in Fig. 1. The modified binary-search algorithmwith digital circuit has the noise problem. The digital noise sweeps the digitally controlled oscillator (DCO) frequencyeffect the performance of the analog circuit. It is difficult to range to match the target frequency. On every change inisolate the noise which generated from the digital part. It is a search direction the frequency gain is reduced by a factor ofgood idea that using the ADPLL in digital systems. 2.

The rest of this paper is organized as follows: Section II Fig. I also shows the proposed search algorithm.will describe the proposed dynamic control gain search. Comparing the modified binary search with our proposedSection III will describe the proposed ADPLL architecture. search, the difference is the change of gain value. In newSection IV will show the simulation result and layout. algorithm, the frequency comparator can find the optimizedSection V is conclusion. gain value and reduce the searching step by the optimized

gain value. So in new searching algorithm, ADPLL do not

0-7803-9390-2/06/$20.00 )2006 IEEE 4867 ISCAS 2006

need to sweep the overall DCO frequency range to match the (4) DCO Enable Generator:external frequency. The DCO enable generator will generate the enable

In phase acquisition mode, our ADPLL aligns the signal and disable signal for digital controlled oscillator. Bybuffered output (do not need divider circuit) of the DCO to using this DCO enable generator we can align the first risingthe matched delay reference clock. In new algorithm, we edge of external signal and internal signal every twoexecute the frequency acquisition and phase acquisition at reference cycles. When the enable signal is low, the DCOthe same time. So we use only one mode to finish the will be disabled and the disable time is very short.frequency acquisition, phase acquisition and frequency/phasemaintenance. In our ADPLL algorithm, the operation is just III. CIRCUIT DESIGNlike the digital phase-locked loop (DPLL) but the design ofthe building block is all digital circuit. A. Phase/Frequency Detector

B. Architecture In conventional ADPLL, the frequency comparatoraccepts the reference clock and the output of DCO outputThere are some major building blocks in the proposed buffer as its inputs. The frequency comparator will generate

ADPLL. They are phase/frequency detector (PDF), gain the Fast signal or the signal Slow. The phase detector alsoregister, DCO, Control unit, DCO enable generator and detects the reference clock and the output of the DCO outputmultiplexer. Fig.2 shows the block diagram of the proposed buffer and generates the Ahead signal or the Behind signal.ADPLL.

In our ADPLL, we combine the two function blocks(frequency detect and phase align) and they work in onemode. So our proposed PFD detects the frequency and the

Register phase at the same time. The PFD also provides theinformation of the gain value without using modified binary

DTlilelay PFI_ Mux: _ = 1_ Addf9uh search. The proposed PFD was shown in the Fig.3.As shows in the Fig.3, our PFD detects the frequency and

phase every two reference cycles so the frequency of thereference clock was divided by two. The positive edge block

Fast will generate a pulse signal at rising edge of the input signal.The output of the positive edge block will clear the output ofeach D Flip-Flop at the rising edge of every two references

Enrialble, | l l lclocks. The fourteen D Flip-Flops detect the frequency andGet ratar Dit generate the information of gain value. The D8 1 signal wasl lt l[)CO < ffDCO Register delayed by two inverters from D8 signal so the D8 signal and

D8_1 signal was very closely.The waveform of our PFD was shown in the Fig.4, it was

Figure 2. ADPLL Architecture shown the case when the ADPLL frequency/phase waslocked. The detected point is at the rising edge of the

The function of each block will be described in the reference clock, when the ADPLL was locked, the D8 signalfollowing: was low and the D8_1 signal was high at the detected point.

(1) PFD If the D8 signal is already high at the detect point, it meansthe DCO frequency is faster than the target frequency. In

The proposed PFD can detect the frequency and phase other words, if the D8 signal is low at the detected point, iterror between internal signal and external signal. It generates means that the DCO frequency is slower than the targettwo types of signals, the first type of signal is Fast/Slow frequency. So our ADPLL lock the frequency by the D Flip-signal. The second type of signal is the gain value for gain Flop and align the phase by the delay method.register.

(2) Multiplexer B. Gain GeneratorBecause the PFD will generate two different gain values In our algorithm, we don't use the modified binary

(one is for fast case and another is for slow case) so we need search algorithm and we generate the gain value by thea multiplexer to select the gain value, output information of the PFD. By the output of the PFD,

we can get two different gain values. The ADPLL select(3)DCO the two gain values by the fast signal. In the Table 1, weDCO is the heart of the ADPLL. It is a ring oscillator and show the relation between the gain value and the output of

it is constructed by inverters. The frequency control the PFD. For example, ifthe DCO frequency is 600MHzmechanism is through the binary weighted control word andthe control word is generated by the DCO register.

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DeIay

FXT c1k 1 EXTdiv2 D1311| ~~~EXTdW2 Fast3MlathkedIWISo,D P2 13 41D26PD3D4 DS 6 7 D175 P8

_5 1aD 1D I12

XI dQ D Q D i . Q I Ii!D I I4Dp IQA

DCO __DO BuffMr output

Figure 3. PFD circuitTable I. Gain Value V.S ds PFD Output Signals|Detected point PFD ZD8D1D8_5D9 DIODlID12 Gain value bit4 Gain|

Inp Output | |[0][1][2] [3][4][5][6][7]v valueMef CL-K ~~~~~~~~~~~~DCOSignal, 4Dt 1 D8 5D9 DIODI DI 0 0lRef ELK FrequencyDCCO CL.KFY nTL 11L L1 (MHz) X

D1_560o 1 0- 0 O O

3: 50560-595 1,P [040 &00'P0 0 1100010004:

.~595-630I 1X1> 1> lOvo O000- P 3-0 6ii30 70,p 1 431901 190 190 0 @ 0+' 11 & lXOO 1 7P

.1.00 007007704'11lo1 l & l507 15 7708404 11 [jJ 1[jJ l[i 1 l f0 111 1 000 31'

E:8 1I l l0840-910 1 [iJ17 [ [if 1 [go P111100+ 634i(When the DCO frequency is bigger than the target frequency)

High

C. Digital Controlled OscillatorE~_1 Low Like most voltage-controlled oscillator, the DCO consists

of a frequency-control mechanism with an oscillator block.Figure 4. PFD waveform(when ADPLL in locked state) There are two parameters to modulate the frequency of the

ring oscillator. One is the propagation delay time of the(600MHz is faster than the target frequency 560MHz), the inverter and another is the total number of inverter. In ourD8 signal and the D8_1 signal are high at detected point and DCO design, we only modulate the parameter of the inverterthe others (D8_5, D9-D 12) are low. When the DCO propagation delay time. But the propagation delay time offrequency is 600MHz, the gain value is three. When the the inverter is controlled by two mechanisms. OneDCO frequency becomes more far from the target frequency, mechanism is the width of the inverter and another is thethe gain value becomes larger. The gain generator just likes turned on voltage of the switch.the charge pump, it provide the magnitude to the Add/Subblock. When the DCO frequency is slower than the target Our proposed DCO was shown in the Fig.5. The DCOfrequency, the fast signal becomes low and the gain value is consists of coarse cell, fine cell, unit gain circuit and voltageprovided by another output information (D4- D7_5) of the divider The DCO control word is the 8 binary weightedPFD. The first case (fast signal is high) is similar with the control signals. The weighted control signals DCO[4]~second case (fast signal is low). We only show the first case DCO[5] control the coarse cell and the others control the finein this section. cell. The switch of the coarse cell is turned on by the

Voltage_A and the switch of the fine cell is turned on by theVdd voltage or Gnd voltage. By the two stages method, we

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XVokageA area. The frequency range of DCO is from 200 MHz to

Unit Voltage_A 750 MHz with a supply voltage 1.2v. The total powerEnable consumption of ADPLL is only 1.7mW and its area is

200um x 100um in a TSMC's 0.13um 1P8M CMOS_ Coarse _Cotfarse L Coarse L Coarse L Coarse 1technology.

celc-e1'll Cel celCerllrACKNOWLEDGMENT

|C010:71 C47 xllz,l,, |The work is supported by National Science Council,Iregister / l R.O.C., under the project NSC 92-2220-E-009-01 1, NSC 93-

D toCole:3 1 2220-E-009-024 and TSMC grant. This work is alsosupported by DoE/DoIT 94-EC-17-A-01-S1-034. Theauthors would like to thank SOC Research Center in NCTUfor support of this research.

| | FiLe L] Fine L] Fine L]Fine L|Fine||Iceln el ntellell Dln | COoutput REFERENCES

Figure 5. The proposed DCO [1] T. Olsson and P. Nilsson, " A digital PLL made from standard cell,"in Proc. 15th ECCTD, pp.277-280, 2001.

Voltage-A [2] T. Olsson and P. Nilsson, " A digitally controlled PLL for SoCapplications," IEEE J. Solid-State Circuits, Vol. 39, pp.751 - 760,May 2004.

[3] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An ALLDigital Phase-Locked Loop with 50-cycle Lock Time Suitable for

W141 7T Wl1 OLj lwlT W171T High Performance Microprocessors," IEEE J. Solid-Statep1 p2 p p4 Circuits,Vol.30, pp.412-422, Apr. 1995.

MPIN OUT

OUTIN

ni n2 nO0 3 n4WI4 1 W151 W161 1[71

Figure 7. (a) Unit Gain CircuitVoltage A

DCO Freq V.S. DCO control word

Figure.6 the coarse cell of the proposed DCOcan save the area and power consumption. The coarse cell of 1000the DCO was shown in the Fig.6. The fine cell is the same Ewith coarse cell but the Voltage A becomes Vdd voltage orGnd voltage. The Unit gain circuit was shown in the Fig.7(a) 200 land Fig.7(b) was simulation result of the DCO frequency vs. 0DCO control word. ` P g 1Z 0 ` 4e

Digital Control WordIV. SIMULATION AND MEASUREMENT RESULTS

The layout was shown in the Fig.8 and the area is 200um Figure 7. (b) the frequency vs. control wordx 100um in a TSMC 0.13um CMOS technology. The DCOruns up to 560MHz (70MHz x 8) with a supply voltage 1.2vand the resolution is 8 bits. The ADPLL total powerconsumption is 1.7mW and the jitter (by built-in jitter test) is161.4ps at DCO output frequency range 560 MHz. --

V. CONCLUSIONS |ix |In this paper, a new type ADPLL for fast lock process, l 1111'll 1111 111pIijll

small area and lOW power consumption iS proposed. A l_______________________proposed PFD is used to reduce the lock cycle time. The Figure 8. Layout Implementationproposed DCO is used to reduce power consumption and

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