A 1.95GHz 28dBm fully integrated packaged Power Amplifier presenting a 3G FOM of 80 (PAE+ACLR)

designed in H9SOIFEM CMOS 130nm Development of an optimized high performances RF SOI power cell

Vincent KNOPIK1, Guillaume BERTRAND2, Augustin MONROY3, Sylvie GACHON4, Julien MORELLE5, Philippe CATHELIN1, Benoit BUTAYE1

(1) R&D RF Design, (2) Technology Models, (3) Technology Process, (4) Project Management, (5) Measurements STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France. vincent.knopik@st.com

Abstract—A fully integrated and packaged Power Amplifier (PA) has been realized in 130nm STMicroelectronics H9SOIFEM. The PA is based on a new dedicated power cell delivering very good RF performances. At 28dBm output power, ACPR is -40dBc and PAE is 40%, reaching a FOM (ACPR+PAE) of 80 at 1.95GHz 3G standard, under 3.4V. Neither linearization nor efficiency enhancement technics have been used. The core power transistor provides very high power added efficiency (PAE) of 75% at a gain of 18dB typical, around 2GHz. This technology has been optimized for low cost RF front end module (FEM) applications.

Keywords: CMOS, SOI, Power Amplifier, 3G, PAE, FOM, Front End Module.

I. INTRODUCTION

SOI technology performance has been proven for RF Switch and LNA applications [1-2-3-4]. Recent development has shown state of the art results with RonxCoff below 120fs [1]. LNA has also been proven in pure SOI reaching very good results at 2GHz [3] and 5.9GHz [4]. PA has also been developed [5-6]. For a PA, both linearity and efficiency are firstly dependent of the load at a given voltage. Linearity asks for low load value, while efficiency asks for high one. Linearization technic like Digital Pre-Distortion can be employed in the high value load case (saturated PA). Efficiency enhancement technic like Envelope Tracking is used for the other case (Linear PA). H9SOIFEM technology offers a tradeoff between frontend and backend to propose optimized PA core solution, limiting the use of such technics. A complete PA demonstrator has been realized, targeting 3G/4G applications at 28dBm. This demonstrator presents the results at board SMA connectors, including real environment, without any deembedding.

Part II and III present the technology overview and the transistors used for power amplification. Part IV describes the full PA design including IC and module. Part V shows the measurement results and the comparison with simulation.

II. H9SOIFEM TECHNOLOGY FOR PA

A. Front end There are several available transistors in H9SOIFEM,

depending on the standard, voltage and operating frequency. For low voltage operation (below 1.2V), or stacked topology, a thin oxide NMOS GO1 transistor presents 60GHz of cut-off frequency (fT) for very high frequency standard. For higher operating voltage, the improved NMOS Switch (SW) transistor with thicker oxide (GO2) can operate at 2.5V DC with a breakdown voltage around 3.7V. The standard NMOS GO2 transistor presents a higher breakdown voltage but a lower fT. For very high operating voltage, an n-channel laterally diffused MOS (NLDMOS) transistor with a BV of 13.5V and fT of 44GHz is available.

Breakdown voltage (BV) is a key element for maximum robustness (VSWR ruggedness). However, the HCI (Hot Carrier Injection) voltage should also be considered. The effect of HCI on PA transistor is reducing the overall gain over time. For instance the NLDMOS HCI voltage is around 8V-10V for a given lifetime. Since the transistor must see high voltage swings at its input/output to target high efficiency, considering BV only is not enough.

H9SOIFEM provides an optimized solution in Power, PAE, Gain, stability, and reliability with its nldemos_nmos25rf transistor, called “interleaved”. Its HCI voltage is increased by the one of GO2 transistor, reaching an average of 10.5-12.5V. The description is given part III.

B. Back end H9SOIFEM offers 4 backend options: 2 full aluminum and

2 with a thick copper (TC) metallization: M4TC and M3TCTA with thick Al (4um). The choice between M4TC and M3TCTA depends on the target. The benefit of an additional thick Al (4um) is to be put in parallel to the one of having one extra thin metal (M3 of M4TC). Having more thin layers allows increasing the MOM capacitance density. Moreover, control and biasing blocks layout is facilitated.

978-1-5090-4391-0/16/$31.00 ©2016 IEEE

III. INTERLEAVED POWER TRANSISTOR

Stacking transistors or using cascode topology to sustain high voltage swing is commonly used in PA design. H9SOIFEM offers an optimized solution based on a combination of a thick oxide transistor and extended one. The layout of this parameterized cell (Pcell) has been done to reduce all the parasitics between the 2 transistors, while ensuring best isolation (stability) and power response over frequency. 2 options are available for this transistor using a standard GO2 device or a GO2 SW one with improved fT.

A. Parameterized Cell(Pcell) The Pcell offers a good flexibility in the usage of the power

transistor. It has 2 gates, one for the bottom transistor called active gate (G), and one for the top transistor (nldemos), called control gate (GC). This gate input is usually low resistive with a high decoupling capacitance to ensure proper operation. Figure 1 presents its topology (symbol). MA and MB are the 2 middle point accesses. It allows checking the voltage swing across the structure (reliability). They can be left unconnected.

Fig 1: Interleaved Power Transistor Topology

B. Transistor ‘s measured performances Different power cells have been realized using the Pell

(4mm, 10mm width). On Wafer (OW) Load Pull measurements have been done. Figure 2 shows the 4mm results at 1.9GHz. The transistor reaches more than 75% PAE keeping a gain above 18dB. PAE at 1dB compression is above 70%. Moreover, Figure 3 demonstrates a really good correlation between the simulation and the measurement. Momentum models and extracted views (calibre PEX) are used for the simulation.

Fig 2: Load Pull Measurements of 4mm Power Transistor (3.6V, 25mA)

Fig 3: Load Pull Measurements of 10mm Power Transistor (3.6V, 70mA). Comparison with simulated models

IV. 3G PA DESIGN

A. Topology Realized in M4TC, the PA is a two stages, single ended

structure. The Driver stage is fully integrated with its input and interstage matching networks, including choke inductor. The power stage output matching network (OMN) has been designed on module. Figure 4 presents the topology. The driver and power transistor sizes are 4mm and 12mm. Both driver and power transistors are Class AB: (3.4V, 20mA) and (3.4V, 130mA) respectively. This combination of biasing points improves AM-PM cancelation (better ACLR) between the stages, as mentioned by Steve C. Cripps page 310 of [7].

Copper pillar flip chip has been used for assembly. Clean and extended ground plane enforces the RF and thermal behavior, as showed on figure 5 (at least 17 GND pillars).

Fig 4: H9SOIFEM PA Topology

Fig 5: H9SOIFEM PA Layout (picture flipped to be aligned with fig 4). 1.2x0.7mm2 for core PA and 1.5x1.5mm2 inclunding pads

978-1-5090-4391-0/16/$31.00 ©2016 IEEE

B. Load and Module Design At 3.4V, the maximum power is more than 31dBm, giving

a load of 5 Ω. The OMN has been designed on module using Keysight Momentum. Figure 6 shows the PA die flip chipped on the module integrating the OMN. The final package picture is also presented. A sample has been opened and the PA die removed. A probe has been applied at pillar area to check the load. Figure 7 shows the result and the good correlation between the measurements of the board alone with the momentum model, including models of the board capacitances.

Fig 6: H9SOIFEM PA Module (4x4mm2)

Fig 7: Measurement and Simulation results of the PA Module OMN, between internal copper pillar and board output SMA

V. MEASUREMENTS AND CONCLUSION

The full PA module has been measured at SMA connectors’ planes, without deembedding, with a VCC of 3.4V. Cascode voltage is 1.8V for both stages. The biasing points are the one described on part IV. In addition to a good correlation with simulation (full board) Figure 8 shows a measured small signal gain of 28dB, a P1dB at 31dBm and a Pmax at 32dBm. PAE at 28dBm is 40%, PAE max is 57%.

Fig 8: Measured CW performances of the PA at board (SMA) planes. Comparison with simulation.

Figure 9 shows the 3G WCDMA ACLR measurement over output power of the full board. At 28dBm, ACLR@5MHz is -41dBc and ACLR@10MHz is lower than -54dBc.

Fig 9: Measured 3G (voice call) ACLR performances of the PA at board (SMA) planes. Comparison with simulation.

The measured FOM (ACLR@5MHz+PAE) reaches 80 at SMA connectors, without any linearization, and efficiency enhancement technics. Regarding existing solutions [8], this is the best result presented for CMOS PA at package level, and core technology.

ACKNOWLEDGMENT

The authors thank all the people involved in the development of the H9SOIFEM technology and demonstrators: R.Bianchi(Technology), RF design team, E.Granger (TLM), M.Coly, Christian Corre and D.Gloria (Tests), JP.Aubert, M.Song (Marketing team), N.Revil, K.Traore (Pcell development), T. Schwartzmann, IMS Bordeaux team of E.Kerhervé, V. Poisson and Keysight members.

REFERENCES

[1] F. Gianesello, A. Monroy ,V. Vialla, et al, “Highly linear and sub 120 fs Ron x Coff 130 nm RF SOI technology targeting 5G carrier aggregation RF switches and FEM SOC,” 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), p9-12.

[2] M. Jaffe, M. Abou-Khalil, A. Botula, et al, “Improvements in SOI technology for RF switches,” 2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), p30-32.

[3] H. Noori, M. Sanner and N. Yanduru, “A 0.8 dB NF, 4.6 dBm IIP3, 1.8–2.2 GHz, low-power LNA in 130 nm RF SOI CMOS technology,” 2015 Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), p1-4.

[4] R.Paulin, P.Cathelin, G.Bertrand, et al, “A 12.7dBm IIP3, 1.34dB NF, 4.9GHz-5.9GHz 802.11a/n LNA in 0.13 m PD-SOI CMOS with Body-Contacted transistor,” 2016 IEEE International Microwave Symposium (IMS).

[5] B. François, P. Reynaert, “Highly Linear Fully Integrated Wideband RF PA for LTE-Advanced in 180-nm SOI,” 2015 IEEE Transactions on Microwave Theory and Techniques, p649-658.

[6] A. Giry, G. Tant, Y. Lamy, C. Raynaud, et al, “A monolithic watt-level SOI LDMOS linear power amplifier with through silicon via for 4G cellular applications,” 2013 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), p19-21.

[7] Steve C. Cripps, RF Power Amplifiers for Wireless Communications book. Artech House Publisher, London. 1999.

[8] K. Oishi, E. Yoshida, Y. Sakai et al, “ A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE,” ISSCC 2014, p60-61.

978-1-5090-4391-0/16/$31.00 ©2016 IEEE

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