A 2GSps, 8-Bit Folding and Interpolation ADC with ...downloads.hindawi.com/journals/js/2017/3984526.pdf · A 2GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration

Research ArticleA 2 GSps, 8-Bit Folding and Interpolation ADC withForeground Calibration in 90 nm CMOS Technology

Yi Zhang,1,2,3 Qiao Meng,4 Changchun Zhang,1,2 Ying Zhang,1,2 Yufeng Guo,1,2

Youtao Zhang,1,5,6 Xiaopeng Li,1,5,6 and Lei Yang1,5,6

1National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing, China2College of Electronics Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China3State Key Laboratory of Millimeter Waves, Southeast University, Nanjing, China4Institute of RF- & OE-ICs, Southeast University, Nanjing, China5Nanjing GuoBo Electronics Co., Ltd., Nanjing, China6Nanjing Electronic Devices Institute, Nanjing, China

Correspondence should be addressed to Yi Zhang; [email protected]

Received 19 September 2016; Revised 9 December 2016; Accepted 21 December 2016; Published 26 January 2017

Academic Editor: Hao Gao

Copyright © 2017 Yi Zhang et al.This is an open access article distributed under the Creative CommonsAttribution License, whichpermits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

A single channel 2GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration inTSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstagesample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foregrounddigital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thusimproving the linearity of the ADC. Chip area of the whole ADC including pads is 930 𝜇m × 930 𝜇m. Postsimulation resultsdemonstrate that, under a single supply of 1.2 volts, the power consumption is 210mW. For the sampling rate of 2GSps, the signalto noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

1. Introduction

High-speed (GSps),media-resolution (6∼8 b), and low poweranalog-to-digital converters (ADCs) are essential in realizinghigh-speed communication systems, test equipment, radar,and radio astronomy systems. For example, the millimeter-wave-based wireless personal area network (WPAN) allowsvery high data rate application (>2Gbps). Multi-GSps and5∼8-bit ADCs are highly demanded and essential in these sys-tems [1]. Another example would be that high-speed ADCsare the core elements in the digital oscilloscopes; they usuallyhave a resolution of more than 8 bits and a sampling rateof over 1 GSps, even 20GSps [2]. However, increased devicemismatch, decreased supply voltage, and excessive powerconsumption prevent current GSps single channel CMOSconverters from being extended to 8 bits. Flash and foldingADCs are the primary candidates for GSps applications dueto their high conversion speed and low latency. Although

the flash architecture has been used in the highest speedADCs, it suffers from the severe disadvantage that it requires2𝑁 comparators for 𝑁 bits of resolution, which results in asubstantial area and power penalty starting at the 8 b level. Asa result, pipelined folding and interpolation (F&I) has beenadopted in our proposed design of 2GSps, 8-bit ADC.

For medium and high resolution ADCs, the foldingfactor 𝐹F and interpolation factor 𝐹I should be large as thecomparators and folding amplifiers can be eliminated by afactor of 𝐹F and 𝐹I, respectively. However, it is inappropriateto realize large folding and interpolation factor in a singlestage. Therefore, cascaded folding and interpolation shouldbe taken. In the proposed design, folding and interpolationfactors have been selected to be 3 × 3 and 2 × 8 to balancethe system area, the speed, and the performance. Interstagesample-and-hold amplifiers (SHAs) are adopted to enhancethe quantization time. Foreground digital assisted calibration

HindawiJournal of SensorsVolume 2017, Article ID 3984526, 7 pageshttps://doi.org/10.1155/2017/3984526

https://doi.org/10.1155/2017/3984526

2 Journal of Sensors

preampinterstage

SHA

F&IF&Icomparator

ANDFine

coding

coarsepreamp comparator DFF

CoarsecodingTHA

&b5

b6b7b8

b2b3b4

b1

Synchronization

Logiccontrol

DFFarrayDACs Counter

Vin+

Vin−

19∗

16∗

12∗

32∗

32∗

6∗

6∗

6∗

F1 = 3

I1 = 2

F2 = 3

I2 = 8

7∗

4∗

8∗

DFF

· · ·

.

.

....

.

.

....

.

.

....

.

.

.

.

.

....

.

.

....

Reference

networklevel

Figure 1: Diagram of the proposed ADC.

is also adopted to improve the performance of ADC causedby device mismatch, the impact of gain error, and othernonideal factors, while at the same time it uses the small sizedtransistors in order to maintain its speed advantage.

The rest of the paper is organized as follows. In the nextsection, key circuits and digital calibration of the ADCwill bepresented; Section 3 shows the layout and system simulationresults of the design. Conclusions will be drawn in Section 4,and acknowledgements are in the last section.

2. Circuit of the Proposed ADC

The proposed ADC is a single channel circuit as shown inFigure 1. The upper part is the main circuit and the underpart is the calibration circuit. For the main circuit, the coarseand the fine channel quantify the signal from the front-endtrack-and-hold amplifier (THA), respectively, and deliver thequantization signal to the 8 D Flip-Flop (DFFs) to get thefinal results. The fine channel is much more complicatedthan the coarse channel. It is composed of 19 preamps (1for redundancy), two F&I stages (6 for the first stage withfolding factor 𝐹F1 = 3 and interpolation factor 𝐹I1 = 2;4 for the second stage with folding factor 𝐹F2 = 3 andinterpolation factor 𝐹I2 = 8), and 12-interstage SHA toenhance the quantization time, 32 comparators, and 32-sparkcode elimination circuit and fine coding circuit. The coarsechannel is composed of 6 preamps, 6 comparators, 7 DFFs,and coarse coding. There is also a synchronization circuit tomake sure that the result is correct.

The under part is the calibration circuit and it includes thelogic control, the counter, the DFF array, and the digital-to-analog converters (DACs). This will be explained further inSection 2.4.

2.1. The Front-End THA. For gigahertz sampling rate opera-tion, it is preferred to have a front-end THA as it can improvethe dynamic performance of an ADC. By holding the analogsample static during digitization, the THA largely removeserrors caused by skews in clock delivery to a large numberof comparators, signal-dependent nonlinearity, and aperturejitter [7].

Bootstrap

Bootstrap

clks_p

clks_p

clksb_n

clksb_n

Prea

mp

arra

y

Vin

Vip

Vin

Vip

Vo+

Voo+

Voo+

VDD Vbias

Vbias

Vbias

2

VDD Vbias 2

Cc

Cc

Cs

Cs

Vo−

Voo−

Voo−

Vout−

Vout+

Figure 2: The designed pipelined THA.

The designed THA takes the open-looped architecture,as it is presented in Figure 2. The bootstrapped switch isadopted as its equalized resistance has little to do with theinput voltage, thus improving the THA’s linearity. Also, itsoverdrive voltage is larger than the normal MOS switch, sothe equalized resistance is smaller, and the sampling rate canbe improved.

As the designed THA should be working at 2GSps whilehaving a resolution of over 8 bits, a slave THA has beendesigned after the master THA, shown in Figure 2. The slaveTHA tracks and holds the signal of the master THA. As theinput signal of slave THA is less varying than the originalinput signal, the linearity requirement of the slave stage ismuch easier to realize than the master stage. To gain a largebandwidth for the THA, the slave stage also takes the boot-strapped switch, but much easier than its master counterpart.

The simulation results demonstrate that the master-slaveTHA has a good performance. For clock of 2GHz, its SNDR

Journal of Sensors 3

61.461.661.8

6262.262.462.662.8

63

0 200 400 600 800 1000 1200

SND

R (d

B)

Input signal (MHz)

SNDR of the THA @ 2GSps

Figure 3: SNDR performance for different input signal frequency@2GSps.

out− out+

ip0 ip

1in1 in2 ip

2in0

R1 R1R2 R2

· · · · · ·

VDA

Vbias

M1 M5 M6M4

M8M7

M3M2

Figure 4: The designed F&I circuit.

performance for different input signal frequency is shown inFigure 3. Simulation results demonstrate that the THA’s signalto noise and distortion ratio (SNDR) is better than 61.5 dB upuntil the Nyquist input frequency.

2.2. Folding and Interpolation Network. With the analogpreprocessing, the F&I architecture can better balance theADC’s area, power, and performance. The preamplifier arraygenerates the original zero-crossing points, but they are neverenough. As can be seen in Figure 1, the two-stage cascadedF&I was taken in this design with interstage SHA circuit inbetween.These two stages are similar so they can be discussedtogether.With the help of F&I network, enough zero-crossingpoint will be generated while the system area and power aremuch smaller than its flash counterpart.

The first key element in designing the folding circuit isthat it should have enough bandwidth tomake sure signal canbe settled within the limited time especially for ultra-high-speedADCs. Second, it should have a certain gain to suppressthe offset of next stage. Third, its offset should be controlledwithin a limited amount.

Figure 4 is the proposed F&I network.M1–M6is the input

differential pair as the folding factor is 3. M7andM

8have two

roles, first to insulate the signal from the input. Second, as thedrain of three MOSFET is connected, its output capacitanceis very large. With small sized M

7and M

8, the bandwidth of

the folding circuit can be increased.The AC simulation of the

0

1

2

3

4

5

6

Freq (Hz)

−2

−1

101

102

103

104

105

106

107

108

109

1010

Av = 5.382 dB

Av = 2.382 dBF−3 dB = 4.897GHz

V(d

B)

Figure 5: AC simulation result of folding circuit.

clk

clkclk

clk

VDD

VDD

VDD

n1

n1

n3

n3

n2

n2

p1

p1

p2

p2

p3

p3

Vo2

Vo2

Vo2

Vo1

Vo1

VoVo1

Figure 6: The four-input AND gate designed.

folding circuit is shown in Figure 5. The gain is 5.382 dB andits −3 dB bandwidth is close to 4.9GHz, suited for the ADC.

2.3.The Spark Code Elimination and Latch Circuit. In the finechannel, the cycled thermometer code is produced after thecomparator array and should be coded into the digital output.Like its flash counterpart, because of the process mismatchand comparator’s metastability, the continues 1s will havesome 0s in between; this is called spark code or bubbles. Thespark code will cause quantization error in ADCs, no matterwhat kind of coding it takes.

In [8], the merits and demerits of rom-coding and gray-coding are compared. According to its conclusion, the rom-coding is taken in this design. First the thermometer codeshould be translated into 1-of-n code, as the possibility of2nd order spark code can be neglected as compared with thefirst-order spark code; usually the three-input AND gate willbe used to eliminate the spark code. Also, before the rom-coding, a latch stage should be added. If not, there will beerror as the delay of different modules can be different. Forthis design, 32 latches will be needed, and they will take up alot of area and power dissipation.

To save area and power, a novel four-input AND gateis created instead of the three-input AND gate, shown inFigure 6. Its three inputs are the same as the three-input


THA

PreampF&I

circuit

Finecomparators

Calibrationclock

generationcircuit

Switcharray

array

5 bit currentDACREF

clkfs

clk_int

Delay Delay

Controllogic

Controllogic

DFF array

DFF array

5-bit current

5-bit current

clk_con

MUX

currentREF

Switcharray

Switcharray

I & II

· · ·

· · ·

· · ·

· · ·

.

.

.

.

.

.

.

.

....

in−

in+

Figure 7: The diagram of the proposed foreground digital assisted calibration circuit.

AND gate; the added fourth input is the clock signal to dothe signal latch. Simulation results demonstrate that the four-input AND gate can eliminate the spark code and at the sametime latch the signal while use less area and power.

2.4. The Foreground Calibration Circuit. With CMOS tech-nology scaling down, it is possible to build faster andlow power digital circuit. However, because of the lowersupply voltage, smaller intrinsic gain, and serious transistormismatch, analog circuit does not benefit as much as itsdigital counterpart. Thus using the digital circuit to improvethe analog performance became more and more fascinating.Here the foreground digital assisted calibration is presentedto calibrate the zero-crossing point error, thus improvingthe performance of the folding and interpolation ADC.Although the background calibration seems better because itwill not interfere the main circuit, in this design foregroundcalibration is adopted. The reasons are listed in here: (1) thebackground calibration is much more complicated and it willtake much more area and power consumption; (2) for thefolding and interpolation ADC, its offset is not sensitive tothe temperature change and environment. In [3], test resultsdemonstrate that the INL of ADC hardly changed within50 hours since being powered up. Also, in [9], the authordemonstrate that, for 10-bit folding ADC, for temperaturechange from 0 to 100 degree, the SNDR change is only 0.9 dB.Figure 7 is the diagram of the proposed foreground digitalassisted calibration circuit and its connection to the maincircuit.

The calibration happened when it is powered up. Theoffset of the preamplifier, the folding, and interpolationnetwork and the comparator array will be measured andstored in the DFF arrays. When the ADC goes into normaloperation, the voltage stored in the DFF arrays will go

through the DACs to be analog and compensate the ADC’soffset.

The calibration circuit contains following importantmodules:

(1) The calibration clock generation circuit: it receives thecalibration trigger and controls the whole calibrationprocess. The key point for the circuit is that thegenerated 16 calibration pulses should not have anyoverlap.

(2) The 5-bit counter: it can add or subtract according tothe comparator results to get the correct digital offsetcode. It is the core of the calibration circuit.

(3) The DFF array: the DFF array can be used to storethe offset voltage in digital form. As one channel ofpreamp calibration needs five DFFs, as mentionedabove, there are 16 channels which need to be cali-brated, so altogether there are 80 DFFs used in here.

(4) The digital-to-analog converters (DACs): the DACsare used to translate the stored digital form offset intoanalog and compensate for the actual offset of theADC.Here, the simple binary currentDAC is adoptedto reduce power and area.

In the simulation, one of the sixteen preamps’ differentialchannels were made to be different. From Figure 8 it can beseen that the channel goes into calibration in 250 ns. Becauseof the mismatch, at first the differential output of the pream-plifier is larger than 150mV, when the calibration ended, theoutput approaches zero, and the output of the comparatorchanges between 0s and 1s.The stored offset in this DFF arrayis between 10101 and 10110, shown in Figure 9.The simulationresults demonstrate that the calibration circuit works all right.


0 200 400 600

0.00

0.42

0.84

1.26

0 200 400 600

0

93

186

Volta

ge (m

V)

Volta

ge (V

)

Time (ns)

−93

Figure 8: Output of preamp and comparator during calibration.

0 200 400 6000.000.420.841.260.000.420.841.260.000.420.841.260.000.410.821.230.000.390.781.17

Time (ns)

V(V

)V

(V)

V(V

)V

(V)

V(V

)

Figure 9: The offset stored in DFFs.


Table 1: Postsimulation results of F&I ADC and comparison with others.

Performance [3] [4] [5] [6] This workTechnology 0.18 𝜇m CMOS 0.18 𝜇m CMOS 90 nm CMOS 90 nm CMOS 90 nm CMOSSupply (V) 1.8 1.8 1 1.2 1.2Clock (GHz) 1.6 1 2.7 1 2SFDR (dB) 56 68.6 28.87 50.84SNDR (dB) 46 56.5 33.6 27.35 45.93Power (mW) 774 1260/channel 50 7.65 210Area (mm2) 3.6 49 (dual ADC) 0.36 0.063 0.865

Figure 10: Layout of the F&I ADC.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5Frequency (f/fs)

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

Am

plitu

de (d

BV)

= 128, ENOB = 7.338, SNDR = 45.93 dB,= 50.84 dBSFDR

Sample point

Figure 11: The spectrum of the ADC (Nyquist @2GSps).

3. Layout and Simulation Results of the ADC

The ADC is designed in TSMC 90 nm CMOS technology.The layout is presented in Figure 10. Its area is 930 𝜇m ×930 𝜇m. For the sampling rate of 2GSps, Nyquist input signalfrequency, the FFT results show that the effective numberof bits (ENOB) is 7.338 bit, presented in Figure 11. For input

signal frequency smaller than 1GHz, the SNDR is better than45.93 dB, which shows that the ADC has a good dynamicperformance.

The ADC’s performance and comparison with otherpublished ones are presented in Table 1.

4. Conclusions

In this paper, a single channel 2GSps, 8-bit F&I ADC withforeground calibration in TSMC 90 nm CMOS technologyis presented. The ADC utilizes cascaded folding, with fore-ground digital assisted calibration to correct the error of zero-crossing point caused by the circuit offset. Chip area of thewhole ADC including pads is 930𝜇m × 930 𝜇m. Postsimu-lation results demonstrate that, under a single supply of 1.2volts, the power consumption is 210mW. For the samplingrate of 2GSps, the SNDR is 45.93 dB for Nyquist input.

Competing Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper.

Acknowledgments

The research was supported by Scientific Research Founda-tion of Nanjing University of Posts and Telecommunications(NUPTSF Grants no. NY213076 and no. NY215138) andOpen Project of State Key Laboratory of Millimeter Waves,Southeast University (no. K201727).

References

[1] H. Yu, A 1V 2.5GS/S 8-bit self-calibrated flash ADC in 90 nm GPCMOS [Ph.D. thesis], UCLA, 2008.

[2] K. Poulton, R. Neff, B. Setterberg et al., “A 20GS/s 8b ADC witha 1MB memory in 0.18 𝜇m CMOS,” in Proceedings of the IEEEInternational Solid-State Circuits Conference (ISSCC ’03), p. 318,February 2003.

[3] R. C. Taft, C. A. Menkus, M. R. Tursi, O. Hidri, and V. Pons,“A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with7.26 ENOB at Nyquist frequency,” IEEE Journal of Solid-StateCircuits, vol. 39, no. 12, pp. 2107–2115, 2004.

[4] R. C. Taft, P. A. Francese, M. R. Tursi et al., “A 1.8 V 1.0 GS/s10b self-calibrating unified-folding-interpolating ADC With9.1 ENOB at nyquist frequency,” IEEE Journal of Solid-StateCircuits, vol. 44, no. 12, pp. 3294–3304, 2009.


[5] Y. Nakajima, A. Sakaguchi, T. Ohkido, N. Kato, T. Matsumoto,and M. Yotsuyanagi, “A background self-calibrated 6b 2.7 GS/sADC with cascade-calibrated folding-interpolating architec-ture,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 707–718, 2010.

[6] S. D’Amico, G. Cocciolo, A. Spagnolo, M. De Matteis, and A.Baschirotto, “A 7.65-mW 5-bit 90-nm 1-Gs/s folded interpolatedADC without calibration,” IEEE Transactions on Instrumenta-tion and Measurement, vol. 63, no. 2, pp. 295–303, 2014.

[7] A. Razzaghi,A single-channel 10b 1GS/sADCwith 2-cycle latencyusing pipelined cascaded folding architecture [Ph.D. thesis],UCLA, 2008.

[8] H. Liu, Z. Wang, Q. Meng, and K. Tang, “Comparison ofthe Gray and binary encoders in high-speed ADC,” Journal ofSoutheast University (Natural Science Edition), vol. 40, no. 3, pp.454–458, 2010.

[9] C.-C. Hsu, C.-C. Huang, Y.-H. Lin, and C.-C. Lee, “A 10b200MS/s pipelined folding ADC with offset calibration,” inProceedings of the 33rd European Solid-State Circuits Confer-ence (ESSCIRC ’07), pp. 151–154, IEEE, Muenchen, Germany,September 2007.

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A 2GSps, 8-Bit Folding and Interpolation ADC with ...downloads.hindawi.com/journals/js/2017/3984526.pdf · A 2GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration