A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS

Technology

Shahriar ShahramianSorin P. Voinigescu

Anthony Chan Carusone

Department of Electrical & Computer Eng.University of Toronto

Canada

Introduction & Motivation I

Digital EqualizerPhoto

Detector

T/H

ADC

AdaptiveEqualizer

ClockRecovery

EqualizedData

• Equalization required at high bit rates• Analog equalization up to 40 Gb/s• Digital equalization is more robust and flexible

• Require full rate Track & Hold Amplifiers

Introduction & Motivation II• Demonstrated 40-GS/sec THA in SiGe BiCMOS

– fT and fMAX of 160 GHz

• CMOS technologies scaling to nanometre– fT and fMAX exceed 200 GHz for in production CMOS

• CMOS is a serious contender for implementing DSP based equalizers above 10 Gb/s

Introduction & Motivation III

• High speed• Low dynamic range• Requires diodes

• High speed• Lower supply• Isolation in hold mode

Diode Sampling Bridge Switched Emitter Follower

J. C. Jensen, et. al.CICC 02

S. Shahramian, et. al.CSICS 05

Introduction & Motivation IV

• Low supply• Low speed due to

series CMOS RON

• Take advantage of high speed CMOS source follower

Series CMOS Sampler Switched Source Follower

I. H. Wang, et. al.Electronic Letters 06

This workCICC 06

0.13-µm CMOS Technology• Simulated fT and

fMAX of 80 GHz• 8 layer

metallization back end with thick RF top metal layers

• Available triple-well CMOS transistors

• Available low power (high VTH) transistors

THA Block DiagramC

lock TIA CML

INVCMLINV

CM

LIN

VClock Path

CS

CS

TIACS

Diff.Pair

Diff.Pair

Data PathIn

put

Output

T/HCS

DRV

DRV

Input Stage DesignTIA

Active loads

Improve open loop

Gain, T

Eliminating current

source transistor

reduces power

supply voltage

Input Stage DesignTIA

Signal matching

through resistive

feedback

Input Stage DesignTIA

50ΩT1

RZ Fin

Noise matching

through transistor

sizing

Input Stage DesignTIA

22C

o2oF

OPT

BGRG

RZ1

ω1R1

ω1W

Transistors biased

at J = 0.25 mA/µm,

increased noise

figure for higher

bandwidth

Input Stage DesignTIA

Simulated bandwidth: 30 GHzSimulated input integrated noise over 30 GHz: 0.5 mVrms

Inductors improve

bandwidth, input

matching and filter

high frequency

noise

Input Stage DesignTIA

Input Stage DesignTIA

CS

CS

Transistors Q1 and Q2 are diode-connected at DC and

therefore can bias the next CS stage

Switched source

follower for maximum

bandwidth

THA Stage DesignT/H

THA Stage DesignT/H

During Track, QSF acts

as a source follower

with current IT

THA Stage DesignT/H

During Hold, IT flows

through RL which turns

QSF off and isolates CH

THA Stage DesignT/H

QT and QH operate in

digital mode and

thus are biased at

J = 0.15mA/µm

High VTH devices are

used to drive QT further

into “OFF” region and

reduce leakage

THA Stage DesignT/H

QSF is implemented as a

triple well transistor to

reduce VEFF and lower

power supply voltage

THA Stage DesignT/H

A linear buffer drives the T/H block with 600mVPP

input and output swing

THA Stage DesignT/HDiff.

Pair

Capacitor Cfth is used to match QSF-CGS and thus cancel

input signal feedthrough during hold mode

THA Stage DesignT/HDiff.

Pair

A linear output driver provides signal to external

50Ω resistors and measurement equipment

THA Stage DesignT/HDiff.

Pair

DRV

DRV

Clock Distribution CMLINV

CMLINV

CMLINV

Converts a single-ended 30-GHz clock signal

to a differential signal with 750mVPP swing

Chip Micrograph• Manufactured

using IBM’s 0.13µm CMOS technology

• The circuit operates from a 1.8V supply and consumes 150mA.

1mm

1mm

TIA

CS

CML INV

TIA CS

DR

V

THA

Diff

. Pai

r

Diff

. Pai

r

CML INV

CML INV

Measurement Results: SP

Measurement Results: SP II

Time Domain

Frequency Domain I

Frequency Domain II

Frequency Domain III

Circuit Comparisonfsample

[GS/s]

Track BW[GHz]

THD[dB @ fin]

Supply[V]

Power[mW]

Process[N / fT]

This Work 30 7 -30 @ 1GHz-29 @ 7GHz

1.8 270 CMOS0.13µm

I. H. Wang el. al.Electronic Letters 06

10 N/A -24.7 @ 5GHz 1.8 200 CMOS0.18µm

J. Lee et. al.JSSC 03

12 14 -23.3 @ 12GHz -5.2 390 InP120 GHz

S. Shahramian et al.CSICS 05

40 43 -27 @ 20GHz-29 @ 10GHz

3.6 540 SiGe160 GHz

Y. Lu et. al.BCTM 05

12 5.5 -52.4 @ 1.5GHz 3.5 700 SiGe200 GHz

Conclusion• CMOS emerges as a contender for high speed

DSP based equalizers• Discussed the design methodology for CMOS

switched source follower THA• Demonstrated the first 30-GS/sec THA in CMOS

Acknowledgement• CMC for chip fabrication and providing CAD

tools• NSERC for financial support• OIT and CFI for equipment• ECIT for providing the network analyzer