JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, 2018 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2018.18.2.281 ISSN(Online) 2233-4866

Manuscript received Jul. 29, 2017; accepted Sep. 26, 2017 School of electrical and computer engineering, Ulsan National Institute of Science and Technology, Ulsan, Korea E-mail : jaejoon@unist.ac.kr

A 4b/cycle Flash-assisted SAR ADC with Comparator Speed-boosting Technique

Kyeonghwan Park, Chansam Park, and Jae Joon Kim

Abstract—This paper presents flash-assisted successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient speed-boosting structure. The incorporation of a 3-bit flash sub-ADC into the SAR conversion path enables 4b/cycle conversion. For further speed boosting, the comparator is designed to include an auxiliary bootstrap capacitor which relieves settling-time bottleneck of capacitive digital-to-analog converters (C-DACs) in asynchronous SAR operation. This 4b/cycle conversion scheme requires only five switching events of C-DACs switching for 8-bit conversion, resulting in 22.32% reduction of additional switching energy. Prototype circuit implementation reveals that the proposed scheme achieves 75% speed enhancement compared to a conventional SAR scheme. For feasibility verification, the proposed flash-assisted SAR ADC was fabricated using a 0.18 mm CMOS process. Measured signal-to-noise and distortion (SNDR) and spurious-free dynamic range (SFDR) of the prototype were 48.49 dB and 64.95 dB respectively. Index Terms—Flash-assisted SAR ADC, 4b/cycle conversion, comparator speed-boosting technique, switching energy, auxiliary bootstrap capacitor

I. INTRODUCTION

Successive approximation register (SAR) analog-to-

digital converters (ADCs) are suitable for low-power applications including wearable devices and wireless sensors. However, there is inherent speed limitation in the SAR ADC architecture because it needs at least N cycle for N bit conversion. Although it can be expanded by time-interleaving, flash-assisted or pipeline schemes [1-4], there needs to improve its inherent power consumption and efficiency. Recently, multi-bit/cycle conversion structures have been introduced to address efficiency, which are implemented by utilizing multiple capacitive digital-to-analog converters (C-DACs) and complex switching algorithm [5] or additional reference generator and comparator [6]. However, the multiple C-DACs structure causes multiple switching energy and area, which is not cost-effective. Complex control blocks are also required for complex switching algorithm. The additional comparator and reference structure requires 2N-1 comparators for the N bit/cycle conversion, and the N value is mostly limited to be below 3-bit. The ADC efficiency has trade-off relationship among speed, power consumption, and area. Thus, if the sampling rate can be improved without increasing the power consumption greatly, the efficiency also would be improved. At the same time, it would be better if the area can be reduced by reducing the number of components.

In this work, we propose a 4-bit/cycle flash-assisted structured SAR ADC that requires about half the number of comparators and only N-3 times C-DAC switching events for N-bit conversion. The C-DAC settling problem, which limits high-speed operation, is tackled by improving the comparator speed through a proposed comparator speed-boosting technique. Section II presents the architecture of this work, and Section III shows its circuit implementation. Section IV and V give

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measurement results and conclusion.

II. PROPOSED ARCHITECTURE

Fig. 1(a) describes a proposed flash-assisted SAR ADC with only 5-bit C-DAC switching for 8-bit conversion, where only single-ended structure is shown for better understanding, but actual implementation is fully differential. It consists of an 8-bit segmented DAC, a time-domain comparator, a 3-bit flash sub-ADC and a SAR logic. Fig. 1(b) presents the operational timing diagram of the proposed ADC. A clock is divided into two phases: one is used as the SAR ADC clock, and the anti-phase is used for the flash sub-ADC to perform a synchronous operation. During the anti-phase clock after MSB decision of the SAR ADC, the flash sub-ADC operates to perform the next 3-bit conversion from the MSB residue which are directly reflected to the segmented DAC. Then, the next SAR conversion for MSB-4 bit starts again and the same operation of the anti-phase flash sub-ADC follows. In this way, 4-bit/cycle flash-assisted SAR conversion is performed. For convenient implementation, the segmented DAC is designed to have thermometer-coded structure [7] for MSB-1 to MSB-3 and MSB-5 to MSB-7 bits so that 3-bit thermometer outputs of the flash sub-ADC can be directly used for the SAR DAC.

The last 3 bits are digitized in the flash sub-ADC, and it does not require additional switching operations of the SAR C-DAC. Therefore, the proposed algorithm can reduce the switching energy. If this work adopts other enhancement methods such as the monotonic [8] and the partial floating switching [9], its switching energy would be further reduced. For low-power applications, neither the dynamic element matching nor calibration technique are implemented in the C-DAC. The 3-bit flash sub-ADC consists of seven differential comparators and single resistor string for differential reference generation. The linearity can be improved by comparing the difference between the two inputs with no mismatch error from single resistor string. For improving energy efficiency and relaxing the C-DAC settling issues, the asynchronous SAR logic is also provided, that is, the C-DACs are switched right after the comparator result comes out. Consequentially, the C-DAC can have settling-time as much as possible for high-speed

operation. Since 4-bit conversion is performed for one SAR cycle, the proposed 4-bit/cycle flash-assisted SAR ADC can reduce 75% conversion time in conventional SAR ADCs.

III. CIRCUIT IMPLEMENTATION

The proposed SAR ADC is energy efficient structure, but still requires the C-DAC settling-time at a high sampling rate [10]. As the sampling rate increases, overall performance degradation may occur due to settling problem of C-DAC. To relax this C-DAC settling requirement, a comparator-speed boosting technique with auxiliary bootstrap capacitors Cboot is proposed in Fig. 2. A time-domain comparator is compared with the time difference of the rising edge of output according to the inputs. Reset and comparison phase are existed by clock as dynamic comparator. During the reset phase of the comparator, the auxiliary bootstrap capacitor has no potential difference between two terminals of capacitor, and the actual charge amount is zero. In other words, two

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(a)

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Fig. 1. 4b/cycle flash-assisted SAR ADC (a) architecture, (b) timing diagram.

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terminals of Cboot are connected to VDD during the reset phase. However, if the bottom plate switches to ground during the comparison phase, then node A and B voltages are discharged instantaneously, and the turn-on time of M7 and M8 can be reduced. Thus, node A and B reach the threshold voltage of M7 and M8 faster than when there is no bootstrap capacitor. Based on this speed boosting technique, it is possible to boost the comparison speed. Therefore, the proposed SAR ADC operates in high sampling rate and reduces settling bottleneck by using the auxiliary bootstrap capacitor. Its simulation results are compared with conventional schemes as shown in Fig. 3. With 2 mV input difference and 14 MHz clock, the comparator response time was improved from 1.317 ns to 0.292 ns by activating the auxiliary bootstrap capacitor. In this way, it can improve the overall speed by eliminating the settling bottleneck in the proposed flash assisted SAR ADC architecture.

Fig. 4 presents the efficiency of the proposed scheme. In the proposed scheme, the efficiency can be changed according to the resolution of the flash sub-ADC. The efficiency of the ADC architecture can be evaluated as a high speed and resolution with small energy consumption. The efficiency index is defined in Fig. 4, where α is the influence factor of the energy that is consumed by a comparator during conversion time versus the C-DAC switching energy. The efficiency index which is modified figure-of-merits expresses the energy efficiency of the ADC architecture and thus the smaller value of efficiency index is the more efficient structure. In Fig. 4, the efficiency index of the proposed architecture was compared with those of conventional and multi-bit SAR

ADCs. Each ADC is assumed to have the same ENOB, sampling rate. The comparator power consumption and Switching energy per conversion cycle are also equal. Thus, the overall comparator power consumption following to the conversion cycle is expressed using Tconv. The optimal structure was obtained by calculating the efficiency index with the switching energy and Tconv. According to the efficiency index, the conventional SAR ADC was 12.28 and the 4-bit flash ADC was 13.6. The 4-bit flash ADC has a larger increase in power consumption than the number of bits that can be converted at one cycle. The efficiency index of the proposed 1-bit SAR operation with 3-bit flash sub-ADC structure was the highest efficient value at 8.89. The 4b/cycle scheme which assisted 3-bit flash sub-ADC is

Fig. 2. Comparator speed boosting technique.

Fig. 3. Simulation results of speed boosting with auxiliary bootstrap capacitor.

Fig. 4. Comparison results of efficiency index with conventional architecture and other structures.

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one of efficient methodology of multi-bit conversion. Fig. 5 presents the proposed switching energy

including the reset phase against VCM-based switching method [11]. As the conversion cycle decreased, the comparison switching energy was compared to figure out the effect of energy saving. The VCM-based switching algorithm can be used to design the proposed ADC, and the degree of saving the energy dissipation can be compared when the scheme is applied. The results are originated from MATLAB behavioral simulations through digital code sweep. The average switching energy of the proposed DAC is 32.375 CV2ref which reflects 23.22% average switching energy reduction against VCM-based switching method. According to the digital code of the proposed conversion, an energy savings up to 39% was achieved. Additional energy savings can be expected if monotonic switching in [8] or several efficient switching algorithms in [9] are applied to the proposed flash-assisted SAR ADC scheme.

IV. MEASUREMENT RESULTS

A prototype of the proposed 4b/cycle flash-assisted SAR ADC for efficient multi-bit conversion was fabricated in a 0.18 μm CMOS process. Fig. 6 shows its chip microphotograph including 8-bit segmented DACs, a flash sub-ADC, a time-domain comparator and a SAR logic, whose core area is 970 μm x 540 μm. In the time-domain comparator, the comparator-speed boosting technique was implemented to be automatically controlled by a synchronized comparator reset signal. The reference resistor string for the flash sub-ADC was

implemented with unit resistors of 1.4 kΩ, which consumes maximum current consumption of 320 μA, resulting in 1.2 mW power consumption of the Flash sub-ADC. The overall power consumption of the proposed flash-assisted SAR ADC was 1.6 mW under a 1.8 V power supply, achieving 75% reduction of conversion time versus conventional SAR ADCs.

The measured fast Fourier transform (FFT) spectrum analysis are shown in Fig. 7. When the sampling rate is at

Fig. 5. Additional switching energy saving with proposed scheme.

Fig. 6. Chip microphotograph.

Fig. 7. Dynamic performance.

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25 MS/s, the signal-to-noise plus distortion ratio (SNDR), spurious free dynamic range (SFDR) and effective number of bit (ENOB) with a 9.77 MHz differential sine-wave inputs were 48.49 dB, 64.95 dB and 7.76 bit, respectively. The lower part of Fig. 7 shows dynamic performance of SNDR and SFDR with respect to sampling rate up to 25 MS/s, where the measure SNDR variation is almost less than 1 dB. This speed enhancement was achieved due to the auxiliary bootstrap capacitor for comparator speed boosting technique. Table 1 summarizes the measured characteristics of the proposed ADC, including the performance comparison with previous works. Since the proposed flash-assisted SAR architecture reduced overall power consumption considerably, relatively comparable Walden figure-of-merit (FoM) of 295 fJ/conversion was achieved.

V. CONCLUSIONS

A 4-bit/cycle SAR conversion structure that utilizes the assistance of the flash sub-ADC and the comparator speed-boosting technique was proposed to improve both speed and power efficiency of previous multi-bit/cycle SAR ADCs. Its prototype design revealed that the ADC conversion time was reduced by 75% and the additional switching energy was also reduced by 23.22%, compared with conventional SAR ADCs.

ACKNOWLEDGMENTS

This research was supported by the Technology Innovation Program (10054548: Development of suspended heterogeneous nanostructure-based hazardous gas microsensor system) funded by the Ministry of Trade, Industry and Energy, South Korea.

REFERENCES

[1] B., Jang, et al, “A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR,” Microelectronics Journal, Vol. 62, pp. 79-84, Feb., 2017

[2] U.-F., Chio et al, “Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC,” Circuits and Systems II, IEEE Transactions on, Vol. 57, No. 8, pp. 607-611, Aug., 2010.

[3] C.-J., Tseng et al, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration,” Circuits and Systems I, IEEE Transactions on, Vol. 61, No. 10, pp. 2805-2815, Oct., 2014.

[4] J., Pernillo et al, “A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS,” Circuits and Systems II, IEEE Transactions on, Vol. 58, No. 12, pp. 837-841, Dec., 2011.

[5] C.-H., Chan, et al, “A 5.5mW 6b 5GS/s 4x-Interleaved 3b/cycle SAR ADC in 65nm CMOS,” Solid-State Circuits Conference, 2015. ISSCC 2015. Digest of Technical Papers. IEEE Inter-national, 22-26, pp. 466-468, Feb. 2015.

[6] H.-K., Hong, et al, “A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/cycle SAR ADC,” Solid-State Circuits, IEEE Journal of, Vol. 50, No. 2, pp. 543-555, Feb., 2015.

[7] P., Harpe, et al, “An Oversampled 12/14b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.1dB SNDR,” Solid-State Circuits Conference, 2014. ISSCC 2014. Digest of Technical Papers. IEEE Inter-national, 9-13, pp. 194-196, Feb.

[8] Z., Zhu, et al, “Vcm-based monotonic capacitor switching scheme for SAR ADC,” Electronics Letters, Vol. 49, No. 5, pp. 327-329, Feb., 2013.

[9] Y., Zhang, et al, “Energy-efficient switching method for SAR ADCs with bottom plate sampling,” Electronics Letters, Vol. 52, No. 9, pp. 690-692, Apr., 2016.

[10] T.-H., Tsai, et al, “An 8b 700 MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique,” Circuits and Systems I, IEEE Transactions on, Vol. 63, No. 5, pp. 683-692, May, 2016.

Table 1. ADC performance summary and comparison

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[11] Y., Zhu, et al, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” Solid-State Circuits, IEEE Journal of, Vol. 45, No. 6, pp. 1111-1121, Jun., 2010.

Kyeonghwan Park was born in Yangsan, Korea, in 1991. He received the B.S. degree in the Department of Electrical and Computer Engineering from Ulsan National Institute of Science and Technology (UNIST), Korea, in 2013.

He is currently pursuing the Ph.D. degree in the Department of Electrical and Computer Engineering from Ulsan National Institute of Science and Technology (UNIST), Korea. His research interests include Successive Approximation Register Analog-to-Digital Converter and sensor systems.

Chansam Park was born in Seoul, Korea, in 1994. He received the B.S. degree in the Department of Electrical and Computer Engineering from Ulsan National Institute of Science and Technology (UNIST), Korea, in 2017. He is currently

pursuing the Combined Master’s and Ph.D. degree in the Department of Electrical and Computer Engineering from Ulsan National Institute of Science and Technology (UNIST), Korea. His research interests include temperature sensor, sensor systems.

Jae Joon Kim received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 1996 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in

1998 and 2003, respectively. From 2000 to 2001, he was with Berkana Wireless Inc., San Jose, CA (now merged into Qualcomm Inc.), where he was involved in designing wireless transceivers. From 2003 to 2005, he was with Hynix Semiconductor, Seoul, working on wireless transceivers and smart-card controllers. From 2005 to 2011, he was a Deputy Director with the Korean government, Ministry of Information and Communications and also Ministry of Trade, Industry & Energy. From 2009 to 2011, he was also with Georgia Institute of Technology, Atlanta, GA as a research engineer II. Since 2011, he has been an Associate Professor with Ulsan National Institute of Science and Technology, Ulsan, Korea. His research interests include integrated circuits for various sensor systems, wireless transceivers, consumer electronics, biomedical appliances, and automotive electronics