134 IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 1, NO. 5, MAY 2018

A 6.1-nW Wake-Up Receiver Achieving −80.5-dBm Sensitivity Viaa Passive Pseudo-Balun Envelope Detector

Po-Han Peter Wang , Student Member, IEEE, Haowei Jiang , Student Member, IEEE,Li Gao , Student Member, IEEE, Pinar Sen , Student Member, IEEE, Young-Han Kim , Fellow, IEEE,

Gabriel M. Rebeiz, Fellow, IEEE, Patrick P. Mercier , Senior Member, IEEE, and Drew A. Hall , Member, IEEE

Abstract—A wake-up receiver (WuRX) that achieves −80.5-dBmsensitivity with only 6.1 nW of power is presented. High sensitivity isachieved via a passive pseudo-balun envelope detector (ED) with a highinput impedance (>750 k� ‖ <1.4 pF) that enables a 30.6-dB pas-sive voltage gain transformer while providing differential output andimproving the conversion gain by 2× compared to a conventional single-ended input passive ED for a given input capacitance. The WuRX isimplemented in a 180-nm CMOS process and operates from a 0.4-Vsupply.

Index Terms—Low-power wide-area network (LPWAN), low-powerwireless, wake-up radios, wake-up receivers (WuRXs).

I. INTRODUCTION

Low-power wide-area networks are a key component of futuresmart cities where infrastructure will be connected via an Internet ofEverything. Many such connected devices (e.g., smart meters, envi-ronmental sensors, and threat monitors) must operate for years fromsmall batteries or energy harvesters, and communicate over long dis-tances. This necessitates inclusion of ultralow power radios with highsensitivity—two parameters that generally trade off directly with eachother.

One way to significantly reduce average power consumption, par-ticularly in event-driven networks with low-average throughput, is toreplace energy expensive synchronization routines of the main radiowith a low power, always-on wake-up receiver (WuRX). However,reducing the WuRX power below that of the main radio typi-cally comes at the cost of reduced sensitivity via a low-complexitydirect-envelope detector (ED) architecture (e.g., −45 dBm sensitiv-ity at 116 nW [1]). Unfortunately, compromising sensitivity is notpragmatic, as network coverage is limited by the least sensitivereceiver.

Reducing the data rate (i.e., baseband bandwidth) is an effectivetechnique to improve the sensitivity of a WuRX. The most importantmetrics for WuRXs in low-average throughput applications are thepower and sensitivity; data rate (and thus wake-up latency) is oftenappropriate to compromise in applications that communicate at lowduty-cycles. In other words, energy/bit is not the most appropriatemetric for WuRXs. Prior work has shown that through a combina-tion of low carrier frequency operation (i.e., FM-band) and reducingthe WuRX data rate, large passive RF voltage gain (at the expenseof larger passive components) when combined with a high inputimpedance active ED results in improved sensitivity at extremely lowpower (e.g., −69 dBm at 4.5 nW [2], [3]), with wake-up latenciesthat still support the needs of low-average throughput applications.

Manuscript received April 25, 2018; revised June 22, 2018 and July 30,2018; accepted August 7, 2018. Date of publication October 12, 2018; dateof current version November 14, 2018. This paper was approved by AssociateEditor Howard Cam Luong. This work was supported by DARPA underContract HR0011-15-C-0134. (Corresponding author: Drew A. Hall.)

The authors are with the Department of Electrical and ComputerEngineering, University of California at San Diego, La Jolla, CA 92093 USA(e-mail: pmercier@ucsd.edu; drewhall@ucsd.edu).

Digital Object Identifier 10.1109/LSSC.2018.2875826

Fig. 1. Block diagram of the proposed WuRX.

Despite these improvements, WuRX sensitivity still lags that of mostmain radios, and must be further improved upon. Since the ED isthe dominant noise source in a direct-ED receiver [3], recent workhas shown that by implementing a multistage passive ED architec-ture, which, unlike active EDs, does not have any 1/f noise [4], highsensitivity at sub-10 nW is possible (i.e., −76 dBm at 7.6 nW [5]).

This letter presents the design of a WuRX that achieves−80.5-dBm sensitivity with only 6.1 nW by:

1) arranging the passive ED in a pseudo-balun topology to performsingle-ended to differential conversion and improve the con-version gain by 2× compared to a conventional single-endedpassive ED for a given input capacitance under the same inputsignal level [1], [5];

2) using higher Vt devices than in conventional passiveEDs [1], [6] to increase the effective input resistance as wellas a body-biasing technique to reduce the input capacitance,which enables the design of a passive voltage gain impedancetransformer with 30.6 dB gain;

3) using a current-reuse baseband amplifier with asymmetricpseudo-resistors that increase the amplifier input impedancewhile avoiding prohibitively long start-up time.

The proposed WuRX architecture along with the passive pseudo-balun ED are described in Section II, while Section III presents themeasurement results and concludes this letter.

II. SYSTEM AND CIRCUITS IMPLEMENTATION

In this section, we present the working principle of each circuitblock. Fig. 1 shows a block diagram of the proposed WuRX archi-tecture where an OOK-modulated waveform is amplified and filteredby a high-Q passive transformer/filter. To support the passive gain,the ED must provide large enough Rin to not degrade the equivalentRp of the transformer. Active EDs [2], [3], [7] offer Rin>100’s of k�

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WANG et al.: 6.1-nW WuRX ACHIEVING −80.5-dBm SENSITIVITY VIA PASSIVE PSEUDO-BALUN ED 135

(a)

(b)

Fig. 2. (a) Conventional passive ED unit cells and architectures. (b) Proposedpassive pseudo-balun ED with bulk tuning unit cell.

with wide bandwidths, but suffer from 1/f noise. Passive EDs, on theother hand, were historically designed with low-Vt devices [6] orwith standard high-Vt devices along with Vt-cancelation techniquesto maximize power (not voltage) conversion efficiency, which resultsin a small Rin. By using higher Vt devices, passive EDs can achievecomparable Rin to active EDs, and, most importantly, do not haveany 1/f noise [4] since there are no dc currents. This permits smallerdevices and thus lower input capacitance, Cin. As such, the proposedpassive ED has a lower noise-equivalent power and lower Cin thanthe active ED in [2] and [3]. The lower Cin allows for a larger sec-ondary coil (at the same carrier frequency), resulting in 30.6 dB ofpassive gain. The ED output is fed to a low-noise baseband amplifierfollowed by a tunable comparator and a 36-bit digital correlator, bothclocked by a relaxation oscillator. The hamming distance between the6× oversampled code and a programmable code is compared againsta programmable threshold to determine a wake-up event.

A. Passive Pseudo-Balun Envelope Detector

Fig. 2(a) and (b) depict conventional and the proposed passive EDunit cells and architectures. Cross-coupled self-mixers [4] rectify adifferential input signal and thus require a center-tapped transformer,which results in lower Q and thus lower passive gain compared to asingle-ended design. Moreover, biasing is implemented using an extraRC network at the RF node that reduces the ED input impedance.On the other hand, a traditional Dickson rectifier operating in sub-Vt [1], [5] can rectify a single-ended input signal, but does not haveany tunability and only has a single-ended output, which requiresa tunable reference circuit for the comparator. To overcome theseissues, a tunable passive pseudo-balun ED architecture is proposed,which is a 2N-stage rectifier with the middle node connected to VCMand the bulk nodes connected to a tunable voltage, Vbulk, to set thebandwidth [Fig. 2(b)]. As such, the baseband ac currents flow inopposite directions relative to ground to form a pseudo-differentialoutput. Compared to the original single-branch N-stage Dicksonrectifier, this structure achieves 2× conversion gain and a 1.5-dBsensitivity improvement under the same input signal level without

(a) (b)

(c) (d)

Fig. 3. Simulation results of ED tradeoffs for N stages with a fixed output

bandwidth: (a) Rin and AV versus Cin, (b) kED and√

v2n versus N, (c) passive

ED SNRED,norm, and (d) N = 5 stages ED tradeoffs for different Vbulk.

sacrificing output bandwidth. Although the second branch of the N-stage ED could be connected in parallel with the first branch withoutflipping the polarity, this results in the same 1.5-dB improvement insensitivity, but only half of the conversion gain and is single-ended.Vbulk is provided by a diode-connected reference ladder with 4-bittunability.

To drive a fixed capacitive load from the baseband amplifier, anED with a large number of stages, N, requires larger transistor widthsto maintain the same output bandwidth, and thus has a larger Cin,which limits the achievable transformer gain. As the transistor widthincreases, the parasitic capacitance from the ED starts to add on tothe fixed capacitive load at the output node, which thus requires Routto decrease further. As shown in Fig. 3(a), larger transformer pas-sive voltage gain, AV, is possible with small N, which has higherRin and lower Cin. However, as shown in Fig. 3(b), since the con-version gain and thus ED scaling factor, kED, are proportional toN, an ED with large N is more suitable for post-ED stage noisesuppression. Moreover, since the passive ED noise power density is

4kBTRout, an ED with a larger N has less total integrated noise,√

v2n.

To find the optimum N, an objective function was developed to com-pare designs with different N under the same output bandwidth andoperating frequency

SNRED,norm = A2V · kED√

v2n

· 10−9 (1)

which is essentially the achievable ED output SNR normalized to itsinput voltage. As shown in Fig. 3(c), an optimum value of N = 5was found for the ED using this equation. On the other hand, theproposed bulk tuning can not only be used to overcome process vari-ation, but can also effectively reduce Cin via smaller devices for anequivalent output bandwidth, and therefore maximize the achievablepassive voltage gain at a given carrier frequency. It is depicted inFig. 3(d) that by forward biasing the bulk-to-source junction diode(< 200 mV), Vt is reduced and allows smaller width transistors to beimplemented for a given output bandwidth (33.3 Hz in this design).Although the proposed ED could be designed with pMOS devicesin a process without a deep N-well, nMOS is adopted in this design

136 IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 1, NO. 5, MAY 2018

(a) (b) (c)

Fig. 4. Schematic of (a) ac-coupled baseband amplifier and (b) fast start-up pseudo-resistor. (c) Simulated and measured resistance and start-up time.

(a) (b) (c)

(e)(d)

Fig. 5. Measurement results showing: (a) power breakdown, (b) transient waveforms for a wake-up event, (c) S11, (d) MDR versus input signal power, and(e) OOK-modulated interferer power versus frequency.

to leverage the higher mobility and thus lower transistor size for agiven output bandwidth.

B. Baseband Circuitry and Coding

With a passive ED, most of the power can be devoted to the sub-sequent baseband amplifier to minimize its noise. A continuous-timeamplifier was implemented using a self-biased, inverter-based struc-ture [Fig. 4(a)]. Both the input and output are ac-coupled to removedc offset, filter 1/f noise, and band-limit the signal. Given the largeED output impedance (> 1G�), the amplifier input capacitance mustbe low enough to maintain the baseband bandwidth while also bal-ancing the 1/f noise. Neutralization capacitors were used to mitigatethe Miller effect and reduce the input capacitance from 12 to 0.4 pF.To not degrade the ED gain, the pseudo-resistors used for biasingneed to be > 1T�, which, when implemented using conventionaltechniques, led to a long start-up time (> 400 s) that could bean issue deploying the WuRX in some applications. An asymmetricpseudo-resistor is proposed that leverages the high nonlinear voltagedependence to speed up settling. When the supply is ramping up, nodeB is rapidly pulled to VDD, while node A (without a dc path to thesupply) stays near ground. As shown in Fig. 4(b), this drives M3−4

into subthreshold triode with reduced Vt (VSG = VSB ∼ VDD/2 andVSD ∼ 0) and thus lower dc resistance (50× lower than a conven-tional implementation), allowing 12× faster startup. Once VSG andVSB approach zero, the pseudo-resistor returns to the high resistancestate so as to not affect the small-signal resistance [Fig. 4(c)].

The output of the baseband amplifier is digitized by a comparatorimplemented using a dynamic gm-C integrator with two 6-bit tun-able load capacitor arrays to adjust the threshold voltage [7]. Using abaseband amplifier relaxes the required tunable threshold step size inthe comparator (i.e., 100’s of μV instead of a few μV), allowing itto be lower power. The 36-bit digital correlator is implemented usingcustom logic cells and computes the Hamming distance between theincoming code and a programmable code. The 200-Hz clock for thecomparator and digital correlator is generated by a relaxation oscil-lator consuming only 520 pW. To overcome phase asynchronization,the baseband signal is oversampled by 6×, and the designed patternprovides 2.5-dB coding gain.

III. MEASUREMENT RESULTS AND CONCLUSION

This circuit was fabricated in a 0.18-μm CMOS process and con-sumes 6.1 nW [Fig. 5(a)]. Measured transient waveforms are shown

WANG et al.: 6.1-nW WuRX ACHIEVING −80.5-dBm SENSITIVITY VIA PASSIVE PSEUDO-BALUN ED 137

TABLE IPERFORMANCE COMPARISON OF STATE-OF-THE-ART SUB-300-NANOWATT WURXS

Fig. 6. Board and die photograph.

in Fig. 5(b) with a 180-ms wake-up latency. The measured trans-former AV was 30.6 dB, kED was 208.7/V, and the amplifier gain was28 dB. Fig. 5(c) shows the measured S11, indicating good matchingat 109 MHz. Fig. 5(d) shows missed detection rate (MDR) curvesafter correlation, where a 0.1% MDR was achieved with random(i.e., unsynchronized) transmission at −80.5 dBm while maintain-ing a false alarm rate < 1/h. Part-to-part measurements (n = 5)showed that the sensitivity and power were all within 0.5 dB and0.2 nW, respectively. Fig. 5(e) depicts the interferer tolerance wherea 33.3-bps PRBS OOK-modulated jammer was used to characterizethe coded error rate for symbol-0 (i.e., false alarms), while an all-1jammer was used for symbol-1 (i.e., missed detections). The interfererpower is defined as the power needed to achieve 0.1% MDR whenthe signal is 1 dB higher than the sensitivity. Table I summarizesthe proposed design and compares it to state-of-the-art sub-300-nWWuRXs. This design achieves the best sensitivity and sensitivity

normalized to 1/Latency. It should be noted for a WuRX, as long asa reasonable wake-up latency is achieved (e.g., <1 second for manylow-average throughput applications), the most important metrics arethe power consumption and sensitivity. Metrics, such as the energy/bitand bandwidth, are not as important since a WuRX has, by design,low throughput. A die and PCB photograph are shown in Fig. 6.

REFERENCES

[1] S. Oh, N. E. Roberts, and D. D. Wentzloff, “A 116nW multi-band wake-upreceiver with 31-bit correlator and interference rejection,” in Proc. IEEECustom Integr. Circuits Conf., San Jose, CA, USA, Sep. 2013, pp. 1–4.

[2] H. Jiang et al., “A 4.5nW wake-up radio with −69dBm sensitivity,” inIEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2017,pp. 416–417.

[3] P.-H. P. Wang et al., “A near-zero-power wake-up receiver achiev-ing −69-dBm sensitivity,” IEEE J. Solid-State Circuits, vol. 53, no. 6,pp. 1640–1652, Jun. 2018.

[4] V. Mangal and P. R. Kinget, “An ultra-low-power wake-up receiverwith voltage-multiplying self-mixer and interferer-enhanced sensitivity,”in Proc. IEEE Custom Integr. Circuits Conf., Austin, TX, USA, Apr. 2017,pp. 1–4.

[5] J. Moody et al., “A −76dBm 7.4nW wakeup radio with automaticoffset compensation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2018,pp. 452–454.

[6] P. T. Theilmann et al., “Near zero turn-on voltage high-efficiency UHFRFID rectifier in silicon-on-sapphire CMOS,” in Proc. IEEE Radio Freq.Integr. Circuits Symp., Anaheim, CA, USA, May 2010, pp. 105–108.

[7] P.-H. P. Wang et al., “A 400 MHz 4.5 nW −63.8 dBm sensitivity wake-upreceiver employing an active pseudo-balun envelope detector,” in Proc.IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2017, pp. 35–38.

[8] A. S. Rekhi and A. Arbabian, “A 14.5mm2 8nW −59.7dBm-sensitivityultrasonic wake-up receiver for power-, area-, and interference-constrainedapplications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2018, pp. 454–456.