IEDM 2003 1

A 90 nm High Volume Manufacturing Logic A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Technology Featuring Novel 45 nm Gate

Length Strained Silicon CMOS TransistorsLength Strained Silicon CMOS Transistors

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann*, K. Johnson#, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar,

P. Smith, K. Zawadzki, S. Thompson and M. Bohr

Logic Technology Development, * TCAD, # QREIntel Corporation, Hillsboro, OR, USA

IEDM 2003 2

90 nm Logic Technology Features90 nm Logic Technology Features

•• Strained Silicon TransistorsStrained Silicon Transistors

•• 1.2 nm Gate Oxide1.2 nm Gate Oxide

•• Nickel Nickel SalicideSalicide

•• 7 Copper Interconnect Layers7 Copper Interconnect Layers

•• LowLow--k CDO Dielectrick CDO Dielectric

•• 1.0 1.0 µµmm22 SRAM CellSRAM Cell

S. Thompson, et. al., 2002 IEDM

IEDM 2003 3

Transistor Strain TechniquesTransistor Strain Techniques

D

G

S S D

G

Tensile SiTensile Si33NN44 Cap Cap

S D

G

Selective Selective SiGeSiGe SS--D D Graded Graded SiGeSiGe Layer Layer

Biaxial Biaxial Tensile Strain Tensile Strain

UniaxialUniaxialCompressive Strain Compressive Strain

UniaxialUniaxialTensile Strain Tensile Strain

Traditional Approach Traditional Approach This Technology This Technology

IEDM 2003 4

Strained PMOS StructureStrained PMOS Structure

SiGeSiGe

•• SiGeSiGe film film embeddedembeddedinto source/draininto source/drain

•• SiGeSiGe film deposited film deposited by selective by selective epitaxyepitaxy

•• Induces large Induces large uniaxialuniaxialcompressive strain in compressive strain in channel channel

•• Dramatic hole mobility Dramatic hole mobility enhancementenhancement

Embedded Geometry + Compressive S/DEmbedded Geometry + Compressive S/D= Large = Large UniaxialUniaxial Channel StrainChannel Strain

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Si Recess Etch

Strained PMOS Process FlowStrained PMOS Process Flow

SiGe Epi Dep

NiSi Formation

•• SiGeSiGe introduced late in the introduced late in the process flow process flow sourcesource--draindrain

•• SiSi Recess Etch + Recess Etch + SiGeSiGe EpiEpidepositiondeposition inserted post inserted post spacer formation to standard spacer formation to standard nonnon--strained processstrained process

•• Ease of implementationEase of implementation

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SalicideSalicide Integration with Integration with SiGeSiGe

1%5%

10%25% 50%75%90%95%99%

10 12 14 16 18 20

NiSi sheet resistance on SiGe (Ohms/square)

•• NiSiNiSi compatible with compatible with SiGeSiGe (Co NOT compatible)(Co NOT compatible)•• NiSiNiSi has better narrow line scaling properties has better narrow line scaling properties

relative to CoSirelative to CoSi2 2 (IEDM 2002)(IEDM 2002)

SiGe

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Strained PMOS Performance Strained PMOS Performance

•• Dramatic performanceDramatic performancegain demonstrated forgain demonstrated forstrained PMOSstrained PMOS

SiSi0.830.83GeGe0.170.17::

> 50% I> 50% IDLINDLIN Gain Gain

> > 25% I25% IDSATDSAT Gain 0102030405060

0 10 20 30% Increase in IDSAT

% In

crea

se in

IDLI

NIncreasing Stress

Gain

IEDM 2003 8

0

5

10

15

0 20 40 60 80ID

SAT G

ain

(%)

0.0E+00

5.0E+04

1.0E+05

1.5E+05

Stre

ss *

Thic

knes

s (D

ynes

/cm

)

Cap Thickness (nm)

High Stress Film

Strained NMOS TransistorStrained NMOS Transistor

•• Developed a Developed a “Highly“Highly--Tensile”Tensile” SiNSiN capping film capping film •• UniaxiallyUniaxially tensile strain induced in channeltensile strain induced in channel•• 10% I10% IDSATDSAT gain from tensile channel strain gain from tensile channel strain

IEDM 2003 9

Benefits of This Strain ApproachBenefits of This Strain Approach

•• Low cost (~2% process cost adder)Low cost (~2% process cost adder)

•• Highly Highly manufacturablemanufacturable way to introduce strainway to introduce strain

•• NMOS and PMOS performance optimized separatelyNMOS and PMOS performance optimized separately

•• Mobility improvement maintained at high Mobility improvement maintained at high vertical fieldsvertical fields

•• Avoids cost, defect and integration issues Avoids cost, defect and integration issues associated with associated with SiGeSiGe waferswafers

•• Scalable to future generationsScalable to future generations

IEDM 2003 10

PMOS PMOS IIDSATDSATvsvs IIOFFOFF

High VHigh VTHTH::IOFF = 40 nA/umIDSAT = 0.7 mA/um

Low VLow VTHTH::IOFF = 400 nA/umIDSAT = 0.8 mA/um

0.1

1

10

100

1000

0.5 0.6 0.7 0.8 0.9IDSAT (mA/µm)

IOFF

(nA

/ µm

) 40nA/m

VVDD DD = 1.2V= 1.2VTTOXOX[physical[physical]] = 1.2nm= 1.2nm

IEDM 2003 11

NMOS NMOS IIDSATDSATvsvs IIOFFOFF

1

10

100

1000

0.9 1 1.1 1.2 1.3 1.4 1.5IDSAT (mA/µm)

IOFF

(nA

/ µm

)

40nA/µm

VVDD DD = 1.2V= 1.2VTTOXOX[physical[physical] ] = 1.2nm= 1.2nm

High VHigh VTHTH::IOFF = 40 nA/umIDSAT = 1.26 mA/um

Low VLow VTHTH::IOFF = 400 nA/umIDSAT = 1.45 mA/um

IEDM 2003 12

SubSub--threshold Characteristicsthreshold Characteristics

0.001

0.01

0.1

1

10

100

1000

10000

-1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2VGS (V)

ID ( µ

A/ µ

m)

PMOS NMOS

|VDS| = 0.05V, 1.2V

LLGATEGATE= 50 nm= 50 nm LLGATEGATE= 45 nm= 45 nm

Well controlled short channel effects Well controlled short channel effects SubthresholdSubthreshold slope <100 mV/decadeslope <100 mV/decade

IEDM 2003 13

Yield Challenge Yield Challenge -- SiGeSiGe DefectsDefectsInitial DevelopmentInitial Development After Focused After Focused EpiEpi

Defect Reduction EffortDefect Reduction Effort

Concern: Concern: Need for Need for SelectiveSelective SiGeSiGe EpiEpi

Superb Superb EpiEpi Film Selectivity Film Selectivity Achieved Across 300mm Wafers Achieved Across 300mm Wafers

IEDM 2003 14

Yield TrendYield Trend

90nm defect reduction trend has been fastest ever 90nm defect reduction trend has been fastest ever 90nm yields are now at level needed for HVM 90nm yields are now at level needed for HVM

1997 1998 1999 2000 2001 2002 2003 2004

Defect Density

(log scale)

0.18µm 0.13µm 0.13µm 90nm200mm 200mm 300mm 300mm

IEDM 2003 15

SummarySummary•• A novel, hA novel, highly ighly manufacturablemanufacturable and costand cost--effective way effective way

to introduce strainto introduce strain is described with devices showing is described with devices showing dramatic performance enhancementdramatic performance enhancement

•• Highest drive currents reported to date at 90 nm nodeHighest drive currents reported to date at 90 nm node

•• 90 nm defect reduction has been fastest ever and 90 nm defect reduction has been fastest ever and yields are now at level needed for high volume yields are now at level needed for high volume manufacturingmanufacturing

•• Advanced CPU products are being ramped on this Advanced CPU products are being ramped on this technology in two 300 mm wafer factoriestechnology in two 300 mm wafer factories

IEDM 2003 16

AcknowledgmentsAcknowledgments

• The authors gratefully acknowledge the many people at Intel who contributed to this work, including individual from the following organizations:

PTD Process and Design GroupsSort Test Technology DevelopmentQuality and Reliability EngineeringTechnology Computer Aided Design

IEDM 2003 17

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www.intel.com/research/silicon