A Capacitor Sharing Technique for RSD Cyclic

ADC

Basem Soufi, Saqib Q. Malik, and Randall L. Geiger,

Electrical and Computer Engineering Department,

Iowa State University

Outline

Background Objective Cyclic ADC Overview Proposed Capacitor Sharing Technique Implementation and Simulation Results Conclusion

Background

Advantages of cyclic ADC: Small die area Low power Moderate conversion speeds High resolution

Applications: Embedded systems Handheld products.

Objective

Objectives of proposed cyclic ADC structure: Power consumption reduction Area reduction No SNR penalty No conversion rate penalty Maintain simple implementation

Outline

Background Objective Cyclic ADC Overview Proposed Capacitor Sharing Technique Implementation and Simulation Results Conclusion

Cyclic ADC OverviewConcept of Operation

Binary search for the digital word that best represents the input

Fixed reference and input manipulation

Vin

Vout

+Vref

-Vref

Vout = 2·Vin - D·Vref

D = -1 D = +1

+Vref-Vref

Cyclic ADC Overview The classical structure

S/H x2 ∑

-Vref +Vref

Vin

To Digital Output

Control

Vout

+

-

+

-

• n-cycles for n-bit output resolution for one-bit per cycle structure

• Sample and hold is needed for comparator

Cyclic ADC Overview The Redundant Sign Digit (RSD) Technique

Vin

+Vref

-Vref

D = -1 D = +1

+Vref-Vref

D = 0

Vout

Vin

Vout

+Vref

-Vref

Vout = 2xVin - DxVref

D = -1 D = +1

+Vref-Vref

• Comparator offset errors are tolerated due to redundancy.

• No need for dedicated input Sample and Hold for comparator

Cyclic ADC Overview Two Stage RSD Cyclic ADC

Modify the sample and hold to a multiplication state

Add another comparison block

Speed is doubled by the addition of simple circuitry

One amplification in each phase – opamp can be shared

Digital Syncronizationand Correction

+x2Vin

DAC1

SC Networks

+x2

DAC2

b0, b1 b0, b1Vin Vin

Logic

-Vref0

+Vref

+

+

-

-

Vin

+Vref/4

-Vref/4 b0 b1

DAC

Final Output

22

Cyclic ADC Overview Conventional SC Networks

The residue voltage is held across the feedback capacitor*

*S. Q. Malik and R. L. Geiger, “Simultaneous Capacitor Sharing and Scaling for Reduced Power in Pipeline ADCs”, Proceedings of IEEE MWSCAS, August 2005.

-

+

DAC2

C2a

C2b

The last residue voltage is not utilized

Initial State

C1b

C1a

Vin

Initial State

-

+

DAC2

CC2a

CC2b

CC1a CC1b

State B

State B

-

+

DAC1

CC2b

CC1a

CC1b

State A

CC2a

State A

End of cycle

Outline

Background Objective Cyclic ADC Overview Proposed Capacitor Sharing Technique Implementation and Simulation Results Conclusion

Proposed Capacitor Sharing TechniqueProposed SC Networks

C1a

C1bVin

C2b

C2a

Initial State

Initial State

Capacitors of second stage are

available to sample the input

En

d o

f cy

cle

State B

-

+

DAC2

C1b

C2a

C2b

State B

C1a

State A

-

+

DAC1

C1a

C1b

C2a C2b

State A

State X

The residue is held across the feedback

capacitors. No sampling capacitors

are needed.

-

+C1a

C1b

C2b

C2a

DAC1

State X

+-

+-

Proposed Capacitor Sharing TechniqueInput Sampling Thermal Noise

Initial State

C1b

C1a

Vin

• For a given input sampling kT/C noise requirement, the proposed circuit capacitors can be reduced by 50%

Proposed

C1a

C1bVin

C2b

C2a

Initial State

ConventionalEach Cap = ‘1C’

Total Input Sampling Capacitance = ‘2C’

Each Cap = ‘0.5C’

Total Input Sampling Capacitance = ‘2C’

Proposed Capacitor Sharing TechniqueLimited Capacitor Scaling

-

+

DAC2

C1b

C2a

C2b

State B

C1a

Sampling Cap = ‘2C’

Sampling Cap = ‘1C’

-

+

C1a

C1bVin

C2b

C2a

Initial State

With residue gain of two, the structure provides optimal* limited capacitor scaling.

*D. W. Cline, and P. R. Gray, “A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter

in 1.2 µm CMOS”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 294-303, March 1996.

Proposed Capacitor Sharing TechniqueCapacitor Loading - Comparison

-

+

DAC1

CC2b

CC1a

CC1b

CC2a

• Capacitive loading on the output of the amplifier is 2 times less in proposed structure.

Each Cap = ‘0.5C’

Conventional Proposed

-

+

DAC1

C1a

C1b

C2a C2b

Each Cap = ‘1C’

Proposed Capacitor Sharing TechniqueCapacitor Loading - Summary

State Conventional Proposed

X N/A ‘0.5C’

A ‘2.5C’ ‘1.25C’

B ‘2.5C’ ‘1.25C’

• The capacitive loading on the opamp is reduced by a minimum of 50%

Proposed Capacitor Sharing TechniqueProposed V.S. Conventional

Structure Cap Area Opamp Power Consumption*

Cycles for n-bit output

Required Clock Lines

Conv. 100% 100% n/2 7

Prop. 50% 50%* n/2 8

*For first-order opamp modeling and no circuit parasitics. Actual savings in opamp power depends on opamp structure and circuit parasitics

Outline

Background Objective Cyclic ADC Overview Proposed Capacitor Sharing Technique Implementation and Simulation Results Conclusion

Implementation

C2b

φ2

φa

φA1

φs

φs

φ1

-

+

DAC1

DAC2φ2

Vin

C2a

C1b

C1a

φA2

φC1

φC2

φs

φs

φs

φa

φa

φa

φ1

φ1

φ1

φ2

φ2

To second Comparator

To first Comparator

The structure is implemented as a 10-bit ADC in 0.5μm CMOS process

Cascode-Cascade opamp structure

Bootstrapped input switch

Dummy switches are added to simplify clocking

Simulation Results

Reconstructed simulation spectrum of 100KHz sinusoidal input signal digitized at 2.3MHz. THD=-76.11dB, SFDR=74.95dB

• All transistor level implementation for circuit components

• Behavioral clocks generation

• Simulations using Spectre

Conclusion

• Lower power, with smaller die area RSD cyclic structure was presented.

• No penalty on SNR performance

• No penalty on conversion rate

• Simple implementation is maintained

Discussion