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“A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25 μm CMOS
technology for applications in the LHC
environment.”
8th Workshop on Electronics for LHC Experiments 9-13 Sept. 2002, Colmar, France
K. Kloukinas, G. Magazzu, A. Marchioro
CERN EP division, 1211 Geneva 23, Switzerland
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 2
Overview
Motive of Work
Description of the macro-cell design
Experimental Results
Conclusions
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 3
Motive of Work
Several Front-End ASICs for the LHC detectors are using the CERN DSM Design Kit in 0.25 μm commercial CMOS technology.
Many ASICs require the use of rather large memories in Readout Pipelines, Readout Buffers and FIFOs.
CERN DSM Design Kit lacks design automation tools for generating customized SRAM blocks.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 4
Proposed Design
Built an SRAM macro-cell that can be configured in terms of word counts and bit organization by means of simple floorplanning procedures.
Initially designed for the needs of the “Kchip” Front-End ASIC used in the CMS ECAL Preshower detector.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 5
CERN-SRAM specifications
Scalable DesignConfigurable Bit organization (n x 9-bit).Configurable Memory Size (128 – 4Kwords).
Synchronous Dual-Port OperationPermits Read/Write operations on the same clock cycle.Typical Operating Frequency: 40 MHz.
Low Power DesignFull Static Operation.Divided Wordline Decoding.
Radiation Tolerant Design
SRAM SRAM
Data In
Read Address
CLK
RDWR
Write Address
Data Out
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 6
Memory Cell
To minimize the macro-cell area a Single Port memory cell is used based on a conventional cross-coupled inverter scheme. Gain in Memory Cell Layout Area = 18%
RBL WBL WBL RBL
W_WL
R_WL
Dual Port SRAM Cell
BL BL
WL
Single Port SRAM Cell
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 7
Memory Cell Design
BL BL
WL
BL GND VDD GND BL
WL
M1
M2
M3
PC8.
42 μ
m
5.60 μm
Single Port memory cellInterconnect: 3 metal layers• 1st for local interconnects• 2nd for vertical bitlines and power lines• 3rd for horizontal wordlinesMemory Cell Area: 47.152 μm2
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 8
SRAM Block Diagram
Dual-port functionality is realized with a time sharing access mechanism.
• Registered Inputs • Latched Outputs
SRAM Array
Row
dec
oder
Column-decoder
Write Drivers
ClkR
WA<n-1..0>
Din<m-1..0>
7
n-7
Read LogicDout
<m-1..0>
W
RA<n-1..0>
Add
r. R
eg.
Add
r. R
eg.
Dat
a R
eg.
Dat
a L
atch
clk
m
TimingLogic
Wor
d-li
ne B
uffe
rs
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 9
SRAM Interface Timing
Clk
WA
R
Din
Dout
WRITE READ READ/WRITEtS tH
W
RA
tS tH
tacc
1 2 3 4 5
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 10
SRAM macro-cell Design
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 11
Address Mux Register
Leaf cell is based on the D-F/F and the 2-input Mux standard cells found in the CERN DSM Design Kit.
True & Complementary output with balanced timing.
Easily sizeable by abutting the necessary number of leaf cells.
Leaf Cell
Q
QSET
CLR
D
Q
QSET
CLR
D
WA
RA
Addr
Clk
AddrZ
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 12
Row Decoder
A6
A0WL
precharge
evaluate
WL0
WL1
WL2
WL3
WL128
A0...A6 A0...A6
Decoder: 7 to 128Hardwire-configured.Pre-routed layout block.
Dynamic NAND-type.Speed, Area, Power advantages over the static NAND-type.Latched output.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 13
Column Decoder
Static NAND-type implementationColumn decoding is one of the last actions to be performed in the read sequence.It can be executed in parallel with other functions, and can be performed as soon as address is available.Its propagation delay does not add to the overall memory access time.
Size ConfigurableMake use of Design kit standard cells.Decoding function is via-hole programmable.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 14
Divided Wordline Decoding
Global Word-lineLocal Word-lineLocal Word-line
Block Select
Block Select
Reduced Power Consumption.The non accessed portions of the memory remain in the precharge state.
Improved Wordline Selection Time. Since the RC delay in each divided wordline is small due to its short length.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 15
Divided Wordline Decoding
SRAM Array
Row
Dec
oder
Column Dec.
Write Drivers
Read Logic
SRAM Array
Write Drivers
Read LogicW
ord-
line
Buf
fers
Wor
d-li
ne B
uffe
rs
SRAM Array
Read Logic
SRAM Array
Read Logic
Wor
d-li
ne B
uffe
rs
Wor
d-li
ne B
uffe
rs
Write DriversWrite Drivers
Global Word-line
Local Word-line
Block Select signals
Address
Data In
Data Out
Column Dec. Column Dec. Column Dec.
Block Pre-Dec.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 16
SRAM macro-cell Design
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 17
Data Input Output Ports
Data Input RegisterLeaf cell is based on the D-F/F standard cell from CERN DSM Design Kit.True & Complementary output with balanced timing.
Data Output LatchLeaf cell is based on the Latch standard cell from CERN DSM Design Kit.
Easily sizeable by abutting the necessary number of leaf cells.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 18
SRAM Data Path
Bit Line Bit Line
Word Line
Data inWrite enable
BLPC
Data outQ
QSET
CLR
D
LLatch
Q
QSET
CLR
D
Clk
precharge
evaluate
precharge
evaluate
Read Logic
Write Drivers
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 19
Read Logic
Substitution of the conventional sense amplifier with an asymmetric inverter.
Reduced Power ConsumptionStable operation al low power supply voltages.Acceptable performance for target applications.Easy to design.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 20
Replica Techniques
ScalabilityWordline select time depends on the size of the memory.Dummy Wordline with replica memory cells to track the wordline charge-discharge time.
Bitline TimingDummy Bitlines to mimic the delay of the bitline path over all conditions.
SRAM Array
BL0
Dummy Bit Lines
WLdummy
Dummy Word Line
128
row
s
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 21
Replica Techniques
Bit Line Bit Line
Local Word Line
Data in
WEN
Data out
Row Decoder
BLPC
LWLdummy
BL0
A6
A0WLPC
WLPC
Block Select
WLdummy
Global Word Line
Dummy Bit Lines
BL BLDummy Word Line
Q
QSET
CLR
D
LLatch
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 22
Timing Logic
Timing Logic
WLpc
BLpc
REN
WEN
Latch
ClkRW
WLdummy
BL0
SRAM Interface
Memory CellArray
Memory CellArray
Data OuputLatch
Data InputRegister
Address MuxRegister
Clk Clk
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 23
Timing Logic
Asynchronous internal timing of control signals.Static operation.Hand-shaking and transition detection to realize internal timing loops.Timing loops are initiated by the system clock and terminated upon completion of the operation.All control signals are forced back to their initial state to prepare for subsequent tasks.During standby periods, bitlines and wordlines precharge-evaluate cycles are not initiated, thus keeping the Power Consumption to a minimum.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 24
Operation and Timing
Clk
BLpc
BL0
WLpc
WLdummy
LWLdummy
Latch
READ WRITE
WEN
REN
tWL
tBL read
tWL
tBL write
BLBL
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 25
Cell Library
Row
Dec
oder
WordLine Buffers SRAM column, 128 x 9bits
Column Decoder
Timing logic
Output Data Latche
Data Input Register
Address Mux Register
Block Pre-Decoder
(50.4 μm x 1086.2 μm)
Size Configurable Fixed Layout
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 26
Floorplanning
gndvdd
Colu
mn
Row
Dec
oder
(128
row
s)
Read logic
Write drv.
Read logic
Write drv.
Read logic
Write drv.
Read logic
Write drv.
Read logic
Write drv.
Read logic
Write drv.
Read logic
Write drv.
BlockWA
RA
DIn
DOut
CLK
WR
Read logic
Write drv.
Pre
Dec
oder
DIn
Reg
DO
ut L
atch
Tim
ing
Add
ress
Reg
Column Decoder
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 27
CAD Tools Support
Digital Simulation
Digital SimulatorVERILOG
SRAMverilog module(parameterized)
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 28
CAD Tools Support
Logic Synthesis
Logic SynthesisTool
SYNOPSYS
SRAMtiming
Design Kit.lib file
Combined.lib file
Combined.db file
compilation
Template
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 29
CAD Tools Support
Place & Route
SRAMtiming
Place & RouteTool
Silicon Ensemble
Design KitTLF file
CombinedTLF file
Layout view
Abstract view
CombinedCTLF file
compilation
LEF file
Template
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 30
Experimental Results
To prove the concept of the SRAM macro-cell scalability and to evaluate the performance of the proposed design we have fabricated two test chips:
a 1Kwords X 9bits anda 4Kwords X 9bits.
Both chips were tested and found functional.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 31
Submitted SRAM Chips
1st PrototypeDesign: CERN_SRAM_1KConfiguration: 1K x 9 bitSize: ~560μm x 1,300μmArea: ~0.73mm2 Density: ~12.6Kbit/mm2
The Memory consists of 2 Blocks of 512 x 9bits.Each Block is composed by 4 Columns of 128 X 9bits.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 32
Submitted SRAM Chips
2nd PrototypeDesign: CERN_SRAM_4KConfiguration: 4K x 9 bitSize: ~1,850μm x 1,300μmArea: ~2.4mm2Density: ~15.4Kbit/mm2
The Memory consists of 8 Blocks of 512 x 9bits.Each Block is composed by 4 Columns of 128 X 9bits.
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 33
CERN SRAM test results
Functional tests Max operating frequency:
Simultaneous Read/Write operations: 70MHz @ 2.5V
Read access time: 7.5ns @ 2.5VPower dissipation:
15μW / MHz @ 2.5V for simultaneous Read/Write operations on the same clock cycle (0.60mW @ 40MHz).
Tests for process variations: Differences in the access time < 1ns for: -3σ, –1.5σ, typ, +1.5σ, +3σ
Test chip: 4Kx9bit
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 34
Performance Tests
Test Chip: 4Kword X 9bitsOperation Frequency: 50MHzPower Supply: 2.5VoltsRead Access Time: 7.5nsec
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 35
Performance Tests
Test Chip: 4Kword X 9bitsPower Supply: 2.0 - 2.7VoltsOperation Frequency: 50MHzTest Patterns:
All 1’s and all 0’sCheckerboardMarching 1’sMarching 0’s
Schmoo Plot
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.00 8.00 10.00 12.00 14.00 16.00
Access Time (nsec)
Po
wer
Su
pp
ly V
olt
age
(V)
Pass
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 36
Power dissipation
Power dissipation of macro-cell.
Test chip: 4Kwords x 9bits
CERN SRAM 4K
0.0
200.0
400.0
600.0
800.0
1000.0
1200.0
20 30 40 50 60 70
Clock frequency (MHz)
Po
we
r D
iss
ipa
tio
n (
uW
)
Standby
Idle
Read
Write
Read/Write
OperationPower
(μW/MHz)Standby 0.10Idle 1.90Read 7.40Write 10.60Read/Write 14.05
Operation DescriptionStandby No operation, addr. & data static.Idle No operation, addr. & data changing in every clk cycleRead checkerboard data patternWrite checkerboard data patternRead/Write checkerboard data pattern
Test Conditions
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 37
Irradiation Tests
Ionizing Total DoseConditions
Source: X-rays.Step Irradiation: 1Mrad, 5Mrad, 10Mrad.Constant dose rate: 21.2 Krad/min.Annealing: 24h @ ~25 oC.Under bias, in Standby mode during irradiation & annealing.
ResultsNo increase in power dissipation.No measurable degradation in performance.
Single Event Upset: Under preparation
Test chip: 4Kwords x 9bit
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 38
CERN SRAM popularity ! ATLAS MCC chip
Memory configuration: 128 x 27bit Detector: ATLAS PIXEL Lab: INFN Genova
ALICE AMBRA chip Memory configuration: 16K X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Torino
ALICE CARLOS chip Memory configuration: 256 X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Bologna
LHCb SYNC chip Memory configuration: 256 X 9 bits Detector: LHCb muon system Lab: INFN Cagliary
ATLAS SCAC chip Memory configuration: 128 x 18bit Detector: ATLAS tracker Lab: NEVIS Labs
ATLAS DTMROC chip Memory configuration: 128 x 153 bits Detector: ATLAS TRT Lab: CERN
CMS Kchip Memory configuration: 2K x 18 bits 128 x 18 bits Detector: CMS Preshower Lab: CERNChips submitted and tested
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 39
Design Support
Delivery of SRAM design libraryDelivery of SRAM design library
Half a day “design course” @ CERNHalf a day “design course” @ CERN
Designer configures his macrocellDesigner configures his macrocell
Review the macrocell designReview the macrocell design
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 40
Conclusions
Design StatusDesign meets target specifications. Macrocell has been successfully used in a number of ASIC designs.
Future PlansNo further development is foreseen.
Design SupportContact Person: [email protected]
Information on the Webhttp://home.cern.ch/kkloukin
Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 41
Floorplanning
WAD
In R
egT
imin
gBlock
Colu
mn
Read logic
Write drv.
gndvdd
RA
DIn
DOut
CLK
WRR
ow D
ecod
er (1
28 r
ows)
Add
ress
Reg
DO
ut L
atch
WorldLine Buffers& Block Decoders
Column Decoder.
WA
DIn
Reg
Tim
ing
Add
ress
Reg
Read logic
Write drv.
Block
Colu
mn
Read logic
Write drv.
Pre
Dec
oder
gndvdd
RA
DIn
DOut
CLK
WRR
ow D
ecod
er (1
28 r
ows)
DO
ut L
atch